An ultra-wideband communication system package structure

Abstract

The application discloses an ultra-wideband communication system packaging structure, which comprises a packaging substrate, a first power supply area and a second power supply area, the first power supply area is used for connecting the power supply pin of a transceiver circuit, the second power supply area is used for connecting the power supply pin of a phase-locked loop circuit, and the layout of the first power supply area and the second power supply area satisfies the maximum physical distance between the two; further comprising an electromagnetic isolation barrier, a plurality of high-frequency adaptive conductive connecting pieces, the distance and size of which are adapted to the signal wavelength of the ultra-wideband communication frequency band, and are used for inhibiting high-frequency parasitic coupling; an analog pin area and a digital pin area, which respectively belong to different physical partitions of the packaging substrate, and are isolated through a ground conductive connecting piece. Through the space-electromagnetic collaborative isolation design of the packaging level, the coupling geometry constraint and the electromagnetic field regulation and control principle are combined, and high-frequency interference inhibition is realized.

Description

Technical Field

[0001] This invention relates to high-frequency communication chip packaging, applicable to UWB systems and millimeter-wave communication systems in the 6.5GHz~10GHz frequency band. Background Technology

[0002] In communication transceiver chips or systems, the UWB frequency band has certain unique characteristics: compared to the low-frequency bands of other public wireless communications (such as 5G and 4G LTE), the UWB frequency band is relatively high, and the parasitic effects of packaging and PCB can have a significant impact on the system. In contrast, millimeter-wave communications, such as the millimeter-wave bands of public wireless communications (like 5G), due to their high frequency and very short wavelength, often integrate the package and the bare chip in a fully integrated design, meaning the transceiver and antenna are already integrated in the package and the bare chip.

[0003] In this situation, if the isolation between the transceiver and the voltage-controlled oscillator (VCO) is insufficient, the signal output from the transmitter's power amplifier will leak to the VCO in the phase-locked loop (PLL), causing the PLL to degrade in performance, become unstable, or even lose lock. On the other hand, if the isolation is insufficient, spurious signals from the VCO will also leak to the transceiver and radiate from the antenna port, causing interference to signals in other frequency bands. For example... Figure 1 As shown.

[0004] The above background information is provided only to aid in understanding the concept and technical solution of this invention. It does not necessarily belong to the prior art of this patent application. In the absence of clear evidence that the above information was disclosed on the filing date of this patent application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0005] This invention proposes a packaging structure for an ultra-wideband communication system to solve the technical problem of isolation between the transceiver and the voltage-controlled oscillator (VCO) in an ultra-wideband (UWB) system.

[0006] To achieve the above objectives, this invention proposes an ultra-wideband communication system packaging structure, comprising: a packaging substrate, including a first power supply region and a second power supply region, wherein the first power supply region is used to connect the power supply pins of the transceiver circuit, and the second power supply region is used to connect the power supply pins of the phase-locked loop circuit, and the layout of the first power supply region and the second power supply region satisfies the maximization of the physical distance between them; and an electromagnetic isolation barrier, including at least two rows of grounding conductive connectors, placed between the first power supply region and the second power supply region, wherein the grounding conductive connectors expand into a continuous ground plane during the packaging reflow process.

[0007] In some embodiments, the system also includes a plurality of high-frequency adaptive conductive connectors, the spacing and size of which are adapted to the signal wavelength of the ultra-wideband communication band, in order to suppress high-frequency parasitic coupling; the pin area is further divided into an analog pin area and a digital pin area, which belong to different physical partitions of the packaging substrate, and the two are isolated by grounding conductive connectors.

[0008] In some embodiments, the grounding conductive connector includes a spherical solder body that expands during reflow soldering to form a continuous grounding plane covering adjacent grounding conductive connectors. The term "spherical" is not strictly limited and may also include quasi-spherical shapes, such as flattened convex shapes.

[0009] In some embodiments, the spacing of the high-frequency adaptive conductive connectors is a predetermined non-resonant spacing range, which is adapted to values ​​outside of integer multiples of 1 / 4 wavelength in the 6.5 GHz to 10 GHz frequency band.

[0010] In some embodiments, the power supply pin of the phase-locked loop circuit provides power to both the voltage-controlled oscillator and the phase-locked loop functional module.

[0011] In some embodiments, the analog pin region and the digital pin region are respectively connected to independent decoupling capacitor networks via inner layer traces on the substrate.

[0012] In some embodiments, the pin level of the grounding conductive connection area of ​​the electromagnetic isolation barrier is low.

[0013] In some embodiments, the size of the packaging substrate is 3mm×3mm to 5mm×5mm; the spacing between the spherical solder bodies is 400μm to 500μm to suppress parasitic coupling effects in the high-frequency band of 6.5GHz to 10GHz; and the diameter of the spherical solder bodies is 250μm to 750μm.

[0014] In some embodiments, the electromagnetic isolation barrier between the first power supply region and the second power supply region comprises at least four columns of ground-grounded earth-shaped solder bodies.

[0015] Compared with existing technologies, the advantages of this invention are as follows: By maximizing the physical distance between the first and second power supply areas through their layout, an electromagnetic isolation barrier is established. The spacing and size of multiple high-frequency adaptive conductive connectors are adapted to the signal wavelengths of ultra-wideband communication bands. Furthermore, the analog pin area and digital pin area belong to different physical partitions of the packaging substrate and are isolated from each other by grounded conductive connectors. This achieves a spatial-electromagnetic synergistic isolation design at the packaging level, coupling geometric constraints and electromagnetic field modulation principles. Spacing isolation reduces near-field coupling, a continuous ground plane reduces electromagnetic leakage, and the high-frequency adaptive solder ball spacing suppresses resonant radiation, thus achieving high-frequency interference suppression. Simulation results show that through the synergistic effect of spatial isolation and electromagnetic shielding, the system isolation is improved by ≥7dB (simulation verification).

[0016] Based on this, the present invention improves the isolation between the transmitter and the phase-locked loop in the packaging, thereby reducing the chip's requirements for PCB routing, reducing the sensitivity to PCB design, reducing system design complexity, making it more compatible with PCB process fluctuations, and improving the tolerance of trace length. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a communication transceiver system that is existing technology and applicable to embodiments of the present invention;

[0018] Figure 2 This is a schematic diagram of the overall return path of existing technology;

[0019] Figure 3 This is a schematic diagram of the separation layout of analog and digital pins on the packaging substrate according to an embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram showing the division of the phase-locked loop region and the transceiver region in an embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of an embodiment of the present invention in which two rows of solder ball grounding pins are introduced between the power supply pin and the transmit pin;

[0022] Figure 6 This is a schematic diagram of an embodiment of the present invention showing eight radio frequency ground pins forming a radio frequency ground wall;

[0023] Figure 7 This is a simulation diagram of the isolation (dB) curve between the receiver and the phase-locked loop power supply circuit in an embodiment of the present invention.

[0024] Figure 8 This is a simulation diagram of the isolation (dB) curve between the transmitter and the phase-locked loop power supply circuit in an embodiment of the present invention.

[0025] Figure 9This is a side view schematic diagram of the actual design of an embodiment of the present invention applied to a PCB board.

[0026] Figure 10 This is a schematic diagram of the bottom of a physical design of an embodiment of the present invention applied to a PCB board. Detailed Implementation

[0027] The embodiments of the present invention will be described in detail below. It should be emphasized that the following description is merely exemplary and is not intended to limit the scope and application of the present invention.

[0028] It should be noted that when a component is referred to as "fixed to" or "is on" another component, it can be directly on or indirectly connected to that other component. When a component is referred to as "connected to" another component, it can be directly connected to or indirectly connected to that other component. Furthermore, a connection can be used for both fixing and circuit / signal connectivity.

[0029] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of the present invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0031] The current challenge in UWB design lies in the fact that its performance is related to the chip, packaging, and PCB. It is necessary to consider the impact of chip, packaging, and board-level design on the system in a unified manner. However, existing technologies usually increase the isolation of the voltage-controlled oscillator at the two levels of chip design and PCB board-level design, without considering the packaging level.

[0032] For example, in chip design, existing technologies mainly improve the isolation of PA-VCO by the following methods during the chip design process: (1) maximizing the spacing between the VCO inductor and the TX (Transmitter) module; (2) arranging the inductors orthogonally to minimize magnetic coupling; (3) using a ground protection ring or patterned ground shield (PGS) under the inductor to block electric field and substrate noise; and figure-eight inductors (NXP (NXP Inc.) Invention Publication-200980112608.0); (4) defining the VCO frequency of the PLL (Phase-Locked Loop) at N times the transmitter frequency, and then generating the local oscillator signal through an N-division circuit, so that the system transmitter frequency and the frequency generated by the PLL are different (Invention Publication-200980130511.2), etc.

[0033] UWB systems have the unique characteristics of high frequency (6.5GHz~10GHz) and high bandwidth (500MHz and 1GHz). Existing technologies cannot guarantee the isolation between the transceiver and the phase-locked loop through optimal chip design and PCB design alone. Packaging design needs to be considered in conjunction with these technologies.

[0034] This invention proposes an ultra-wideband communication system packaging structure, including: a packaging substrate, an electromagnetic isolation barrier, multiple high-frequency adaptive conductive connectors, an analog pin area, and a digital pin area.

[0035] The packaging substrate includes a first power supply region and a second power supply region. The first power supply region is used to connect the power supply pins of the transceiver circuit, and the second power supply region is used to connect the power supply pins of the phase-locked loop (PLL) circuit. The layout of the first and second power supply regions maximizes the physical distance between them. The power supply pins of the PLL circuit simultaneously provide power to both the voltage-controlled oscillator (VCO) and the PLL functional module. The package substrate dimensions range from 3mm × 3mm to 5mm × 5mm.

[0036] The electromagnetic isolation barrier includes at least two rows of grounding conductive connectors positioned between a first power supply area and a second power supply area. During reflow soldering, the grounding conductive connectors expand into a continuous ground plane. Each grounding conductive connector includes spherical solder bodies that expand during reflow soldering to form a continuous ground plane covering adjacent grounding conductive connectors. The pin level of the grounding conductive connector region of the electromagnetic isolation barrier is low. The spacing between the spherical solder bodies is 400 μm to 500 μm to suppress parasitic coupling effects in the high-frequency band (6.5 GHz to 10 GHz); the diameter of the spherical solder bodies is 250 μm to 750 μm. The electromagnetic isolation barrier also includes at least four rows of grounding spherical solder bodies. In some alternative embodiments, low-level or ground pins may be named differently than directly as "ground" or "low level," but they may be used to connect to low level or ground via external PCB circuitry, and their intended meaning is also "ground" or "low level," thus falling under the category of "ground" or "low level" as used in this application.

[0037] The spacing and size of multiple high-frequency adaptive conductive connectors are adapted to the signal wavelengths of ultra-wideband communication bands to suppress high-frequency parasitic coupling. The spacing of the high-frequency adaptive conductive connectors is within a predetermined non-resonant spacing range, which is adapted to values ​​other than integer multiples of 1 / 4 wavelength in the 6.5 GHz to 10 GHz band.

[0038] The analog pin area and the digital pin area belong to different physical partitions of the package substrate and are isolated from each other by a grounding conductive connection. The analog pin area and the digital pin area are respectively connected to independent decoupling capacitor networks through the inner layer traces of the substrate.

[0039] In the UWB system described in this embodiment of the invention, the chip is in a BGA package. The power and ground pads need to pass through leads, substrate, solder balls, and PCB, making the entire return current path very long. Assuming the chip thickness is 100um, the BGA substrate thickness is 100um, the solder ball height is 250um, and the first layer of the PCB is 100um thick, the power and ground return current is achieved through capacitors on the PCB. Therefore, the trace length between the power supply and the capacitor on the circuit board also needs to be added. Here, we assume the trace length on the PCB is 2000um. Then, the total power return current path from the chip's power pad to the bare chip's ground pad is 3100um ((100um+100um+250um+100um)*2+2000um).

[0040] In EMI design, it's necessary to check whether the signal line length and signal frequency create resonance. Specifically, when the wiring length is an integer multiple of 1 / 4 of the signal wavelength, the wire will resonate, radiating electromagnetic waves and causing interference. From an antenna radiation perspective, if the signal line length is 1 / 4 wavelength, the current distribution follows a sinusoidal function, with the current reaching its maximum at the bottom and minimum at the end. This current distribution is conducive to forming a more ideal radiation pattern, resulting in an antenna radiation gain of 2.15 dB. The wavelengths at frequencies of 6.5 GHz and 8 GHz are 46150 μm and 37500 μm, respectively. Their quarter-wavelengths are 11537.5 μm and 9375 μm. The previously mentioned total return path length from power to ground is 3100 μm. Figure 2 As shown, although not exactly equal to 1 / 4 wavelength, it still has a considerable radiation effect (antenna gain is approximately -10dB). Especially in the power supply loop of the voltage-controlled oscillator (VCO), if not handled properly—for example, if the system manufacturer further increases the power supply traces in the PCB design; if the decoupling capacitor is not selected appropriately; or if a thicker PCB board is used, increasing the power supply loop's antenna radiation gain—it will increase the isolation between the transceiver and the VCO, ultimately affecting the VCO's performance and the transceiver's spurious radiation requirements. The current main approach is to perform EMI modeling and simulation of critical circuits on the PCB, enabling system manufacturers to minimize the coupling between critical circuits in the PCB design.

[0041] The embodiments of the present invention mainly improve the isolation between the transmitter and the voltage-controlled oscillator through the packaging layer, thereby reducing the pull of the transmitter on the local oscillator signal.

[0042] In PCB design, the isolation between the power amplifier and the phase-locked loop (PLL) is increased by increasing the distance between them and adding shielding covers to sensitive circuits such as the power amplifier and PLL. This prevents insufficient isolation between the transceiver and the PLL in the UWB chip package, which could lead to frequency pulling of the transmitter power amplifier on the PLL's voltage-controlled oscillator, and also avoids stray leakage from the transmitter due to insufficient isolation between the transceiver and the PLL. This is mainly achieved through the following design concept:

[0043] (1) By setting and dividing the UWB packaged solder balls, the power supply distance between the transceiver and the voltage-controlled oscillator of the phase-locked loop is increased.

[0044] (2) The power supply voltage of the phase-locked loop and the transceiver are grounded through two rows of multiple solder ball pins. The solder balls of the BGA package are spherical and composed of tin and other alloy elements. After the solder balls melt, they form a ground wall for spatial isolation, thereby increasing the isolation between the power supply system of the transceiver and the phase-locked loop.

[0045] (3) Properly configure the transceiver pins and phase-locked loop (PLL) function pins. The PLL power supply pins refer to the pins that supply power to the voltage-controlled oscillator (VCO) of the PLL, including but not limited to the pins that supply power to other functional circuits. The grounding pins used to isolate the transceiver and the PLL are not limited to pins that are only set to ground, but also include pins in this area with a low level.

[0046] Based on this approach, the technical solution of the embodiments of the present invention is described in detail below: Example

[0047] Figure 3 The diagram shows the layout of analog and digital pins on a UWB chip packaging substrate. The red broken line in the middle is for illustrative purposes only and is not an actual line in the product; it merely indicates the logical division between areas. The left side of the red broken line represents the analog pin area, and the right side represents the digital pin area. The package size is 4mm x 4mm, with 64 pins (8 rows and 8 columns). The right-hand area is primarily used for digital circuit pins. The grounds for analog and digital pins are separated and connected via the PCB ground plane. This arrangement helps reduce noise between the analog and digital domains. The solder balls for digital and analog pins are arranged according to the most convenient routing method for UWB wafer pins on the packaging substrate to divide the area.

[0048] In this embodiment, the phase-locked loop and the RF front-end transceiver are kept as far apart as possible, and the final layout is as follows. Figure 4 As shown, the lower left of the chip is set as the RF front-end transceiver area, and the upper part of the 4th and 5th rows of the chip is set as the RF phase-locked loop area. Figure 4 In the diagram, the straight lines within the border are schematic and not actual lines in the product body; they are only used to indicate the logical division between areas. Specifically, RX RF is the receiver section of the transmitter; TX RF is the transmitter's transmitter transmission section; GND RF is the transmitter's ground pin; VDD PLL is the power supply voltage of the phase-locked loop (PLL); VDD LDO PLL is the power supply voltage of the PLL output via a low-dropout linear regulator; and GND PLL is the PLL's ground pin.

[0049] This embodiment also includes two rows of solder ball grounding pins between the power supply pins and the transmit pins connecting the RF phase-locked loop region, such as... Figure 5 As shown. Figure 5In the diagram, the straight lines within the border are schematic and not actual lines in the product body; they are only used to indicate the logical division between areas. The diagonal lines within the border represent the path from the phase-locked loop area to the transceiver area. The overall size of the BGA (8x8 pins) chip is 4mm x 4mm, the ball pitch is 400um (industry ball pitch is generally 300um~1500um), and the diameter of the solder balls is 250um (industry ball pitch is generally 100um~750um).

[0050] After actual board-level processing in the UWB system, the size of the solder balls will increase due to the flattening of the solder balls after melting. Assuming the diameter of the melted solder ball is 300µm, for example... Figure 6 As shown, Figure 6 In the diagram, the straight lines within the border are schematic and not actual lines in the product body; they are only used to illustrate the logical division between areas. The diagonal lines within the border represent the path from the phase-locked loop (PLL) area to the transceiver area. From the plan view, four RF ground pins isolate the power supply pins and transmit pins of the RF PLL area. These four RF ground pins, along with other RF ground pins, form a good ground wall. This eight RF ground pins forming the RF ground wall increase the isolation between the transmitter and the PLL power supply system.

[0051] This embodiment takes the suppression of resonant radiation in the 6.5GHz~8GHz frequency band as an example. The details of the solution are as follows:

[0052] Substrate: 4mm×4mm BT resin substrate (tolerance ±0.1mm);

[0053] Solder balls: SnAgCu alloy solder balls, array 8×8, spacing 400±25μm, diameter 250±15μm; the spacing between the transceiver area (lower left) and the VCO area (above the 4th-5th rows) is ≥1.6mm (1 / 3 of the diagonal).

[0054] Layout: The diagonal spacing between the transceiver area and the VCO area is 3.2mm (56% of the substrate diagonal of 4√2mm);

[0055] Grounding barrier: two rows of solder balls (spacing 400±20μm), reflow soldering peak temperature 240±5℃.

[0056] Test Items Example 1 Comparative example (without floor or wall) Improvement rate Isolation between the receiver and the phase-locked loop power supply circuit @ 6.5GHz~8GHz 57.4dB 50.5dB 6.9dB Isolation between transmitter and phase-locked loop power supply circuit @ 6.5GHz~8GHz 66.8dB 59.2dB 7.6dB The embodiments of the present invention improve the isolation between the transmitter and the phase-locked loop in terms of packaging, and reduce the requirements of the chip for PCB wiring.

[0057] Figure 7 This is a simulation diagram of the isolation (dB) curve between the receiver and the phase-locked loop power supply circuit according to an embodiment of the present invention. Figure 8This is a simulation graph showing the isolation (dB) curve between the transmitter and the phase-locked loop power supply circuit according to an embodiment of the present invention. The simulation results show that the isolation between the transmitter and receiver and the phase-locked loop is improved by about 7dB, indicating that this solution can effectively increase the isolation between the transceiver and the phase-locked loop.

[0058] Figure 9 , 10 This is a schematic diagram of a physical design according to an embodiment of the present invention. The PCB board has two layers, and the approximately spherical component at the bottom is a solder ball.

[0059] The above description provides a further detailed explanation of the present invention in conjunction with specific / preferred embodiments, and it should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various substitutions or modifications can be made to these described embodiments without departing from the concept of the present invention, and all such substitutions or modifications should be considered within the scope of protection of the present invention. In the description of this specification, the reference to terms such as "an embodiment," "some embodiments," "preferred embodiment," "example," "specific example," or "some examples," etc., indicates that the specific features, structures, materials, or characteristics described in connection with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate different embodiments or examples and features of different embodiments or examples described in this specification without contradiction. Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made herein without departing from the scope defined by the appended claims.

Claims

1. A packaging structure for an ultra-wideband communication system, characterized in that, include: The packaging substrate includes a first power supply area and a second power supply area. The first power supply area is used to connect the power supply pins of the transceiver circuit, and the second power supply area is used to connect the power supply pins of the phase-locked loop circuit. The layout of the first power supply area and the second power supply area satisfies the requirement of maximizing the physical distance between them. The electromagnetic isolation barrier includes at least two rows of grounded conductive connectors placed between the first power supply area and the second power supply area. During the encapsulation reflow process, the grounded conductive connectors expand to cover a continuous ground plane covering adjacent grounded conductive connectors. It also includes multiple high-frequency adaptive conductive connectors, the spacing and size of which are adapted to the signal wavelength of the ultra-wideband communication frequency band to suppress high-frequency parasitic coupling. The spacing of the high-frequency adaptive conductive connectors is within a predetermined non-resonant spacing range, and the spacing range is adapted to values ​​outside of integer multiples of 1 / 4 wavelength in the 6.5GHz to 10GHz frequency band. The pin area is further divided into an analog pin area and a digital pin area, belonging to different physical partitions of the packaging substrate, and isolated from each other by grounded conductive connectors. The analog pin area and the digital pin area are respectively connected to independent decoupling capacitor networks through inner layer traces on the substrate to achieve high-frequency interference suppression.

2. The packaging structure according to claim 1, characterized in that, The grounding conductive connector includes a spherical solder body, which expands during reflow soldering to form a continuous grounding plane covering adjacent grounding conductive connectors.

3. The packaging structure according to claim 1, characterized in that, The power supply pin of the phase-locked loop circuit provides power to both the voltage-controlled oscillator and the phase-locked loop functional module.

4. The packaging structure according to claim 1, characterized in that, The pin level of the grounding conductive connection area of ​​the electromagnetic isolation barrier is low.

5. The packaging structure according to claim 2, characterized in that, The package substrate has a size of 3mm×3mm to 5mm×5mm; the spherical solder body spacing is 400μm to 500μm to suppress parasitic coupling effects in the high-frequency band of 6.5GHz to 10GHz; and the spherical solder body diameter is 250μm to 750μm.

6. The packaging structure according to claim 1, characterized in that, The electromagnetic isolation barrier between the first power supply area and the second power supply area comprises at least four columns of ground-grounded earth-shaped solder bodies.

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