Three-dimensional memory device and preparation method thereof, and electronic equipment

Abstract

The invention provides a three-dimensional memory device, a preparation method thereof and electronic equipment. The three-dimensional memory device comprises a substrate and a plurality of memory units, the storage unit comprises a read transistor and a write transistor; the read transistor is provided with a first read source-drain region, a read channel region and a second read source-drain region which extend along a first horizontal direction, the write transistor is provided with a first write source-drain region, a write channel region and a second write source-drain region which extend along an L shape, and the second write source-drain region serves as a storage grid of the read transistor and is connected with the read source-drain region. The three-dimensional stacking technology is introduced, the storage units are stacked in the vertical direction to improve the overall density of the memory, meanwhile, the indium gallium zinc oxide with the wide-band-gap characteristic is used as a channel material to reduce transistor leakage current, and therefore the data retention time is prolonged, the refresh rate is reduced, and device power consumption is reduced; the structure of the storage unit is optimized, capacitor preparation is omitted in combination with a 2T0C structure, preparation of more transistors is achieved in the same space, and the density of the storage unit is further improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor storage technology, and in particular to a three-dimensional storage device, a preparation method thereof, and an electronic device. Background Art

[0002] DRAM (Dynamic Random Access Memory) is the core memory technology of modern computer systems, primarily used for main memory and cache storage. Its high speed, low cost, and high density make it a key component for data storage in computer systems. DRAM's basic operating principle is to store each bit of data in a memory cell composed of transistors and capacitors. Transistors control the charge and discharge states of capacitors, thereby determining whether bits can be written or read; capacitors store charge, with the presence or absence of charge representing the bit value of the stored data. Silicon-based 1T1C (a memory cell consisting of one transistor and one capacitor) DRAM is currently the most common memory implementation, increasing storage density by continuously shrinking feature sizes. However, with advancements in process technology, traditional silicon-based DRAM is facing a series of physical limitations and manufacturing challenges.

[0003] As DRAM cell size shrinks, leakage current in traditional silicon-based 1T1C memory cells increases, shortening data retention and requiring more frequent refresh operations, which increases power consumption and reduces efficiency. Scaling feature sizes in traditional silicon-based 1T1C DRAM still relies heavily on high-precision photolithography, resulting in complex and costly manufacturing processes and making further increases in storage density difficult. Summary of the Invention

[0004] The purpose of the embodiments of the present disclosure is to provide a three-dimensional memory device and a manufacturing method thereof, and an electronic device, so as to solve the performance bottlenecks and process difficulties faced by DRAM in the prior art.

[0005] The embodiments of the present disclosure adopt the following technical solution: a three-dimensional memory device, comprising: a substrate and a plurality of memory cells arranged on the substrate, the memory cells being repeatedly arranged along a first horizontal direction, a second horizontal direction, and a vertical direction, the first horizontal direction and the second horizontal direction being parallel to the surface of the substrate, the first horizontal direction and the second horizontal direction being perpendicular, and the vertical direction being perpendicular to the surface of the substrate; each of the memory cells comprising a read transistor and a write transistor; the read transistor having a first read source-drain region, a read channel region, and a second read source-drain region extending along the first horizontal direction; the write transistor having a first write source-drain region, a write channel region, and a second write source-drain region extending along an L-shape, a line connecting the first write source-drain region and the write channel region being parallel to the first horizontal direction, a line connecting the write channel region and the second write source-drain region being parallel to the second horizontal direction, and the second write source-drain region being connected to the read source-drain region as a storage gate of the read transistor.

[0006] In some embodiments, it also includes: a plurality of read word lines and write word lines extending along the vertical direction; the read channel region includes a portion of the read word line and a first gate dielectric layer, a first semiconductor layer, and a second gate dielectric layer sequentially arranged around the read word line, the first gate dielectric layer and the first semiconductor layer are U-shaped, the second gate dielectric layer covers the bottom of the first semiconductor layer away from the first gate layer, and is connected to the second write source and drain region; the write channel region includes a portion of the write word line and a third gate dielectric layer and a second semiconductor layer sequentially arranged outside the write word line, the third gate dielectric layer and the second semiconductor layer are both L-shaped, and the side of the second semiconductor layer away from the third gate dielectric layer is respectively connected to the first write source and drain region and the second write source and drain region.

[0007] In some embodiments, all of the memory cells arranged in a column along a vertical direction share the same read word line and the write word line.

[0008] In some embodiments, it also includes: multiple bit lines extending along the second horizontal direction, the first read source drain region and the first write source drain region of the memory cell are both connected to the bit lines, and all the memory cells arranged in a row along the second horizontal direction share one bit line.

[0009] In some embodiments, two storage cells adjacent to each other along the second horizontal direction have mirror-symmetrical shapes with respect to an imaginary straight line along the first horizontal direction; two storage cells adjacent to each other along the first horizontal direction have mirror-symmetrical shapes with respect to an imaginary straight line along the second horizontal direction.

[0010] In some embodiments, the second read source and drain region is grounded.

[0011] In some embodiments, the first semiconductor layer and the second semiconductor layer are both metal oxides.

[0012] In some embodiments, the gaps between the memory cells are filled with a supporting material, which is insulating.

[0013] The embodiment of the present disclosure also provides a method comprising: providing a substrate; alternately preparing isolation layers and sacrificial layers on the surface of the substrate to obtain a stacked structure; etching a plurality of through-hole groups on the stacked structure and filling the through-hole groups with a first insulating material, each of the through-hole groups including a first through-hole and a second through-hole arranged along a first horizontal direction, two through-hole groups adjacent to each other along a second horizontal direction have mirror-symmetrical shapes with respect to an imaginary straight line along the first horizontal direction, two through-hole groups adjacent to each other along the first horizontal direction have mirror-symmetrical shapes with respect to an imaginary straight line along the second horizontal direction, the first horizontal direction and the second horizontal direction are parallel to the surface of the substrate, the first horizontal direction and the second horizontal direction are perpendicular, and the vertical direction is perpendicular to the surface of the substrate; etching a plurality of third through-holes on the stacked structure and filling the third through-holes with a second insulating material, the third through-holes being located between two first through-holes adjacent to each other along the second horizontal direction; etching a plurality of fourth through-holes on the stacked structure, the orthographic projection of the fourth through-hole on the substrate being equal to the orthographic projection of the two through-holes adjacent to each other along the second horizontal direction. The orthographic projections of all through holes in the group are connected; a gate dielectric material is deposited on the wall surface of the fourth through hole, and the fourth through hole is filled with the second insulating material; a plurality of fifth through holes are etched on the stacked structure, the fifth through hole is located between two adjacent through hole groups along the second horizontal direction, the orthographic projection of the fifth through hole on the substrate is connected to the orthographic projection of the third through hole, and does not overlap with the orthographic projection of the fourth through hole; the gate dielectric material and the second insulating material in the fourth through hole are etched, and the gate dielectric material on the wall surface of the fourth through hole along the second horizontal direction is retained to form a second gate dielectric layer; semiconductor material and gate dielectric material are sequentially deposited on the exposed surface of the current stacked structure, and the fourth through hole and the fifth through hole are filled with conductive material; a plurality of sixth through holes are etched on the stacked structure, the sixth through holes extending along the first horizontal direction and used for deep trench isolation of the fourth through hole and the fifth through hole; the second insulating material and the isolation layer are removed; the exposed semiconductor material and gate dielectric material are removed; insulating material is filled for isolation, and chemical mechanical polishing is performed.

[0014] An embodiment of the present disclosure further provides an electronic device, comprising at least the three-dimensional storage device as described above.

[0015] The beneficial effects of the embodiments of the present disclosure are as follows: introducing three-dimensional stacking technology to stack memory cells vertically to improve the overall density of the memory, while using wide-bandgap indium gallium zinc oxide as a channel material to reduce transistor leakage current, thereby extending data retention time, reducing refresh rate and lowering device power consumption; in addition, the structure of the memory cell is optimized, and the capacitor preparation is omitted in combination with the 2T0C structure, so that more transistors can be prepared in the same space, further improving the density of DRAM memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 2 is a circuit schematic diagram of a 2T0C memory cell according to a first embodiment of the present disclosure;

[0018] Figure 2 A partially enlarged structural diagram of a three-dimensional memory device according to a first embodiment of the present disclosure;

[0019] Figure 3 Flowchart of a method for preparing a three-dimensional memory device according to a second embodiment of the present disclosure;

[0020] Figures 4 to 16 FIG. 1 is a schematic diagram of a process for forming a three-dimensional memory device in the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below in conjunction with the drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this document.

[0022] DRAM (Dynamic Random Access Memory) is the core memory technology of modern computer systems, primarily used for main memory and cache storage. Its high speed, low cost, and high density make it a key component for data storage in computer systems. DRAM's basic operating principle is to store each bit of data in a memory cell composed of transistors and capacitors. Transistors control the charge and discharge states of capacitors, thereby determining whether bits can be written or read; capacitors store charge, with the presence or absence of charge representing the bit value of the stored data. Silicon-based 1T1C (a memory cell consisting of one transistor and one capacitor) DRAM is currently the most common memory implementation, increasing storage density by continuously shrinking feature sizes. However, with advancements in process technology, traditional silicon-based DRAM is facing a series of physical limitations and manufacturing challenges.

[0023] As DRAM cell size shrinks, leakage current in traditional silicon-based 1T1C memory cells increases, shortening data retention and requiring more frequent refresh operations, which increases power consumption and reduces efficiency. Scaling feature sizes in traditional silicon-based 1T1C DRAM still relies heavily on high-precision photolithography, resulting in complex and costly manufacturing processes and making further increases in storage density difficult.

[0024] In order to solve the above problems, the first embodiment of the present disclosure provides a three-dimensional memory device, which utilizes a 2T0C memory cell structure and combines a stackable vertical design to achieve a density increase of the memory cell. The implementation principle diagram is shown in FIG. Figure 1 As shown, a write transistor Wtr and a read transistor Rtr are mainly used; wherein the source end of the write transistor is connected to the gate end of the read transistor, that is, Figure 1 The design operates by applying a high level to the WWL terminal of the write transistor to turn on the write transistor. At this time, the WBL terminal of the write transistor is high, charging the SN point of the read transistor. Signal reading is performed by applying a high level to the RBL terminal of the read transistor. If the SN point is already charged, the current signal can be read. If the SN point is not charged, there is no current in the RBL terminal.

[0025] Figure 2 FIG. 1 shows a partially enlarged structural diagram of the three-dimensional memory device of this embodiment. Figure 2 As shown, the three-dimensional memory device includes a substrate (not shown in the figure) and a plurality of memory cells (such as Figure 2 , the memory cells are repeatedly arranged along the first horizontal direction, the second horizontal direction, and the vertical direction. The first horizontal direction X and the second horizontal direction Y are parallel to the surface of the substrate, the first horizontal direction X and the second horizontal direction Y are perpendicular to each other, and the vertical direction Z is perpendicular to the surface of the substrate.

[0026] In this embodiment, each memory cell includes a read transistor 10 and a write transistor 20. The read transistor 10 has a first read source-drain region 11, a read channel region 12, and a second read source-drain region 13 extending along a first horizontal direction. The write transistor 20 has a first write source-drain region 21, a write channel region 22, and a second write source-drain region 23 extending along an L-shape. Figure 2 As shown, the connection line between the first write source and drain region 21 and the write channel region 22 is parallel to the first horizontal direction X, the connection line between the write channel region 22 and the second write source and drain region 23 is parallel to the second horizontal direction Y, and the second write source and drain region 23 is connected to the read source and drain region 12 as the storage gate of the read transistor 10.

[0027] In this embodiment, the memory device further includes a plurality of read word lines RWL and write word lines WWL extending along the vertical direction Z. The read word lines RWL and the write word lines WWL do not overlap and are used to perform gate control operations on the read transistor 10 and the write transistor 20, respectively. The read channel region 12 includes a portion of the read word line RWL and a first gate dielectric layer 121 (corresponding to the gate dielectric layer 121) sequentially arranged around the read word line RWL. Figure 2 The yellow layer adjacent to the RWL), the first semiconductor layer 122 (corresponding to Figure 2 The orange-yellow layer surrounding the RWL) and the second gate dielectric layer 123 (corresponding to Figure 2 The first gate dielectric layer 121 and the first semiconductor layer 122 are U-shaped. The second gate dielectric layer 123 covers the bottom of the first semiconductor layer 122 away from the first gate dielectric layer 121 and is connected to the second write source and drain region 23 to form a U-shaped structure. Figure 2 The U-shaped channel region shown; the write channel region 22 includes a portion of the write word line WWL and a third gate dielectric layer 221 (corresponding to the outer side of the write word line WWL) sequentially arranged Figure 2 yellow layer adjacent to the WWL) and the second semiconductor layer 222 (corresponding to Figure 2 The third gate dielectric layer 221 and the second semiconductor layer 222 are both L-shaped, and the side of the second semiconductor layer 222 away from the third gate dielectric layer 221 is connected to the first write source drain region 21 and the second write source drain region 23, respectively, forming a Figure 2 The L-shaped channel region is shown.

[0028] It should be noted that the second write source-drain region 23 in this embodiment also serves as the storage gate of the read transistor 10, that is, it serves as the data storage node SN when writing data, and combines the stored voltage level to implement conduction control of the read transistor 10 when reading data. At the same time, the read channel region of the read transistor 10 in this embodiment is further provided with a read word line RWL to achieve dual gate control of the first semiconductor layer in the read channel region. The first semiconductor layer is designed to surround the read word line RWL, which can achieve faster channel formation speed when controlling the read transistor, improve the transistor conduction rate, and achieve better storage efficiency.

[0029] like Figure 2 As shown, combined with the vertical arrangement of the read word line RWL and the write word line WWL, the memory cells in this embodiment that are arranged in columns along the vertical direction share the same read word line RWL and write word line WWL, that is, in the memory cells in the same column, all read transistors share a read word line RWL, and all write transistors share a write word line WWL. In the actual control process, it is also necessary to cooperate with the design of the bit line BL to achieve read and write control of a specific memory cell. The bit line BL in this embodiment extends along the second horizontal direction, and is simultaneously connected to the first read source and drain region 11 and the first write source and drain region 12 of the memory cell, which is equivalent to the read transistor and the write transistor sharing the same bit line BL, thereby simplifying the memory cell structure. The second read source and drain region 13 is grounded, and it can achieve grounding operation in any way, which is not limited in this embodiment. It can be achieved by, for example, Figure 2 It should be noted that all memory cells arranged in a row along the second horizontal direction share one bit line BL.

[0030] In some embodiments, two storage cells adjacent to each other along the second horizontal direction have mirror-symmetrical shapes about an imaginary straight line along the first horizontal direction, and two storage cells adjacent to each other along the first horizontal direction have mirror-symmetrical shapes about an imaginary straight line along the second horizontal direction. The purpose of doing this is to facilitate the simplification of the process during the preparation process. In actual design, the specific storage cell shape can be set according to needs, and this embodiment does not impose specific restrictions.

[0031] In this embodiment, the first semiconductor layer 122 and the second semiconductor layer 222 can both be made of metal oxide semiconductor materials, including but not limited to indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). Their wide bandgap properties are utilized to reduce transistor leakage current, thereby extending the data retention time of the memory cell, reducing reliance on frequent refresh operations, and reducing overall power consumption. The first read source and drain region 11, the second read source and drain region 13, the first write source and drain region 21, the second write source and drain region 23, the bit line BL, the read word line RWL, and the write word line WWL are all made of conductive materials. Typically, the materials for these layers can each independently be a stack of one or more layers of titanium nitride, tungsten, indium zinc oxide, or other conductive materials. In actual fabrication, different materials can be selected based on different functions. For example, indium zinc oxide (IZO) can be used as the material for the word line and bit line, and titanium nitride (TiN) can be used for the source and drain. The first gate dielectric layer 121, the second gate dielectric layer 123 and the third gate dielectric layer 221 are mainly prepared by using insulating materials, especially dielectric materials with high dielectric constants (High-K materials). The use of High-K materials for gate dielectric materials can further reduce the gate leakage current of the transistor and improve the performance of the transistor, including but not limited to silicon oxide SiO, aluminum oxide AlO x , Hafnium-based oxide HfO x It should be noted that when the materials of the above-mentioned layers are actually selected, a high etching selectivity ratio between the materials of adjacent layers should also be ensured to ensure the etching effect during the etching process of materials of different layers during the preparation process.

[0032] Corresponding to the gaps between adjacent storage cells, a supporting material is used to fill them in this embodiment. The supporting material should be insulating to ensure that crosstalk between storage cells is reduced as much as possible and to achieve isolation of each level inside the storage cell from the external environment.

[0033] This embodiment introduces three-dimensional stacking technology to stack memory cells vertically to improve the overall density of the memory. At the same time, it uses indium gallium zinc oxide with wide bandgap characteristics as the channel material to reduce transistor leakage current, thereby extending data retention time, reducing refresh rate and lowering device power consumption. In addition, the structure of the memory cell is optimized, and the capacitor preparation is omitted in combination with the 2T0C structure, so that more transistors can be prepared in the same space, further improving the density of DRAM memory cells.

[0034] The second embodiment of the present disclosure provides a method for manufacturing a three-dimensional memory device according to the first embodiment, and its flow chart is as follows: Figure 3 As shown, it mainly includes steps S1 to S13:

[0035] S1, providing a substrate.

[0036] The substrate is a base plate used to support the memory, and one or more film layers can be formed on the substrate. The type of substrate can be an insulator substrate, a semiconductor substrate, a conductor substrate, etc. Among them, the insulator substrate can include a glass substrate, a quartz substrate, a sapphire substrate, a zirconium oxide substrate, a resin substrate, etc. The semiconductor substrate can include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. The conductor substrate can include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. In some embodiments, the substrate can also be a flexible substrate, such as a polyimide (PI) substrate, a polyethylene terephthalate (PET) substrate, or a surface-treated polymer soft film substrate. In some embodiments, the substrate can also be called a wafer.

[0037] S2, alternately preparing isolation layers 100 and sacrificial layers 200 on the surface of the substrate to obtain a stacked structure.

[0038] In this embodiment, a stacked structure can be obtained by alternately depositing an isolation layer 100 and a sacrificial layer 200 on a substrate, and the memory is prepared by processing the stacked structure. Among them, the isolation layer 100 is used to isolate different memory cell layers, and the sacrificial layer 200 will be partially or completely sacrificed during the device preparation process to provide a basis for subsequent etching and preparation. This embodiment does not limit the method of preparing the isolation layer 100 and the sacrificial layer 200. The two can be deposited in the same way or in different ways. For example, the method of depositing materials includes but is not limited to sputtering, evaporation, chemical vapor deposition, atomic layer deposition, etc.

[0039] In this embodiment, the isolation layer 100 can be formed by depositing an isolation material (e.g., an insulating material), and the sacrificial layer 200 can be formed by depositing a material having an etching selectivity ratio with the material of the isolation layer 100. For example, the isolation layer 100 is made of silicon oxide, and the sacrificial layer 200 is made of titanium nitride, tungsten, indium zinc oxide, or other materials having conductive properties, so that the remaining portion of the sacrificial layer 200 can be directly used as a partial conductive layer of the memory cell. Figure 4 FIG. 1 shows a schematic diagram of the stack structure of this embodiment. In addition, a CMP stop layer can be deposited on the top layer of the stack structure (eg, Figure 4 The pink layer at the top of the graph is used to guide the stop position in the subsequent chemical mechanical polishing operation. It should be noted that Figure 4 The stacking numbers of isolation layers 100 and sacrificial layers 200 shown are for illustration only, and more can be stacked as needed, for example, hundreds of isolation layers 100 and hundreds of sacrificial layers 200 can be stacked alternately to meet the requirements of completing more memory cell preparation processes through the same process step.

[0040] S3 , etching a plurality of through-hole groups on the stacked structure and filling the through-hole groups with a first insulating material, wherein each through-hole group includes a first through-hole and a second through-hole arranged along a first horizontal direction.

[0041] The number of through-hole groups prepared in this embodiment is designed according to actual process conditions, and when the through-hole positions are determined, it is ensured that two through-hole groups adjacent to each other along the second horizontal direction have mirror-symmetrical shapes with respect to an imaginary straight line along the first horizontal direction, and two through-hole groups adjacent to each other along the first horizontal direction have mirror-symmetrical shapes with respect to an imaginary straight line along the second horizontal direction, such as Figure 5 As shown. In this embodiment, the first horizontal direction and the second horizontal direction are parallel to the surface of the substrate, the first horizontal direction and the second horizontal direction are perpendicular to the surface of the substrate, and the vertical direction is perpendicular to the surface of the substrate. It should be noted that during the execution of this step, deep trenches for isolation can also be simultaneously formed to achieve insulation between memory cells.

[0042] S4, etching a plurality of third through holes on the stack structure and filling the third through holes with a second insulating material.

[0043] The third through hole 330 of this embodiment is located between two adjacent first through holes 310 along the second horizontal direction. Figure 6 As shown, the second insulating material 420 is different from the first insulating material 410 , and the two may have different etching selectivities.

[0044] S5, etching a plurality of fourth through holes on the stacked structure.

[0045] The orthographic projection of the fourth through hole 340 on the substrate is connected to the orthographic projections of all through holes of the two adjacent through hole groups along the second horizontal direction, such as Figure 7 As shown, the fourth through hole 340 and the third through hole 330 are staggered in the second horizontal direction and are not directly connected to each other.

[0046] S6 , depositing a gate dielectric material on the wall surface of the fourth through hole, and filling the fourth through hole with the second insulating material 420 .

[0047] In fact, when the gate dielectric material 430 is deposited, the gate dielectric material 430 with the same thickness is grown on all exposed surfaces of the current stack structure, which can be achieved by atomic layer deposition (ALD). Figure 8 The subsequent filling of the second insulating material 420 needs to ensure that the second insulating material 420 fills the fourth through hole, as shown in FIG. Figure 9 The second insulating material 420 of this embodiment may be aluminum oxide Al2O3.

[0048] S7, etching a plurality of fifth through holes on the stack structure.

[0049] In this embodiment, the fifth through hole 350 is located between two adjacent through hole groups along the second horizontal direction. The orthographic projection of the fifth through hole 350 on the substrate is connected to the orthographic projection of the third through hole 330 and does not overlap with the orthographic projection of the fourth through hole 340. During actual etching, the stacked structure can be etched using a dry etching method to form the fifth through hole 350.

[0050] S8, etching the gate dielectric material and the second insulating material in the fourth through hole, leaving the gate dielectric material on the hole wall surface of the fourth through hole along the second horizontal direction, to form a second gate dielectric layer.

[0051] The gate dielectric material 430 and the second insulating material 420 in the fourth through hole 340 are removed by wet etching, and the gate dielectric material 430 on the hole wall surface along the second horizontal direction in the fourth through hole 340 is retained to form the second gate dielectric layer of the read transistor. Figure 10 shown.

[0052] S9, sequentially depositing a semiconductor material and a gate dielectric material on the exposed surface of the current stacked structure, and filling the fourth through hole and the fifth through hole with a conductive material.

[0053] Specifically, the semiconductor material 500 and the gate dielectric material 430 are grown on the exposed surface of the stacked structure based on the ALD method, mainly referring to the currently exposed sidewalls of the fourth through hole 340 and the fifth through hole 350, which are used to form the channel regions of the read transistor and the write transistor. The conductive material 600 filled at the end is used to prepare the read word line and the write word line, as shown in FIG. Figure 11 shown.

[0054] S10, etching a plurality of sixth through holes on the stack structure.

[0055] The sixth through hole 360 ​​of this embodiment extends along the first horizontal direction and is mainly used to perform deep trench isolation on the fourth through hole 340 and the fifth through hole 350 so that they can simultaneously form the channel portions of the read transistor or write transistor of adjacent different memory cells, such as Figure 12 As shown, the etching method of the sixth through hole 360 ​​can also be based on dry etching.

[0056] S11, removing the second insulating material and the isolation layer.

[0057] The second insulating material 420 filled in step S4 is completely removed by wet etching, and the protected portion of the semiconductor material 500 is exposed to facilitate subsequent operations, such as Figure 13 Then, the isolation layer 100 is removed, which can be completed by lateral etching, as shown in FIG. Figure 14 shown.

[0058] S12, removing the exposed semiconductor material and gate dielectric material.

[0059] After the second insulating material 420 is completely removed, the currently exposed semiconductor material 500 and gate dielectric material 430 are wet-etched to remove the exposed semiconductor material 500 and gate dielectric to form an L-shaped channel region of the write transistor, such as Figure 15 shown.

[0060] S13, filling with insulating material for isolation and performing chemical mechanical grinding.

[0061] Finally, the storage units are electrically isolated by filling with insulating materials, and the surface is smoothed by chemical mechanical grinding to form a Figure 16 The three-dimensional memory device shown.

[0062] It should be noted that the optional materials for each layer in this embodiment have been described in the first embodiment and are not limited here; the thickness of each layer during actual preparation can be set according to the actual device size requirements, process conditions and selected materials, and is not limited in this embodiment.

[0063] This embodiment introduces three-dimensional stacking technology to stack memory cells vertically to improve the overall density of the memory. In addition, the structure of the memory cell is optimized, and the capacitor preparation is omitted in combination with the 2T0C structure, so that more transistors can be prepared in the same space, further improving the density of the DRAM memory cell.

[0064] A third embodiment of the present disclosure provides an electronic device, which at least includes the three-dimensional memory device provided by the first embodiment of the present disclosure.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A three-dimensional memory device, characterized in that: include: A substrate and a plurality of memory cells arranged on the substrate, wherein the memory cells are repeatedly arranged along a first horizontal direction, a second horizontal direction, and a vertical direction, wherein the first horizontal direction and the second horizontal direction are parallel to a surface of the substrate, the first horizontal direction and the second horizontal direction are perpendicular to the surface of the substrate, and the vertical direction is perpendicular to the surface of the substrate; Each of the storage cells includes a read transistor and a write transistor; the read transistor has a first read source-drain region, a read channel region, and a second read source-drain region extending along the first horizontal direction; the write transistor has a first write source-drain region, a write channel region, and a second write source-drain region extending along an L-shape; a line connecting the first write source-drain region and the write channel region is parallel to the first horizontal direction, a line connecting the write channel region and the second write source-drain region is parallel to the second horizontal direction, and the second write source-drain region serves as a storage gate of the read transistor and is connected to the read source-drain region.

2. The three-dimensional memory device according to claim 1, wherein: Also includes: a plurality of read word lines and write word lines extending along the vertical direction; The read channel region includes a portion of the read word line and a first gate dielectric layer, a first semiconductor layer, and a second gate dielectric layer sequentially arranged around the read word line, wherein the first gate dielectric layer and the first semiconductor layer are U-shaped, and the second gate dielectric layer covers the bottom of the first semiconductor layer away from the first gate layer and is connected to the second write source and drain region; The write channel region includes a portion of the write word line and a third gate dielectric layer and a second semiconductor layer sequentially arranged on the outside of the write word line, the third gate dielectric layer and the second semiconductor layer are both L-shaped, and the side of the second semiconductor layer away from the third gate dielectric layer is respectively connected to the first write source and drain region and the second write source and drain region.

3. The three-dimensional memory device according to claim 2, wherein: All the memory cells arranged in a column along the vertical direction share the same read word line and the write word line.

4. The three-dimensional memory device according to claim 1, wherein: Also includes: A plurality of bit lines extend along the second horizontal direction, the first read source drain region and the first write source drain region of the memory cells are connected to the bit lines, and all the memory cells arranged in a row along the second horizontal direction share one bit line.

5. The three-dimensional memory device according to claim 1, wherein: Two storage cells adjacent to each other along the second horizontal direction have mirror-symmetrical shapes with respect to an imaginary straight line along the first horizontal direction; Two memory cells adjacent to each other along the first horizontal direction have mirror-symmetrical shapes with respect to an imaginary straight line along the second horizontal direction.

6. The three-dimensional memory device according to claim 1, wherein: The second read source and drain region is grounded.

7. The three-dimensional memory device according to claim 1, wherein: The first semiconductor layer and the second semiconductor layer are both metal oxides.

8. The three-dimensional memory device according to any one of claims 1 to 7, characterized in that: The gaps between the memory cells are filled with a supporting material, which is insulating.

9. A method for preparing a three-dimensional memory device according to any one of claims 1 to 8, characterized in that: include: providing a substrate; Alternately preparing isolation layers and sacrificial layers on the surface of the substrate to obtain a stacked structure; Etching a plurality of through-hole groups on the stacked structure and filling the through-hole groups with a first insulating material, each of the through-hole groups including a first through-hole and a second through-hole arranged along a first horizontal direction, two through-hole groups adjacent to each other along a second horizontal direction having mirror-symmetrical shapes with respect to an imaginary straight line along the first horizontal direction, and two through-hole groups adjacent to each other along the first horizontal direction having mirror-symmetrical shapes with respect to an imaginary straight line along the second horizontal direction, the first horizontal direction and the second horizontal direction being parallel to a surface of the substrate, the first horizontal direction and the second horizontal direction being perpendicular, and the vertical direction being perpendicular to the surface of the substrate; Etching a plurality of third through holes on the stacked structure and filling the third through holes with a second insulating material, wherein the third through holes are located between two adjacent first through holes along the second horizontal direction; Etching a plurality of fourth through holes on the stacked structure, wherein the orthographic projections of the fourth through holes on the substrate are connected to the orthographic projections of all through holes of two adjacent through hole groups along the second horizontal direction; depositing a gate dielectric material on the wall surface of the fourth through hole, and filling the fourth through hole with the second insulating material; Etching a plurality of fifth through holes on the stacked structure, wherein the fifth through holes are located between two adjacent through hole groups along the second horizontal direction, and an orthographic projection of the fifth through hole on the substrate is connected to an orthographic projection of the third through hole and does not overlap with an orthographic projection of the fourth through hole; Etching the gate dielectric material and the second insulating material in the fourth through hole to retain the gate dielectric material on the hole wall surface of the fourth through hole along the second horizontal direction to form a second gate dielectric layer; Depositing a semiconductor material and a gate dielectric material in sequence on the exposed surface of the current stack structure, and filling the fourth through hole and the fifth through hole with a conductive material; Etching a plurality of sixth through holes on the stacked structure, wherein the sixth through holes extend along the first horizontal direction and are used to perform deep trench isolation on the fourth through hole and the fifth through hole; removing the second insulating material and the isolation layer; Removing the exposed semiconductor material and gate dielectric material; Fill with insulating material for isolation and perform chemical mechanical grinding.

10. An electronic device, characterized in that: At least comprising the three-dimensional memory device according to any one of claims 1 to 8.

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