Three-dimensional memory device and preparation method thereof, and electronic equipment
Through the design and material selection of three-dimensional memory devices, the leakage current and process complexity of traditional silicon-based DRAMs in the reduction process are solved, and high-density and low-power memory devices are optimized and stable.
Patent Information
- Application Number
- CN202510620763.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-14
- Publication Date
- 2025-08-29
AI Technical Summary
In the process of shrinking, traditional silicon-based DRAM memory cells face problems such as increased leakage current, shortened data retention time, complex manufacturing process and high cost, making it difficult to further improve the storage density.
Using a three-dimensional memory device structure, by alternately stacking isolation layers and memory cell layers on the substrate, combining the surrounding gate transistor structure and vertical bit line design, a wide bandgap material such as indium gallium zinc oxide is used as channel material, simplifying the process flow and optimizing the memory cell structure.
It improves storage density, extends data retention time, reduces power consumption, simplifies manufacturing processes, solves the problem of difficulty in reading capacitor signals of underlying devices, and improves the performance and stability of memory devices.
Smart Images
Figure CN120568754A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor storage technology, and in particular to a three-dimensional storage device, a preparation method thereof, and an electronic device. Background Art
[0002] DRAM (Dynamic Random Access Memory) is the core memory technology of modern computer systems, primarily used for main memory and cache storage. Its high speed, low cost, and high density make it a key component for data storage in computer systems. DRAM's basic operating principle is to store each bit of data in a memory cell composed of transistors and capacitors. Transistors control the charge and discharge states of capacitors, thereby determining whether bits can be written or read; capacitors store charge, with the presence or absence of charge representing the bit value of the stored data. Silicon-based 1T1C (a memory cell consisting of one transistor and one capacitor) DRAM is currently the most common memory implementation, increasing storage density by continuously shrinking feature sizes. However, with advancements in process technology, traditional silicon-based DRAM is facing a series of physical limitations and manufacturing challenges.
[0003] As DRAM cell size shrinks, leakage current in traditional silicon-based 1T1C memory cells increases, shortening data retention and requiring more frequent refresh operations, which increases power consumption and reduces efficiency. Scaling feature sizes in traditional silicon-based 1T1C DRAM still relies heavily on high-precision photolithography, resulting in complex and costly manufacturing processes and making further increases in storage density difficult. Summary of the Invention
[0004] The object of the present invention is to provide a three-dimensional memory device and a method for manufacturing the same, and an electronic device to solve the problems existing in the prior art;
[0005] The present invention provides a three-dimensional memory device, which includes a substrate, an isolation layer and a memory cell layer;
[0006] Along the vertical direction, a plurality of isolation layers and memory cell layers are alternately stacked on the substrate;
[0007] Each of the storage unit layers includes a plurality of storage unit groups;
[0008] The memory cell group includes a plurality of memory cells sequentially arranged along a first horizontal direction, and a common word line extending along the first horizontal direction;
[0009] The storage unit includes a transistor and a capacitor;
[0010] The transistor includes a first electrode, a second electrode, a gate, and a channel layer, wherein the first electrode and the second electrode are located at both ends of the channel layer, the gate is arranged around the channel layer, and a gate dielectric layer is arranged between the gate and the channel layer, and the gates of the transistors located in the same memory cell group are all electrically connected to the word line;
[0011] A first electrode of the transistor is electrically connected to the capacitor, and a second electrode of the transistor is connected to the bit line.
[0012] A method for preparing the three-dimensional memory device as described above, comprising:
[0013] providing a substrate;
[0014] Alternately preparing isolation layers and metal layers on the surface of the substrate to obtain a stacked structure;
[0015] Etching the stacked structure along a vertical direction to form a plurality of groups of first through holes and second through holes;
[0016] Laterally etching the metal layer to form a lateral channel between the first through hole and the second through hole in the same group;
[0017] Depositing a metal material on the exposed surface of the current stack structure to form a first metal material layer;
[0018] depositing a gate dielectric on the exposed surface of the first metal material layer to form a first gate dielectric layer;
[0019] depositing a semiconductor material on the exposed surface of the first gate dielectric layer to form a semiconductor material layer;
[0020] Etching the semiconductor material layer, retaining the semiconductor material in the lateral channel during the etching process to form a channel layer of the transistor;
[0021] depositing an isolation material on the exposed surface of the current stack structure to form a first isolation material layer;
[0022] Etching the first isolation material layer to retain the first isolation material in the lateral channel;
[0023] Wet-etching the first gate dielectric layer to retain the gate dielectric material in the lateral channel to form a gate dielectric layer of the transistor;
[0024] Wet-etching the first metal layer to retain the metal material in the lateral channel to form a gate of the transistor;
[0025] depositing an isolation material on the exposed surface of the current stack structure to form a second isolation material layer;
[0026] wet-etching the second isolation material layer to retain the second isolation material in the lateral channel;
[0027] depositing a metal material on the exposed surface of the current stacked structure to form a second metal material layer;
[0028] wet-etching the second metal material layer to retain the metal material in the lateral channel;
[0029] depositing a gate dielectric material on the exposed surface of the current stack structure to form a second gate dielectric material layer;
[0030] Filling the first through hole and the second through hole with metal material, and grinding the upper surface of the stacked structure to expose the uppermost isolation layer;
[0031] Perform deep trench isolation and fill with isolation material.
[0032] An electronic device comprises the three-dimensional memory device described above.
[0033] Beneficial effects:
[0034] By introducing three-dimensional stacking technology, memory cells are stacked vertically to increase the overall density of the memory, and the structure of the memory cells is optimized, a vertical bit line design is used to solve the problem of difficulty in reading the capacitance signal of the bottom device when the number of stacked layers is large. At the same time, the gate-around transistor structure is combined to enhance the gate hole capability, improve the performance of the transistor device, and achieve performance optimization and stability improvement of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0036] Figure 1 A partially enlarged schematic diagram of a three-dimensional memory device provided in a specific embodiment of the present invention;
[0037] Figures 2A-21B The preparation process diagram of the three-dimensional memory device provided by the specific embodiment of the present invention, each figure number includes two pictures A and B, where A is a schematic diagram of the overall structure and B is a partial enlarged picture, such as Figure 2A This is a schematic diagram of the overall structure of the stacking structure formed in step S1. Figure 2B and Figure 2A A partial enlarged view of DETAILED DESCRIPTION
[0038] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0039] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction, and therefore should not be understood as limiting the present invention.
[0040] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a communication between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.
[0041] like Figure 1 As shown, this embodiment provides a three-dimensional memory device, which includes a substrate, an isolation layer, and a memory cell layer.
[0042] Along the vertical direction, a plurality of isolation layers and memory cell layers are alternately stacked on the substrate.
[0043] Each memory cell layer includes a plurality of memory cell groups. The memory cell groups include a plurality of memory cells sequentially arranged along a first horizontal direction and a common word line extending along the first horizontal direction.
[0044] A memory cell includes a transistor and a capacitor.
[0045] The transistor includes a first electrode, a second electrode, a gate and a channel layer.
[0046] The first electrode and the second electrode are located at two ends of the gate, and an isolation material is provided between the first electrode, the second electrode and the gate.
[0047] The gate is arranged around the channel layer, and a gate dielectric layer is arranged between the gate and the channel layer. The gates of the transistors in the same memory cell group are all electrically connected to the word line.
[0048] A first electrode of the transistor is electrically connected to the capacitor, and a second electrode of the transistor is connected to the bit line.
[0049] Specifically, the capacitor includes a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode.
[0050] The first capacitor electrode is a columnar structure that vertically penetrates all memory cell layers and isolation layers between adjacent memory cell layers.
[0051] The outer surface of the first capacitor electrode is covered with a capacitor dielectric layer, and the outer surface of the capacitor dielectric layer is surrounded by a plurality of circles of second capacitor electrodes.
[0052] Adjacent second capacitor electrodes are separated by an isolation layer, and the second capacitor electrodes are electrically connected to the first electrode of the transistor located on the same layer. In actual manufacturing, the first electrode of the transistor can directly serve as the second capacitor electrode. Therefore, the first electrode and the second capacitor electrode are not clearly distinguished in the drawings.
[0053] The bit line is a common bit line, and the common bit line is a columnar structure that vertically passes through all memory cell layers and isolation layers between adjacent memory cell layers;
[0054] Second electrodes of all transistors in all memory cell layers at the same position in the horizontal direction are connected to a common word line.
[0055] The above-mentioned first electrode, second electrode, gate, first capacitor electrode, second capacitor electrode, common word line and common bit line are made of conductive materials. Under normal circumstances, the preparation materials of the above-mentioned layers can be independently a stack of one or more material layers of titanium nitride, tungsten, indium zinc oxide, or other materials with conductive properties. In actual preparation, different materials can be selected according to different functions. For example, indium zinc oxide IZO is used as the preparation material of the gate, and titanium nitride TiN is used to prepare the common bit line and source and drain. The channel layer is prepared by using semiconductor materials. This embodiment mainly uses metal oxide semiconductor materials, including but not limited to indium gallium zinc oxide IGZO materials, indium tin zinc oxide ITZO materials, etc., and uses its wide bandgap characteristics to reduce the leakage current of the transistor, thereby extending the data retention time of the storage unit, reducing dependence on frequent refresh operations, and reducing overall power consumption. For insulating layers such as isolation layers, gate dielectric layers, protective layers, and capacitor dielectric layers in capacitors, they are mainly prepared by using insulating materials, including but not limited to silicon oxide SiO, aluminum oxide AlO x , Hafnium-based oxide HfO x It should be noted that for gate dielectric materials and capacitor dielectric materials, dielectric materials with high dielectric constants (High-K materials) can be mainly selected. The use of High-K materials for gate dielectric materials can further reduce the gate leakage current of transistors and improve transistor performance. The use of High-K materials for capacitor dielectric materials can increase the capacitance and slow down the discharge of capacitors. It should be noted that when selecting the materials of the above-mentioned layers, a high etching selectivity ratio between the materials of adjacent layers should also be ensured to ensure the etching effect during the etching process of materials of different layers during the preparation process.
[0056] In summary, the three-dimensional memory device provided in this embodiment has the following advantages:
[0057] Using three-dimensional stacking technology, memory cells are stacked vertically to increase the overall density of the memory. At the same time, wide-bandgap indium gallium zinc oxide is used as the channel material to reduce transistor leakage current, thereby extending data retention time, reducing refresh rate and lowering device power consumption. In addition, the structure of the memory cell is optimized, and a vertical bit line design is used to solve the problem of difficulty in reading the capacitance signal of the bottom device when the number of stacked layers is large. At the same time, the gate-around transistor structure is combined to enhance the gate hole capability, improve the performance of the transistor device, and achieve performance optimization and stability improvement of the memory device.
[0058] In this embodiment, the memory cell can be a combination of one transistor, one capacitor, and one common bit line. Alternatively, the memory cell can be a combination of two transistors, two capacitors, and one common bit line. In this embodiment, the two transistors share one common bit line. The specific structure is shown below:
[0059] The memory cell includes a first transistor, a second transistor, a first capacitor, a second capacitor and a common bit line.
[0060] The first transistor and the second transistor are located at two sides of a common bit line, and one electrode of the first transistor and the second transistor are both connected to the common bit line.
[0061] The first capacitor is located outside the first transistor, and the other electrode of the first transistor is connected to the first capacitor. The second capacitor is located outside the second transistor, and the other electrode of the second transistor is connected to the second capacitor.
[0062] Reference Figures 2A to 19B In this embodiment, a method for preparing the three-dimensional memory device as described above is also provided, which includes the following steps:
[0063] S1, providing a substrate;
[0064] S2, alternately preparing an isolation layer 1 and a sacrificial layer 2 on the surface of the substrate to obtain a stacked structure, Figure 2A and Figure 2B The stacking structure formed in this step is shown;
[0065] In step S2 , both the isolation layer 1 and the sacrificial layer 2 can be made of insulating materials. In this case, two insulating materials are grown alternately. After etching a basic pattern, one of the materials is replaced with a metal by etching and growing.
[0066] In this embodiment, the sacrificial layer 2 is described by taking a metal material as an example, specifically as shown below:
[0067] In step S2, the thickness of the isolation layer 1 is 20 nm, the material of the isolation layer is silicon oxide, the thickness of the metal layer is 60 nm, and the material of the sacrificial layer 2 is titanium nitride, tungsten or indium zinc oxide or other materials with conductive properties.
[0068] S3, etching the stacked structure along the vertical direction to form multiple groups of first through holes 3 and second through holes 4, Figure 3A and Figure 3B shows a schematic diagram of the structure after etching through holes in the stacked structure;
[0069] In step S3 , the diameter of the first through hole is 100-500 nm, the diameter of the second through hole is 20-200 nm, and the distance between the first through hole and the second through hole is 20-200 nm.
[0070] S4, laterally etching the metal layer to form a transverse channel 5 between the first through hole and the second through hole in the same group, Figure 4A and Figure 4B A schematic diagram of the structure forming the transverse channel is shown;
[0071] During the lateral etching of the metal layer, the first through-hole and the second through-hole are connected, forming a lateral channel between the first through-hole and the second through-hole. The lateral channel provides space for the subsequent fabrication of the transistor communication structure. During the etching process, it is necessary to ensure that the metal layer between adjacent memory cells in the horizontal direction is not etched. This portion of the metal layer forms a common word line extending in the horizontal direction.
[0072] S5, depositing a metal material on the exposed surface of the current stacked structure to form a first metal material layer 6, Figure 5A and Figure 5B is a schematic diagram of the structure after the first metal material layer is formed;
[0073] The first metal material is titanium nitride, and the thickness of the first metal material layer is 15 nm. The first metal material layer is grown by ALD (atomic layer deposition) to ensure that the thickness of the grown first metal material layer is uniform.
[0074] S6, depositing a gate dielectric on the exposed surface of the first metal material layer to form a first gate dielectric layer 7, Figure 6A and Figure 6B Schematic diagram of the structure after gate dielectric deposition;
[0075] The gate dielectric material is hafnium-based oxide HfO x The thickness of the first gate dielectric layer is 8 nm, and the growth method of the gate dielectric material can also be achieved based on ALD.
[0076] S7, depositing a semiconductor material on the exposed surface of the first gate dielectric layer 7 to form a semiconductor material layer 8, Figure 7A and Figure 7B is a schematic diagram of the structure for depositing semiconductor materials;
[0077] IGZO is selected as the semiconductor material. The thickness of the semiconductor layer is 15nm. It should be noted that when actually growing IGZO, the IGZO material should be included to fill the lateral channel.
[0078] S8, etching the semiconductor material layer, retaining the semiconductor material in the lateral channel during the etching process to form a channel layer of the transistor, Figure 8A and Figure 8BThis is a schematic diagram of the structure after wet etching of semiconductor materials;
[0079] The semiconductor material layer is etched by wet etching, and only the semiconductor material in the lateral channel is retained during etching, while the rest is etched away, so that the remaining semiconductor material in the lateral channel forms the channel layer of the transistor.
[0080] S9, depositing an isolation material on the exposed surface of the current stack structure to form a first isolation material layer 9, Figure 9A and Figure 9B is a schematic diagram of the structure after deposition of isolation material;
[0081] The isolation material is deposited based on ALD. The isolation material is Al2O3 and the thickness of the isolation material is 15 nm.
[0082] S10, etching the first isolation material layer to retain the first isolation material in the lateral channel, Figure 10A and Figure 10B A schematic diagram of the structure for etching away the isolation material layer;
[0083] The first isolation material is etched by wet etching, and only the channel material in the transverse channel is retained during etching, while the rest is etched away.
[0084] S11, wet etching the first gate dielectric layer to retain the gate dielectric material in the lateral channel to form the gate dielectric layer of the transistor, Figure 11A and Figure 11B It is a structural schematic diagram of wet etching the gate dielectric layer;
[0085] The gate dielectric layer is wet-etched to retain the gate dielectric material in the lateral channel as the gate dielectric layer of the transistor, and the remaining portion is etched away.
[0086] S12, wet etching the first metal layer to retain the metal material in the lateral channel to form the gate of the transistor, Figure 12A and Figure 12B This is a schematic diagram of the structure after the metal layer is wet-etched;
[0087] The first metal layer is wet-etched to retain only a portion of metal material surrounding the channel in the lateral channel as a gate layer.
[0088] S13, depositing an isolation material on the exposed surface of the current stack structure to form a second isolation material layer 10, Figure 13A and Figure 13B is a schematic diagram of the structure after deposition of isolation material;
[0089] The isolation material is deposited based on ALD, the isolation material is Al2O3, and the thickness of the isolation material is 30nm.
[0090] S14, wet-etching the second isolation material layer to retain the second isolation material in the lateral channel, Figure 14A and Figure 14B This is a schematic diagram of the structure after wet etching of the isolation material layer;
[0091] S15, depositing metal material on the exposed surface of the current stacked structure to form a second metal material layer 11, Figure 15A and Figure 15B Schematic diagram of the structure after depositing metal material;
[0092] The metal material is deposited based on ALD, and the thickness of the metal material is 60 nm.
[0093] S16, wet etching the second metal material layer to retain the metal material in the lateral channel, Figure 16A and Figure 16B Schematic diagram of the structure after etching away the metal material layer;
[0094] The metal material in the first through hole is etched away by wet etching.
[0095] S17, depositing a gate dielectric material on the exposed surface of the current stack structure to form a second gate dielectric material layer 12, Figure 17A and Figure 17B is a schematic diagram of the structure after depositing the gate dielectric material;
[0096] The gate dielectric material is deposited based on ALD. The gate dielectric material is hafnium-based oxide HfO x , with a thickness of 8nm, and the second gate dielectric is used to form a dielectric layer of the capacitor.
[0097] S18, filling the first through hole with metal material and grinding the upper surface of the stacked structure to expose the uppermost isolation layer, Figure 18A and 18B It is a schematic diagram of the structure after filling with metal material;
[0098] S19, after CMP polishing, deep trench isolation is performed and filled with isolation material. Figure 19A and Figure 19B For CMP grinding, Figure 20A and Figure 20B For deep trench isolation, Figure 21A and Figure 21B Schematic diagram of the structure filled with isolation material.
[0099] This embodiment introduces three-dimensional stacking technology to stack memory cells vertically to increase the overall density of the memory, meeting the needs of future high-density storage applications. It also simplifies the process flow and reduces the cost of memory device preparation. In addition, the memory cell structure is manufactured using lateral etching and thin film deposition technology, effectively avoiding high-precision photolithography and further simplifying the process flow. At the same time, wide-bandgap indium gallium zinc oxide is used as the channel material to reduce transistor leakage current, thereby extending data retention time, reducing refresh rate and device power consumption. In addition, the structure of the memory cell is optimized, and a vertical bit line design is used to solve the problem of difficulty in reading the capacitance signal of the bottom device when the number of stacked layers is large. At the same time, the gate-around transistor structure is combined to enhance the gate hole capability, improve transistor device performance, and achieve performance optimization and stability improvement of the memory device.
[0100] In this embodiment, an electronic device is also provided, which includes at least the three-dimensional storage device provided by the first embodiment of the present disclosure to achieve high-density, low-power data storage, thereby helping the overall stable and low-power operation of the electronic device.
[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A three-dimensional memory device, characterized in that: comprising a substrate, an isolation layer and a memory cell layer; Along the vertical direction, a plurality of isolation layers and memory cell layers are alternately stacked on the substrate; Each of the storage unit layers includes a plurality of storage unit groups; The memory cell group includes a plurality of memory cells sequentially arranged along a first horizontal direction, and a common word line extending along the first horizontal direction; The storage unit includes a transistor and a capacitor; The transistor includes a first electrode, a second electrode, a gate, and a channel layer, wherein the first electrode and the second electrode are located at both ends of the channel layer, the gate is arranged around the channel layer, and a gate dielectric layer is arranged between the gate and the channel layer, and the gates of the transistors located in the same memory cell group are all electrically connected to the word line; A first electrode of the transistor is electrically connected to the capacitor, and a second electrode of the transistor is connected to the bit line.
2. The three-dimensional memory device according to claim 1, wherein: The capacitor includes a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode; The first capacitor electrode is a columnar structure extending vertically through all memory cell layers and the isolation layers between adjacent memory cell layers; The outer surface of the first capacitor electrode is covered with a capacitor dielectric layer, and the outer surface of the capacitor dielectric layer is surrounded by a plurality of circles of second capacitor electrodes; Adjacent second capacitor electrodes are separated by an isolation layer, and the second capacitor electrodes are electrically connected to the first electrodes of the transistors located in the same layer.
3. The three-dimensional memory device according to claim 1, wherein: The bit line is a common bit line, and the common bit line is a columnar structure that vertically passes through all memory cell layers and isolation layers between adjacent memory cell layers; Second electrodes of all the transistors in all the memory cell layers that are located at the same position in the horizontal direction are connected to a common word line.
4. The three-dimensional memory device according to claim 3, wherein: The memory cell includes a first transistor, a second transistor, a first capacitor, a second capacitor and a common bit line; The first transistor and the second transistor are located on both sides of a common bit line, and one electrode of the first transistor and the second transistor are both connected to the common bit line; The first capacitor is located outside the first transistor, and the other electrode of the first transistor is connected to the first capacitor. The second capacitor is located outside the second transistor, and the other electrode of the second transistor is connected to the second capacitor.
5. A method for preparing a three-dimensional memory device according to any one of claims 1 to 4, characterized in that: include: providing a substrate; Alternately preparing isolation layers and isolation layers on the surface of the substrate to obtain a stacked structure; Etching the stacked structure along a vertical direction to form a plurality of groups of first through holes and second through holes; Laterally etching the isolation layer to form a lateral channel between the first through hole and the second through hole in the same group; Depositing a metal material on the exposed surface of the current stack structure to form a first metal material layer; depositing a gate dielectric on the exposed surface of the first metal material layer to form a first gate dielectric layer; depositing a semiconductor material on the exposed surface of the first gate dielectric layer to form a semiconductor material layer; Etching the semiconductor material layer, retaining the semiconductor material in the lateral channel during the etching process to form a channel layer of the transistor; depositing an isolation material on the exposed surface of the current stack structure to form a first isolation material layer; Etching the first isolation material layer to retain the first isolation material in the lateral channel; Wet-etching the first gate dielectric layer to retain the gate dielectric material in the lateral channel to form a gate dielectric layer of the transistor; Wet-etching the first metal layer to retain the metal material in the lateral channel to form a gate of the transistor; depositing an isolation material on the exposed surface of the current stack structure to form a second isolation material layer; wet-etching the second isolation material layer to retain the second isolation material in the lateral channel; depositing a metal material on the exposed surface of the current stacked structure to form a second metal material layer; wet-etching the second metal material layer to retain the metal material in the lateral channel; depositing a gate dielectric material on the exposed surface of the current stack structure to form a second gate dielectric material layer; Filling the first through hole and the second through hole with metal material, and grinding the upper surface of the stacked structure to expose the uppermost isolation layer; Perform deep trench isolation and fill with isolation material.
6. The method for preparing a three-dimensional memory device according to claim 5, wherein: The insulating layer and the isolation material include silicon oxide or aluminum oxide.
7. The method for preparing a three-dimensional memory device according to claim 5, wherein: The aperture of the first through hole is larger than the aperture of the second through hole.
8. The method for preparing a three-dimensional memory device according to claim 7, wherein: The diameter of the first through hole is 100-500 nm, the diameter of the second through hole is 20-200 nm, and the distance between the first through hole and the second through hole is 20-200 nm.
9. The method for preparing a three-dimensional memory device according to claim 5, wherein: The semiconductor material is a metal oxide semiconductor material.
10. An electronic device, characterized in that: The device comprises the three-dimensional memory device according to any one of claims 1 to 4.