Trench Schottky diode based on strip-type terminal and preparation method thereof

Abstract

The present invention relates to the field of semiconductor device technology, and in particular to a trench Schottky diode based on strip-type terminals and a method for preparing the same. The diode comprises a semiconductor substrate and multiple trench structures therein, a barrier metal layer, and electrodes; the trench structure comprises an outer terminal trench structure and an inner single-cell trench structure; the terminal trench structure comprises N terminal trenches, the innermost terminal trench width being greater than the single-cell trench width, 1≤N≤10; the spacing between the N terminal trenches gradually increases from the inside outward; the terminal trenches are strip-shaped; the single-cell trench structure comprises circular hole single-cell trenches arranged in an equilateral triangle array on the inner side, and an outer ring single-cell trench structure comprising circular hole single-cell trenches and elliptical hole single-cell trenches arranged alternately at equal intervals; the terminal trench structure and the single-cell trench structure comprise trenches, a gate oxide layer covering the inner walls of the trenches, and a polysilicon filling layer located on the surface of the gate oxide layer and filling the trenches. The diode has the advantages of uniformly distributing the electric field during reverse withstand voltage, reducing the risk of failure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a trench Schottky diode based on a stripe-type terminal and a preparation method thereof. Background Art

[0002] The Trench Schottky diode (TMBS) is a majority carrier device that utilizes the contact barrier between metal and semiconductor. By utilizing the charge coupling effect of the metal-oxide-semiconductor (MOS) structure, the electric field intensity distribution in the drift region between the MOS structures is changed, suppressing the peak electric field intensity at the surface of the Schottky barrier junction in the drift region, causing the peak electric field intensity to appear within the device body, thereby optimizing the device's forward and reverse electrical parameter characteristics. Because this diode has the characteristics of a lower forward voltage drop and faster speed than ordinary pn structure diodes, it has a wide range of applications in modern communications, ultra-high-speed devices, microwave circuits, switching power supplies, inverters, and drives.

[0003] In the design of TMBS products, there are two types of grooves. One is a large-area array of circular hole-type single-cell grooves arranged in the chip, and the other is the terminal groove at the outermost circle of the chip. In order to ensure the reverse breakdown characteristics of the product, it is necessary to keep the distance from each outermost circular hole groove to the terminal groove equal, that is, D1=D2. In order to ensure D1=D2, the existing design needs to design the terminal groove into an arc shape. Therefore, the unit cell of the existing technical solution is also a circular or regular polygonal groove, arranged in an equilateral triangle array, such as Figure 1 This structural design has the following disadvantages: (1) There are sharp corners at the intersection of the arc-shaped terminal grooves. This sharp corner position will cause electric field concentration when the device withstands reverse voltage, which is prone to thermal breakdown failure in terminal applications (see Figure 1 ). When reverse voltage is applied to TMBS products, the electric field will concentrate near the groove and will be more concentrated at the sharp corners. As the reverse voltage increases, the electric field concentration position will first break down. The high electric field intensity and high current density at this position will cause heat concentration and there will be a risk of chip burning and breakdown failure. (2) In the manufacture of TMBS product chips, the lithography window boundary of the contact hole lithography should be at the center of the terminal groove. If the lithography boundary deviates from the terminal groove, the chip will directly break down and lose its reverse cutoff function (such as Figure 2 (B in the middle). The arc-shaped terminal design increases the difficulty of the contact hole lithography process, requiring stricter contact hole lithography alignment accuracy and contact hole size control, which can easily affect product yield and increase costs. Summary of the Invention

[0004] In order to solve the above problems, the present invention provides a trench Schottky diode based on a strip-type terminal and a preparation method thereof.

[0005] The first object of the present invention is to provide a trench Schottky diode based on a stripe-type terminal, comprising a semiconductor substrate, a plurality of trench structures located within the semiconductor substrate, a barrier metal layer connecting the trench structures and an electrode on the surface of the semiconductor substrate; the trench structure comprises an outer terminal trench structure and an inner unit cell trench structure;

[0006] The terminal groove structure includes N terminal grooves, the width of the innermost terminal groove is greater than the width of the unit cell groove, 1≤N≤10; the spacing between the N terminal grooves gradually increases from the inside to the outside; the terminal grooves are strip-shaped;

[0007] The unit cell groove structure includes circular hole unit cell grooves distributed in an equilateral triangle array on the inner side, and an outer ring unit cell groove structure close to the innermost terminal groove; the outer ring unit cell groove structure is composed of circular hole unit cell grooves and elliptical hole unit cell grooves alternately arranged at equal intervals;

[0008] The terminal trench structure and the unit cell trench structure include a trench, a gate oxide layer covering the inner wall of the trench, and a polysilicon filling layer located on the surface of the gate oxide layer and filling the trench.

[0009] Preferably, the distances from the boundaries of the circular hole unit cell groove and the elliptical hole unit cell groove to the innermost terminal groove are D1 and D2 respectively; D1=D2.

[0010] Preferably, the value range of D1 and D2 is 0.2~20um.

[0011] Preferably, the width W of all the unit cell trenches in the unit cell trench structure is 单 Range: 0.1um≤W 单 ≤10um; the side length of the trench Schottky diode based on the strip-type terminal is 50mil≤L≤300mil.

[0012] Preferably, the innermost terminal groove has a width of 0.2-5 μm and a depth of 1-5 μm.

[0013] Preferably, the semiconductor substrate includes a base and an epitaxial layer, the trench structure is located in the epitaxial layer, and a Schottky barrier is formed at a portion where the barrier metal layer contacts the epitaxial layer.

[0014] A second object of the present invention is to provide a method for preparing a trench Schottky diode based on a stripe-type terminal, which is used to prepare a trench Schottky diode based on a stripe-type terminal, and specifically comprises the following steps:

[0015] S1. Providing a semiconductor substrate, growing a layer of silicon dioxide mask on the front of the semiconductor substrate;

[0016] S2. etching the silicon dioxide mask in the trench structure region to expose the semiconductor substrate;

[0017] S3. Etching the front surface of the semiconductor substrate to form a trench structure;

[0018] S4. removing the silicon dioxide mask and growing a gate oxide layer on the front surface of the semiconductor substrate and within the trench structure;

[0019] S5. Filling a polysilicon filling layer on the front surface of the semiconductor substrate and in the trench structure using a low-pressure chemical vapor deposition method; retaining the polysilicon filling layer filled in the trench structure and removing excess polysilicon on the surface;

[0020] S6. Growing a layer of silicon dioxide on the front surface of the semiconductor substrate using chemical vapor deposition; Etching the silicon dioxide and the gate oxide layer on the surface of the semiconductor substrate to form a barrier region window and expose the front surface of the semiconductor substrate; The boundary position of the barrier region window is set at the center of the cross section of the innermost terminal trench;

[0021] S7. Depositing a barrier metal layer on the front of the semiconductor substrate, the metal being titanium or nickel-platinum alloy;

[0022] S8. performing high temperature annealing to react the portion of the barrier metal layer in contact with the semiconductor substrate to form a Schottky barrier;

[0023] S9. Use evaporation or sputtering to deposit metal on the front surface of the semiconductor substrate to form a positive electrode, and deposit metal on the back surface of the semiconductor substrate to form a back electrode, wherein both the positive electrode and the back electrode are made of aluminum or silver.

[0024] Preferably, the etching in step S2 is performed by photolithography or dry etching; the step S3 is performed by dry etching, and the etching gas is at least one of chlorine, sulfur hexafluoride, and hydrogen bromide; the high-temperature annealing in step S8 is performed in a gas atmosphere of nitrogen with a purity of more than 99%, and the annealing temperature is 600~1000°C.

[0025] Preferably, the thickness of the silicon dioxide mask is 0.1-1 um; the gate oxide layer is silicon dioxide with a thickness of 0.1-1 um; and the thickness of the barrier metal layer is 0.01-1 um.

[0026] Compared with the prior art, the present invention can achieve the following beneficial effects:

[0027] The present invention proposes a new TMBS product design, designing the terminal grooves as long strips, and using alternating circular and elliptical grooves at the edge of the chip. This design not only ensures that all circular and elliptical hole single-cell grooves are equidistant from the innermost terminal groove, but also solves the problem of electric field concentration at the sharp corners of the arc-shaped terminals and the high difficulty of the contact hole photolithography process. In addition, the present invention designs the terminal grooves as strips, so that the electric field is evenly distributed in a direction perpendicular to the terminal grooves during reverse withstand voltage, avoiding electric field concentration at sharp corners and reducing the risk of failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic structural plan view of a trench Schottky diode provided by the prior art; the arrows in the figure indicate that the electric field distribution of the arc-shaped terminal is concentrated at the sharp corner.

[0029] Figure 2 This is a schematic diagram of the lithographic window boundary and contact hole lithographic bias of the contact hole of a trench Schottky diode under ideal conditions provided by the prior art; in the figure, A represents the lithographic window boundary of the contact hole under ideal conditions, and B represents the contact hole lithographic bias.

[0030] Figure 3 1 is a schematic top view of an overall trench Schottky diode structure based on a strip-type terminal provided according to an embodiment of the present invention.

[0031] Figure 4 It is a partially enlarged top view of a trench Schottky diode based on a strip-type terminal provided according to an embodiment of the present invention.

[0032] Figure 5 Schematic diagram of the electric field distribution of a trench Schottky diode based on a stripe-type terminal provided according to an embodiment of the present invention.

[0033] Figure 6 The diagram is a schematic diagram of the boundary of the terminal trench lithography window of the trench Schottky diode based on the stripe-type terminal provided in accordance with an embodiment of the present invention.

[0034] Figure 7 is a schematic cross-sectional view of a semiconductor substrate provided according to an embodiment of the present invention.

[0035] Figure 8 It is a schematic cross-sectional view of the etching trench structure provided in an embodiment of the present invention.

[0036] Figure 9 It is a schematic cross-sectional view after etching to form a barrier region window according to an embodiment of the present invention.

[0037] Figure 10 1 is a schematic overall cross-sectional view of a trench Schottky diode based on a stripe-type terminal provided according to an embodiment of the present invention.

[0038] Figure 11 This is a failure MAP scrap distribution diagram of trench Schottky diodes provided by the prior art.

[0039] Reference numerals:

[0040] 1. Circular hole unit cell groove;

[0041] 2. Elliptical hole unit cell groove;

[0042] 3. Innermost terminal groove;

[0043] 4. Positive electrode;

[0044] 5. Back electrode;

[0045] 6. Base;

[0046] 7. Epitaxial layer;

[0047] 8. Silicon dioxide mask;

[0048] 9. Gate oxide layer;

[0049] 10. Polysilicon filling layer;

[0050] 11. Barrier region window;

[0051] 12. Barrier metal layer;

[0052] 13. Schottky barrier. DETAILED DESCRIPTION

[0053] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, identical modules are denoted by identical reference numerals. In the case of identical reference numerals, their names and functions are also identical. Therefore, their detailed description will not be repeated.

[0054] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation of the present invention.

[0055] The present invention provides a trench Schottky diode based on a stripe-type terminal, comprising a semiconductor substrate, a plurality of trench structures located in the semiconductor substrate, a barrier metal layer connecting the trench structures and an electrode on the surface of the semiconductor substrate;

[0056] The groove structure includes an outer terminal groove structure and an inner unit cell groove structure;

[0057] The terminal groove structure includes N terminal grooves, wherein the width of the innermost terminal groove is greater than the width of the unit cell groove; 1≤N≤10; the spacing between the N terminal grooves gradually increases from the inside to the outside, and the spacing value range is 0.1~20um; the number of terminal grooves can be selected according to actual application; the greater the number of terminal grooves, the stronger the edge protection of the chip, but the utilization rate of the chip barrier area decreases, and in actual application, the number of terminal grooves generally does not exceed 10;

[0058] The innermost terminal groove width is 0.2~5um and the depth is 1~2.5um;

[0059] The single cell groove structure includes circular hole single cell grooves distributed in an equilateral triangle array on the inner side, and an outer ring single cell groove structure close to the innermost terminal groove; the outer ring single cell groove structure is composed of circular hole single cell grooves and elliptical hole single cell grooves arranged alternately at equal intervals, and the distances from the boundaries of the circular hole single cell groove and the elliptical hole single cell groove to the innermost terminal groove are D1 and D2 respectively, D1=D2, and the value range is 0.2~20um; the width W of all single cell grooves in the single cell groove structure is 单 Range: 0.1um≤W 单 ≤10um;

[0060] The side length of the trench Schottky diode based on the stripe type terminal is 50mil≤L≤300mil.

[0061] Figure 3-Figure 4 The schematic diagram of the overall and partial top view of the trench Schottky diode structure based on the strip-type terminal is shown. The trench Schottky diode structure based on the strip-type terminal is rectangular with a side length of 50 mil ≤ L ≤ 300 mil; it includes an outer terminal trench structure and an inner unit cell trench structure;

[0062] The unit cell groove structure includes circular hole unit cell grooves 1 distributed in an equilateral triangle array on the inner side, and an outer ring unit cell groove structure close to the innermost terminal groove 3; the outer ring unit cell groove structure is composed of circular hole unit cell grooves 1 and elliptical hole unit cell grooves 2 arranged alternately at equal intervals, the distance from the boundary of the circular hole unit cell groove 1 to the innermost terminal groove 3 is D1, and the distance from the boundary of the elliptical hole unit cell groove 2 to the innermost terminal groove 3 is D2, and D1=D2;

[0063] The terminal groove structure includes N terminal grooves, the width of the innermost terminal groove 3 is greater than the width of the unit cell groove; 1≤N≤10; the spacing between the N terminal grooves gradually increases from the inside to the outside.

[0064] Figure 5 The electric field distribution of the trench Schottky diode based on the stripe-type terminal is shown. It can be seen that the electric field distribution of the stripe-type terminal is uniform.

[0065] Example 1

[0066] This embodiment provides a trench Schottky diode based on a stripe-type terminal, comprising a semiconductor substrate, a plurality of trench structures located in the semiconductor substrate, a barrier metal layer connecting the trench structures and an electrode on the surface of the semiconductor substrate;

[0067] The groove structure includes an outer terminal groove structure and an inner unit cell groove structure;

[0068] The specific parameters include:

[0069] Wafer thickness 725um;

[0070] The side length design size is 130mil;

[0071] The semiconductor substrate includes a base and an epitaxial layer, the trench structure is located in the epitaxial layer, the doping type of the base is a P-doped base, the epitaxial layer is a P-doped epitaxial layer, and the epitaxial layer has a thickness of 6 μm;

[0072] The resistivity of the trench Schottky diode is 0.35 om·cm;

[0073] The width of all single-cell grooves (circular hole single-cell grooves and elliptical hole single-cell grooves) is 0.5um;

[0074] The distances from the boundary of the circular hole single cell groove and the elliptical hole single cell groove to the innermost terminal groove are D1 and D2, respectively, and D1=D2=1.5um;

[0075] The innermost terminal groove is 0.8um wide and 2.3um deep;

[0076] A method for preparing a trench Schottky diode based on a stripe terminal (see Figure 7-10 ), specifically including the following steps:

[0077] S1. Figure 7 As shown, a semiconductor substrate is provided, which includes a base 6 and an epitaxial layer 7 located on the surface of the base 6; a silicon dioxide mask 8 is grown on the surface of the epitaxial layer 7, and the growth method can adopt TEOS decomposition, thermal oxidation and other processes; the epitaxial layer 7 is a silicon-based epitaxial wafer; the silicon dioxide mask 8 has a thickness ranging from 0.1 to 1 μm;

[0078] S2. Etching the silicon dioxide mask 8 in the trench structure region to expose the epitaxial layer 7; etching using photolithography and dry etching processes;

[0079] S3. Figure 8 As shown, the front side of the epitaxial layer 7 is etched to form a trench structure in the epitaxial layer 7; a dry etching process is adopted, and the etching gas is one or more mixed gases such as chlorine, sulfur hexafluoride, and hydrogen bromide, and the different selectivity ratios of etching silicon and silicon dioxide are utilized;

[0080] S4. The silicon dioxide mask 8 is removed by etching with a mixture of ammonium fluoride and hydrofluoric acid, wherein the volume ratio of ammonium fluoride to hydrofluoric acid is 1 to 150:1 and the temperature of the mixture ranges from 20 to 30°C; Figure 9 As shown, a gate oxide layer 9 is grown on the device surface and inside the trench using a thermal oxidation process, and the temperature range of the thermal oxidation process is 800-1200°C; the gate oxide layer 9 is silicon dioxide with a thickness of 0.1-1 μm;

[0081] S5. Filling the front and trench structures with a polysilicon filling layer 10 using low-pressure chemical vapor deposition (LPCVD) with silane and phosphine as the reaction gases; retaining the polysilicon filling layer 10 within the trench structure, removing excess polysilicon from the surface, and employing a dry etching process with sulfur hexafluoride or chlorine as the etching gas;

[0082] S6. Using chemical vapor deposition (CVD) to grow a layer of silicon dioxide on the surface of the device; dry-etching the silicon dioxide and the gate oxide layer on the surface of the epitaxial layer 7 to form a barrier region window 11, exposing the surface of the epitaxial layer 7; the boundary position of the barrier region window 11 is set at the center of the cross section of the innermost terminal trench 3;

[0083] S7. A barrier metal layer 12 is deposited using a sputtering or evaporation process. The metal type may be titanium or nickel-platinum alloy. The metal thickness range is 0.01 to 1 um.

[0084] S8. Figure 10 As shown, the entire device is subjected to high-temperature annealing to react with the portion of the barrier metal layer 12 in contact with the epitaxial layer 7 to form a Schottky barrier 13; the annealing gas atmosphere is nitrogen with a purity of more than 99%, and the annealing temperature range is: 600~1000℃;

[0085] S9. Deposit metal on the front side to form a positive electrode 4, then thin the wafer to a thickness of 100-500 μm; then deposit metal on the back side to form a back electrode 5. The preparation process can use evaporation or sputtering, and the metal type of the electrode can be aluminum or silver.

[0086] Example 2

[0087] For the trench Schottky diode with stripe terminals in Example 1, four design schemes were developed. Each design scheme included different X- and Y-direction offsets for the hole lithography. The X-direction offsets were 0, 0.1, 0.2, and 0.3 μm, respectively, and the Y-direction offset was 0.2 μm. The groups were numbered 1, 2, 3, and 4, respectively.

[0088] Prepare as Figure 1-Figure 2The trench Schottky diode with arc-shaped terminals shown in the figure was fabricated using conventional methods. Four sets of design proposals were developed, each containing different X- and Y-direction offsets for the aperture lithography. The X-direction offsets were 0, 0.1, 0.2, and 0.3 μm, respectively, and the Y-direction offset was 0.2 μm. The groups were numbered 5, 6, 7, and 8, respectively.

[0089] Ideally, the contact hole lithography window boundary is at the center of the terminal trench, see Figure 2 A. In the actual processing process, as long as the X-direction contact hole lithography bias is less than 1 / 2 of the terminal groove width, it can ensure that the contact hole lithography window boundary is inside the terminal groove, and reverse breakdown failure will not occur. However, in the actual chip processing process, the lithography will have a certain offset. The stronger the production line process capability, the smaller the probability of bias and the smaller the bias. However, in the mass production process, zero bias is usually not met. After the existing design scheme has a bias in the Y direction, the bias window in the X direction will become smaller. The bias window is T, and T is less than 1 / 2 of the terminal groove width. See Figure 2 The terminal groove of the present invention is long and narrow, which solves the above technical problems. After the hole lithography is biased in the Y direction, it does not affect the bias window in the X direction. T is still equal to 1 / 2 of the terminal groove width. Figure 6 .

[0090] The design above underwent bias pull processing during the hole lithography process. After product fabrication, parameter testing was conducted using the following standards: VZ > 52V, IR < 20uA, and VF < 470mV. The parameters and test results are shown in Table 1.

[0091] Table 1 Hole lithography bias parameters and test results

[0092]

[0093] From the results in Table 1, we can see that the qualified rate of the existing arc-shaped terminal design scheme begins to drop significantly after the hole lithography exceeds 0.2um in the Y direction and 0.2um in the X direction. The qualified rate failure MAP waste distribution diagram of the 8th group of experimental chips is shown in the figure below. Figure 11 The figure shows a regular lithography SHOT distribution, with the failure point area marked with an ×, which clearly shows that the low pass rate is affected by lithography bias. However, the four groups of samples designed by the present invention did not have the problem of low pass rate, with a pass rate of ≥98.11%.

[0094] The design schemes of Group 1 and Group 5 were selected for chip packaging, and the reverse limit voltage withstand capability of the chip was tested. The results are shown in Table 2.

[0095] Table 2 Comparison results of reverse ultimate withstand voltage capability

[0096]

[0097] As can be seen from Table 2, the existing design of trench Schottky diodes with arc-shaped terminals began to fail in large numbers after the reverse withstand voltage exceeded 6kV, while the design of the present invention only showed minor failures after 9kV. This shows that the reverse withstand voltage of the product designed by the present invention after packaging is significantly better than that of the existing design under the same process conditions. The design of the present invention has a greater tolerance for hole lithography bias, resulting in a higher chip yield when the hole lithography bias is present, reducing the difficulty of production and processing, and the reverse withstand voltage after packaging is better than that of the existing design.

[0098] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved. This is not limited herein.

[0099] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A trench Schottky diode based on a stripe-type terminal, comprising a semiconductor substrate, a plurality of trench structures within the semiconductor substrate, a barrier metal layer connecting the trench structures and an electrode on the surface of the semiconductor substrate; characterized in that: The groove structure includes an outer terminal groove structure and an inner unit cell groove structure; The terminal groove structure includes N terminal grooves, the width of the innermost terminal groove is greater than the width of the unit cell groove, 1≤N≤10; the spacing between the N terminal grooves gradually increases from the inside to the outside; the terminal grooves are strip-shaped; The unit cell groove structure includes circular hole unit cell grooves distributed in an equilateral triangle array on the inner side, and an outer ring unit cell groove structure close to the innermost terminal groove; the outer ring unit cell groove structure is composed of circular hole unit cell grooves and elliptical hole unit cell grooves alternately arranged at equal intervals; The terminal trench structure and the unit cell trench structure include a trench, a gate oxide layer covering the inner wall of the trench, and a polysilicon filling layer located on the surface of the gate oxide layer and filling the trench.

2. A trench Schottky diode based on a stripe-type terminal according to claim 1, characterized in that: The distances from the boundaries of the circular hole unit cell groove and the elliptical hole unit cell groove to the innermost terminal groove are D1 and D2 respectively; D1=D2.

3. The trench Schottky diode based on a stripe-type terminal according to claim 2, characterized in that: The value range of D1 and D2 is 0.2~20um.

4. The trench Schottky diode based on a stripe-type terminal according to claim 1, characterized in that: The width W of all the unit cell trenches in the unit cell trench structure is 单 Range: 0.1um≤W 单 ≤10um; the side length of the trench Schottky diode based on the strip-type terminal is 50mil≤L≤300mil.

5. The trench Schottky diode based on a stripe-type terminal according to claim 1, characterized in that: The innermost terminal groove has a width of 0.2-5 μm and a depth of 1-5 μm.

6. A trench Schottky diode based on a stripe-type terminal according to any one of claims 1 to 5, characterized in that: The semiconductor substrate includes a base and an epitaxial layer. The trench structure is located in the epitaxial layer. A Schottky barrier is formed at a portion where the barrier metal layer contacts the epitaxial layer.

7. A method for preparing a trench Schottky diode based on a stripe-type terminal, for preparing the trench Schottky diode based on a stripe-type terminal according to any one of claims 1 to 6, characterized in that: The specific steps include: S1. Providing a semiconductor substrate, growing a layer of silicon dioxide mask on the front of the semiconductor substrate; S2. etching the silicon dioxide mask in the trench structure region to expose the semiconductor substrate; S3. Etching the front surface of the semiconductor substrate to form a trench structure; S4. removing the silicon dioxide mask and growing a gate oxide layer on the front surface of the semiconductor substrate and within the trench structure; S5. Filling a polysilicon filling layer on the front surface of the semiconductor substrate and in the trench structure using a low-pressure chemical vapor deposition method; retaining the polysilicon filling layer filled in the trench structure and removing excess polysilicon on the surface; S6. Growing a layer of silicon dioxide on the front surface of the semiconductor substrate using chemical vapor deposition; Etching the silicon dioxide and the gate oxide layer on the surface of the semiconductor substrate to form a barrier region window and expose the front surface of the semiconductor substrate; The boundary position of the barrier region window is set at the center of the cross section of the innermost terminal trench; S7. Depositing a barrier metal layer on the front of the semiconductor substrate, the metal being titanium or nickel-platinum alloy; S8. performing high temperature annealing to react the portion of the barrier metal layer in contact with the semiconductor substrate to form a Schottky barrier; S9. Use evaporation or sputtering to deposit metal on the front surface of the semiconductor substrate to form a positive electrode, and deposit metal on the back surface of the semiconductor substrate to form a back electrode, wherein both the positive electrode and the back electrode are made of aluminum or silver.

8. The method for preparing a trench Schottky diode based on a stripe-type terminal according to claim 7, characterized in that: The etching in step S2 is performed by photolithography or dry etching; the etching gas in step S3 is dry etching, and the etching gas is at least one of chlorine, sulfur hexafluoride, and hydrogen bromide; the high-temperature annealing in step S8 is performed by nitrogen with a purity of more than 99% and an annealing temperature of 600-1000°C.

9. The method for preparing a trench Schottky diode based on a stripe-type terminal according to claim 7, characterized in that: The thickness of the silicon dioxide mask is 0.1-1 μm; the gate oxide layer is silicon dioxide with a thickness of 0.1-1 μm; and the thickness of the barrier metal layer is 0.01-1 μm.

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