Semiconductor devices, power modules and electronic devices

Abstract

This disclosure provides a semiconductor device, power module, and electronic device, relating to the field of semiconductor technology, for reducing the dynamic on-resistance of a semiconductor device while increasing its breakdown voltage. The semiconductor device includes a substrate, a buffer layer, a channel layer, a barrier layer, a barrier modulation layer, a gate, a source, and a drain. The buffer layer is doped with acceptor elements and includes a first acceptor doped region and a second acceptor doped region. The acceptor element density in the second acceptor doped region is less than that in the first acceptor doped region. In a projection onto a first surface of the substrate, the second acceptor doped region overlaps with the drain, and a portion of the second acceptor doped region is located on the side of the drain closer to the barrier modulation layer. The above semiconductor device is applied in a power module.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device, power module, and electronic device. Background Technology

[0002] High Electron Mobility Transistor (HEMT) has gradually become a research and application hotspot in semiconductor devices due to its excellent characteristics such as wide bandgap, high breakdown electric field and high electron saturation velocity. Summary of the Invention

[0003] The purpose of embodiments of this disclosure is to provide a semiconductor device, power module, and electronic device for reducing the dynamic on-resistance of the semiconductor device while increasing its breakdown voltage.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a semiconductor device is provided. The semiconductor device includes a substrate, a buffer layer, a channel layer, a barrier layer, a barrier modulation layer, a gate, a source, and a drain; the buffer layer, channel layer, and barrier layer are stacked on the substrate along a direction away from the substrate; the barrier modulation layer is disposed on the side of the barrier layer away from the substrate; the gate is disposed on the side of the barrier modulation layer away from the substrate; the source and drain are respectively disposed on opposite sides of the barrier modulation layer along a first direction, and are respectively spaced apart from the barrier modulation layer; the first direction is perpendicular to the thickness direction of the substrate; wherein, the buffer layer is doped with acceptor elements, and the buffer layer includes a first acceptor doped region and a second acceptor doped region, the acceptor element density in the second acceptor doped region being less than the acceptor element density in the first acceptor doped region; in a projection onto a first surface of the substrate, the second acceptor doped region overlaps with the drain, and a portion of the second acceptor doped region is located on the side of the drain closer to the barrier modulation layer.

[0006] In the aforementioned semiconductor device, the buffer layer is non-uniformly doped with acceptor elements. Since only the doping density of a single acceptor element needs to be controlled, the process can be simplified. The second acceptor-doped region is located on the drain side near the barrier modulation layer, and its acceptor element density is low. Therefore, when the semiconductor device is subjected to drain voltage in the off-state, the depletion layer cannot rapidly extend below the drain. Compared to related technologies with a buffer layer having a uniform distribution and high acceptor element doping density, this semiconductor device can shift the electric field peak concentrated at the drain end towards the barrier modulation layer. Simultaneously, in this semiconductor device, because the first acceptor-doped region covered by the barrier modulation layer retains a high doping density of acceptor elements, the electric field peak concentrated at the edge of the barrier modulation layer can be shifted towards the drain. This simultaneous shift of the electric field peak at the drain end and the electric field peak concentrated at the edge of the barrier modulation layer redistributes the electric field in the drift region, resulting in a flatter off-state electric field and thus improving the breakdown voltage of the semiconductor device.

[0007] Secondly, the channel layer and barrier layer are made of materials with different band gaps, thus forming a heterojunction. The spontaneous polarization and piezoelectric polarization effects of the heterojunction induce a two-dimensional electron gas at the interface between the channel layer and the barrier layer. When the semiconductor device is turned off and subjected to a reverse drain voltage, the acceptor traps in the buffer layer can capture electrons, forming space charge and regulating the reverse electric field distribution of the semiconductor device. Since the acceptor element density of the second acceptor doped region near the drain is low, the trapping of the two-dimensional electron gas under high reverse bias can be reduced, thereby reducing the dynamic on-resistance of the semiconductor device. The acceptor element density of the first acceptor doped region near the barrier modulation layer is high, which can maintain high resistivity and prevent punch-through leakage. This avoids the situation where the resistance of the buffer layer decreases due to the low acceptor element density of the first acceptor doped region near the barrier modulation layer, making it easy for leakage current paths to form, thus preventing premature breakdown of the semiconductor device.

[0008] Therefore, the semiconductor device provided in this embodiment not only has a high breakdown voltage but also a low dynamic on-resistance.

[0009] In some embodiments, the second acceptor doped region is embedded in the first acceptor doped region, and in a positive projection onto the first surface of the substrate, the first acceptor doped region overlaps with the source and the barrier modulation layer.

[0010] In some embodiments, the first acceptor doped region includes a first portion and a second portion, the first portion being located on the side of the second acceptor doped region near the source electrode; the second portion being located on the side of the first portion and the second acceptor doped region near the substrate, and the second portion being connected to the first portion.

[0011] In some embodiments, the surface of the first portion of the first acceptor doped region away from the substrate is flush with the surface of the second acceptor doped region away from the substrate.

[0012] In some embodiments, along the first direction, the distance between the boundary of the second acceptor doped region near the source and the boundary of the barrier modulation layer away from the source is less than the distance between the boundary of the second acceptor doped region near the source and the boundary of the drain near the barrier modulation layer.

[0013] In some embodiments, along the first direction and along the direction from the source to the drain, the second acceptor doped region includes at least two sub-acceptor doped regions, wherein the density of acceptor elements in the at least two sub-acceptor doped regions gradually decreases.

[0014] In some embodiments, along the first direction and along the direction from the source to the drain, the second acceptor doped region includes at least two sub-acceptor doped regions, and its size gradually increases along the thickness direction of the substrate.

[0015] In some embodiments, along the first direction and along the direction from the source to the drain, the density of acceptor elements in the at least two sub-acceptor doped regions is equal or gradually decreases.

[0016] In some embodiments, the interface between the at least two sub-acceptor doped regions and the first acceptor doped region is stepped.

[0017] In some embodiments, the density of acceptor elements in the first acceptor-doped region is 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The density of acceptor elements in the second acceptor-doped region is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 .

[0018] In some embodiments, the device further includes: a passivation layer located on the side of the barrier layer away from the substrate and between the drain and the barrier modulation layer, and between the source and the barrier modulation layer.

[0019] On the other hand, a power module is provided, including the semiconductor device as described in any of the above embodiments.

[0020] In another aspect, an electronic device is provided, including a power module as described in any of the above embodiments.

[0021] The power modules and electronic devices described above have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0023] Figure 1 A structural diagram of an electronic device provided for some embodiments of this disclosure;

[0024] Figure 2 A structural diagram of a semiconductor device provided for some embodiments of this disclosure;

[0025] Figure 3 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;

[0026] Figure 4 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;

[0027] Figure 5 Simulation diagrams of the channel electric field distribution of three semiconductor devices with different structures provided for some embodiments of this disclosure under the same reverse drain voltage;

[0028] Figure 6 for Figure 5 A partial enlarged view of the simulation diagram of the electric field distribution in the channel;

[0029] Figure 7 A schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure;

[0030] Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 A schematic diagram illustrating a method for manufacturing a display panel according to some embodiments of this disclosure;

[0031] Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18A schematic diagram illustrating another method for manufacturing a display panel provided for some embodiments of this disclosure;

[0032] Figure 19 , Figure 20 and Figure 21 This is a schematic diagram illustrating another method for fabricating a display panel, provided for some embodiments of this disclosure. Detailed Implementation

[0033] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0034] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0035] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0036] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0037] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0038] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0039] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the areas shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0040] like Figure 1 As shown, this disclosure provides an electronic device 1000. The electronic device 1000 can be a fast charger, an uninterruptible power supply (UPS), a power motor, or other electronic devices.

[0041] Continue to refer to Figure 1 The electronic device 1000 includes a power module 1001 and a circuit board 1002. The power module 1001 and the circuit board 1002 are electrically connected. The circuit board 1002 converts the external power supply into the voltage or current required for the power module 1001 to operate.

[0042] For example, circuit board 1002 may include a printed circuit board (PCB) or the like.

[0043] For example, circuit board 1002 may include multiple conductive layers. The multiple conductive layers within circuit board 1002 may be separated from each other by dielectric layers.

[0044] The aforementioned power module 1001 includes semiconductor devices.

[0045] The above-mentioned semiconductor devices will be described in detail below.

[0046] refer to Figure 2 The semiconductor device 100 includes a substrate 10, a buffer layer 20, a channel layer 30, a barrier layer 40, a barrier modulation layer 50, a gate 53, a source 51, and a drain 52.

[0047] The buffer layer 20, channel layer 30, and barrier layer 40 are stacked on the substrate 10 along a direction away from the substrate 10; the barrier modulation layer 50 is disposed on the side of the barrier layer 40 away from the substrate 10; the gate 53 is disposed on the side of the barrier modulation layer 50 away from the substrate 10; the source 51 and drain 52 are respectively disposed on both sides of the barrier modulation layer 50 along the first direction X, and are respectively spaced from the barrier modulation layer 50; the first direction X is perpendicular to the thickness direction of the substrate 10; the buffer layer 20 is doped with acceptor elements, and the buffer layer 20 includes a first acceptor doped region 21 and a second acceptor doped region 22, the density of acceptor elements in the second acceptor doped region 22 is less than the density of acceptor elements in the first acceptor doped region 21; in the orthographic projection onto the first surface m1 of the substrate 10, the second acceptor doped region 22 overlaps with the drain 52, and a portion of the second acceptor doped region 22 is located on the side of the drain 52 closer to the barrier modulation layer 50.

[0048] Semiconductor device 100 forms an inversion layer channel on the surface of barrier modulation layer 50 by applying a voltage to gate 53, thereby controlling the conduction and turn-off between source 51 and drain 52. For example, when the voltage on gate 53 exceeds the threshold voltage, the channel opens, charge carriers flow from the source to the drain, and semiconductor device 100 conducts; when the voltage on gate 53 is lower than the threshold voltage, the channel disappears, and semiconductor device 100 turns off.

[0049] In the aforementioned semiconductor device 100, the buffer layer 20 is non-uniformly doped with acceptor elements. Since only the doping density of a single acceptor element needs to be controlled, the process can be simplified. The second acceptor doped region 22 is partially located on the side of the drain 52 near the barrier modulation layer 50, and the acceptor element density of the second acceptor doped region 22 is low. Therefore, when the semiconductor device 100 is subjected to a voltage at the drain 52 in the off state, the depletion layer cannot rapidly extend below the drain 52. Compared to related technologies with a buffer layer 20 having a uniform distribution and high acceptor element doping density, the aforementioned semiconductor device 100 can shift the electric field peak concentrated at the drain 52 towards the direction closer to the barrier modulation layer 50. Simultaneously, in the aforementioned semiconductor device 100, since the first acceptor doped region 21 covered by the barrier modulation layer 50 retains a high doping density of acceptor elements, the electric field peak concentrated at the edge of the barrier modulation layer 50 can be shifted towards the direction closer to the drain 52. In this way, the electric field peak at the drain 52 terminal and the electric field peak concentrated at the edge of the barrier modulation layer 50 are transferred simultaneously, causing the electric field in the drift region to redistribute, and the off-state electric field of the semiconductor device 100 to be flatter, thereby increasing the breakdown voltage of the semiconductor device 100.

[0050] Secondly, the channel layer 30 and the barrier layer 40 have different band gaps, thus forming a heterojunction. The spontaneous polarization and piezoelectric polarization effects of the heterojunction induce a two-dimensional electron gas at the interface of the channel layer 30 near the barrier layer 40. When the semiconductor device 100 is turned off and subjected to a reverse drain voltage, the acceptor traps in the buffer layer 20 can capture electrons, forming space charge and regulating the reverse electric field distribution of the semiconductor device 100. Due to the second acceptor doped region near the drain 52... The low density of the acceptor element in region 22 reduces the trapping of two-dimensional electron gas under high reverse bias, thereby lowering the dynamic on-resistance of the semiconductor device 100. The high density of the acceptor element in the first acceptor doped region 21 near the barrier modulation layer 50 maintains high resistivity, preventing punch-through leakage. This avoids the situation where the low density of the acceptor element in the first acceptor doped region 21 near the barrier modulation layer 50 leads to a decrease in the resistance of the buffer layer 20, making it easier for leakage current paths to form, thus preventing premature breakdown of the semiconductor device. Therefore, the semiconductor device provided in this embodiment not only has a high breakdown voltage but also a low dynamic on-resistance.

[0051] In this article, "acceptor elements doped in buffer layer 20" refers to elements that can stably accept valence band electrons and generate mobile holes in the valence band in buffer layer 20.

[0052] In some embodiments, the acceptor element includes iron, carbon, or magnesium.

[0053] In some embodiments, the material of the barrier modulation layer 50 includes gallium nitride (GaN) and is P-type doped.

[0054] In some embodiments, the density of acceptor elements in the first acceptor doped region 21 is 2 to 10 times the density of acceptor elements in the second acceptor doped region 22. For example, 2 times, 5 times, 8 times, or 10 times.

[0055] The gradient difference between the density of acceptor elements in the first acceptor doped region 21 and the density of acceptor elements in the second acceptor doped region 22 is within a certain range, which allows the depletion region to gradually extend from the first acceptor doped region 21 to the second acceptor doped region 22, avoiding abrupt changes in the electric field at the interface, thereby suppressing the electric field concentration at the drain edge.

[0056] For example, the density of acceptor elements in the first acceptor doped region 21 is 1×10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The density of acceptor elements in the second acceptor doped region 22 is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 .

[0057] The density of acceptor elements in the first acceptor doped region 21 and the density of acceptor elements in the second acceptor doped region 22 are within this range. In this way, the first acceptor doped region 21 can provide sufficient ionized acceptors to ensure the suppression of punch-through leakage current in the semiconductor device 100, and the second acceptor doped region 22 can reduce the density of deep-level acceptor traps, thereby reducing the probability of carriers being trapped in the semiconductor device 100 during switching and improving the dynamic resistance of the semiconductor device 100.

[0058] For example, the density of acceptor elements in the first acceptor doped region 21 is 1 × 10⁻⁶. 17 cm -3 In this case, the density of acceptor elements in the second acceptor doped region 22 is 1×10⁻⁶. 16 cm -3 .

[0059] For example, the density of acceptor elements in the first acceptor doped region 21 is 3 × 10⁻⁶. 17 cm -3 In this case, the density of acceptor elements in the second acceptor doped region 22 is 3 × 10⁻⁶. 16 cm -3 .

[0060] For example, the density of acceptor elements in the first acceptor doped region 21 is 1 × 10⁻⁶. 18 cm -3 In this case, the density of acceptor elements in the second acceptor doped region 22 is 1×10⁻⁶. 17 cm -3 .

[0061] For example, the density of acceptor elements in the first acceptor doped region 21 is 1×10⁻⁶. 19 cm -3 In this case, the density of acceptor elements in the second acceptor doped region 22 is 1×10⁻⁶. 18 cm -3 .

[0062] In some embodiments, the second acceptor doped region 22 is embedded in the first acceptor doped region 21, and in the orthographic projection onto the first surface m1 of the substrate 10, the first acceptor doped region 21 overlaps with the source 51 and the barrier modulation layer 50.

[0063] Because the acceptor traps in the buffer layer 20 affect the depletion of the two-dimensional electron gas in the channel when the semiconductor device 100 is subjected to reverse drain voltage in the off state. When the acceptor trap density in the buffer layer 20 is high, the two-dimensional electron gas in the channel extends more rapidly with the increase of reverse drain voltage, and the net surface density of the two-dimensional electron gas in the channel is lower. At this time, the peak electric field on the channel surface is more likely to be concentrated on the drain electrode 52 side.

[0064] When the acceptor trap density in the buffer layer 20 is low, compared to when the acceptor trap density in the buffer layer 20 is high, the depletion region extension of the two-dimensional electron gas in the channel with the increase of reverse drain voltage is relatively slow, and the net remaining two-dimensional electron gas surface density in the channel is relatively higher. The peak electric field on the channel surface is more easily concentrated near the drain 52 and gate 53 of the barrier modulation layer 50. Therefore, when the acceptor trap density of the first acceptor doped region 21 is higher than that of the second acceptor doped region 22, the extension of the two-dimensional electron gas depletion region in the channel near the barrier modulation layer 50 is accelerated, and the peak electric field of the barrier modulation layer 50 near the drain 52 and gate 53 is reduced when the semiconductor device 100 withstands high drain voltage in the off-state. Since the influence of acceptor element doping in the buffer layer 20 on the channel surface electric field gradually weakens with increasing depth, the second acceptor doped region 22 needs to have a certain depth in the buffer layer 20. Therefore, in some embodiments, the lower surface of the second acceptor doped region 22 near the substrate 10 can also coincide with the surface of the buffer layer 20 near the substrate 10.

[0065] In some embodiments, continue to refer to Figure 2 The semiconductor device 100 further includes a passivation layer 60, which is located on the side of the barrier layer 40 away from the substrate 10 and between the drain 52 and the barrier modulation layer 50, and between the source 51 and the barrier modulation layer 50.

[0066] The passivation layer 60 covers the surface of the barrier layer 40 away from the substrate. It not only passivates defect states such as dangling bonds on the surface of the barrier layer 40, reducing surface recombination speed and making gate control more stable, but also blocks impurity diffusion and maintains interface stability when the semiconductor device 100 operates at high temperatures. The passivation layer 60 is also located between the drain 52 and the barrier modulation layer 50, and between the source 51 and the barrier modulation layer 50. This prevents short circuits between the source, drain, and gate, or between the gate and other conductive layers, ensuring the normal operation of the semiconductor device 100. Furthermore, the passivation layer 60 provides support for the gate 53, allowing it to extend beyond the barrier modulation layer 50 and partially cover the passivation layer 60. This extension of the gate 53 beyond the barrier modulation layer 50 can form a field plate structure, dispersing the peak electric field, originally concentrated on the surface or sharp corners of the semiconductor device 100, to a wider area, preventing premature breakdown due to excessively high local electric fields. It also facilitates the subsequent fabrication of metal interconnects.

[0067] In some embodiments, reference Figure 2 Along the first direction X, the distance L1 between the source 51 and the barrier modulation layer 50 is smaller than the distance L2 between the drain 52 and the barrier modulation layer 50.

[0068] The barrier modulation layer 50 is used to optimize the carrier transport path. Along the first direction X, the distance L1 between the source 51 and the barrier modulation layer 50 is short. This not only shortens the lateral path of carriers (such as electrons) from the source 51 to the barrier modulation layer 50, reducing the resistance component during conduction, but also accelerates the expansion of the depletion layer when the semiconductor device 100 is turned off, reducing turn-off time and switching losses. Secondly, under short-circuit conditions of the semiconductor device 100, the short distance L1 between the source 51 and the barrier modulation layer 50 along the first direction X can also deplete the carriers below the channel more quickly, limiting the peak value of the short-circuit current, thereby improving the short-circuit withstand capability of the semiconductor device 100.

[0069] Meanwhile, the long spacing L2 between the drain 52 and the barrier modulation layer 50 not only maintains a sufficient drift region length and expands the depletion region on the drain 52 side, thereby improving the overall withstand voltage capability of the semiconductor device 100, but also reduces the capacitance on the drain 52 side, further improving high-frequency switching performance. The long spacing L2 between the drain 52 and the barrier modulation layer 50 also disperses the heat dissipation area during short circuits, preventing localized overheating failure of the semiconductor device 100.

[0070] In some embodiments, continue to refer to Figure 2The first acceptor doped region 21 includes a first portion 212 and a second portion 211. The first portion 212 is located on the side of the second acceptor doped region 22 near the source electrode 51. The second portion 211 is located on the side of the first portion 212 and the second acceptor doped region 22 near the substrate 10, and the second portion 211 is connected to the first portion 212.

[0071] In some embodiments, the surface of the first portion 212 of the first acceptor doped region 21 away from the substrate 10 is flush with the surface of the second acceptor doped region 22 away from the substrate 10. That is, the top surface of the first portion 212 is flush with the top surface of the second acceptor doped region 22. This ensures a uniform distribution of the electric field on the surface of the semiconductor device and avoids local concentration of the electric field due to the height difference between the first portion 212 and the second acceptor doped region 22. For example, it can make premature breakdown more likely to occur at the edge of a step. Secondly, during the switching process of the semiconductor device 100, the flush top surface can also accelerate the lateral transport of charge carriers and reduce switching delay; it can also prevent the formation of parasitic channels at the junction of the first portion 212 and the second acceptor doped region 22, such as the carrier accumulation path caused by the height difference between the first portion 212 and the second acceptor doped region 22, thereby reducing the leakage current of the semiconductor device 100 and suppressing parasitic conduction.

[0072] In some embodiments, continue to refer to Figure 2 Along the first direction X, the distance J1 between the boundary of the second acceptor doped region 22 near the source 51 and the boundary of the barrier modulation layer 50 away from the source 51 is less than the distance J2 between the boundary of the second acceptor doped region 22 near the source 51 and the boundary of the drain 52 near the barrier modulation layer 50.

[0073] Thus, the first acceptor-doped region 21 is located below the gate 53. During turn-off, it can be rapidly depleted through strong electric field coupling, shortening the turn-off delay. The first acceptor-doped region 21 has a high acceptor element density, which is beneficial for providing more ionizable holes and accelerating the lateral expansion of the depletion layer. When the semiconductor device 100 is in the off state, the synergistic effect of the first acceptor-doped region 21 and the electric field of the gate 53 forms a depletion region barrier, preventing the high voltage of the drain 52 from penetrating into the gate 53, enhancing the reverse blocking capability. The electric field peak of the barrier modulation layer 50 near the drain 52 is weakened, which is also beneficial for the high acceptor density buffer layer 20 to suppress punch-through current.

[0074] In some embodiments, reference Figure 3 Along the first direction X and along the direction from the source 51 to the drain 52, the second acceptor doped region 22 includes at least two sub-acceptor doped regions 221, and the density of acceptor elements in the at least two sub-acceptor doped regions 221 gradually decreases.

[0075] Along the first direction X and from the source 51 to the drain 52, the density of acceptor elements in the second acceptor doped region 22 gradually decreases. This naturally guides carriers to expand uniformly towards the drain 52, improving the stability of high-current operation. The decreasing acceptor element density from the source 51 to the drain 52 creates a smooth electric field gradient, preventing the electric field from concentrating at a certain location, thereby increasing the breakdown voltage of the semiconductor device 100 along the first direction X. Compared to a semiconductor device 100 with a second acceptor doped region 22 having a constant acceptor element density, the semiconductor device 100 with a gradient-doped second acceptor doped region 22 not only accelerates the expansion of the depletion layer but also effectively shortens the device's turn-off time, thus significantly reducing turn-off losses.

[0076] In some embodiments, reference Figure 4 Along the first direction X and along the direction from the source 51 to the drain 52, the second acceptor doped region 22 includes at least two sub-acceptor doped regions 221, and its size gradually increases along the thickness direction of the substrate 10.

[0077] For example, along the first direction X and along the direction from the source 51 to the drain 52, the second acceptor doped region 22 includes three sub-acceptor doped regions 221, and along the direction from the source 51 to the drain 52, the size of the three sub-acceptor doped regions 221 gradually increases along the thickness direction of the substrate 10.

[0078] In other embodiments, along the first direction X and along the direction from the source 51 to the drain 52, the number of sub-acceptor doped regions 221 included in the second acceptor doped region 22 can be 2, 5, 6 or 8, and there is no limitation here.

[0079] For example, the interfaces between at least two sub-acceptor doped regions 221 and the first acceptor doped region 21 are stepped.

[0080] like Figure 4 As shown, the interfaces between the three sub-acceptor doped regions 221 and the first acceptor doped region 21 are stepped. Since the buffer layer 20 requires a certain number of acceptor traps to ensure its semi-insulation, it absorbs the punch-through current between the drain 52 and the source 51. The stepped interface between at least two sub-acceptor doped regions 221 and the first acceptor doped region 21 reduces the off-state peak electric field on the drain 52 side while maximizing the retention of the original high acceptor trap density in the buffer layer 20, effectively suppressing the punch-through current between the drain 52 and the source 51.

[0081] In the case where the second acceptor doped region 22 includes at least two sub-acceptor doped regions 221 along the first direction X and from the source 51 to the drain 52, and its size gradually increases along the thickness direction of the substrate 10, the acceptor element density in the at least two sub-acceptor doped regions 221 is equal along the first direction X and from the source 51 to the drain 52. This ensures that the carrier mobility is not affected by the density fluctuation of the acceptor element, ensuring the stability of carrier transport. Furthermore, since the thickness of the sub-acceptor doped region 221 near the source 51 is small, the lateral resistance of the semiconductor device 100 can be reduced. Secondly, if the acceptor element density of the sub-acceptor doped regions 221 in the second acceptor doped region 22 is a single value, then at least two sub-acceptor doped regions 221 can be formed in a single epitaxial growth, reducing process complexity and lowering the risk of interface defects. In the case that the second acceptor doped region 22 includes at least two sub-acceptor doped regions 221 along the first direction X and along the direction from the source 51 to the drain 52, and the size gradually increases along the thickness direction of the substrate 10, the density of acceptor elements in the at least two sub-acceptor doped regions 221 gradually decreases along the first direction X and along the direction from the source 51 to the drain 52.

[0082] Along the first direction X and along the direction from the source 51 to the drain 52, the density of the acceptor element in the second acceptor doped region 22 gradually decreases, which can reduce the depletion and scattering of the two-dimensional electron gas in the channel when the semiconductor device 100 is in forward operation and improve the stability of the semiconductor device 100 when it is in high current operation.

[0083] Therefore, by controlling both the size of the sub-acceptor doped region 221 along the thickness direction of the substrate 10 and the density of the acceptor element in the sub-acceptor doped region 221, a comprehensive improvement in the performance of the semiconductor device 100 is achieved.

[0084] like Figure 4 As shown, along the first direction X and along the direction from the source 51 to the drain 52, the second acceptor doped region 22 includes three sub-acceptor doped regions 221. The size of the three sub-acceptor doped regions 221 gradually increases along the thickness direction of the substrate 10, and along the first direction X and along the direction from the source 51 to the drain 52, the density of acceptor elements in the three sub-acceptor doped regions 221 gradually decreases.

[0085] To verify the reverse characteristics of the semiconductor device provided in this embodiment, a computer was used to simulate the channel electric field distribution of three different semiconductor devices (Example 1, Comparative Example 1, and Comparative Example 2) under the same reverse drain voltage. The simulation diagrams of the channel electric field distribution of the three different semiconductor devices under the same reverse drain voltage can be found in the reference diagram. Figure 5 and Figure 6 The structure of the buffer layer 20 of the semiconductor device in Example 1 can be referred to as follows: Figure 2 The semiconductor device 100 shown has an acceptor element density of 1×10⁻⁶ in the first acceptor doped region 21 of the buffer layer 20. 18 cm -3 The density of acceptor elements in the second acceptor doped region 22 is 1×10⁻⁶. 17 cm -3 In Comparative Example 1, the buffer layer 20 of the semiconductor device is not partitioned, and the density of acceptor elements in the buffer layer 20 is 1 × 10⁻⁶. 18 cm -3 In Comparative Example 2, the buffer layer 20 of the semiconductor device is not partitioned, and the density of acceptor elements in the buffer layer 20 is 1 × 10⁻⁶. 17 cm -3 .

[0086] exist Figure 5 and Figure 6 In the diagram, the horizontal axis represents the coordinates of the transverse cross-section of the semiconductor device on the channel surface, in μm. The cross-section direction is perpendicular to the thickness direction of the substrate 10. The origin of the X-axis represents the edge of the source 51 near the barrier modulation layer 50, and the positive direction of the X-axis is from the source 51 to the drain 52. The vertical axis represents the magnitude of the channel electric field of the semiconductor device, in V / cm. It can be seen that compared with the semiconductor device in Comparative Example 1, the electric field at the drain 52 end of the semiconductor device in Example 1 is significantly reduced, while the electric field at the edge of the barrier modulation layer 50 is slightly increased. Compared with the semiconductor device in Comparative Example 2, the electric field at the drain 52 end of the semiconductor device in Example 1 shows almost no increase, and the peak electric field at the edge of the barrier modulation layer 50 is slightly reduced.

[0087] The simulation diagram illustrating the channel electric field distribution demonstrates that the semiconductor device provided in this embodiment can achieve reverse electric field modulation of a semiconductor device with a uniformly distributed acceptor element in the buffer layer 20, thus optimizing the reverse characteristics of the semiconductor device. Furthermore, the semiconductor device provided in this embodiment retains the high resistivity of the buffer layer 20, preventing premature breakdown of the semiconductor device caused by leakage current in the buffer layer 20 with excessively low acceptor element density. In addition, the semiconductor device provided in this embodiment reduces the acceptor element density within the buffer layer 20 between the gate and drain, resulting in a decrease in the density of the trapped two-dimensional electron gas in the buffer layer 20 under off-state stress, thus reducing the dynamic on-resistance.

[0088] Embodiments of this disclosure also provide a method for fabricating a semiconductor device, referencing... Figure 7 This includes the following steps:

[0089] Step S1: Refer to the reference Figures 8-11 or in combination Figure 8 , Figure 13 and Figure 14 A buffer layer 20 is formed on the substrate 10. The buffer layer 20 is doped with acceptor elements. The buffer layer 20 includes a first acceptor doped region 21 and a second acceptor doped region 22. The density of acceptor elements in the second acceptor doped region 22 is less than the density of acceptor elements in the first acceptor doped region 21.

[0090] In some embodiments, step S1 includes:

[0091] Step S11: Refer to Figure 8 An initial buffer layer 200 is formed on the substrate 10, and the initial buffer layer 200 is doped with acceptor elements.

[0092] For example, the density of acceptor elements doped in the initial buffer layer 200 is 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 .

[0093] Step S12: Reference Figure 9 The initial buffer layer 200 located in the target region Q is etched to form the first recess C, and the remaining initial buffer layer 200 forms the first acceptor doped region 21.

[0094] Step S13: Refer to the reference Figure 10 and Figure 11 A second buffer layer 220 is formed in the first recess C, and an acceptor element is doped in the second buffer layer 220, forming a second acceptor doped region 22.

[0095] For example, the density of acceptor elements doped in the second buffer layer 220 is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 .

[0096] Reference Figure 10 and Figure 11 The step of forming the second buffer layer 220 includes: performing a planarization (Chemical Mechanical Planarization, CMP) on the surface of the second buffer layer 220 away from the substrate 10, so that the top surface of the first acceptor doped region 21 furthest from the substrate 10 is flush with the top surface of the second acceptor doped region 22.

[0097] In other embodiments, step S1 includes:

[0098] Step Q11: Refer to Figure 8 An initial buffer layer 200 is formed on the substrate 10, and the initial buffer layer 200 is doped with acceptor elements.

[0099] Step Q12: Refer to Figure 13 A mask pattern T is formed on the side of the initial buffer layer 200 away from the substrate 10, and the mask pattern T exposes the initial buffer layer 200 of the target region Q.

[0100] Step Q13: Refer to the reference Figure 13 and Figure 14 Acceptor composite ions are injected into the initial buffer layer 200 of the target region Q using the mask pattern T as a mask, so that the initial buffer layer 200 located in the target region Q forms a second acceptor doped region 22, and the remaining initial buffer layer 200 forms the first acceptor doped region 21.

[0101] Here, the acceptor recombination ions include N-type ions. The N-type ions recombine with the acceptors originally present in the initial buffer layer 200, reducing the density of acceptor elements in the initial buffer layer 200 located in the target region Q, thereby forming a second acceptor doped region 22 in the initial buffer layer 200 located in the target region Q.

[0102] For example, N-type ions include silicon ions or germanium ions.

[0103] The implantation depth of the acceptor composite ions is less than the thickness of the initial buffer layer 200, and the implanted dose is less than the density of the acceptor elements in the initial buffer layer 200.

[0104] In some embodiments, after injecting acceptor composite ions into the initial buffer layer 200 of the target region Q using the mask pattern T as a mask, an annealing process is further included to activate the N-type ions.

[0105] Step S2: Reference Figure 12 A channel layer 30 and a barrier layer 40 are sequentially formed on the side of the buffer layer 20 away from the substrate 10.

[0106] Step S3: Continue to refer to Figure 12 A barrier modulation layer 50, a source 51, and a drain 52 are formed on the side of the barrier layer 40 away from the substrate 10. The source 51 and the drain 52 are respectively disposed on both sides of the barrier modulation layer 50 along the first direction X, and are respectively spaced from the barrier modulation layer 50. The first direction X is perpendicular to the thickness direction of the substrate 10. In the orthographic projection onto the first surface m1 of the substrate 10, the second acceptor doped region 22 overlaps with the drain 52, and a portion of the second acceptor doped region 22 is located on the side of the drain 52 closer to the barrier modulation layer 50.

[0107] Step S4: Continue to refer to Figure 12 A passivation layer 60 and a gate 53 are formed.

[0108] Here, the passivation layer 60 is located on the side of the barrier layer 40 away from the substrate 10, and is located between the drain 52 and the barrier modulation layer 50, and between the source 51 and the barrier modulation layer 50. The gate 53 is located on the side of the barrier modulation layer 50 away from the substrate 10.

[0109] In some embodiments, reference Figure 15 In step S12, the depth of the first depression C gradually increases. Specifically, referring to... Figure 18 After the barrier modulation layer 50, source 51 and drain 52 are formed on the side of the barrier layer 40 away from the substrate 10, the depth of the first recess C gradually increases along the first direction X and along the direction from the source 51 to the drain 52.

[0110] As the depth of the first depression C gradually increases, step S13 can be combined with reference. Figure 16 and Figure 17 A second buffer layer 220 is formed in the first recess C, and an acceptor element is doped in the second buffer layer 220, forming a second acceptor doped region 22.

[0111] Reference Figure 16 and Figure 17 The step of forming the second buffer layer 220 includes: performing a planarization (Chemical Mechanical Planarization, CMP) on the surface of the second buffer layer 220 away from the substrate 10, so that the top surface of the first acceptor doped region 21 furthest from the substrate 10 is flush with the top surface of the second acceptor doped region 22.

[0112] In some embodiments, step Q13 includes:

[0113] Step Q131: Reference Figure 19 A first mask pattern T1 is formed on the side of the initial buffer layer 200 away from the substrate 10, and the first mask pattern T1 exposes the initial buffer layer 200 of the first sub-target region Q1.

[0114] Step Q132: Refer to the reference Figure 19 and Figure 20 Acceptor composite ions are injected into the initial buffer layer 200 of the first sub-target region Q1 using the first mask pattern T1 as a mask.

[0115] Step Q133: Reference Figure 20 A second mask pattern T2 is formed on the side of the initial buffer layer 200 away from the substrate 10, and the second mask pattern T2 exposes the initial buffer layer 200 of the second sub-target region Q2.

[0116] Step Q134: Refer to the reference Figure 20 and Figure 21Acceptor-recombined ions are injected into the initial buffer layer 200 of the second sub-target region Q2 using the second mask pattern T2 as a mask; the first sub-target region Q1 and the second sub-target region Q2 are arranged along the first direction X and along the direction from the source 51 to the drain 52 (refer to the reference here). Figure 18 Furthermore, the depth to which acceptor composite ions are injected into the initial buffer layer 200 of the second sub-target region Q2 is greater than the depth to which acceptor composite ions are injected into the initial buffer layer of the first sub-target region Q1.

[0117] Step Q135: Reference Figure 21 Acceptor composite ions are injected into the initial buffer layer 200 of the third sub-target region Q3 using the third mask pattern T3 as a mask.

[0118] Here, the second sub-target region Q2 and the third sub-target region Q3 are arranged along the first direction X and along the direction from the source 51 to the drain 52 (refer to the reference here). Figure 18 , Figure 20 and Figure 21 Furthermore, the depth to which acceptor composite ions are injected into the initial buffer layer 200 of the third sub-target region Q3 is greater than the depth to which acceptor composite ions are injected into the initial buffer layer 200 of the second sub-target region Q2.

[0119] In some embodiments, the dose of acceptor composite ions injected into the initial buffer layer 200 of the first sub-target region Q1, the second sub-target region Q2, and the third sub-target region Q3 may remain constant or be gradually increased.

[0120] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A buffer layer, a channel layer, and a barrier layer are stacked on the substrate in a direction away from the substrate; A barrier modulation layer is disposed on the side of the barrier layer away from the substrate; A gate is disposed on the side of the barrier modulation layer away from the substrate; The source and drain are respectively disposed on both sides of the barrier modulation layer along the first direction, and are respectively spaced apart from the barrier modulation layer; the first direction is perpendicular to the thickness direction of the substrate; The buffer layer is doped with acceptor elements, and the buffer layer includes a first acceptor doped region and a second acceptor doped region. The density of acceptor elements in the second acceptor doped region is less than the density of acceptor elements in the first acceptor doped region. In the orthographic projection onto the first surface of the substrate, the second acceptor doped region overlaps with the drain, and a portion of the second acceptor doped region is located on the side of the drain closer to the barrier modulation layer. The second acceptor doped region is embedded in the first acceptor doped region. In the orthographic projection onto the first surface of the substrate, the first acceptor doped region overlaps with the source and the barrier modulation layer. The first acceptor doped region includes a first part and a second part, wherein the first part is located on the side of the second acceptor doped region closer to the source electrode; The second portion is located on the side of the first portion and the second acceptor doped region close to the substrate, and the second portion is connected to the first portion.

2. The semiconductor device according to claim 1, characterized in that, The surface of the first portion of the first acceptor doped region away from the substrate is flush with the surface of the second acceptor doped region away from the substrate.

3. The semiconductor device according to claim 1, characterized in that, Along the first direction, the distance between the boundary of the second acceptor doped region near the source and the boundary of the barrier modulation layer away from the source is less than the distance between the boundary of the second acceptor doped region near the source and the boundary of the drain near the barrier modulation layer.

4. The semiconductor device according to claim 1, characterized in that, Along the first direction and along the direction from the source to the drain, the second acceptor doped region includes at least two sub-acceptor doped regions, wherein the density of acceptor elements in the at least two sub-acceptor doped regions gradually decreases.

5. The semiconductor device according to claim 1, characterized in that, Along the first direction and along the direction from the source to the drain, the second acceptor doped region includes at least two sub-acceptor doped regions, and its size gradually increases along the thickness direction of the substrate.

6. The semiconductor device according to claim 5, characterized in that, Along the first direction and along the direction from the source to the drain, the density of acceptor elements in the at least two sub-acceptor doped regions is equal or gradually decreases.

7. The semiconductor device according to claim 5, characterized in that, The interfaces between the at least two sub-acceptor doped regions and the first acceptor doped region are stepped.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The density of acceptor elements in the first acceptor-doped region is 1×10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The density of acceptor elements in the second acceptor-doped region is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 .

9. The semiconductor device according to any one of claims 1 to 7, characterized in that, Also includes: A passivation layer is located on the side of the barrier layer away from the substrate, and is located between the drain and the barrier modulation layer, and between the source and the barrier modulation layer.

10. A power module, characterized in that, include: The semiconductor device as described in any one of claims 1 to 9.

11. An electronic device, characterized in that, include: The power module as described in claim 10.

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