Semiconductor device and chip
By introducing modulation and polarization enhancement layers into semiconductor devices, the problem of low gate reliability in high electron mobility transistors is solved, and the device's voltage withstand capability and gate control capability are improved.
Patent Information
- Application Number
- CN202511138188.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-13
- Publication Date
- 2025-11-14
AI Technical Summary
Existing high electron mobility transistors have low gate reliability and are prone to premature breakdown and aging due to peak electric fields.
In a semiconductor device, a modulation layer is introduced. The modulation layer material is the same as that of the barrier layer, which is an aluminum-based nitride. However, the aluminum molar percentage is lower than that of the barrier layer, and the concentration of the first acceptor doped in the modulation layer is lower than that in the cap layer. Combined with a polarization enhancement layer, the polarization effect is enhanced, the peak electric field at the gate interface is reduced, and the gate control capability is improved.
It improves the gate reliability of semiconductor devices, avoids premature breakdown caused by peak electric fields, and enhances gate control capability and device withstand voltage capability.
Smart Images
Figure CN120957453A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and chip. Background Technology
[0002] High electron mobility transistors (HEMTs) have gradually become a research and application hotspot in semiconductor devices due to their excellent characteristics such as wide bandgap, high breakdown electric field, and high electron saturation velocity. However, existing HEMTs suffer from low gate reliability. Summary of the Invention
[0003] The purpose of this disclosure is to provide a semiconductor device and chip for improving the gate reliability of the semiconductor device.
[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:
[0005] On one hand, a semiconductor device is provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a cap layer, a gate, a source, a drain, and a modulation layer; the channel layer and the barrier layer are stacked on the substrate along a direction away from the substrate; the cap layer is disposed on the side of the barrier layer away from the substrate; the cap layer is doped with a first acceptor; the gate is disposed on the side of the cap layer away from the substrate; the source and drain are respectively disposed on both sides of the cap layer along a first direction, and are respectively spaced apart from the cap layer; the first direction is perpendicular to the thickness direction of the substrate; the modulation layer is at least disposed between the gate and the cap layer; the modulation layer is doped with a first acceptor, and the concentration of the first acceptor in the modulation layer is lower than the concentration of the first acceptor in the cap layer; the materials of the modulation layer and the barrier layer both include aluminum-based nitrides, and the molar percentage of aluminum in the modulation layer is less than or equal to the molar percentage of aluminum in the barrier layer.
[0006] In the aforementioned semiconductor device, the concentration of the first acceptor in the modulation layer is lower than that in the cap layer. That is, the concentration of the first acceptor in the cap layer is high, while the concentration in the modulation layer is low. This allows for a sufficient hole concentration in the cap layer with its high first acceptor concentration, which is beneficial for depleting the two-dimensional electron gas at the heterojunction interface between the channel layer and the barrier layer. This enables the semiconductor device to be in a turn-off state at zero gate voltage, improving gate control capability. The low concentration of the first acceptor in the modulation layer reduces the hole concentration in the region below the gate. This avoids excessively high first acceptor concentration at the interface between the modulation layer and the gate, which could introduce defects or charge inhomogeneities. Consequently, it avoids the formation of a high peak electric field at the interface between the modulation layer and the gate, thus preventing such peak electric fields from accelerating gate degradation and reducing breakdown voltage.
[0007] Furthermore, both the modulation layer and the barrier layer are made of aluminum-based nitrides, and the molar percentage of aluminum in the modulation layer is less than or equal to the molar percentage of aluminum in the barrier layer. The modulation layer's aluminum-based nitride material enhances polarization, thereby increasing the two-dimensional electron gas concentration at the interface between the barrier layer and the channel layer. Since a higher molar percentage of aluminum enhances polarization, ensuring that the molar percentage of aluminum in the modulation layer is less than or equal to the molar percentage of aluminum in the barrier layer can, to some extent, mitigate gate breakdown caused by excessively high electron concentration in the channel below the gate pin.
[0008] Therefore, the gate reliability of the above-mentioned semiconductor devices is high.
[0009] In some embodiments, the modulation layer also covers at least a portion of the sidewalls of the cap layer.
[0010] In some embodiments, the modulation layer covers the sidewall of the cap layer facing the source, and / or the sidewall of the cap layer facing the drain.
[0011] In some embodiments, the modulation layer is further located between the cap layer and the drain, and is in contact with the surface of the barrier layer away from the substrate, and a first gap exists between the modulation layer and the drain.
[0012] In some embodiments, the modulation layer is also located between the cap layer and the source electrode, and is in contact with the surface of the barrier layer away from the substrate.
[0013] In some embodiments, one end of the modulation layer is in contact with the side of the source electrode near the cap layer, and the other end of the modulation layer is in contact with the side of the drain electrode near the cap layer.
[0014] In some embodiments, there is a first gap between the orthogonal projection of the modulation layer onto the substrate and the orthogonal projection of the drain onto the substrate, and a second gap between the orthogonal projection of the source onto the substrate; the semiconductor device further includes: a first polarization enhancement layer, at least a portion of which is disposed in the first gap and / or the second gap, and is in contact with the surface of the barrier layer away from the substrate.
[0015] In some embodiments, the first polarization enhancement layer covers the side of the modulation layer away from the substrate.
[0016] In some embodiments, the materials of the first polarization enhancement layer and the barrier layer both comprise aluminum-based nitrides, and the molar percentage of aluminum in the first polarization enhancement layer is greater than or equal to the molar percentage of aluminum in the barrier layer.
[0017] In some embodiments, the first acceptor includes magnesium, zinc, beryllium, or carbon.
[0018] On the other hand, a chip is provided, comprising the semiconductor device as described in any of the above embodiments.
[0019] The chip described above has the same structure and beneficial technical effects as the semiconductor devices provided in some of the above embodiments, and will not be described again here. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.
[0021] Figure 1 A structural diagram of an electronic device provided for some embodiments of this disclosure;
[0022] Figure 2 A structural diagram of a semiconductor device provided for some embodiments of this disclosure;
[0023] Figure 3 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;
[0024] Figure 4 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;
[0025] Figure 5 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;
[0026] Figure 6 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;
[0027] Figure 7 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;
[0028] Figure 8 A structural diagram of another semiconductor device provided for some embodiments of this disclosure;
[0029] Figure 9 A schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure;
[0030] Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 and Figure 21 This is a schematic diagram illustrating a method for manufacturing a display panel according to some embodiments of the present disclosure. Detailed Implementation
[0031] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0032] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.
[0033] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0034] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the content of this document.
[0035] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.
[0036] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.
[0037] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the areas shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.
[0038] Figure 1 This is a structural diagram of an electronic device 1000 provided for some embodiments of the present disclosure. The electronic device 1000 may be a fast charger, an uninterruptible power supply (UPS), a power motor, or other electronic devices.
[0039] Continue to refer to Figure 1 The electronic device 1000 includes a chip 1001 and a circuit board 1002. The chip 1001 and the circuit board 1002 are electrically connected. The circuit board 1002 converts the external power supply into the voltage or current required for the chip 1001 to operate.
[0040] For example, circuit board 1002 may include a printed circuit board (PCB) or the like.
[0041] For example, circuit board 1002 may include multiple conductive layers. The multiple conductive layers within circuit board 1002 may be separated from each other by dielectric layers.
[0042] The aforementioned chip 1001 includes semiconductor devices.
[0043] The above-mentioned semiconductor devices will be described in detail below.
[0044] Embodiments of this disclosure provide a semiconductor device 100. (See reference...) Figure 2 The semiconductor device 100 includes a substrate 10, a buffer layer 20, a channel layer 30, a barrier layer 40, a cap layer 50, a gate 70, a source 71, and a drain 72.
[0045] The buffer layer 20, the channel layer 30, and the barrier layer 40 are stacked on the substrate 10 along the direction away from the substrate 10; the cap layer 50 is disposed on the side of the barrier layer 40 away from the substrate 10; the cap layer 50 is doped with a first acceptor; the gate 70 is disposed on the side of the cap layer 50 away from the substrate 10; the source 71 and the drain 72 are respectively disposed on both sides of the cap layer 50 along the first direction X, and are respectively spaced apart from the cap layer 50; the first direction X is perpendicular to the thickness direction of the substrate 10.
[0046] Since the channel layer 30 and the barrier layer 40 form a heterojunction interface, a large potential well exists at this interface due to the spontaneous polarization and piezoelectric polarization effects. In this structure, electrons are confined at the interface between the channel layer 30 and the barrier layer 40, thereby inducing a high-density two-dimensional electron gas on the side of the channel layer 30 near the barrier layer 40. The cap layer 50 is doped with first acceptors, generating holes. These holes recombine with electrons in the two-dimensional electron gas, forming a depletion region at the heterojunction interface. This neutralizes the electrostatic effects of the polarization charge, thereby eliminating the two-dimensional electron gas and forming an enhancement-mode semiconductor device.
[0047] The inventors discovered that in order to fully deplete the two-dimensional electron gas at the heterojunction interface, the cap layer 50 needs to be doped with a high concentration of first acceptors. However, during the formation of the cap layer 50, due to the tailing effect, the concentration of first acceptors at the interface between the cap layer 50 and the gate 70 is higher than that inside the cap layer 50. This will cause a high peak electric field to be formed at the interface between the cap layer 50 and the gate 70, which may cause the semiconductor device 100 to break down prematurely, reduce the withstand voltage of the semiconductor device 100, and cause the semiconductor device 100 to age prematurely.
[0048] To address the aforementioned technical problems, embodiments of this disclosure provide a semiconductor device 100. (See reference...) Figure 3 The semiconductor device 100 includes a substrate 10, a channel layer 30, a barrier layer 40, a cap layer 50, a modulation layer 60, a gate 70, a source 71, and a drain 72.
[0049] In this configuration, a channel layer 30 and a barrier layer 40 are stacked on the substrate 10 along a direction away from the substrate 10; a cap layer 50 is disposed on the side of the barrier layer 40 away from the substrate 10; the cap layer 50 is doped with a first acceptor; a gate 70 is disposed on the side of the cap layer 50 away from the substrate 10; a source 71 and a drain 72 are respectively disposed on both sides of the cap layer 50 along a first direction X, and are respectively spaced apart from the cap layer 50; the first direction X is perpendicular to the thickness direction of the substrate 10; a modulation layer 60 is disposed at least between the gate 70 and the cap layer 50; the modulation layer 60 is doped with a first acceptor, and the concentration of the first acceptor in the modulation layer 60 is lower than the concentration of the first acceptor in the cap layer 50; the materials of the modulation layer 60 and the barrier layer 40 both include aluminum-based nitrides, and the molar percentage of aluminum in the modulation layer 60 is less than or equal to the molar percentage of aluminum in the barrier layer 40.
[0050] In the aforementioned semiconductor device 100, the concentration of the first acceptor in the modulation layer 60 is lower than that in the cap layer 50. That is, the concentration of the first acceptor in the cap layer 50 is high, while the concentration in the modulation layer 60 is low. This allows for a sufficient hole concentration in the cap layer 50 with its high first acceptor concentration, which is beneficial for depleting the two-dimensional electron gas at the heterojunction interface between the channel layer 30 and the barrier layer 40. This enables the semiconductor device 100 to be in a turn-off state at zero gate voltage, improving the control capability of the gate 70. The low concentration of the first acceptor in the modulation layer 60 reduces the hole concentration in the region below the gate 70. This avoids excessively high first acceptor concentration at the interface between the modulation layer 60 and the gate 70, which could introduce defects or charge inhomogeneities. Consequently, it prevents the formation of a high peak electric field at the interface between the modulation layer 60 and the gate 70, thus preventing such a peak electric field from accelerating the degradation of the gate 70 and reducing the breakdown voltage.
[0051] Furthermore, since both the modulation layer 60 and the barrier layer 40 are made of aluminum-based nitrides, and the molar percentage of aluminum in the modulation layer 60 is less than or equal to the molar percentage of aluminum in the barrier layer 40, the modulation layer 60, being made of aluminum-based nitrides, can enhance polarization. This increases the two-dimensional electron gas concentration at the interface between the barrier layer 40 and the channel layer 30. Since a higher molar percentage of aluminum enhances polarization, the fact that the molar percentage of aluminum in the modulation layer 60 is less than or equal to the molar percentage of aluminum in the barrier layer 40 can, to some extent, alleviate gate breakdown caused by excessively high electron concentration in the channel below the gate pin. Therefore, the gate reliability of the aforementioned semiconductor device 100 is high.
[0052] The first acceptor doped in the modulation layer 60 can be: the first acceptor is not intentionally doped in the modulation layer 60; or the first acceptor is actively introduced into the modulation layer 60, and the concentration of the first acceptor introduced into the modulation layer 60 is lower than the concentration of the first acceptor introduced into the cap layer 50.
[0053] In some embodiments, the material of the substrate 10 includes at least one of silicon, silicon carbide, gallium nitride, sapphire, and diamond.
[0054] In some embodiments, the material of the channel layer 30 includes gallium nitride.
[0055] In some embodiments, the material of the barrier layer 40 includes at least one of aluminum gallium nitride and aluminum nitride.
[0056] In some embodiments, the material of the gate 70 includes a metal, such as titanium nitride (TiN).
[0057] In some embodiments, the source electrode 71 is made of metal.
[0058] For example, the material of source 71 includes at least one of titanium, aluminum, nickel, gold, and titanium nitride (TiN).
[0059] For example, the source electrode 71 is made of a titanium / aluminum / titanium / titanium nitride (TiN) stacked structure. Alternatively, the source electrode 71 is made of a titanium / aluminum / nickel / gold stacked structure.
[0060] refer to Figure 3 The surface of the barrier layer 40 away from the substrate 10 has a first groove C1. A portion of the source 71 fills the first groove C1, so that the source 71 and the two-dimensional electron gas at the heterojunction interface of the channel layer 30 and the barrier layer 40 form an ohmic contact. This shortens the distance between the source 71 and the two-dimensional electron gas, increases the tunneling probability of the two-dimensional electron gas, reduces the contact resistance, and thus reduces the on-resistance of the semiconductor device 100 and improves the on-conductivity of the semiconductor device 100.
[0061] In some embodiments, the material of the drain electrode 72 includes metal.
[0062] For example, the material of the drain electrode 72 includes at least one of titanium, aluminum, nickel, gold, and titanium nitride (TiN).
[0063] For example, the drain electrode 72 is made of a titanium / aluminum / titanium / titanium nitride (TiN) stacked structure. Alternatively, the drain electrode 72 is made of a titanium / aluminum / nickel / gold stacked structure.
[0064] refer to Figure 3The surface of the barrier layer 40 away from the substrate 10 has a second groove C2. A portion of the drain 72 fills the second groove C2, so that the drain 72 and the two-dimensional electron gas at the heterojunction interface of the channel layer 30 and the barrier layer 40 form an ohmic contact. This shortens the distance between the drain 72 and the two-dimensional electron gas, increases the tunneling probability of the two-dimensional electron gas, reduces the contact resistance, and thus reduces the on-resistance of the semiconductor device 100 and improves the on-conductivity of the semiconductor device 100.
[0065] In some embodiments, the material of the cap layer 50 includes gallium nitride (GaN), and the cap layer 50 is doped with a first acceptor, the first acceptor being of P-type conductivity.
[0066] For example, the first acceptor may include magnesium (Mg), zinc (Zn), beryllium (Be), or carbon (C), etc.
[0067] For example, the concentration of the first acceptor in the cap layer 50 is 5 × 10⁻⁶. 18 ~10×10 19 cm -3 For example, the concentration of the first acceptor in the cap layer 50 is 5 × 10⁻⁶. 18 6×10 18 cm -3 2×10 19 cm -3 Or 10×10 19 cm -3 .
[0068] For example, the concentration of the first acceptor in the modulation layer 60 is less than or equal to 1 × 10⁻⁶. 18 cm -3 For example, the concentration of the first acceptor in the modulation layer 60 is 0 or 1 × 10⁻⁶. 18 cm -3 0.8×10 18 cm -3 0.5×10 18 cm -3 Or 0.2×10 18 cm -3 .
[0069] In some embodiments, the thickness of the modulation layer 60 is 2 nm to 30 nm. For example, the thickness of the modulation layer 60 is 2 nm, 10 nm, 15 nm, 20 nm, or 30 nm.
[0070] In some embodiments, both the modulation layer 60 and the barrier layer 40 are made of at least one of aluminum gallium nitride (AlGaN) and aluminum nitride (AlN). Furthermore, the molar percentage of aluminum in the modulation layer 60 is less than the molar percentage of aluminum in the barrier layer 40.
[0071] For example, both the modulation layer 60 and the barrier layer 40 are made of aluminum gallium nitride (AlGaN), with the molar percentage of aluminum in the modulation layer 60 being 0.5% to 39.5% and the molar percentage of aluminum in the barrier layer 40 being 1% to 40%.
[0072] For example, when the molar percentage of aluminum in the modulation layer 60 is 0.5%, the molar percentage of aluminum in the barrier layer 40 is 1%.
[0073] For example, when the molar percentage of aluminum in the modulation layer 60 is 10%, the molar percentage of aluminum in the barrier layer 40 is 15%.
[0074] For example, when the molar percentage of aluminum in the modulation layer 60 is 20%, the molar percentage of aluminum in the barrier layer 40 is 30%.
[0075] For example, when the molar percentage of aluminum in modulation layer 60 is 39.5%, the molar percentage of aluminum in barrier layer 40 is 40%.
[0076] In some embodiments, both the modulation layer 60 and the barrier layer 40 are made of at least one of aluminum gallium nitride (AlGaN) and aluminum nitride (AlN). Furthermore, the molar percentage of aluminum in the modulation layer 60 is equal to the molar percentage of aluminum in the barrier layer 40.
[0077] For example, both the modulation layer 60 and the barrier layer 40 are made of aluminum gallium nitride (AlGaN), with the molar percentage of aluminum in the modulation layer 60 being 1% to 40% and the molar percentage of aluminum in the barrier layer 40 being 1% to 40%.
[0078] For example, when the molar percentage of aluminum in the modulation layer 60 is 1%, the molar percentage of aluminum in the barrier layer 40 is also 1%.
[0079] For example, when the molar percentage of aluminum in the modulation layer 60 is 10%, the molar percentage of aluminum in the barrier layer 40 is also 10%.
[0080] For example, when the molar percentage of aluminum in the modulation layer 60 is 20%, the molar percentage of aluminum in the barrier layer 40 is also 20%.
[0081] For example, when the molar percentage of aluminum in the modulation layer 60 is 40%, the molar percentage of aluminum in the barrier layer 40 is also 40%.
[0082] In some embodiments, the barrier layer 40 is not doped with first acceptors. Since the electrons in the two-dimensional electron gas in the heterojunction formed by the barrier layer 40 and the channel layer 30 primarily originate from the polarization charge of the barrier layer 40, if the barrier layer 40 were doped with acceptors, these first acceptors would neutralize the polarization-induced positive charge, leading to a decrease in the concentration of the two-dimensional electron gas. Therefore, not doping the barrier layer 40 with first acceptors is beneficial for the semiconductor device 100 to maintain a high carrier density.
[0083] In some embodiments, the concentration of the first acceptor in the barrier layer 40 is lower than the concentration of the first acceptor in the modulation layer 60. Since the cap layer 50 is located on the side of the barrier layer 40 away from the substrate 10, and the cap layer 50 is doped with the first acceptor, during the fabrication of the semiconductor device 100, the first acceptor diffuses from the cap layer 50 to the barrier layer 40, resulting in a portion of the first acceptor also existing in the barrier layer 40.
[0084] In some embodiments, continue to refer to Figure 3 The semiconductor device 100 also includes a buffer layer 20, which is disposed between the substrate 10 and the channel layer 30. The buffer layer 20 can be one or more layers. The buffer layer 20 can form a high-resistance region to prevent longitudinal leakage of the semiconductor device 100.
[0085] For example, the material of the buffer layer 20 includes gallium nitride.
[0086] In some embodiments, continue to refer to Figure 3 The semiconductor device 100 also includes a nucleation layer 91 located between the substrate 10 and the buffer layer 20. The nucleation layer 91 can alleviate the lattice mismatch between the buffer layer 20 and the substrate 10, reduce the dislocation density of the grown buffer layer 20, and alleviate the warping or cracking caused by the difference in the coefficient of thermal expansion between the buffer layer 20 and the substrate 10.
[0087] For example, the material of nucleation layer 91 includes aluminum nitride.
[0088] In some embodiments, continue to refer to Figure 3 The semiconductor device 100 also includes a second polarization enhancement layer 92, which is located between the channel layer 30 and the barrier layer 40.
[0089] The material of the second polarization enhancement layer 92 includes aluminum nitride. When the material of the channel layer 30 includes gallium nitride and the material of the barrier layer 40 includes aluminum gallium nitride, and the material of the second polarization enhancement layer 92 is aluminum nitride, the molar percentage of aluminum in the second polarization enhancement layer 92 is the highest. The higher the molar percentage of aluminum, the stronger the polarization, which is beneficial to increasing the density of the two-dimensional electron gas and improving the performance of the semiconductor device 100.
[0090] refer to Figure 4 The modulation layer 60 also covers at least a portion of the sidewalls of the cap layer 50. In this way, the modulation layer 60 can also repair etching damage on the surface of the cap layer 50 and protect the cap layer 50, preventing an increase in leakage current of the semiconductor device 100, thereby improving the reliability of the semiconductor device 100.
[0091] For example, continue to refer to Figure 4The modulation layer 60 covers the sidewall of the cap layer 50 facing the source 71. The modulation layer 60 can not only effectively passivate the surface states of the sidewall of the cap layer 50 facing the source 71 and eliminate surface dangling bonds, but also reduce the lateral leakage path between the source 71 and the gate 70.
[0092] For example, continue to refer to Figure 4 The modulation layer 60 covers the sidewall of the cap layer 50 facing the drain electrode 72.
[0093] refer to Figure 5 The modulation layer 60 is also located between the cap layer 50 and the drain 72, and is in contact with the surface of the barrier layer 40 away from the substrate 10. There is a first gap L1 between the modulation layer 60 and the drain 72. Since the cap layer 50 has a depletion effect on the two-dimensional electron gas, a peak electric field will be formed at the gate when the drain 72 is pressurized, which will cause the semiconductor device 100 to fail easily at the gate. The modulation layer 60 can regulate the band structure at the edge of the cap layer 50 and moderately reduce the concentration gradient of the two-dimensional electron gas at the gate. Under the high bias voltage of the drain 72, the modulation layer 60 can reconstruct the electric field distribution and transfer the peak electric field from the gate to the interior of the modulation layer 60, making the electric field distribution smoother, thereby suppressing the peak electric field.
[0094] The phrase "the modulation layer 60 is in contact with the surface of the barrier layer 40 away from the substrate 10, and there is a first gap L1 between the modulation layer 60 and the drain 72" means that the modulation layer 60 extends from the cap layer 50 toward the drain 72 and toward the drain 72 toward the cap layer 50, and there is a first gap L1 between the modulation layer 60 and the drain 72. Here, the dimension of the modulation layer 60 extending from the cap layer 50 toward the drain 72 and toward the drain 72 toward the cap layer 50 can be 0.5μm, 1μm, or 1.5μm.
[0095] In some embodiments, reference Figure 6 The modulation layer 60 is also located between the cap layer 50 and the source 71, and is in contact with the surface of the barrier layer 40 away from the substrate 10.
[0096] In some embodiments, continue to refer to Figure 6 One end of the modulation layer 60 is in contact with the side of the source electrode 71 near the cap layer 50, and the other end of the modulation layer 60 is in contact with the side of the drain electrode 72 near the cap layer 50.
[0097] In some embodiments, reference Figure 7 The modulation layer 60 has a first gap L1 between its orthographic projection onto the substrate 10 and the drain 72 has a first gap L2 between its orthographic projection onto the substrate 10 and the source 71 has a second gap L2.
[0098] Continue to refer to Figure 7In a semiconductor device 100, where a first gap L1 exists between the orthographic projection of the modulation layer 60 onto the substrate 10 and the orthographic projection of the drain 72 onto the substrate 10, and a second gap L2 exists between the modulation layer 60 and the source 71 onto the substrate 10, the semiconductor device 100 further includes a first polarization enhancement layer 80. At least a portion of the first polarization enhancement layer 80 is disposed within the first gap L1 and is in contact with the surface of the barrier layer 40 away from the substrate 10. This allows the first polarization enhancement layer 80 to increase the two-dimensional electron gas concentration corresponding to the first gap L1, providing a low-resistance current path for the semiconductor device 100. The low two-dimensional electron gas concentration corresponding to the cap layer 50 and the modulation layer 60 helps ensure complete channel depletion at zero gate voltage, achieving stable normally-off operation and improving the switching speed of the semiconductor device 100. This partitioned control of the two-dimensional electron gas concentration balances the conflict between the normally-off characteristics and the conduction performance of the semiconductor device 100.
[0099] In some embodiments, the material of the first polarization enhancement layer 80 is the same as the material of the barrier layer 40. This helps to repair the etching damage caused to the surface of the barrier layer 40 away from the substrate 10 by the etching process during the formation of the cap layer 50 when the first polarization enhancement layer 80 is grown at high temperature, thereby improving the reliability of the dynamic on-resistance of the semiconductor device 100.
[0100] In some embodiments, both the material of the first polarization enhancement layer 80 and the material of the barrier layer 40 comprise aluminum-based nitrides, and the molar percentage of aluminum in the first polarization enhancement layer 80 is greater than the molar percentage of aluminum in the barrier layer 40. This allows the first polarization enhancement layer 80 to increase the two-dimensional electron gas concentration corresponding to the first gap L1, providing a low-resistance current path for the semiconductor device 100.
[0101] For example, the molar percentage of aluminum in the first polarization enhancement layer 80 is 1.5% to 40%, and the molar percentage of aluminum in the barrier layer 40 is 1% to 39.5%.
[0102] For example, the molar percentage of aluminum in the first polarization enhancement layer 80 is 1.5%, and the molar percentage of aluminum in the barrier layer 40 is 1%.
[0103] For example, the molar percentage of aluminum in the first polarization enhancement layer 80 is 20%, and the molar percentage of aluminum in the barrier layer 40 is 39.5%.
[0104] For example, the molar percentage of aluminum in the first polarization enhancement layer 80 is 40%, and the molar percentage of aluminum in the barrier layer 40 is 40%.
[0105] In some embodiments, both the material of the first polarization enhancement layer 80 and the material of the barrier layer 40 comprise aluminum-based nitrides, and the molar percentage of aluminum in the first polarization enhancement layer 80 is equal to the molar percentage of aluminum in the barrier layer 40. This allows the first polarization enhancement layer 80 to increase the two-dimensional electron gas concentration corresponding to the first gap L1, providing a low-resistance current path for the semiconductor device 100.
[0106] For example, the molar percentage of aluminum in the first polarization enhancement layer 80 is 1% to 40%, and the molar percentage of aluminum in the barrier layer 40 is 1% to 40%.
[0107] For example, the molar percentage of aluminum in the first polarization enhancement layer 80 is 1%, and the molar percentage of aluminum in the barrier layer 40 is 1%.
[0108] For example, the molar percentage of aluminum in the first polarization enhancement layer 80 is 20%, and the molar percentage of aluminum in the barrier layer 40 is 20%.
[0109] For example, the molar percentage of aluminum in the first polarization enhancement layer 80 is 40%, and the molar percentage of aluminum in the barrier layer 40 is 40%.
[0110] For example, the material of the first polarization enhancement layer 80 and the material of the barrier layer 40 both include at least one of aluminum gallium nitride and aluminum nitride.
[0111] For example, the materials of the first polarization enhancement layer 80 and the barrier layer 40 both include aluminum gallium nitride.
[0112] For example, the materials of the first polarization enhancement layer 80 and the barrier layer 40 both include aluminum nitride.
[0113] In some embodiments, continue to refer to Figure 7 At least a portion of the first polarization enhancement layer 80 is disposed in the second gap L2 and is in contact with the surface of the barrier layer 40 away from the substrate 10. In this way, the first polarization enhancement layer 80 can increase the two-dimensional electron gas concentration corresponding to the second gap L2, providing a low-resistance current path for the semiconductor device 100.
[0114] In some embodiments, continue to refer to Figure 7 At least a portion of the first polarization enhancement layer 80 is disposed in the first gap L1 and the second gap L2, and is in contact with the surface of the barrier layer 40 away from the substrate 10. In this way, the first polarization enhancement layer 80 can simultaneously increase the two-dimensional electron gas concentration corresponding to the first gap L1 and the second gap L2, providing a low-resistance current path for the semiconductor device 100.
[0115] In some embodiments, the thickness of the first polarization enhancement layer 80 is 1 nm to 30 nm. For example, the thickness of the first polarization enhancement layer 80 is 1 nm, 10 nm, 15 nm, 20 nm, or 30 nm.
[0116] In some embodiments, reference Figure 8 The first polarization enhancement layer 80 covers the side of the modulation layer 60 away from the substrate 10.
[0117] Embodiments of this disclosure also provide a method for fabricating a semiconductor device, referencing... Figure 9 This includes the following steps:
[0118] Step S1: Reference Figure 10 A buffer layer 20, a channel layer 30, and a barrier layer 40 are sequentially formed on the substrate 10.
[0119] Here, the material of barrier layer 40 includes aluminum-based nitrides.
[0120] In some embodiments, before forming the buffer layer 20 on the substrate 10, a nucleation layer (not shown) is formed on the substrate 10, and after forming the buffer layer 20, the nucleation layer is located between the substrate 10 and the buffer layer 20.
[0121] In some embodiments, before forming the barrier layer 40, a second polarization enhancement layer is formed on the side of the channel layer 30 away from the substrate 10, and after forming the barrier layer 40, the second polarization enhancement layer is located between the channel layer 30 and the barrier layer 40.
[0122] Step S2: Refer to the reference Figure 10 and Figure 11 A cap layer 50 is formed on the side of the barrier layer 40 away from the substrate 10, and the cap layer 50 is doped with a first acceptor.
[0123] Step S2 here includes:
[0124] Step S21: Reference Figure 10 An initial cap layer 500 is formed on the side of the barrier layer 40 away from the substrate 10.
[0125] Step S22: Reference Figure 11 Remove part of the initial cap layer 500, and the remaining initial cap layer 500 forms cap layer 50.
[0126] Here, the process of removing part of the initial cap layer 500 includes a dry etching process.
[0127] For example, a mask pattern is formed on the side of the initial cap layer 500 away from the substrate 10 using a photolithography process. The mask pattern exposes a portion of the initial cap layer 500, and a mixed gas of Cl2 and ClB3 is used to remove a portion of the initial cap layer 500.
[0128] Step S3: Refer to the reference Figure 12 , Figure 13 , Figure 14 and Figure 15A modulation layer 60 is formed on the side of the cap layer 50 away from the substrate 10; the modulation layer 60 is doped with a first acceptor, and the concentration of the first acceptor in the modulation layer 60 is lower than the concentration of the first acceptor in the cap layer 50; the material of the modulation layer 60 and the material of the barrier layer 40 both include aluminum-based nitrides, and the molar percentage of aluminum in the modulation layer 60 is less than or equal to the molar percentage of aluminum in the barrier layer 40.
[0129] Step S3 here includes:
[0130] Step S31: Reference Figure 12 An initial mask medium M0 is formed on the side of the cap layer 50 away from the substrate 10, the sidewall of the cap layer 50, and the surface of the barrier layer 40 away from the substrate 10.
[0131] Here, the process for forming the initial mask medium M0 includes plasma-enhanced chemical vapor deposition (PECVD).
[0132] Step S32: Refer to the reference Figure 12 and Figure 13 The portion of the initial mask medium M0 located on the side of the cap layer 50 is removed, and the remaining initial mask medium M0 forms the mask medium M. There is a gap between the mask medium M and the cap layer 50.
[0133] Here, the process for removing the portion of the initial mask medium M0 located on the side of the cap layer 50 includes an etching process. For example, a dry etching process can be used, specifically CF4 and CHF3 dry etching to remove the portion of the initial mask medium M0. Alternatively, a wet etching process can be used, specifically HCl to etch and remove the portion of the initial mask medium M0.
[0134] The material of the mask medium M includes silicon dioxide.
[0135] Step S33: Reference Figure 14 A modulation layer 60 is formed on the side of the cap layer 50 away from the substrate 10 and on the sidewall of the cap layer 50.
[0136] Here, the process for forming the modulation layer 60 includes metal-organic chemical vapor deposition (MOCVD).
[0137] The modulation layer 60 is made of at least one of aluminum gallium nitride (AlGaN) and aluminum nitride (AlN). Due to the large lattice mismatch between the nitride and the mask medium M, and the poor adhesion of the nitride to the mask medium M, it is assumed that the modulation layer 60 is not grown on the surface of the mask medium M.
[0138] Step S34: Refer to the reference Figure 14 and Figure 15 Remove the mask medium M.
[0139] Here, the process for removing the mask medium M includes wet etching. For example, HCl is used to etch and remove the mask medium M.
[0140] Step S4: Reference Figure 16 The first polarization enhancement layer 80 is formed.
[0141] The first polarization enhancement layer 80 is located on the surface of the barrier layer 40 away from the substrate 10, the surface of the modulation layer 60 away from the substrate, and the sidewall of the modulation layer 60.
[0142] Step S5: Reference Figure 17 A source 71 and a drain 72 are formed on the side of the barrier layer 40 away from the substrate 10. The source 71 and the drain 72 are respectively disposed on both sides of the cap layer 50 along the first direction X, and are respectively spaced from the cap layer 50. The first direction X is perpendicular to the thickness direction of the substrate 10.
[0143] The first polarization enhancement layer 80 is at least partially disposed between the cap layer 50 and the drain 72 and between the cap layer 50 and the source 71.
[0144] Here, step S5 includes:
[0145] Step S51: Reference Figure 17 The formation of the source electrode 71 and the drain electrode 72 also includes forming a first groove C1 and a second groove C2 on the side of the barrier layer 40 away from the substrate 10. The first groove C1 and the second groove C2 are respectively disposed on both sides of the cap layer 50 along the first direction X, and are respectively spaced from the cap layer 50. When the first polarization enhancement layer 80 is formed, the first groove C1 and the second groove C2 also penetrate the first polarization enhancement layer 80.
[0146] Here, the process for forming the first groove C1 and the second groove C2 includes an etching process. For example, a mixture of Cl2 and ClB3 gas is used to remove part of the first polarization enhancement layer 80 and the barrier layer 40.
[0147] Step S52: Continue to refer to Figure 17 This forms a source 71 and a drain 72, with the source 71 filling the first groove C1 and the drain 72 filling the second groove C2.
[0148] Here, the process for forming the source electrode 71 and the drain electrode 72 includes a sputtering process. The metal outside the regions of the source electrode 71 and the drain electrode 72 is removed by dry etching, and the source electrode 71 and the drain electrode 72 are then annealed in an N2 atmosphere.
[0149] Step S6: Continue to refer to Figure 18 A gate 70 is formed on the side of the modulation layer 60 away from the substrate 10.
[0150] Here, the process for forming the gate 70 includes a sputtering process. The metal outside the gate 70 region is then removed by dry etching.
[0151] When the first polarization enhancement layer 80 is formed, a gate 70 is formed on the side of the first polarization enhancement layer 80 away from the substrate 10, and the gate 70 overlaps with the orthogonal projection of the cap layer 50 onto the substrate 10.
[0152] In other embodiments, reference is made to... Figure 19 In step S3, a modulation layer 60 is formed on the side of the cap layer 50 away from the substrate 10, and the modulation layer 60 also covers the surface of the barrier layer 40 away from the substrate 10. That is, during the formation of the modulation layer 60, it is not necessary to form... Figure 13 In the mask medium M, the modulation layer 60 is grown on the surface of the barrier layer 40 away from the substrate 10.
[0153] exist Figure 19 Based on, refer to Figure 20 In step S4, a first polarization enhancement layer 80 is formed on the side of the modulation layer 60 away from the substrate 10.
[0154] In step S5, refer to Figure 21 The first groove C1 and the second groove C2 also penetrate the modulation layer 60.
[0155] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A channel layer and a barrier layer are stacked on the substrate in a direction away from the substrate; A cap layer is disposed on the side of the barrier layer away from the substrate; the cap layer is doped with a first acceptor; A gate is disposed on the side of the cap layer away from the substrate; The source and drain are respectively disposed on both sides of the cap layer along the first direction, and are respectively spaced apart from the cap layer; the first direction is perpendicular to the thickness direction of the substrate; A modulation layer is disposed at least between the gate and the cap layer; the modulation layer is doped with a first acceptor, and the concentration of the first acceptor in the modulation layer is lower than the concentration of the first acceptor in the cap layer; The materials of the modulation layer and the barrier layer both include aluminum-based nitrides, and the molar percentage of aluminum in the modulation layer is less than or equal to the molar percentage of aluminum in the barrier layer.
2. The semiconductor device according to claim 1, characterized in that, The modulation layer also covers at least a portion of the sidewalls of the cap layer.
3. The semiconductor device according to claim 2, characterized in that, The modulation layer covers the sidewall of the cap layer facing the source, and / or the sidewall of the cap layer facing the drain.
4. The semiconductor device according to claim 2, characterized in that, The modulation layer is also located between the cap layer and the drain, and is in contact with the surface of the barrier layer away from the substrate, and a first gap exists between the modulation layer and the drain.
5. The semiconductor device according to claim 4, characterized in that, The modulation layer is also located between the cap layer and the source electrode, and is in contact with the surface of the barrier layer away from the substrate.
6. The semiconductor device according to claim 5, characterized in that, One end of the modulation layer is in contact with the side of the source electrode near the cap layer, and the other end of the modulation layer is in contact with the side of the drain electrode near the cap layer.
7. The semiconductor device according to any one of claims 1 to 5, characterized in that, There is a first gap between the orthogonal projection of the modulation layer onto the substrate and the orthogonal projection of the drain onto the substrate, and a second gap between the orthogonal projection of the source onto the substrate; The semiconductor device further includes: a first polarization enhancement layer, at least a portion of which is disposed in the first gap and / or the second gap, and in contact with the surface of the barrier layer away from the substrate.
8. The semiconductor device according to claim 7, characterized in that, The first polarization enhancement layer covers the side of the modulation layer away from the substrate.
9. The semiconductor device according to claim 7, characterized in that, The materials of the first polarization enhancement layer and the barrier layer both include aluminum-based nitrides, and the molar percentage of aluminum in the first polarization enhancement layer is greater than or equal to the molar percentage of aluminum in the barrier layer.
10. The semiconductor device according to claim 1, characterized in that, The first acceptor includes magnesium, zinc, beryllium, or carbon.
11. A chip, characterized in that, include: The semiconductor device as described in any one of claims 1 to 10.