Preparation method of BC battery, BC electrode and BC battery assembly

Abstract

The invention relates to a preparation method of a BC battery, a BC electrode and a BC battery assembly, and belongs to the field of BC battery preparation. Depositing a tunneling oxide layer, a low-doped Poly and a first barrier layer on the surface of the silicon substrate; depositing heavily doped Poly on the first barrier layer for multiple times to form multiple layers of heavily doped Poly, and depositing a layer of intrinsic Poly between two adjacent layers of heavily doped Poly; after each time of heavily doped Poly deposition is finished, introducing hydrogen to remove a phosphorus source; a second barrier layer is deposited on the heavily doped Poly farthest from the silicon substrate, and phosphorus residues on the surface of the graphite boat are effectively reduced by introducing a middle intrinsic layer structure and cooperating with hydrogen cleaning and high-frequency plasma bombardment, so that boat printing defects are reduced, and the process stability and the product yield are improved.

Description

Technical Field

[0001] The present invention belongs to the field of BC battery preparation, and in particular relates to a BC battery preparation method, a BC electrode, and a BC battery assembly. Background Art

[0002] Back-contact (BC) cells, due to their lack of metal obstruction on the front, offer higher light absorption efficiency and have been widely researched and applied in high-efficiency crystalline silicon solar cells in recent years. In a BC structure, charge carriers must be transported laterally across the back of the cell to the electrodes. In addition to its passivation function, the poly-Si layer also serves as a conductive pathway.

[0003] To reduce series resistance (Rs) and transmission losses, BC cells typically require the deposition of a 200-400 nm thick poly-Si layer. BC cells based on p-type silicon wafers use a phosphorus-doped polysilicon (n-type Poly-Si) layer that can be thicker than 250 nm. However, thicker n-type Poly-Si layers can negatively impact wafer quality due to compressive stress caused by phosphorus doping and a mismatch in thermal expansion coefficients with the substrate.

[0004] Based on this, a preparation method of a BC battery, a BC electrode, and a BC battery assembly are proposed. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a BC battery preparation method, a BC electrode, and a BC battery assembly, which are used to reduce the compressive stress caused by phosphorus doping and the influence of the mismatch between the thermal expansion coefficient and the substrate.

[0006] To solve the above technical problems, the present invention is achieved through the following technical solutions: A method for preparing a BC battery, comprising: providing a silicon substrate; Depositing a tunneling oxide layer, a low-doped Poly layer and a first barrier layer on the surface of the silicon substrate; Depositing heavily doped Poly on the first barrier layer multiple times to form a multilayer heavily doped Poly, and depositing a layer of intrinsic Poly between two adjacent heavily doped Poly layers; After each heavy-doped Poly deposition, hydrogen is introduced to remove the phosphorus source; A second barrier layer is deposited on the heavily doped Poly layer farthest from the silicon substrate.

[0007] In another aspect, a BC battery is provided. The BC battery is prepared by the above-mentioned method for preparing a BC battery, and the BC battery comprises: Silicon substrate; a tunneling oxide layer, located on the first surface of the silicon substrate; The first lightly doped Poly: deposited on the tunnel oxide layer, is an N-type phosphorus-doped polysilicon layer; A first barrier layer: located on the first lightly doped polysilicon layer; Heavily doped Poly: Deposited on the first barrier layer, it is a highly phosphorus-doped N-type polysilicon layer; The heavily doped Poly layer is provided with one or more doped polysilicon layers which are transformed from the intrinsic Poly layer through annealing and diffusion.

[0008] On the other hand, a photovoltaic module is provided, including a BC battery prepared by using the above-mentioned preparation method of a BC battery or the above-mentioned BC battery. Beneficial effects

[0009] (1) The embodiment of the present disclosure introduces 1 to 3 intrinsic Poly layers into the multi-layer phosphorus-doped Poly structure. By reducing the internal stress caused by film stress and thermal expansion mismatch, it effectively suppresses the warping of silicon wafers caused by excessively thick phosphorus-doped layers, especially those with a thickness greater than 250 nm. This significantly reduces the risks of abnormalities such as cutting misalignment and annealing card caused by warping, and improves overall production stability and automation adaptability. (2) The embodiment of the present disclosure provides hydrogen flushing and high-frequency plasma bombardment cleaning steps after phosphorus-doped Poly deposition, which effectively removes the phosphorus source remaining on the surface of the graphite boat, significantly reduces the probability of boat print defects such as black corner pieces, improves the surface passivation effect of the next boat silicon wafer, and thus improves the overall yield and consistency of the battery cell; (3) The intrinsic Poly layer inserted in the embodiment of the present disclosure can serve as a phosphorus source buffer layer, allowing excess phosphorus in the upper and lower phosphorus-doped Poly layers to diffuse into the intrinsic layer during the subsequent annealing process, without weakening the lateral conductivity and at the same time alleviating stress accumulation; (4) The embodiment of the present disclosure removes phosphorus residues on the graphite boat by combining high-temperature hydrogen gas injection with high-frequency plasma bombardment, effectively reducing the accumulation of pollution in the next boat.

[0010] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 This is a flow chart of the method according to an embodiment of the present disclosure; Figure 2 This is an overall structural diagram of an embodiment of the present disclosure; Figure 3 This is a diagram of the heavily doped Poly structure according to an embodiment of the present disclosure; Figure 4 This is a picture of a BC battery with a bad boat print and black corners.

[0013] Figure numerals: silicon substrate-100, tunneling oxide layer-10, first lightly doped Poly-20, first barrier layer-30, heavily doped Poly-40, second barrier layer-50, first heavily doped polysilicon layer-401, first intrinsic polysilicon layer-402, second heavily doped polysilicon layer-403. DETAILED DESCRIPTION

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0015] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0016] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0017] In existing BC cells, to reduce series resistance (Rs) and improve fill factor, BC cells based on p-type silicon wafers use a phosphorus-doped polysilicon (n-type Poly-Si) layer, deposited to a thickness of 200 to 300 nm. However, thicker phosphorus-doped polysilicon layers can cause silicon wafer warping due to compressive stress caused by phosphorus doping and a mismatch in thermal expansion coefficient with the substrate.

[0018] To solve the above problems, the embodiments of the present application provide a method for preparing a BC battery, a BC electrode, and a BC battery assembly. By inserting 1 to 3 layers of intrinsic Poly with a thickness of 5 to 20 nm in the middle of phosphorus-doped poly, the thickness of the phosphorus-doped poly is generally 100 nm or even thinner after being divided. The thickness of the intrinsic Poly is significantly thinner than that of the phosphorus-doped poly. After subsequent annealing, phosphorus elements will diffuse into this layer of the phosphorus-doped poly. If this layer is too thick, it will affect the lateral transmission of the entire poly. At the same time, hydrogen is used to clean the phosphorus source introduced during the heavy doping process before the deposition of the intrinsic Poly. In this way, the middle intrinsic poly layer is set to be phosphorus-free, which can improve the warping after poly. Through annealing, the excess phosphorus sources in the heavy doped poly layers above and below the intrinsic layer can diffuse into this layer, thereby not affecting the lateral transmission capability.

[0019] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0020] like Figure 1 As shown, in some embodiments, a method for preparing a BC battery includes the following steps: Step S100, providing a silicon substrate; Specifically, the silicon substrate is a P-type silicon wafer.

[0021] Step S200, forming a deposited tunneling oxide layer on the surface of the silicon substrate; Specifically, the tunneling oxide layer is a silicon dioxide layer with a thickness of 1 to 2 nm.

[0022] Step S300, depositing a layer of low-doped Poly on the tunnel oxide layer; Specifically, the low-doped Poly layer is a lightly doped N-type Poly layer, specifically a phosphorus-doped polysilicon layer with a thickness of 10 to 30 nm, and 20 nm can be particularly selected.

[0023] Step S400, depositing a first barrier layer on the low-doped Poly; Specifically, the barrier layer is a silicon dioxide layer with a thickness of 0.5-1 nm.

[0024] Step S500, depositing a heavily doped Poly layer on the barrier layer; Specifically, the heavily-doped Poly layer is a heavily-doped N-type Poly layer, specifically a phosphorus-doped polysilicon layer, with a thickness of 50 to 150 nm.

[0025] Step S600, depositing a layer of intrinsic Poly on the barrier layer; Specifically, the thickness of the intrinsic Poly layer is 5 to 20 nm.

[0026] Step S700, depositing a layer of heavily doped Poly on the intrinsic Poly; Specifically, the heavily doped Poly layer is a heavily doped N-type Poly layer, specifically a phosphorus-doped polysilicon layer with a thickness of 50-150 nm. In some disclosures, the total thickness is 260nm, the lightly doped layer inside is 20nm, the outermost layer is 20, and the remaining 220nm. If the intrinsic layer is 20nm, the thickness of the two heavily doped layers separated is 100nm.

[0027] Step S800, depositing a second barrier layer on the heavily doped Poly; Specifically, the barrier layer is silicon dioxide or silicon oxynitride, and has a thickness of 5-30 nm.

[0028] Step S900: After the deposition process is completed, the air is evacuated, nitrogen is passed through to back pressure, and the poly-plated semi-finished product is taken out of the boat. The semi-finished product enters the annealing process for further processing.

[0029] Through this embodiment, a tunneling oxide layer, a lightly doped n-type polysilicon layer, a first barrier layer, a first heavily doped n-type polysilicon layer, an intrinsic non-doped polysilicon layer, and a second heavily doped n-type polysilicon layer are first deposited on a P-type silicon substrate, and finally a second barrier layer is formed. During the deposition process, an intrinsic polysilicon layer is inserted between the two heavily doped polysilicon layers, which can significantly reduce the accumulation of compressive stress in the film layer caused by phosphorus doping, suppress the warping of the silicon wafer, and avoid the occurrence of Figure 4 The boat print shown is bad.

[0030] The middle intrinsic poly layer does not contain phosphorus, which can improve the warping after poly. Through annealing, the excess phosphorus source of the heavily doped poly layers above and below the intrinsic layer can diffuse into this layer, thereby not affecting the lateral transmission capability.

[0031] It should be understood that in some embodiments, after completing step S700, steps S600 and S700 may be repeated multiple times as needed. In some specific embodiments, before depositing the tunnel oxide layer, the silicon wafer is first placed in a coating furnace tube of a PECVD device for heating, and the furnace tube temperature is 380° C. to 480° C.; Furthermore, lowering the temperature of the furnace tube is beneficial to reducing the warping of thick poly. The temperature is preferably 400° C. It is understandable that setting the temperature too low will affect the deposition rate.

[0032] In some specific embodiments, the specific steps of step S200 are as follows: after nitrogen filling, entering the boat, heating, constant temperature, evacuation, leak detection, and evacuation and pre-filling, the tunnel oxide layer is deposited, and the specific parameters are set within the following ranges: nitrous oxide flow rate 5000~20000Sccm, duration 70~120s, pressure 1200~2500mTorr, and power 8000W~18000W.

[0033] Preferably, the nitrous oxide flow rate is 10000 Sccm, the duration is 90 s, the pressure is 1900 mTorr, the power is 15000 W, and the thickness of the tunnel oxide layer is 1.5 nm.

[0034] In some specific embodiments, the specific parameters of step S300 are set within the following ranges: silane flow rate 2000 sccm to 5000 sccm, hydrogen flow rate 5000 to 20000 sccm, phosphine flow rate 50 to 400 sccm, pressure 2500 to 5000 mTorr, power 8000 W to 18000 W, and duration 100 to 300 s.

[0035] Preferably, the silane flow rate is 3000 sccm, the hydrogen flow rate is 10000 sccm, the phosphine flow rate is 200 sccm, the pressure is 3500 mTorr, the power is 10000 W, and the duration is 200 s.

[0036] In some specific embodiments, the specific parameters of step S400 are set within the following ranges: nitrous oxide flow rate 5000-20000 Sccm, duration 40-70 s, pressure 1200-2500 mTorr, and power 8000 W-18000 W.

[0037] Preferably, the nitrous oxide flow rate is 10000 Sccm, the duration is 60 s, the pressure is 2000 mTorr, and the power is 11000 W.

[0038] In some specific embodiments, the specific parameters of step S500 are set within the following ranges: silane flow rate 2000 sccm to 5000 sccm, hydrogen flow rate 5000 to 20000 sccm, phosphine flow rate 300 to 1000 sccm, pressure 2500 to 5000 mTorr, power 8000 W to 18000 W, and duration 300 to 600 s.

[0039] Preferably, the silane flow rate is 3500 sccm, the hydrogen flow rate is 10000 sccm, the phosphine flow rate is 600 sccm, the pressure is 3500 mTorr, the power is 11000 W, and the duration is 450 s.

[0040] In other embodiments, after step S500 is completed, hydrogen is introduced into the device to exhaust the phosphine, thereby facilitating the subsequent step S600 of depositing intrinsic Poly; Furthermore, the total amount of hydrogen gas introduced is substantially equivalent to 3 to 5 times the volume of the reaction gas in the furnace tube, and the time for introducing hydrogen is longer than 40 seconds, generally selected to be more than 120 seconds.

[0041] The specific parameter ranges are as follows: hydrogen flow rate 5000~20000Sccm, power 8000W~18000W, for a furnace tube with a length of 4.2m and a diameter of 0.54m, and a duration of 40~400s; at the same time, the pulse should also be turned on to facilitate the ionization of hydrogen to generate ions to bombard the phosphorus-containing substances attached to the graphite boat.

[0042] Hydrogen has a relatively low cost and good process compatibility. Hydrogen ions are mild and not prone to corroding the graphite boat. Hydrogen ions can react with phosphorus-containing Poly to generate gases or plasmas such as silane and phosphine or related ions. These reactants are pumped away by the vacuum pump, reducing phosphorus residue. Oxidizing gases easily react with carbon and thus damage the graphite boat. They also react with phosphorus to generate P2O5, which is difficult to volatilize, and the effect of removing phosphorus is not ideal.

[0043] In other embodiments, the specific parameters of step S600 are set within the following ranges: silane flow rate 2000 sccm to 5000 sccm, hydrogen flow rate 5000 to 20000 sccm, pressure 2500 to 5000 mTorr, power 8000 W to 18000 W, and duration 50 to 300 s. Intrinsic Poly can significantly reduce the compressive stress generated by the phosphorus-doped Poly layer. Preferably, the silane flow rate is 3500 sccm, the hydrogen flow rate is 1200 sccm, the pressure is 3500 mTorr, the power is 1300 W, and the duration is 150 s.

[0044] In some specific embodiments, the specific parameters of step S700 are set within the following ranges: silane flow rate 2000 sccm to 5000 sccm, hydrogen flow rate 5000 to 20000 sccm, phosphine flow rate 300 to 1000 sccm, pressure 2500 to 5000 mTorr, power 8000 W to 18000 W, and duration 300 to 600 s.

[0045] Preferably, the silane flow rate is 3500 sccm, the hydrogen flow rate is 13000 sccm, the phosphine flow rate is 700 sccm, the pressure is 4000 mTorr, the power is 12000 W, and the duration is 450 s.

[0046] In other embodiments, after step S700 is completed, hydrogen is introduced into the apparatus to exhaust the phosphine, thereby facilitating the deposition of a mask layer free of phosphorus. Furthermore, when hydrogen is introduced into the device, pulses are simultaneously turned on to reduce phosphorus-containing substances on the surface of the graphite boat through high temperature and ion bombardment, thereby preventing the graphite boat from having a negative impact on the semi-finished product when it is used next time.

[0047] In some disclosures, the specific parameter ranges are as follows: hydrogen flow rate 5000~20000Sccm, power 8000W~18000W, and duration 40%~100% of the re-doping process duration.

[0048] With this design, after the phosphorus-doped poly deposition process is completed and before the mask plating begins, hydrogen needs to be introduced and high frequency is turned on at the same time. Through high temperature and plasma bombardment, the phosphorus source deposited on the graphite boat is cleaned to avoid negative impact on the products of the next boat. The duration must be longer than 40% of the re-doping process duration. In addition, this process also ensures that the phosphorus content of the mask layer is greatly reduced, which can also improve the negative impact of phosphorus on the next boat.

[0049] In some specific embodiments, the specific parameters of step S800 are set within the following ranges: silane flow rate 1000 sccm to 5000 sccm, nitrous oxide flow rate 5000 to 20000 Sccm, duration 30 to 150 s, pressure 1200 to 2500 mTorr, and power 8000 W to 18000 W.

[0050] Preferably, the silane flow rate is 3000 sccm, the nitrous oxide flow rate is 12500 sccm, the duration is 85 s, the pressure is 2000 mTorr, and the power is 12000 W.

[0051] Compared with the existing technology in which BC cells use a single thick Poly-doped structure that easily causes serious silicon wafer warping and boat print contamination, this implementation scheme effectively reduces phosphorus residue on the surface of the graphite boat by introducing an intermediate intrinsic layer structure and coordinating it with hydrogen cleaning and high-frequency plasma bombardment, thereby reducing the occurrence of boat print defects and improving process stability and product yield; at the same time, by controlling the stress distribution of the film layer through multiple segmented deposition methods, a low-warping, low-defect, high-efficiency BC cell preparation process is achieved, providing technical support for the large-scale manufacturing of high-efficiency photovoltaic products.

[0052] The various process parameters involved in the above embodiments all provide recommended ranges or preferred values. It should be understood that these parameters are not uniquely bound to each other, but can be freely combined and matched within the ranges described based on factors such as actual equipment specifications, product structure design requirements, and process optimization goals.

[0053] Some other embodiments of the present disclosure are a BC battery, such as Figure 2 、 Figure 3 As shown, the above-mentioned BC battery is prepared by any of the above-mentioned BC battery preparation methods, and the BC battery includes: Silicon substrate 100; Tunneling oxide layer 10: located on the first surface of the silicon substrate, is a thin silicon dioxide or silicon oxynitride layer with a thickness of 1 to 2 nm, and is used to construct a selective tunneling interface for carriers.

[0054] The first lightly doped Poly20: deposited on the tunneling oxide layer, it is an N-type phosphorus-doped polysilicon layer used to provide good electron selective contact and low series resistance. The doping concentration is lower than the subsequent heavily doped layer.

[0055] The first barrier layer 30 is located on the first lightly doped polysilicon layer and is a layer of silicon dioxide or silicon oxynitride with a thickness of 0.5 to 1 nm. It is used to isolate phosphorus diffusion during the subsequent polysilicon layer deposition process and improve structural stability.

[0056] Heavily doped Poly40: Deposited on the first barrier layer, this layer is a highly phosphorus-doped N-type polysilicon layer, typically 200-300 nm thick, used to enhance electron selective conduction. Furthermore, the heavily doped Poly40 layer has a thickness of 250-300 nm, preferably 360 nm, and a phosphorus concentration of approximately 5E20.

[0057] The heavily doped Poly layer is provided with multiple layers of intrinsic Poly with a thickness of 5 to 20 nm, which is used to relieve the compressive stress in the film caused by the upper and lower layers of doped polysilicon, reduce the warping of the silicon wafer, and absorb the diffused phosphorus in the subsequent annealing to maintain the continuity of conduction.

[0058] The second barrier layer 50 is located on the heavily doped polysilicon layer and is a silicon dioxide or silicon oxynitride layer with a thickness of 5 to 30 nm. It is used to construct the final protective layer or dielectric interface.

[0059] In some specific embodiments, the heavily doped Poly40 structure is as follows: The first heavily doped polysilicon layer 401 is deposited on the first barrier layer and is a highly phosphorus-doped N-type polysilicon layer with a thickness of generally 100 to 150 nm. The first intrinsic polysilicon layer 402 is deposited on the first intrinsic polysilicon layer, with a thickness of 5 to 20 nm, preferably 10 nm.

[0060] The second heavily doped polysilicon layer 403 is deposited on the first intrinsic polysilicon layer and is a second highly phosphorus-doped N-type polysilicon layer with a thickness of 100-150 nm.

[0061] After annealing, the phosphorus elements in the first heavily doped polysilicon layer 401 and the second heavily doped polysilicon layer 403 diffuse into the first intrinsic polysilicon layer 402 to transform it into a doped polysilicon layer.

[0062] This BC battery introduces a multi-layer structure design and an intrinsic Poly sandwich structure, which greatly alleviates the film compressive stress and silicon wafer warping problems caused by heavily phosphorus-doped Poly, thereby improving product consistency and yield.

[0063] Other embodiments of the present disclosure are a photovoltaic module, including a BC battery prepared by the above-mentioned BC battery preparation method, or a BC battery with the above-mentioned structure. The photovoltaic module connects multiple BC battery units in series and parallel to form a module structure with high mechanical strength and excellent environmental adaptability.

[0064] In some embodiments, the BC battery comprises: Silicon substrate; Tunneling oxide layer: located on the first surface of the silicon substrate, with a thickness of 1 to 2 nm.

[0065] The first lightly doped Poly: deposited on the tunnel oxide layer, is an N-type phosphorus-doped polysilicon layer.

[0066] The first barrier layer is located on the first lightly doped polysilicon layer and is a layer of silicon dioxide or silicon oxynitride with a thickness of 0.5 to 1 nm.

[0067] Heavily doped Poly: Deposited on the first barrier layer, it is a highly phosphorus-doped N-type polysilicon layer with a thickness of generally 200 to 300 nm.

[0068] The heavily doped Poly layer is provided with one or more doped polysilicon layers, which are transformed from intrinsic Poly through annealing diffusion, with a thickness of 5 to 20 nm. This configuration is used to relieve the compressive stress in the film caused by the upper and lower layers of doped polysilicon, reduce silicon wafer warping, and at the same time, in subsequent annealing, the phosphorus element in the heavily doped Poly layer diffuses into the intrinsic Poly layer, transforming it into a doped polysilicon layer to maintain conductive continuity.

[0069] The second barrier layer is located on the heavily doped polysilicon layer and is a silicon dioxide or silicon oxynitride layer with a thickness of 5 to 30 nm.

[0070] Throughout this specification, references to terms such as "one embodiment," "example," or "specific example" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0071] The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for preparing a BC battery, characterized in that: include: providing a silicon substrate; Depositing a tunneling oxide layer, a low-doped Poly layer and a first barrier layer on the surface of the silicon substrate; Depositing heavily doped Poly on the first barrier layer multiple times to form a multilayer heavily doped Poly, and depositing a layer of intrinsic Poly between two adjacent heavily doped Poly layers; After each heavy-doped Poly deposition, hydrogen is introduced to remove the phosphorus source; A second barrier layer is deposited on the heavily doped Poly layer farthest from the silicon substrate.

2. The method for preparing a BC battery according to claim 1, characterized in that: The heavily doped Poly layer is a phosphorus-doped polysilicon layer, and the thickness of the heavily doped Poly layer between the first barrier layer and the second barrier layer is 200-400 nm.

3. The method for preparing a BC battery according to claim 1, characterized in that: Before depositing the tunnel oxide layer, the silicon substrate first enters the coating furnace tube of the PECVD equipment to heat up, and the furnace tube temperature is 380℃~480℃.

4. The method for preparing a BC battery according to claim 1, characterized in that: The thickness of the intrinsic Poly is 5 to 20 nm, and the number of layers is 1 to 3.

5. The method for preparing a BC battery according to claim 1, characterized in that: The total amount of hydrogen gas introduced before depositing intrinsic Poly is basically 3 to 5 times the amount of reaction gas in the furnace tube, and the time for introducing hydrogen is longer than 120s.

6. The method for preparing a BC battery according to claim 1, characterized in that: The duration of hydrogen introduction before depositing the second barrier layer is 40% to 100% of the general duration of the heavy doping process, and the high frequency is turned on at the same time.

7. The method for preparing a BC battery according to claim 1, characterized in that: Two layers of heavily doped Poly are arranged between the first barrier layer and the second barrier layer, and an intrinsic Poly is arranged between the two layers of heavily doped Poly.

8. A BC battery, characterized in that: The BC battery is prepared by the preparation method of a BC battery according to any one of claims 1 to 7, and the BC battery comprises: Silicon substrate; a tunneling oxide layer, located on the first surface of the silicon substrate; The first lightly doped Poly: deposited on the tunnel oxide layer, is an N-type phosphorus-doped polysilicon layer; A first barrier layer: located on the first lightly doped polysilicon layer; Heavily doped Poly: Deposited on the first barrier layer, it is a highly phosphorus-doped N-type polysilicon layer; The heavily doped Poly layer is provided with one or more doped polysilicon layers which are transformed from the intrinsic Poly layer through annealing and diffusion.

9. A BC battery according to claim 1, characterized in that: The thickness of heavily doped Poly is 200 to 400 nm.

10. A photovoltaic module, characterized in that: It includes preparing a BC battery using the preparation method of a BC battery described in any one of claims 1 to 7, or the BC battery described in claim 8 or 9.

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