Heterojunction solar cells and their fabrication methods, photovoltaic modules

Abstract

This invention relates to the field of solar cells, and discloses a heterojunction solar cell and its fabrication method, as well as a photovoltaic module. It includes: a silicon substrate; a first intrinsic passivation layer disposed on the light-receiving surface of the silicon substrate, the first intrinsic passivation layer being divided into a first region, a second region, and an isolation region between the two regions; a patterned first doped layer disposed on the first intrinsic passivation layer in the first region; the first doped layer containing a dopant element; a patterned antireflection layer disposed on the first intrinsic passivation layer in the second region, the first doped layer and the antireflection layer being separated by the isolation region; the antireflection layer containing a specified element, the specified element belonging to the same group as the dopant element in the first doped layer; and a patterned first transparent conductive layer disposed on the first doped layer. The heterojunction solar cell of this application, while ensuring high solar energy utilization, can suppress the entry of the specified element from the antireflection layer into the first doped layer.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a heterojunction solar cell and its preparation method, as well as a photovoltaic module. Background Technology

[0002] As the core device for converting sunlight into electrical energy, the efficiency of sunlight utilization is a key factor affecting the performance of heterojunction solar cells. Therefore, improving heterojunction solar cells to enhance light utilization is an important way to promote the advancement of photovoltaic technology.

[0003] In the process of improving heterojunction solar cells, light utilization can be improved by adding new functional layers. However, the newly added functional layers may affect the performance of other layers in the heterojunction solar cell. For example, they may affect the electrical performance of the doped layers in the heterojunction solar cell, leading to the degradation of the performance of the doped layers. Summary of the Invention

[0004] This invention discloses a heterojunction solar cell and its fabrication method, as well as a photovoltaic module. This heterojunction solar cell can reduce the influence of a specified element in the antireflection layer on the first doped layer while ensuring high solar energy utilization.

[0005] In a first aspect, embodiments of this application disclose a heterojunction solar cell, the heterojunction solar cell comprising:

[0006] Silicon substrate;

[0007] The first intrinsic passivation layer is disposed on the light-receiving surface of the silicon substrate, and the first intrinsic passivation layer is divided into a first region, a second region, and an isolation region located between the first region and the second region.

[0008] A patterned first doped layer is disposed on the surface of the first intrinsic passivation layer away from the silicon substrate, and the position of the first doped layer corresponds to the first region; the first doped layer contains doping elements.

[0009] A patterned antireflection layer is disposed on the surface of the first intrinsic passivation layer away from the silicon substrate, and the position of the antireflection layer corresponds to the second region. The first doped layer and the antireflection layer are separated by the isolation region. The antireflection layer has a specified element, which belongs to the same main group as the doping element of the first doped layer.

[0010] A patterned first transparent conductive layer is disposed on the side surface of the first doped layer opposite to the silicon substrate.

[0011] Furthermore, along the thickness direction of the silicon substrate, the orthographic projection width of the isolation region is D, where D satisfies: 0 mm < D ≤ 0.26 mm.

[0012] Further, along the thickness direction of the silicon substrate, the orthogonal projection width of the first doped layer on the silicon substrate is 0.025 mm to 1.0 mm; and / or,

[0013] Along the thickness direction of the silicon substrate, the width of the antireflection layer projected onto the silicon substrate is 0.5 mm to 1.1 mm; and / or,

[0014] The antireflection layer is thicker than the first doped layer.

[0015] Furthermore, the thickness of the antireflection layer is 75 nm to 100 nm.

[0016] Furthermore, the specified element includes nitrogen, and the first doped layer is an N-type doped layer.

[0017] Furthermore, along the direction from the silicon substrate to the first intrinsic passivation layer, the antireflection layer sequentially comprises a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer;

[0018] Wherein, the thickness of the silicon nitride layer is 15 nm to 20 nm; and / or,

[0019] The uniformity of the thickness of the silicon nitride layer is less than 4%; and / or,

[0020] The refractive index of the silicon nitride layer is 1.9~1.95; and / or,

[0021] The uniformity of the refractive index of the silicon nitride layer is less than 0.6%; and / or,

[0022] The silicon nitride layer has an extinction coefficient of 1.2 × 10⁻⁶ at a wavelength of 250 nm. -13 ~5.0×10 -8 ; and / or,

[0023] The thickness of the silicon oxynitride layer is 10 nm to 15 nm; and / or,

[0024] The uniformity of the thickness of the silicon oxynitride layer is less than 4%; and / or,

[0025] The refractive index of the silicon oxynitride layer is 1.7~1.75; and / or,

[0026] The uniformity of the refractive index of the silicon oxynitride layer is less than 0.6%; and / or,

[0027] The extinction coefficient of the silicon oxynitride layer at a wavelength of 250 nm is 0~1.56×10⁻⁶. -13 ; and / or,

[0028] The thickness of the silicon oxide is 50 nm to 65 nm; and / or,

[0029] The uniformity of the thickness of the silicon oxide is less than 4%; and / or,

[0030] The refractive index of the silicon oxide layer is 1.5~1.55; and / or,

[0031] The uniformity of the refractive index of the silicon oxide layer is less than 0.6%; and / or,

[0032] The extinction coefficient of the silicon oxide layer is 0 at a wavelength of 250 nm.

[0033] Furthermore, the first doped layer includes a first doped silicon layer close to the silicon substrate and a second doped silicon layer located on the side of the first doped silicon layer away from the silicon substrate;

[0034] The doping concentration of the second doped silicon layer is higher than that of the first doped silicon layer.

[0035] Furthermore, the heterojunction solar cell also includes:

[0036] The second intrinsic passivation layer is disposed on the back surface of the silicon substrate. The second intrinsic passivation layer includes a first thickness region and a second thickness region. The second thickness region is a thickness reduction region relative to the first thickness region, so that the second intrinsic passivation layer in the second thickness region forms a recessed structure.

[0037] A patterned second doped layer is disposed on the surface of the second intrinsic passivation layer away from the silicon substrate, and the position of the second doped layer corresponds to the second thickness region. The second doped layer has an opposite conductivity type to the first doped layer.

[0038] A patterned second transparent conductive layer is disposed on the side surface of the second doped layer opposite to the silicon substrate.

[0039] Furthermore, the second intrinsic passivation layer includes a first passivation layer stacked together and a patterned second passivation layer. The first passivation layer is disposed on the back surface of the silicon substrate, and the second passivation layer is disposed on the side of the first passivation layer facing away from the silicon substrate, and the second passivation layer is located in the first thickness region.

[0040] The thickness of the second passivation layer is 3 mm to 5 mm, and the thickness of the first passivation layer is 6 mm to 12.5 mm.

[0041] Furthermore, along the direction from the silicon substrate to the second intrinsic passivation layer, the first portion of the passivation layer sequentially includes a first passivation sublayer, a second passivation sublayer, and a third passivation sublayer;

[0042] Wherein, the thickness of the first passivation sublayer is 1 nm to 2.5 nm; and / or,

[0043] The structure factor of the first passivation sublayer is 65%~75%; and / or,

[0044] The thickness of the second passivation sublayer is 2 nm to 4 nm; and / or,

[0045] The structure factor of the second passivation sublayer is 30%~50%; and / or,

[0046] The thickness of the third passivation sublayer is 3 nm to 6 nm; and / or,

[0047] The structure factor of the third passivation sublayer is 5% to 25%.

[0048] Further, along the thickness direction of the silicon substrate, the orthographic projection width of the first thickness region on the silicon substrate is 0.5 mm to 1.2 mm; and / or,

[0049] Along the thickness direction of the silicon substrate, the width of the second doped layer projected onto the silicon substrate is 0.047 mm to 1.41 mm.

[0050] Furthermore, the first doped layer is an N-type doped layer, the second doped layer is a P-type doped layer, and along the thickness direction of the silicon substrate, the orthogonal projection width of the N-type doped layer on the silicon substrate is smaller than the orthogonal projection width of the P-type doped layer on the silicon substrate.

[0051] Furthermore, along the thickness direction of the silicon substrate, the orthographic projection pattern formed by the N-type doped layer and the isolation regions located on both sides of the N-type doped layer coincides with the orthographic projection pattern of the P-type doped layer.

[0052] Furthermore, the second doped layer includes a third doped silicon layer near the silicon substrate and a fourth doped silicon layer disposed on the side of the third doped silicon layer away from the silicon substrate; wherein the doping concentration of the fourth doped silicon layer is higher than that of the third doped silicon layer.

[0053] Secondly, this application discloses a method for fabricating a heterojunction solar cell, which includes the following steps:

[0054] A first intrinsic passivation layer is prepared on the light-receiving surface of a silicon substrate, wherein the first intrinsic passivation layer has a first region, a second region, and an isolation region located between the first region and the second region;

[0055] A patterned first doped layer is prepared on the first intrinsic passivation layer in the first region, and the first doped layer contains doping elements;

[0056] A patterned antireflection layer is fabricated on the first intrinsic passivation layer in the second region, the antireflection layer being separated from the first doped layer by the isolation region; the antireflection layer has a specified element, the specified element being an element belonging to the same main group as the doping element of the first doped layer;

[0057] A patterned first transparent conductive layer is fabricated on the first doped layer;

[0058] Post-processing yields the heterojunction solar cell.

[0059] Further, the first doped layer includes a first doped silicon layer and a second doped silicon layer, and the step of preparing the first doped layer includes:

[0060] The first doped silicon layer is prepared on the first intrinsic passivation layer in the first region;

[0061] A second doped silicon layer is prepared on the first doped silicon layer, wherein the doping concentration of the second doped silicon layer is higher than that of the first doped silicon layer.

[0062] Further, the antireflection layer comprises a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and the step of preparing the antireflection layer using plate-type PECVD includes:

[0063] The silicon nitride layer is prepared on the first intrinsic passivation layer in the second region:

[0064] The silicon oxynitride layer is prepared on the silicon nitride layer;

[0065] The silicon oxide layer is prepared on the silicon oxynitride layer;

[0066] The preparation parameters for the silicon nitride layer include: a SiH4 flow rate of 600 sccm~700 sccm, a H2 flow rate of 12000 sccm~14000 sccm, an NH3 flow rate of 1500 sccm~2100 sccm, a N2 flow rate of 1000 sccm~2000 sccm, a heating plate spacing of 35 mm~45 mm, a pressure of 300 Pa~400 Pa, a power of 10.0 kW~11.5 kW, an ignition time of 50 s~60 s, a heating plate temperature of 200 ℃~220 ℃, and a deposition rate of 1.0 A / s~1.5 A / s; and / or,

[0067] The preparation parameters for the silicon oxynitride layer include: a SiH4 flow rate of 300 sccm to 400 sccm, a H2 flow rate of 6000 sccm to 8000 sccm, a NH3 flow rate of 1000 sccm to 1600 sccm, a N2O flow rate of 300 sccm to 400 sccm, a heating plate spacing of 35 mm to 45 mm, a pressure of 200 Pa to 350 Pa, a power of 9.0 kW to 10.5 kW, an ignition time of 20 s to 30 s, a heating plate temperature of 200 ℃ to 220 ℃, and a deposition rate of 1.0 A / s to 1.5 A / s; and / or,

[0068] The preparation parameters for the silicon oxide layer include: a SiH4 flow rate of 200 sccm to 300 sccm, a H2 flow rate of 2000 sccm to 3000 sccm, a N2O flow rate of 200 sccm to 300 sccm, a heating plate spacing of 35 mm to 45 mm, a pressure of 100 Pa to 150 Pa, a power of 3.0 kW to 4.5 kW, an ignition time of 50 s to 60 s, a heating plate temperature of 200℃ to 220℃, and a deposition rate of 1.0 A / s to 1.5 A / s.

[0069] Furthermore, the preparation method further includes:

[0070] A first passivation layer and a patterned second passivation layer are prepared on the back surface of the silicon substrate to form a second intrinsic passivation layer with a thickness reduction region, wherein the thickness reduction region is a region without the second passivation layer.

[0071] A patterned second doped layer is prepared on the first portion of the passivation layer in the thickness reduction region;

[0072] The first passivation layer is prepared before the first doped layer is prepared.

[0073] The fabrication of the patterned second portion of the passivation layer and the fabrication of the second doped layer are performed after the fabrication of the first doped layer and before the fabrication of the antireflection layer.

[0074] Further, the first passivation layer includes a first passivation sublayer, a second passivation sublayer, and a third passivation sublayer, and the steps for preparing the first passivation layer include:

[0075] The first passivation sublayer is prepared on the backlight surface of the silicon substrate;

[0076] The second passivation sublayer is prepared on the first passivation sublayer;

[0077] The third passivation sublayer is prepared on the second passivation sublayer.

[0078] Furthermore, the preparation parameters for the first passivation sublayer include: the process gas comprises SiH4 and N2O, with a SiH4 to N2O flow ratio of 1:1 to 1:5; the gas pressure is 40 Pa to 90 Pa; the ignition power is 1200 W to 1600 W; and the ignition time is 2 s to 4 s; and / or,

[0079] When preparing the second passivation sublayer, the preparation parameters include: the process gas includes SiH4 and H2, and the flow ratio of SiH4 to H2 is 1:1 to 1:5; the gas pressure is 40 Pa to 90 Pa; the ignition power is 800 W to 1200 W; and the ignition time is 4 s to 6 s; and / or,

[0080] When preparing the third passivation sublayer, the preparation parameters include: the process gas includes SiH4 and H2, and the flow ratio of SiH4 and H2 is 1:1 to 1:5; the gas pressure is 40 Pa to 90 Pa; the ignition power is 600 W to 800 W; and the ignition time is 40 s to 60 s.

[0081] Furthermore, when preparing the second passivation layer, the preparation parameters include: the process gas includes SiH4 and H2, and the flow ratio of SiH4 and H2 is 1:1 to 1:5, the gas pressure is 40 Pa to 90 Pa, the ignition power is 600 W to 800 W, and the ignition time is 40 s to 60 s.

[0082] Further, the second doped layer includes a third doped silicon layer and a fourth doped silicon layer, and the step of fabricating a patterned second doped layer on the first portion of the passivation layer in the thickness reduction region includes:

[0083] The third doped silicon layer is prepared on the first portion of the passivation layer in the thickness reduction region;

[0084] The fourth doped silicon layer is prepared on the third doped silicon layer, wherein the doping concentration of the fourth doped silicon layer is higher than that of the third doped silicon layer.

[0085] Furthermore, a second doped layer is disposed on the backlight surface of the silicon substrate, and the post-processing steps include:

[0086] A patterned second transparent conductive layer is fabricated on the second doped layer;

[0087] A first electrode is fabricated on the side of the first transparent conductive layer opposite to the silicon substrate;

[0088] A second electrode is fabricated on the side of the second transparent conductive layer opposite to the silicon substrate.

[0089] Thirdly, embodiments of this application disclose a photovoltaic module, the photovoltaic module comprising: a heterojunction solar cell as described in any one of the first aspects, or a heterojunction solar cell prepared by the preparation method described in the second aspect.

[0090] Compared with the prior art, the beneficial effects of this application are as follows:

[0091] This application provides a heterojunction solar cell and its fabrication method, as well as a photovoltaic module. The silicon substrate has a first intrinsic passivation layer sequentially disposed on its light-receiving surface. A patterned first doped layer and a patterned antireflection layer are then disposed on the first intrinsic passivation layer. These patterned first doped layer and antireflection layer significantly improve the absorption and utilization efficiency of sunlight. Furthermore, because the first doped layer and the antireflection layer are separated by an isolation region, the isolation region inhibits the entry of specific elements from the antireflection layer into the first doped layer, thus preventing any adverse effects on the first doped layer. In other words, the heterojunction solar cell of this application ensures high sunlight utilization while reducing the impact of specific elements in the antireflection layer on the first doped layer.

[0092] Specifically, the first intrinsic passivation layer of this application has a first region, a second region, and an isolation region located between the first region and the second region. A patterned first doped layer is disposed on the first intrinsic passivation layer in the first region, and a patterned antireflection layer is disposed on the first intrinsic passivation layer in the second region. Therefore, the isolation region can play an isolating role, preventing the antireflection layer from contacting the first doped layer. This effectively blocks the specified elements in the antireflection layer from entering the first doped layer, preventing the specified elements in the same main group as the doped elements from affecting the performance of the first doped layer. This ensures the performance of the first doped layer to a high degree, thereby helping to improve the performance of heterojunction solar cells.

[0093] Furthermore, the patterned first doped layer in this application helps reduce parasitic absorption in the first doped layer, thereby improving the light utilization efficiency of the heterojunction solar cell. In addition, by setting a patterned first transparent conductive layer and a patterned antireflection layer next to the patterned first transparent conductive layer and the first doped layer, the light absorption and utilization efficiency of the antireflection layer is higher than that of the first transparent conductive layer. Therefore, through the synergistic effect of the first transparent conductive layer and the antireflection layer, the light absorption and utilization efficiency is further improved. Attached Figure Description

[0094] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0095] Figure 1 This is a schematic diagram of the structure of a heterojunction solar cell provided in an embodiment of this application;

[0096] Figure 2 This is a schematic diagram of the structure of a solar cell containing an enlarged view of the first intrinsic passivation layer provided in the embodiments of this application;

[0097] Figure 3 This is a schematic diagram of the structure of the first antireflection layer and the first doped layer provided in the embodiments of this application;

[0098] Figure 4 This is a schematic diagram of the structure of the second antireflection layer and the first doped layer provided in the embodiments of this application;

[0099] Figure 5 This is a schematic diagram of the third type of antireflection layer and the first doped layer provided in the embodiments of this application;

[0100] Figure 6 This is a schematic diagram of the structure of a solar cell containing a first doped silicon layer, as provided in the embodiments of this application.

[0101] Figure 7 This is a schematic diagram of the structure of the back surface of a solar cell provided in an embodiment of this application;

[0102] Figure 8 This is a schematic diagram of the structure of a solar cell containing an enlarged view of the first part of the passivation layer, provided in an embodiment of this application;

[0103] Figure 9 This is a schematic diagram of the structure of the second type of solar cell provided in the embodiments of this application;

[0104] Figure 10This is a schematic diagram of the structure of a solar cell containing a third doped silicon layer, as shown in the embodiment of this application.

[0105] Icons: 1. Silicon substrate; 2. First intrinsic passivation layer; 21. First region; 22. Second region; 23. Isolation region; 2a. First sublayer; 2b. Second sublayer; 2c. Third sublayer; 2d. Fourth sublayer; 3. First doped layer; 31. First doped silicon layer; 311. First doped sublayer; 312. Second doped sublayer; 313. Third doped sublayer; 32. Second doped silicon layer; 4. Antireflection layer; 41. Silicon nitride layer; 42. Silicon oxynitride layer; 43. Silicon oxide layer; 5. First transparent layer 6. Conductive layer; 7. First electrode; 8. Second intrinsic passivation layer; 9. First thickness region; 10. Second thickness region; 11. First partial passivation layer; 12. First passivation sublayer; 13. Second passivation sublayer; 14. Third passivation sublayer; 15. Second passivation sublayer; 16. Second doped layer; 17. Third doped silicon layer; 18. Fourth doped sublayer; 19. Fifth doped sublayer; 10. Sixth doped sublayer; 11. Fourth doped silicon layer; 12. Second transparent conductive layer; 13. Second electrode. Detailed Implementation

[0106] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0107] In this invention, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to be constructed and operated in a specific orientation.

[0108] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0109] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, components, or parts (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, components, or parts. Unless otherwise stated, "a plurality of" means two or more.

[0110] The technical solutions provided by the present invention will be further described below with reference to the embodiments and accompanying drawings.

[0111] For heterojunction solar cells, improving the absorption and utilization rate of sunlight is a key parameter for enhancing the performance of heterojunction solar cells. To improve the absorption and utilization rate of sunlight, one can reduce the parasitic absorption of the doped layer to improve the absorption and utilization rate of sunlight; on the other hand, one can reduce the reflectivity of sunlight to improve the absorption and utilization rate of sunlight.

[0112] Therefore, setting patterned doped layers can reduce parasitic absorption in the doped layers, thereby improving the absorption and utilization rate of sunlight. Additionally, by adding other functional layers, such as antireflection layers, next to the doped layers, the reflectivity of sunlight can be reduced, further improving the absorption and utilization rate. However, the applicant's research found that the added functional layers undergo a coating-around phenomenon during fabrication. Furthermore, since these functional layers may contain elements that affect the performance of the doped layers (i.e., elements in the same group as the dopant elements in the doped layers), these elements from the coating-around layer can enter the doped layers, resulting in impaired electrical performance and hindering the effective improvement of heterojunction solar cell performance.

[0113] Based on the above problems, this application provides a heterojunction solar cell and its preparation method, as well as a photovoltaic module. Under the action of the isolation region, the heterojunction solar cell can suppress the entry of specified elements in the antireflection layer into the first doped layer, thereby helping to ensure the electrical performance of the doped layer.

[0114] The first aspect, such as Figure 1 As shown in the figure, this application discloses a heterojunction solar cell, which includes:

[0115] Silicon substrate 1;

[0116] The first intrinsic passivation layer 2 is disposed on the light-receiving surface of the silicon substrate 1. The first intrinsic passivation layer 2 is divided into a first region 21, a second region 22 and an isolation region 23 located between the first region 21 and the second region 22.

[0117] A patterned first doped layer 3 is disposed on the surface of the first intrinsic passivation layer 2 away from the silicon substrate 1, and the position of the first doped layer 3 corresponds to the first region 21; the first doped layer 3 contains doped elements.

[0118] A patterned antireflection layer 4 is disposed on the surface of the first intrinsic passivation layer 2 away from the silicon substrate 1, and the position of the antireflection layer 4 corresponds to the second region 22. The first doped layer 3 and the antireflection layer 4 are separated by an isolation region 23. The antireflection layer 4 has a specified element, which belongs to the same main group as the doping element of the first doped layer 3.

[0119] A patterned first transparent conductive layer 5 is disposed on the side surface of the first doped layer 3 facing away from the silicon substrate 1.

[0120] In one optional embodiment, the first doped layer 3 is an N-type doped layer, and the doping element includes one of phosphorus, arsenic, and antimony, while the specified element in the antireflection layer 4 includes nitrogen. In another optional embodiment, the second doped layer 8 is a P-type doped layer, and the doping element includes one of boron, gallium, and indium, while the specified element in the antireflection layer 4 includes aluminum. Preferably, when the first doped layer 3 is an N-type doped layer and the doping element is phosphorus, it is more conducive to improving the performance of the first doped layer 3.

[0121] This application helps reduce parasitic absorption of the first doped layer 3 by providing a patterned first doped layer 3 on the first region 21 of the first intrinsic passivation layer 2. Furthermore, the antireflection layer 4 has a higher absorption and utilization rate of sunlight compared to the first transparent conductive layer 5. Therefore, in order to further improve the absorption and utilization rate of sunlight, this application provides an antireflection layer 4 on the second region 22 of the first intrinsic passivation layer 2 and a patterned first transparent conductive layer 5 on the first doped layer 3. Thus, through the synergistic effect of the antireflection layer 4 and the first transparent conductive layer 5, the absorption and utilization rate of sunlight can be further improved.

[0122] Furthermore, since the specified element in the antireflection layer 4 and the dopant element in the first doped layer 3 belong to the same main group, the specified element will affect the performance of the first doped layer 3. Therefore, in order to prevent the specified element from entering the first doped layer 3, this application also provides an isolation region 23 between the first region 21 and the second region 22. The isolation region 23 has the effect of isolation, preventing the antireflection layer 4 from contacting the first doped layer 3, thereby effectively blocking the specified element in the antireflection layer 4 from entering the first doped layer 3, preventing the specified element from affecting the performance of the first doped layer 3, thereby ensuring the performance of the first doped layer 3 to a higher extent and improving the performance of the heterojunction solar cell.

[0123] Furthermore, since the patterned first transparent conductive layer 5 is directly located on the first doped layer 3, the first transparent conductive layer 5 will not directly contact the first intrinsic passivation layer 2. That is, only the first intrinsic passivation layer 2 is provided on the isolation region 23, thereby avoiding damage to the first intrinsic passivation layer 2 by the first transparent conductive layer 5 and ensuring the passivation effect of the first intrinsic passivation layer 2 to a high degree.

[0124] In summary, this application, by setting a patterned antireflection layer 4, a patterned first doped layer 3, and a patterned first transparent conductive layer 5, helps to significantly improve the absorption and utilization rate of sunlight. Furthermore, by setting an isolation region 23 between the antireflection layer 4 and the first doped layer 3, it can effectively block designated elements in the antireflection layer 4 from entering the first doped layer 3, ensuring the performance of the first doped layer 3, and thus contributing to the improvement of the performance of heterojunction solar cells.

[0125] The doped layer includes at least one of a doped microcrystalline silicon layer, a doped polycrystalline silicon layer, and a doped amorphous silicon layer. Preferably, the doped layer is a doped microcrystalline silicon layer.

[0126] Furthermore, the material of the first intrinsic passivation layer 2 includes an intrinsic amorphous silicon layer, such as... Figure 2 As shown, and along the direction from the silicon substrate 1 to the first intrinsic passivation layer 2 (see...). Figure 2 In the Y1 direction, the first intrinsic passivation layer 2 sequentially includes a first sublayer 2a, a second sublayer 2b, a third sublayer 2c, and a fourth sublayer 2d; wherein, the thickness of the first sublayer 2a is 1 nm to 2.5 nm and the structure factor is 65% to 75%; the thickness of the second sublayer 2b is 2 nm to 4 nm and the structure factor is 30% to 50%; the thickness of the third sublayer 2c is 3 nm to 6 nm and the structure factor is 5% to 25%; and the fourth sublayer 2d is a hydrogenated passivation layer.

[0127] By controlling the thickness and structure factor of the first sublayer 2a within the aforementioned range, the film density of the first sublayer 2a is improved, thereby contributing to a higher degree of prevention of epitaxial growth. The thickness and structure factor of the second sublayer 2b are also within the aforementioned range, allowing the second sublayer 2b to react with unreacted groups in the first sublayer 2a, thus reducing the accumulation of yellow powder. The third sublayer 2c, as the main passivation layer, has its thickness and structure factor controlled within the aforementioned range, further ensuring the passivation effect of the third sublayer 2c. The fourth sublayer 2d is a hydrogenated passivation layer, thus exhibiting good contact with the first doped layer 3, which helps optimize carrier transport at the interface.

[0128] Furthermore, along the thickness direction of silicon substrate 1 (see...) Figure 1The width of the positive projection of the isolation region 23 (in the Y direction) is D, where D satisfies: 0 mm < D ≤ 0.26 mm. When D is within this range, the influence of the specified elements in the antireflection layer 4 on the electrical performance of the first doped layer 3 can be further avoided; moreover, within this width range, it also helps to ensure that the widths of the first doped layer 3 and the antireflection layer 4 are appropriate. Therefore, the first doped layer 3 can effectively exert its conductivity while reducing parasitic absorption, and the antireflection layer 4 can exert its antireflection effect to a high degree, thereby helping to further improve the performance of the heterojunction solar cell. For example, D is 0.02 mm, 0.1 mm, 0.15 mm, 0.2 mm, 0.26 mm, etc.

[0129] Furthermore, along the thickness direction of the silicon substrate 1, the orthographic projection width of the first doped layer 3 on the silicon substrate 1 is 0.025 mm to 1.0 mm. When the orthographic projection width of the first doped silicon layer 31 is within the above range, it helps to further reduce the parasitic absorption of the first doped layer 3 and further improve the absorption and utilization rate of sunlight. For example, the orthographic projection width of the first doped layer 3 is 0.025 mm, 0.25 mm, 0.5 mm, 0.75 mm, 1.0 mm, etc.

[0130] Furthermore, along the thickness direction of the silicon substrate 1, the orthographic projection width of the antireflection layer 4 on the silicon substrate 1 is 0.5 mm to 1.1 mm. When the orthographic projection width of the antireflection layer 4 is within the above range, it helps to further improve the utilization rate of sunlight; and it can also effectively reduce the diffusion content of the specified elements in the antireflection layer 4 into the first doped layer 3, thereby helping to further ensure the performance of the first doped layer 3. For example, the orthographic projection width of the antireflection layer 4 is 0.5 mm, 0.65 mm, 0.75 mm, 0.85 mm, 1.1 mm, etc.

[0131] In the first alternative implementation, such as Figure 3 As shown, the thickness of the antireflection layer 4 is smaller than the thickness of the first doped layer 3; as Figure 4 As shown, in the second optional embodiment, the thickness of the antireflection layer 4 is equal to the thickness of the first doped layer 3; as Figure 5 As shown, in the third optional embodiment, the thickness of the antireflection layer 4 is thicker than the thickness of the first doped layer 3. In this case, since the thickness of the antireflection layer 4 is higher than that of the doped layer, the antireflection layer 4 helps to block impurities such as water vapor and acid gas from laterally diffusing to the side of the first doped layer 3, reducing the probability of impurities contacting the first doped layer 3, thereby helping to ensure the stability of the first doped layer 3 to a higher degree.

[0132] Furthermore, the thickness of the antireflection layer 4 is 75 nm to 100 nm. The thickness of the antireflection layer 4 not only affects the content of the specified element within it, but also affects the antireflection effect of the antireflection layer 4. Therefore, when the thickness is within the above range, the antireflection effect of the antireflection layer 4 is further improved. By setting an isolation region 23 between the antireflection layer 4 and the first doped layer 3, the influence of the specified element on the first doped layer 3 is avoided. For example, the thickness of the antireflection layer 4 is 75 nm, 77 nm, 85 nm, 95 nm, 100 nm, etc.

[0133] Further, see the return Figure 1 Along the direction from the silicon substrate 1 to the first intrinsic passivation layer 2, the antireflection layer 4 sequentially includes a silicon nitride layer 41, a silicon oxynitride layer 42, and a silicon oxide layer 43.

[0134] The thickness of silicon nitride layer 41 is 15 nm to 20 nm, and the uniformity of its thickness is less than 4%. The thickness of silicon oxynitride layer 42 is 10 nm to 15 nm, and the uniformity of its thickness is less than 4%. The thickness of silicon oxide is 50 nm to 65 nm, and the uniformity of its thickness is less than 4%. When the thickness and uniformity of silicon nitride layer 41, silicon oxynitride layer 42, and silicon oxide layer 43 are within the above ranges, it indicates a high degree of film matching, which helps to improve the absorption and utilization rate of sunlight. Furthermore, this thickness also helps to control the content of specified elements in antireflection layer 4, thereby reducing the interference of specified elements in antireflection layer 4 on the first doped layer 3, and thus helping to further improve the effect of the first doped layer 3.

[0135] The refractive index of silicon nitride layer 41 is 1.9~1.95; the uniformity of the refractive index of silicon nitride layer 41 is less than 0.6%; the refractive index of silicon oxynitride layer 42 is 1.7~1.75; the uniformity of the refractive index of silicon oxynitride layer 42 is less than 0.6%; the refractive index of silicon oxide layer 43 is 1.5~1.55; the uniformity of the refractive index of silicon oxide layer 43 is less than 0.6%. When the refractive indices and refractive index uniformity of silicon nitride layer 41, silicon oxynitride layer 42, and silicon oxide layer 43 are within the above ranges, it helps to reduce the reflectivity of sunlight to a greater extent, thereby further improving the absorption and utilization rate of sunlight.

[0136] The extinction coefficient of silicon nitride layer 41 at a wavelength of 250 nm is 1.2 × 10⁻⁶. -13 ~5.0×10 -8 The extinction coefficient of silicon oxynitride layer 42 at a wavelength of 250 nm is 0~1.56×10⁻⁶. -13The extinction coefficient of silicon oxide layer 43 is 0 at a wavelength of 250 nm. When the extinction absorption of silicon nitride layer 41, silicon oxynitride layer 42, and silicon oxide layer 43 is within the above range, it further demonstrates that the antireflection layer 4 of this application effectively improves the absorption and utilization rate of sunlight.

[0137] In this application, the thickness refers to the average thickness, the extinction coefficient refers to the average value, and the refractive index also refers to the average value. Taking the silicon nitride layer 41 as an example, when testing its thickness, the value is calculated by measuring the thickness of the silicon nitride layer 41 at multiple locations, reflecting the overall thickness level of the silicon nitride layer 41 in the thickness direction; when testing its extinction coefficient, the value is calculated by measuring the extinction coefficient of the silicon nitride layer 41 at multiple locations; when testing its refractive index, the value is calculated by measuring the refractive index of the silicon nitride layer 41 at multiple locations.

[0138] Furthermore, when using an ellipsometer to test the thickness, extinction coefficient, and refractive index of the silicon nitride layer 41, at least five points should be taken on the silicon nitride layer 41, and the thickness, extinction coefficient, and refractive index of each of these five points should be measured to obtain the average value of the measurement data. For example, an ellipsometer manufactured by Sentch GmbH, Germany, model SE-800, can be used for testing. This application does not limit the specific testing method, as long as it achieves the purpose of this application.

[0139] The uniformity of film thickness is determined by first taking samples of the film and then calculating the uniformity of the film thickness based on the measured maximum and minimum values. Uniformity = (maximum value - minimum value) / (maximum value + minimum value). The uniformity of refractive index is determined by first taking samples of the film and then calculating the uniformity of the refractive index based on the measured maximum and minimum values. Uniformity = (maximum value - minimum value) / (maximum value + minimum value).

[0140] Furthermore, when the antireflection layer 4 of this application is a silicon nitride layer 41, a silicon oxynitride layer 42, and a silicon oxide layer 43, the designated element in the antireflection layer 4 is nitrogen. This is because the gas source for preparing the silicon nitride layer 41 includes N2 and SiH4; the gas source for preparing the silicon oxynitride layer 42 includes SiH4, NH3, and N2O; and the gas source for preparing the silicon oxide layer 43 includes SiH4 and N2O. All of these gases contain nitrogen, and these nitrogen elements and the dopant elements of the N-type doped layer are in the same group, thus affecting the performance of the N-type doped layer. The impact is even greater when the dopant element of the N-type doped layer is phosphorus. Therefore, by setting an isolation region 23 between the antireflection layer 4 and the first doped layer 3, the interference of nitrogen elements on phosphorus elements can be effectively avoided, thereby improving the performance of the heterojunction solar cell to a greater extent.

[0141] Further, see the return Figure 1 The first doped layer 3 includes a first doped silicon layer 31 close to the silicon substrate 1 and a second doped silicon layer 32 located on the side of the first doped silicon layer 31 away from the silicon substrate 1; wherein the doping concentration of the second doped silicon layer 32 is higher than that of the first doped silicon layer 31.

[0142] Since the doping concentration of the second doped silicon layer 32 is higher than that of the first doped silicon layer 31, the presence of the second doped silicon layer 32 further increases the concentration of charge carriers and improves the conductivity of the heterojunction solar cell. Furthermore, the highly doped second doped silicon layer 32 has a higher bandgap compatibility and better contact effect with the first transparent conductive layer 5, which helps the charge carriers to be transported from the second doped silicon layer 32 to the first transparent conductive layer 5.

[0143] Furthermore, such as Figure 6 As shown, along the direction from the silicon substrate 1 to the first intrinsic passivation layer 2, the first doped silicon layer 31 sequentially includes a first doped sublayer 311, a second doped sublayer 312, and a third doped sublayer 313.

[0144] The thickness of the first doped sublayer 311 is 1 nm to 2 nm; the thickness of the second doped sublayer 312 is 12 nm to 20 nm; and the thickness of the third doped sublayer 313 is 2 nm to 3 nm. When the thicknesses of the first doped sublayer 311, the second doped sublayer 312, and the third doped sublayer 313 are within the above ranges, the adaptability of these three doped sublayers is higher, which is more conducive to the transport of charge carriers.

[0145] The band gap of the first doped sublayer 311 is 2.0 eV to 2.3 eV; the band gap of the second doped sublayer 312 is 2.4 eV to 2.8 eV; and the band gap of the third doped sublayer 313 is 2.4 eV to 2.8 eV. When the band gaps of the first doped sublayer 311, the second doped sublayer 312, and the third doped sublayer 313 are within the above ranges, the band gap matching of these three doped sublayers is higher, which is more conducive to reducing carrier recombination at the interface. Furthermore, the band gap matching degree between the first doped sublayer 311 and the first intrinsic passivation layer 2 is higher, and the band gap matching degree between the third doped sublayer 313 and the second doped silicon layer 32 is higher, thereby further promoting the transport of carriers from the first intrinsic passivation layer 2 to the second doped silicon layer 32.

[0146] The conductivity of the first doped sublayer 311 is 10. -2 S / cm~10 2 S / cm; the conductivity of the second doped sublayer 312 is 10. - 1 S / cm~10 1 S / cm; the conductivity of the third doped sublayer 313 is 10. 1 S / cm~103 S / cm. When the conductivity of the first doped sublayer 311, the second doped sublayer 312, and the third doped sublayer 313 is within the above range, it indicates that the three doped sublayers have good conductivity and high conductivity matching, which helps to improve the performance of heterojunction solar cells to a greater extent.

[0147] The crystallinity of the first doped sublayer 311 is 15%~25%; the crystallinity of the second doped sublayer 312 is 25%~35%; and the crystallinity of the third doped sublayer 313 is 25%~30%. When the crystallinity of the first doped sublayer 311, the second doped sublayer 312, and the third doped sublayer 313 is within the above range, it indicates that the matching degree of the crystallinity of these three sublayers is higher, which is conducive to the migration of charge carriers at the interface. Furthermore, the matching degree of the crystallinity of the first doped sublayer 311 with that of the first intrinsic passivation layer 2 is higher, and the matching degree of the crystallinity of the third doped sublayer 313 with that of the second doped silicon layer 32 is higher, thereby further promoting the transport of charge carriers from the first intrinsic passivation layer 2 to the second doped silicon layer 32.

[0148] Furthermore, the thickness of the second doped silicon layer 32 is 1.5 nm to 2 nm. When the thickness of the second doped silicon layer 32 is within the above range, its matching degree with the first doped silicon layer 31 is relatively high, which facilitates the transport of charge carriers from the first doped silicon layer 31 to the second doped silicon layer 32. For example, the thickness of the second doped silicon layer 32 is 1.5 nm, 1.6 nm, 1.7 nm, 1.9 nm, 2 nm, etc.

[0149] Furthermore, the structure factor of the second doped silicon layer 32 is 20% to 35%. When the structure factor of the second doped silicon layer 32 is within the above range, it indicates that the film density of the second doped silicon layer 32 is relatively good and there are fewer defects, thereby helping to further reduce the recombination of charge carriers in the second doped silicon layer 32. For example, the structure factor of the second doped silicon layer 32 is 20%, 27%, 30%, 32%, 35%, etc.

[0150] The band gap was determined by measuring the transmittance and reflectance of the film using a HITACHI UH4150 spectrophotometer. Absorption was calculated from the transmittance and reflectance, and then further calculated using the Tauc Plot method (derived from UV-Vis absorption spectral data) to obtain the band gap. Conductivity was measured using a Keithley 4200A-SCS electrochemical measuring instrument with a four-probe method. Crystallinity was measured using a Horiba LabRAM Odyssey micro Raman spectrometer; the area ratio of the microcrystal peaks was calculated by fitting the curve. The structure factor was measured using a PerkinElmerSpectrum 3 Fourier transform infrared spectrometer; the area of ​​Si-H2 and Si-H was fitted, and the Si-H2 area to the total area represents the structure factor. This application does not limit the specific testing methods, as long as they achieve the purpose of this application.

[0151] The thickness of the first doped layer 3 is 15 nm to 30 nm. When the thickness of the first doped layer 3 is within this range, it helps to reduce parasitic absorption and improve the contact effect with the first transparent conductive layer 5. When the first doped layer 3 includes a first doped silicon layer 31 and a second doped silicon layer 32, the thickness refers to the total thickness of the first doped silicon layer 31 and the second doped silicon layer 32. For example, the thickness of the first doped layer 3 is 15 nm, 17 nm, 20 nm, 25 nm, 30 nm, etc.

[0152] Further, see the return Figure 1 The heterojunction solar cell also includes a first electrode 6, which is disposed on the side surface of the first transparent conductive layer 5 away from the silicon substrate 1; along the thickness direction of the silicon substrate 1, the orthogonal projection pattern of the first electrode 6 on the silicon substrate 1 is located within the range of the orthogonal projection pattern of the first doped layer 3.

[0153] In the first embodiment, the area of ​​the orthographic projection pattern of the first electrode 6 is smaller than the area of ​​the orthographic projection pattern of the first doped layer 3, that is, the orthographic projection pattern of the first electrode 6 covers part of the orthographic projection pattern of the first doped layer 3; in the second embodiment, the area of ​​the orthographic projection shape of the first electrode 6 is equal to the area of ​​the orthographic projection pattern of the first doped layer 3, that is, the orthographic projection pattern of the first electrode 6 coincides with the orthographic projection pattern of the first doped layer 3.

[0154] Furthermore, along the thickness direction of the silicon substrate 1, the orthographic projection width of the first electrode 6 on the silicon substrate 1 is 25 μm to 35 μm. A width of the first electrode 6 within this range is more conducive to improving the carrier collection capability. For example, the orthographic projection width of the first electrode 6 is 25 μm, 27 μm, 29 μm, 31 μm, 35 μm, etc.

[0155] Furthermore, such as Figure 1 and Figure 7 As shown, heterojunction solar cells also include:

[0156] The second intrinsic passivation layer 7 is disposed on the back surface of the silicon substrate 1. The second intrinsic passivation layer 7 includes a first thickness region 7a and a second thickness region 7b. The second thickness region 7b is a thickness reduction region relative to the first thickness region 7a, so that the second intrinsic passivation layer 7 in the second thickness region 7b forms a recessed structure.

[0157] A patterned second doped layer 8 is disposed on the surface of the second intrinsic passivation layer 7 away from the silicon substrate 1, and the position of the second doped layer 8 corresponds to the second thickness region 7b. The second doped layer 8 has the opposite conductivity type to the first doped layer 3.

[0158] A patterned second transparent conductive layer 9 is disposed on the side surface of the second doped layer 8 facing away from the silicon substrate 1.

[0159] The second intrinsic passivation layer 7 of this application includes a first thickness region 7a and a second thickness region 7b. The second intrinsic passivation layer 7 in the second thickness region 7b forms a recessed structure, and the second doped layer 8 is located within the recessed structure. The second transparent conductive layer 9 is located on the second doped layer 8. Therefore, the charge carriers in the second thickness region 7b can be directly transported to the second transparent conductive layer 9 through the second doped layer 8, which helps to shorten the transport path of the charge carriers. In addition, since the sidewall of the first thickness region 7a is in contact with the second doped layer 8, the charge carriers in the first thickness region 7a can be transported from the sidewall to the second doped layer 8, and then to the second transparent conductive layer 9, further improving the transport capability of the charge carriers.

[0160] Furthermore, the combined effect of the first thickness region 7a and the second thickness region 7b enables passivation of the silicon substrate 1, reducing carrier recombination. Moreover, by providing a patterned second transparent conductive layer 9, direct contact between the second transparent conductive layer 9 and the second intrinsic passivation layer 7 is avoided, thus helping to prevent damage to the second intrinsic passivation layer 7.

[0161] The material of the second intrinsic passivation layer 7 includes a second intrinsic amorphous silicon layer.

[0162] Further, see the return Figure 7 The second intrinsic passivation layer 7 includes a first passivation layer 71 stacked together and a patterned second passivation layer 72. The first passivation layer 71 is disposed on the back surface of the silicon substrate 1, and the second passivation layer 72 is disposed on the side of the first passivation layer 71 facing away from the silicon substrate 1, and the second passivation layer 72 is located in the first thickness region 7a.

[0163] The second passivation layer 72 has a thickness of 3 mm to 5 mm, and the first passivation layer 71 has a thickness of 6 mm to 12.5 mm.

[0164] When the thicknesses of the first passivation layer 71 and the second passivation layer 72 are within the aforementioned range, it helps to further improve the passivation effect and also helps to further shorten the carrier transport distance, thereby further improving the performance of the heterojunction solar cell. For example, the thickness of the second passivation layer 72 is 3 mm, 3.5 mm, 4 mm, 4.5 mm, 5 mm, etc.; the thickness of the first passivation layer 71 is 6 mm, 7 mm, 8 mm, 10 mm, 12.5 mm, etc.

[0165] Furthermore, such as Figure 8 As shown, along the direction from the silicon substrate 1 to the second intrinsic passivation layer 7 (see...) Figure 8 In the Y2 direction), the first passivation layer 71 includes a first passivation sublayer 711, a second passivation sublayer 712, and a third passivation sublayer 713 in sequence;

[0166] The thickness of the first passivation sublayer 711 is 1 nm to 2.5 nm; the structure factor of the first passivation sublayer 711 is 65% to 75%; the thickness of the second passivation sublayer 712 is 2 nm to 4 nm; the structure factor of the second passivation sublayer 712 is 30% to 50%; the thickness of the third passivation sublayer 713 is 3 nm to 6 nm; the structure factor of the third passivation sublayer 713 is 5% to 25%.

[0167] By controlling the thickness and structural factor of the first passivation sublayer 711 within the aforementioned range, the film density of the first passivation sublayer 711 is improved, thereby contributing to a higher degree of prevention of epitaxial growth. By controlling the thickness and structural factor of the second passivation sublayer 712 within the aforementioned range, the second passivation sublayer 712 can react with the unreacted groups in the first passivation sublayer 711, thereby reducing the accumulation of yellow powder. In addition, the third passivation sublayer 713, as the main passivation layer, is further ensured by controlling its thickness and structural factor within the aforementioned range.

[0168] Furthermore, along the thickness direction of the silicon substrate 1, the orthographic projection width of the first thickness region 7a on the silicon substrate 1 is 0.5 mm to 1.2 mm. When the orthographic projection width of the first thickness region 7a is within the above range, it helps to improve the passivation effect on the silicon substrate 1, thereby further improving the performance of the heterojunction solar cell. For example, the orthographic projection width of the first thickness region 7a is 0.5 mm, 0.7 mm, 0.9 mm, 1.1 mm, 1.2 mm, etc.

[0169] Along the thickness direction of the silicon substrate 1, the orthographic projection width of the second doped layer 8 on the silicon substrate 1 is 0.047 mm to 1.41 mm. When the orthographic projection width of the second doped layer 8 is within the above range, it helps to further ensure the carrier transport capability of the second doped layer 8. For example, the orthographic projection width of the second doped layer 8 is 0.047 mm, 0.2 mm, 0.6 mm, 1.0 mm, 1.41 mm, etc.

[0170] Further, see the return Figure 1 The first doped layer 3 is an N-type doped layer, and the second doped layer 8 is a P-type doped layer. Along the thickness direction of the silicon substrate 1, the orthogonal projection width of the N-type doped layer on the silicon substrate 1 is smaller than the orthogonal projection width of the P-type doped layer on the silicon substrate 1.

[0171] Since the carrier electrons in the N-type doped layer have a higher transport capacity than the carriers in the P-type doped layer, the above configuration can improve the carrier collection effect of the P-type doped layer, thereby achieving a relative balance between the carrier collection capabilities of the N-type and P-type doped layers, which helps to further improve the performance of heterojunction solar cells.

[0172] In one alternative implementation, such as Figure 9 As shown, along the thickness direction of the silicon substrate 1, the orthographic projection pattern formed by the N-type doped layer and the isolation regions 23 located on both sides of the N-type doped layer partially coincides with the orthographic projection pattern of the P-type doped layer; see reference [link to previous section]. Figure 1 In another optional embodiment, along the thickness direction of the silicon substrate 1, the orthographic projection pattern formed by the N-type doped layer and the isolation regions 23 located on both sides of the N-type doped layer coincides with the orthographic projection pattern of the P-type doped layer. This embodiment helps to further promote the transport of charge carriers on the light-receiving surface and the back-lighting surface, thereby helping to improve the performance of the heterojunction solar cell to a greater extent.

[0173] Further, see the return Figure 1 The second doped layer 8 includes a third doped silicon layer 81 on the side close to the silicon substrate 1 and a fourth doped silicon layer 82 disposed on the side of the third doped silicon layer 81 away from the silicon substrate 1; wherein the doping concentration of the fourth doped silicon layer 82 is higher than that of the third doped silicon layer 81.

[0174] Since the doping concentration of the fourth doped silicon layer 82 is higher than that of the third doped silicon layer 81, the presence of the fourth doped silicon layer 82 further increases the concentration of charge carriers and improves the conductivity of the heterojunction solar cell. Furthermore, the highly doped fourth doped silicon layer 82 has a higher bandgap compatibility and better contact effect with the second transparent conductive layer 9, which helps the charge carriers to be transported from the fourth doped silicon layer 82 to the second transparent conductive layer 9.

[0175] Furthermore, such as Figure 10As shown, along the direction from the silicon substrate 1 to the second intrinsic passivation layer 7, the third doped silicon layer 81 sequentially includes a fourth doped sublayer 811, a fifth doped sublayer 812, and a sixth doped sublayer 813.

[0176] The thickness of the fourth doped sublayer 811 is 1 nm to 2 nm; the thickness of the fifth doped sublayer 812 is 15 nm to 25 nm; and the thickness of the sixth doped sublayer 813 is 2 nm to 14 nm. When the thicknesses of the fourth doped sublayer 811, the fifth doped sublayer 812, and the sixth doped sublayer 813 are within the above ranges, the adaptability of these three doped sublayers is higher, which is more conducive to the transport of charge carriers.

[0177] The conductivity of the fourth doped sublayer 811 is 10. -2 S / cm~10 2 S / cm; the conductivity of the fifth doped sublayer 812 is 10. - 1 S / cm~10 1 S / cm; the conductivity of the sixth doped sublayer 813 is 10. 1 S / cm~10 3 S / cm. When the conductivity of the fourth doped sublayer 811, the fifth doped sublayer 812, and the sixth doped sublayer 813 is within the above range, it indicates that the conductivity of these three doped sublayers is good and the conductivity matching is high, which helps to improve the performance of solar cells to a greater extent.

[0178] The crystallinity of the fourth doped sublayer 811 is 15%~25%; the crystallinity of the fifth doped sublayer 812 is 20%~30%; and the crystallinity of the sixth doped sublayer 813 is 30%~45%. When the crystallinity of the fourth doped sublayer 811, the fifth doped sublayer 812, and the sixth doped sublayer 813 is within the above range, it indicates that the matching degree of the crystallinity of these three sublayers is higher, which is conducive to the migration of charge carriers at the interface.

[0179] Furthermore, the thickness of the fourth doped silicon layer 82 is 1.5 nm to 2 nm. When the thickness of the fourth doped silicon layer 82 is within the above range, its matching degree with the third doped silicon layer 81 is relatively high, which facilitates the transport of charge carriers from the third doped silicon layer 81 to the fourth doped silicon layer 82. For example, the thickness of the fourth doped silicon layer 82 is 1.5 nm, 1.6 nm, 1.7 nm, 1.9 nm, 2 nm, etc.

[0180] Furthermore, the structure factor of the fourth doped silicon layer 82 is 10% to 20%. When the structure factor of the fourth doped silicon layer 82 is within the above range, it indicates that the film density of the fourth doped silicon layer 82 is relatively good and there are fewer defects, thereby helping to further reduce carrier recombination in the fourth doped silicon layer 82. For example, the structure factor of the fourth doped silicon layer is 10%, 12%, 14%, 16%, 20%, etc.

[0181] The thickness of the second doped layer 8 is 20 nm to 45 nm. When the thickness of the second doped layer 8 is within this range, it helps to reduce parasitic absorption and improve the contact effect with the second transparent conductive layer 9. When the second doped layer 8 includes a third doped silicon layer 81 and a fourth doped silicon layer 82, the thickness refers to the total thickness of the third doped silicon layer 81 and the fourth doped silicon layer 82. For example, the thickness of the second doped layer 8 is 20 nm, 30 nm, 35 nm, 40 nm, 45 nm, etc.

[0182] Further, see the return Figure 1 The heterojunction solar cell also includes a second electrode 10, which is disposed on the side surface of the second transparent conductive layer 9 away from the silicon substrate 1; in the planar direction of the heterojunction solar cell, the orthographic projection pattern of the second electrode 10 is located within the orthographic projection pattern of the second doped layer 8.

[0183] In the first embodiment, the area of ​​the orthographic projection pattern of the second electrode 10 is smaller than the area of ​​the orthographic projection pattern of the second doped layer 8, that is, the orthographic projection pattern of the second electrode 10 covers part of the orthographic projection pattern of the second doped layer 8; in the second embodiment, the area of ​​the orthographic projection shape of the second electrode 10 is equal to the area of ​​the orthographic projection pattern of the second doped layer 8, that is, the orthographic projection pattern of the second electrode 10 coincides with the orthographic projection pattern of the second doped layer 8.

[0184] Furthermore, in the thickness direction of the silicon substrate 1, the orthogonal projection width of the second electrode 10 onto the silicon substrate 1 is 47 μm to 53 μm. A width within this range is more conducive to improving the carrier collection capability. For example, the orthogonal projection width of the second electrode 10 is 47 μm, 48 μm, 50 μm, 52 μm, 53 μm, etc.

[0185] Furthermore, the thickness of the first intrinsic passivation layer 2 is less than the thickness of the second intrinsic passivation layer 7, wherein the thickness of the second intrinsic passivation layer 7 is the sum of the thicknesses of the first part of the passivation layer 71 and the second part of the passivation layer 72. This is because the first intrinsic passivation layer 2 is disposed on the light-receiving surface, so by disposing of the first intrinsic passivation layer 2 with a smaller thickness, the absorption and utilization rate of sunlight is further improved, while by disposing of the second intrinsic passivation layer 7 with a larger thickness, the passivation effect on the back surface is further improved, thereby helping to further improve the performance of the heterojunction solar cell.

[0186] In one optional embodiment, the thickness of the first intrinsic passivation layer 2 is H1, where H1 satisfies: 5 nm ≤ H1 < 16 nm; and the thickness of the second intrinsic passivation layer 7 is H2, where H2 satisfies: 5 nm < H2 ≤ 16 nm. When the thickness is within the above range, it is more helpful to improve the passivation effect on the back surface while increasing the utilization rate of sunlight on the light-receiving surface.

[0187] Secondly, this application discloses a method for fabricating a heterojunction solar cell, which includes the following steps:

[0188] A first intrinsic passivation layer is prepared on the light-receiving surface of a silicon substrate, wherein the first intrinsic passivation layer has a first region, a second region, and an isolation region located between the first region and the second region;

[0189] A patterned first doped layer is prepared on the first intrinsic passivation layer in the first region, and the first doped layer contains doping elements;

[0190] A patterned antireflection layer is fabricated on the first intrinsic passivation layer in the second region, and the antireflection layer is separated from the first doped layer by an isolation region; the antireflection layer has a specified element, which belongs to the same main group as the doping element of the first doped layer;

[0191] A patterned first transparent conductive layer is fabricated on the first doped layer;

[0192] Post-processing yields heterojunction solar cells.

[0193] Optionally, when preparing passivation layers, silicon-doped layers, dielectric layers, transparent conductive layers, and other films on a silicon substrate, at least one of the following can be used: plasma-enhanced chemical vapor deposition (PECVD), catalytic chemical vapor deposition (CATCVD), high-density plasma chemical vapor deposition (HDPCVD), microwave plasma chemical vapor deposition (MPCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), and physical vapor deposition (PVD).

[0194] Preferably, the above-mentioned film layer is prepared using plate-type PECVD, which results in a film layer with higher thickness uniformity and better quality, thus contributing to improved performance of heterojunction solar cells. Furthermore, since the first and second doped layers of this application have patterned structures, it helps reduce the high costs associated with plate-type PECVD preparation, thereby reducing production costs while achieving high-quality film layers.

[0195] In addition, taking the fabrication of a patterned first doped layer as an example, in one optional embodiment, when fabricating the patterned first doped layer, the entire first doped layer is first fabricated, and then a portion of the first doped silicon layer is etched to remove that portion of the first doped silicon layer, thereby obtaining a patterned structure.

[0196] In another alternative implementation, before fabricating the patterned first doped silicon layer, a mask is first placed on the first intrinsic passivation layer, and then the first doped layer is directly fabricated. After fabrication, the mask is removed to obtain the patterned structure. Compared with the etching method, the mask method has a simpler fabrication process and higher process controllability, which helps to ensure the quality of the first doped layer.

[0197] The first doped layer includes a first doped silicon layer and a second doped silicon layer, and the steps for preparing the first doped layer include:

[0198] A first doped silicon layer is prepared on the first intrinsic passivation layer in the first region;

[0199] A second doped silicon layer is prepared on the first doped silicon layer, and the doping concentration of the second doped silicon layer is higher than that of the first doped silicon layer.

[0200] Furthermore, in the step of preparing the first doped silicon layer using plate PECVD, the preparation parameters include: SiH4 flow rate of 300 sccm~600 sccm, H2 flow rate of 60000 sccm~90000 sccm, PH3 flow rate of 600 sccm~1200 sccm, N2O flow rate of 20 sccm~60 sccm, heating plate spacing of 20 mm~60 mm, pressure of 400 Pa~700 Pa, power of 15 kW~30 kW, ignition time of 150 s~200 s, and heating plate temperature of 170 ℃~210 ℃.

[0201] In the step of preparing the second doped silicon layer using plate PECVD, the preparation parameters include: SiH4 flow rate of 600 sccm~900 sccm, H2 flow rate of 6000 sccm~9000 sccm, PH3 flow rate of 2100 sccm~3600 sccm, heating plate spacing of 30 mm~40 mm, pressure of 100 Pa~150 Pa, power of 1.5 kW~2 kW, ignition time of 10 s~15 s, heating plate temperature of 200 ℃~220 ℃, and deposition rate of 1.0 A / s~1.5 A / s.

[0202] By controlling the preparation parameters within the above range, the reaction between process gases is sufficiently complete and the reaction rate is appropriate, ensuring that the prepared film has high density and few defects, thereby helping to reduce carrier recombination.

[0203] Furthermore, the antireflection layer comprises a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. The steps for fabricating the antireflection layer using plate-type PECVD include:

[0204] A silicon nitride layer is prepared on the first intrinsic passivation layer in the second region:

[0205] A silicon oxynitride layer is prepared on a silicon nitride layer;

[0206] A silicon oxide layer is prepared on a silicon oxynitride layer;

[0207] The preparation parameters for the silicon nitride layer include: SiH4 flow rate of 600 sccm~700 sccm, H2 flow rate of 12000 sccm~14000 sccm, NH3 flow rate of 1500 sccm~2100 sccm, N2 flow rate of 1000 sccm~2000 sccm, heating plate spacing of 35 mm~45 mm, pressure of 300 Pa~400 Pa, power of 10.0 kW~11.5 kW, ignition time of 50 s~60 s, heating plate temperature of 200 ℃~220 ℃, and deposition rate of 1.0 A / s~1.5 A / s.

[0208] The preparation parameters for the silicon oxynitride layer include: SiH4 flow rate of 300 sccm~400 sccm, H2 flow rate of 6000 sccm~8000 sccm, NH3 flow rate of 1000 sccm~1600 sccm, N2O flow rate of 300 sccm~400 sccm, heating plate spacing of 35 mm~45 mm, pressure of 200 Pa~350 Pa, power of 9.0 kW~10.5 kW, ignition time of 20 s~30 s, heating plate temperature of 200 ℃~220 ℃, and deposition rate of 1.0 A / s~1.5 A / s.

[0209] The preparation parameters for the silicon oxide layer include: SiH4 flow rate of 200 sccm~300 sccm, H2 flow rate of 2000 sccm~3000 sccm, N2O flow rate of 200 sccm~300 sccm, heating plate spacing of 35 mm~45 mm, pressure of 100 Pa~150 Pa, power of 3.0 kW~4.5 kW, ignition time of 50 s~60 s, heating plate temperature of 200℃~220 ℃, and deposition rate of 1.0 A / s~1.5 A / s.

[0210] By controlling the preparation parameters within the above range, the reaction between process gases is sufficiently complete and the reaction rate is appropriate, ensuring that the prepared film has high density and few defects, thereby helping to reduce carrier recombination.

[0211] Furthermore, the preparation method also includes:

[0212] A first passivation layer and a patterned second passivation layer are fabricated on the back surface of a silicon substrate to form a second intrinsic passivation layer with a thickness reduction region, wherein the thickness reduction region is the region without the second passivation layer.

[0213] A patterned second doped layer is fabricated on the first portion of the passivation layer in the thickness reduction region;

[0214] The preparation of the first passivation layer is performed before the preparation of the first doped layer;

[0215] The fabrication of the patterned second passivation layer and the fabrication of the second doped layer are performed after the fabrication of the first doped layer and before the fabrication of the antireflection layer.

[0216] Furthermore, the first passivation layer includes a first passivation sublayer, a second passivation sublayer, and a third passivation sublayer, and the steps for preparing the first passivation layer include:

[0217] A first passivation sublayer is fabricated on the backlight surface of a silicon substrate;

[0218] A second passivation sublayer is prepared on the first passivation sublayer;

[0219] A third passivation sublayer is prepared on the second passivation sublayer.

[0220] Furthermore, the preparation parameters for the first passivation sublayer include: the process gas includes SiH4 and N2O, and the flow ratio of SiH4 to N2O is 1:1 to 1:5; the gas pressure is 40 Pa to 90 Pa; the ignition power is 1200 W to 1600 W; and the ignition time is 2 s to 4 s.

[0221] When preparing the second passivation sublayer, the preparation parameters include: the process gas includes SiH4 and H2, and the flow ratio of SiH4 and H2 is 1:1 to 1:5; the gas pressure is 40 Pa to 90 Pa; the ignition power is 800 W to 1200 W; and the ignition time is 4 s to 6 s.

[0222] When preparing the third passivation sublayer, the preparation parameters include: the process gas includes SiH4 and H2, and the flow ratio of SiH4 and H2 is 1:1 to 1:5, the gas pressure is 40 Pa to 90 Pa, the ignition power is 600 W to 800 W, and the ignition time is 40 s to 60 s.

[0223] By controlling the preparation parameters within the above range, the reaction between process gases is sufficiently complete and the reaction rate is appropriate, ensuring that the prepared film has high density and few defects, thereby helping to reduce carrier recombination.

[0224] Furthermore, when preparing the second passivation layer, the preparation parameters include: the process gas includes SiH4 and H2, and the flow ratio of SiH4 and H2 is 1:1 to 1:5, the gas pressure is 40 Pa to 90 Pa, the ignition power is 600 W to 800 W, and the ignition time is 40 s to 60 s.

[0225] By controlling the preparation parameters within the above range, the reaction between process gases is sufficiently complete and the reaction rate is appropriate, ensuring that the prepared film has high density and few defects, thereby helping to reduce carrier recombination.

[0226] Furthermore, the second doped layer includes a third doped silicon layer and a fourth doped silicon layer, and the step of fabricating the patterned second doped layer on the first portion of the passivation layer in the thickness reduction region includes:

[0227] A third doped silicon layer is prepared on the first part of the passivation layer in the thickness reduction region;

[0228] A fourth doped silicon layer is prepared on the third doped silicon layer, and the doping concentration of the fourth doped silicon layer is higher than that of the third doped silicon layer.

[0229] In the step of preparing the third doped silicon layer using plate PECVD, the preparation parameters include: process gases including SiH4, B2H6 and H2, the volume percentage of B2H6 to SiH4 being 0.8%~1.5%, the flow rate ratio of SiH4 to H2 being 1:300~1:400, the spacing between the heating plates being 20 mm~60 mm, the pressure being 500 Pa~800 Pa, the power being 20 kW~35 kW, the ignition time being 200 s~300 s, and the temperature of the heating plates being 150 ℃~180 ℃.

[0230] In the step of preparing the fourth doped silicon layer using plate-type PECVD, the preparation parameters include: process gases including SiH4, B2H6, and H2; the volume percentage ratio of B2H6 to SiH4 is 2%~4%; the flow rate ratio of SiH4 to H2 is 1:300~1:400; the spacing between the heating plates is 30 mm~40 mm; the pressure is 120 Pa~170 Pa; the power is 2.5 kW~3.0 kW; the ignition time is 20 s~25 s; the temperature of the heating plates is 200 ℃~220 ℃; and the deposition rate is 1.0 A / s~1.5 A / s.

[0231] By controlling the preparation parameters within the above range, the reaction between process gases is sufficiently complete and the reaction rate is appropriate, ensuring that the prepared film has high density and few defects, thereby helping to reduce carrier recombination.

[0232] In addition, the steps for preparing the first intrinsic passivation layer using plate-type PECVD include:

[0233] When preparing the first sublayer on a silicon substrate, the preparation parameters include: process gases including SiH4 and N2O, with a flow ratio of SiH4 to N2O of 1:1 to 1:5, gas pressure of 40 Pa to 90 Pa, ignition power of 1200 W to 1600 W, and ignition time of 2 s to 4 s.

[0234] When preparing the second sublayer on the first sublayer, the preparation parameters include: the process gas includes SiH4 and H2, and the flow ratio of SiH4 and H2 is 1:1 to 1:5; the gas pressure is 40 Pa to 90 Pa; the ignition power is 800 W to 1200 W; and the ignition time is 4 s to 6 s.

[0235] When preparing the third sublayer on the second sublayer, the preparation parameters include: the process gas includes SiH4 and H2, and the flow ratio of SiH4 and H2 is 1:1 to 1:5; the gas pressure is 90 Pa to 140 Pa; the ignition power is 600 W to 800 W; and the ignition time is 40 s to 60 s.

[0236] By controlling the preparation parameters within the above range, the reaction between process gases is sufficiently complete and the reaction rate is appropriate, ensuring that the prepared film has high density and few defects, thereby helping to reduce carrier recombination.

[0237] The preparation parameters for the first transparent conductive layer include: in the step of preparing the first transparent conductive layer using plate PECVD, the power is 5.5 kW to 6.0 kW, the O2 flow rate is 20 sccm to 22 sccm, the Ar flow rate is 1200 sccm to 1400 sccm, and the Ar / H2 flow rate is 1200 sccm to 1400 sccm; in the step of preparing the second transparent conductive layer using plate PECVD, the power is 5.0 kW to 5.5 kW, the O2 flow rate is 14 sccm to 16 sccm, the Ar flow rate is 600 sccm to 900 sccm, and the Ar / H2 flow rate is 800 sccm to 1000 sccm.

[0238] By controlling the preparation parameters within the above range, the reaction between process gases is sufficiently complete and the reaction rate is appropriate, ensuring that the prepared film has high density and few defects, thereby helping to reduce carrier recombination.

[0239] Furthermore, a second doped layer is disposed on the backlight surface of the silicon substrate, and the post-processing steps include:

[0240] A patterned second transparent conductive layer is fabricated on the second doped layer;

[0241] A first electrode is fabricated on the side of the first transparent conductive layer that is away from the silicon substrate;

[0242] A second electrode is fabricated on the side of the second transparent conductive layer that is away from the silicon substrate.

[0243] Furthermore, prior to the step of fabricating the first intrinsic passivation layer on the light-receiving surface of the silicon substrate, the fabrication method further includes:

[0244] A protective layer is prepared on the back surface of a silicon substrate;

[0245] After texturing the light-receiving surface of the silicon substrate, the protective layer on the backlight surface is removed.

[0246] In this step, a protective layer is first prepared on the backlight surface to protect it. Then, during the texturing process, this protective layer can protect the backlight surface and prevent it from being etched, thereby ensuring that the film structure of the backlight surface is not affected.

[0247] In the step of preparing the protective layer using plate-type PECVD, the power is 3 kW to 5 kW, the flow rate of SiH4 is 150 sccm to 200 sccm, the flow rate of N2 is 500 sccm to 700 sccm, the flow rate of H2 is 1000 sccm to 2000 sccm, the pressure is 110 Pa to 150 Pa, and the spacing between the heating plates is 30 mm to 40 mm.

[0248] The protective layer prepared by the above method is made of silicon nitride, and its thickness is 50 nm to 60 nm. The uniformity of the protective layer thickness is less than 6%. The refractive index of the protective layer is 2.15 to 2.20, and its uniformity is less than 0.6%. The extinction coefficient of the protective layer at a wavelength of 250 nm is 0.4589 to 0.745. When the protective layer meets the above ranges, it can effectively protect the backlight surface, thereby helping to prevent the backlight surface from being etched and keeping it in a polished state, which is conducive to the subsequent deposition of the second intrinsic passivation layer.

[0249] Thirdly, embodiments of this application disclose a photovoltaic module, which includes: a heterojunction solar cell according to the first aspect, or the heterojunction solar cell prepared by the preparation method according to the second aspect.

[0250] The technical solution of this application will be further explained below with reference to more specific embodiments and experimental test results.

[0251] Example 1:

[0252] This embodiment provides a heterojunction solar cell:

[0253] The silicon substrate of this heterojunction solar cell has a first intrinsic passivation layer on its light-receiving surface. The first intrinsic passivation layer has a patterned first doped layer and a patterned antireflection layer, which are separated by an isolation region. A first transparent conductive layer is disposed on the first doped layer, and a first electrode is disposed on the first transparent conductive layer. The first doped layer is an N-type doped layer with phosphorus as the dopant element, and the designated element in the antireflection layer is nitrogen. In the thickness direction of the silicon substrate, the orthographic projection width of the first doped layer is 0.7 mm, the orthographic projection width of the antireflection layer is 0.8 mm, the orthographic projection width of the isolation region is 0.23 mm, and the orthographic projection width of the first electrode is 30 μm.

[0254] A second intrinsic passivation layer is disposed on the back surface of the silicon substrate. The second intrinsic passivation layer includes a first passivation layer stacked on top of a patterned second passivation layer. A second doped layer is disposed on the first passivation layer, a second transparent conductive layer is disposed on the second doped layer, and a second electrode is disposed on the second transparent conductive layer. The second doped layer is a P-type doped layer. Along the thickness direction of the silicon substrate, the orthographic projection pattern formed by the N-type doped layer and the isolation regions located on both sides of the N-type doped layer coincides with the orthographic projection pattern of the P-type doped layer.

[0255] This embodiment also provides a method for fabricating this heterojunction solar cell:

[0256] The N-type silicon substrate was initially polished with NaOH and H2O to remove dirt and impurities from the surface. P diffusion was then used to displace the metallic impurities in the silicon substrate. Finally, the silicon substrate was polished.

[0257] A protective layer with a thickness of 55 nm, a thickness uniformity of 4%, a refractive index of 2.18, a refractive index uniformity of 0.4%, and an extinction coefficient of 0.545 at a wavelength of 250 nm was fabricated on the back surface of a silicon substrate. The fabrication parameters included: using plate-type PECVD to fabricate the protective layer, with a cavity size of 2 × 2 m. 2 The power is 4 kW, the flow rate of SiH4 is 170 sccm, the flow rate of N2 is 600 sccm, the flow rate of H2 is 1500 sccm, the pressure is 130 Pa, and the spacing between the heating plates is 35 mm.

[0258] After texturing the light-receiving surface of the silicon substrate, the protective layer on the backlight surface is removed.

[0259] The first passivation layer was fabricated on the back surface of a silicon substrate using plate-type PECVD:

[0260] A first passivation sublayer with a thickness of 2 nm and a structure factor of 70% was prepared. The preparation parameters included: a SiH4 to N2O flow ratio of 1:3.5, a gas pressure of 60 Pa, an ignition power of 1500 W, and an ignition time of 3 s.

[0261] A second passivation sublayer with a thickness of 3 nm and a structure factor of 40% was prepared. The preparation parameters included: a SiH4 to H2 flow ratio of 1:3.5, a gas pressure of 60 Pa, an ignition power of 1000 W, and an ignition time of 5 s.

[0262] A third passivation sublayer with a thickness of 4.5 nm and a structure factor of 15% was prepared. The preparation parameters included: process gases including SiH4 and H2, with a SiH4 to H2 flow ratio of 1:2.5, a gas pressure of 100 Pa, an ignition power of 400 W, and an ignition time of 50 s.

[0263] A first intrinsic passivation layer is fabricated on the light-receiving surface of a silicon substrate using plate-type PECVD. This first intrinsic passivation layer includes a first sublayer, a second sublayer, a third sublayer, and a fourth sublayer, wherein the fourth sublayer is a hydrogenated passivation layer.

[0264] A first sublayer with a thickness of 1.5 nm and a structure factor of 70% was prepared. The preparation parameters included: a SiH4 to N2O flow ratio of 1:3.5, a gas pressure of 60 Pa, an ignition power of 1500 W, and an ignition time of 2.5 s.

[0265] A second sublayer with a thickness of 2.5 nm and a structure factor of 40% was prepared. The preparation parameters included: a SiH4 to N2O flow ratio of 1:3, a gas pressure of 70 Pa, an ignition power of 1000 W, and an ignition time of 5 s.

[0266] A third sublayer with a thickness of 3 nm and a structure factor of 10% was prepared. The preparation parameters included: process gases including SiH4 and H2 with a SiH4 to H2 flow ratio of 1:3, gas pressure of 100 Pa, ignition power of 700 W, and ignition time of 50 s.

[0267] The fourth sublayer was prepared with the following parameters: H2 flow rate of 10000 sccm, pressure of 120 Pa, power of 2.0 kW, and process time of 15 s.

[0268] A mask was placed on the first intrinsic passivation layer, and a patterned first doped silicon layer and a second doped silicon layer were sequentially fabricated using plate-type PECVD to obtain a first doped layer with a thickness of 23 nm.

[0269] Fabrication of the first doped silicon layer: The cavity size is 2 × 2 m 2The flow rates of SiH4 were 300 sccm to 600 sccm, H2 were 60,000 sccm to 90,000 sccm, PH3 were 600 sccm to 1200 sccm, and N2O were 20 sccm to 60 sccm. The spacing between the heating plates was 70 mm, the pressure was 400 Pa to 700 Pa, the power was 15 kW to 30 kW, the ignition time was 150 s to 200 s, and the temperature of the heating plates was 190 ℃. The first doped silicon layer prepared included a first doped sublayer (the thickness of the first doped sublayer was 1.5 nm, the band gap was 2.04 eV, and the conductivity was 10⁻⁶ eV). -2 S / cm, crystallinity 17%), second doped sublayer (second doped sublayer thickness 15 nm, band gap 2.5 eV, conductivity 10 -1 S / cm, crystallinity 30%), third doped sublayer (thickness of the third doped sublayer is 2.5 nm, band gap is 2.6 eV, conductivity is 100 S / cm, crystallinity is 28%).

[0270] Fabrication of a second doped silicon layer with a thickness of 1.5 nm: cavity size 2 × 2 m 2 The flow rate of SiH4 was 700 sccm, the flow rate of H2 was 7000 sccm, the flow rate of PH3 was 2500 sccm, the spacing between the heating plates was 35 mm, the pressure was 120 Pa, the power was 1.8 kW, the ignition time was 12 s, the temperature of the heating plates was 210 ℃, and the deposition rate was 1.2 A / s.

[0271] Take out mask one and place mask two on the first passivation layer. Use plate PECVD to prepare the second passivation layer with a thickness of 3.5 nm. The process gas includes SiH4 and H2, and the flow ratio of SiH4 to H2 is 1:4. The gas pressure is 60 Pa, the ignition power is 700 W, and the ignition time is 50 s.

[0272] Remove mask two and place mask three on the second intrinsic passivation layer. Use plate-type PECVD to sequentially fabricate a patterned third doped silicon layer and a fourth doped silicon layer on the first passivation layer to obtain the second doped layer.

[0273] Fabrication of the third doped silicon layer: The cavity size is 2 × 2 m 2The volume percentage of B2H6 to SiH4 was 0.8%–1.5%, the flow ratio of SiH4 to H2 was 1:300–1:400, the spacing between the heating plates was 40 mm, the pressure was 500 Pa–800 Pa, the power was 20 kW–35 kW, the ignition time was 200 s–300 s, and the temperature of the heating plates was 160 ℃. The prepared third doped silicon layer included a fourth doped sublayer (the thickness of the fourth doped sublayer was 1.5 nm, and its conductivity was 10⁻⁶). -2 S / cm, crystallinity 17%), fifth doped sublayer (thickness of the fifth doped sublayer is 17 nm, conductivity 10 ppm). -1 S / cm, crystallinity 25%), sixth doped sublayer (sixth doped sublayer thickness is 4 nm, conductivity is 10 S / cm, crystallinity is 33%);

[0274] Fabrication of a fourth doped silicon layer with a thickness of 2 nm: the cavity size is 2 × 2 m 2 The volume percentage of B2H6 to SiH4 was 3%, the flow ratio of SiH4 to H2 was 1:350, the spacing between the heating plates was 40 mm, the pressure was 150 Pa, the power was 2.8 kW, the ignition time was 22 s, the temperature of the heating plates was 210 ℃, and the deposition rate was 1.3 A / s.

[0275] Remove mask three and place mask four on the first doped layer and the first intrinsic passivation layer. Use plate-type PECVD to prepare a patterned antireflection layer on the first intrinsic passivation layer. The antireflection layer includes a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

[0276] The extinction coefficient of a sample with a thickness of 18 nm, a thickness uniformity of 3%, a refractive index of 1.92, a refractive index uniformity of 0.4%, and a wavelength of 250 nm was 1.2 × 10⁻⁶. -10 The preparation parameters for the silicon nitride layer are as follows: SiH4 flow rate is 650 sccm, H2 flow rate is 13000 sccm, NH3 flow rate is 1800 sccm, N2 flow rate is 1500 sccm, heating plate spacing is 40 mm, pressure is 350 Pa, power is 11.0 kW, ignition time is 55 s, heating plate temperature is 210 ℃, and deposition rate is 1.2 A / s.

[0277] The extinction coefficient of a sample with a thickness of 12 nm, a thickness uniformity of 3%, a refractive index of 1.72, a refractive index uniformity of 0.4%, and a wavelength of 250 nm was 1.56 × 10⁻⁶. -13When preparing the silicon oxynitride layer, the parameters included: SiH4 flow rate of 350 sccm, H2 flow rate of 7000 sccm, NH3 flow rate of 1200 sccm, N2O flow rate of 350 sccm, heating plate spacing of 40 mm, pressure of 300 Pa, power of 9.8 kW, ignition time of 25 s, heating plate temperature of 210 ℃, and deposition rate of 1.2 A / s.

[0278] When preparing a silicon oxide layer with a thickness of 55 nm, a thickness uniformity of 3%, a refractive index of 1.52, a refractive index uniformity of 0.4%, and an extinction coefficient of 0 at a wavelength of 250 nm, the preparation parameters include: a SiH4 flow rate of 250 sccm, a H2 flow rate of 2500 sccm, a N2O flow rate of 250 sccm, a heating plate spacing of 40 mm, a pressure of 120 Pa, a power of 3.8 kW, an ignition time of 55 s, a heating plate temperature of 210 ℃, and a deposition rate of 1.2 A / s.

[0279] Post-processing steps include:

[0280] Remove mask three and place mask one on the antireflection layer and the first doped layer. Use plate-type PECVD to fabricate a patterned first transparent conductive layer with a thickness of 90 nm. Fabrication parameters include: cavity size of 2 × 2 m. 2 The power is 5.8 kW, the flow rate of O2 is 21 sccm, the flow rate of Ar is 900 sccm, and the flow rate of Ar / H2 is 1300 sccm;

[0281] Remove mask one and place mask three on the second doped layer and the second intrinsic passivation layer. Use plate-type PECVD to fabricate a patterned second transparent conductive layer with a thickness of 100 nm on the second doped layer. The fabrication parameters include: a cavity size of 2 × 2 m. 2 The power is 5.3 kW, the flow rate of O2 is 15 sccm, the flow rate of Ar is 800 sccm, and the flow rate of Ar / H2 is 900 sccm;

[0282] A first electrode with a width of 30 μm and a height of 10 μm is fabricated on the side of the first transparent conductive layer away from the silicon substrate;

[0283] A second electrode with a width of 30 μm and a height of 10 μm is fabricated on the side of the second transparent conductive layer away from the silicon substrate.

[0284] Example 2:

[0285] The only difference between this embodiment and Embodiment 1 is that the orthographic projection width of the isolation area is 0.26mm.

[0286] Example 3:

[0287] The only difference between this embodiment and Embodiment 1 is that the orthographic projection width of the isolation area is 0.1 mm.

[0288] Example 4:

[0289] The only difference between this embodiment and Embodiment 1 is that the orthographic projection width of the isolation area is 0.3 mm.

[0290] Example 5:

[0291] The only difference between this embodiment and Embodiment 1 is that the thickness of the antireflection layer is equal to the thickness of the first doped layer.

[0292] Example 6:

[0293] The only difference between this embodiment and Embodiment 1 is that the total thickness of the first passivation layer is 12.5 mm.

[0294] Embodiment seven:

[0295] The only difference between this embodiment and Embodiment 1 is that the total thickness of the first passivation layer is 6 mm.

[0296] Embodiment 8:

[0297] The only difference between this embodiment and Embodiment 1 is that the total thickness of the first passivation layer is 4 mm.

[0298] Example 9:

[0299] The only difference between this embodiment and Embodiment 1 is that the thickness of the second intrinsic passivation layer is the same everywhere, and the thickness of the second intrinsic passivation layer is 13.5 mm.

[0300] Comparative Example 1:

[0301] The only difference between this comparative example and Example 1 is that the patterned antireflection layer and the patterned first doped layer are not separated by an isolation region, that is, the antireflection layer and the first doped layer are in direct contact.

[0302] Comparative Example 2:

[0303] The only difference between this comparative example and Example 1 is that no patterned antireflection layer is provided; that is, only a patterned first doped layer and a patterned first transparent conductive layer are provided on the first intrinsic passivation layer.

[0304] Performance testing

[0305] The solar cells prepared in Examples 1 to 9 and Comparative Examples 1 to 2 were subjected to the following related tests:

[0306] This application describes the performance testing of a solar cell, using a GIV-60 testing machine manufactured by Zhongsen Electric Technology Co., Ltd., to assess its open-circuit voltage, short-circuit current, and fill factor. The tested solar cell had a silicon wafer size of 210 mm × 105 mm and a calibrated light intensity of 1000 ± 5 W / m². The experimental results are as follows.

[0307] Table 1 Performance test results of solar cells

[0308]

[0309] Analysis of the data from Examples 1 to 4 and Comparative Example 1 shows that the photoelectric conversion efficiency of Examples 1 to 4 is better than that of Comparative Example 1. This demonstrates that setting an isolation region between the antireflection layer and the patterned first doped layer effectively blocks the interference of nitrogen elements in the antireflection layer on phosphorus elements in the first doped layer, ensuring the effectiveness of the first doped layer and thus contributing to improving the photoelectric conversion efficiency of the heterojunction solar cell.

[0310] Analysis of the data from Example 1 and Comparative Example 2 shows that the photoelectric conversion efficiency of Example 1 is superior to that of Comparative Example 2. This demonstrates that by setting a patterned antireflection layer, the presence of this layer helps improve the absorption and utilization rate of sunlight, promotes the generation of more photogenerated carriers, and thus helps improve the photoelectric conversion efficiency of the heterojunction solar cell.

[0311] Analysis of the data from Examples 1 and 5 shows that the photoelectric conversion efficiency of Example 1 is better than that of Example 5. This demonstrates that by setting the thickness of the antireflection layer to be greater than that of the first doped layer, the antireflection layer can effectively block the influence of impurities on the first doped layer, thereby further ensuring the performance of the first doped layer and thus significantly improving the photoelectric conversion efficiency of the heterojunction solar cell.

[0312] Analysis of the data from Examples 1, 6 to 8 shows that the photoelectric conversion efficiency of Examples 1, 6, and 7 is better than that of Example 8. This indicates that the thickness of the first passivation layer in Examples 1, 6, and 7 is superior. At this thickness, the first passivation layer effectively passivates the silicon substrate and significantly reduces the carrier transport distance, thereby contributing to further improvement in the photoelectric conversion efficiency of the heterojunction solar cell.

[0313] Analysis of the data from Examples 1 and 9 shows that the photoelectric conversion efficiency of Example 1 is better than that of Example 9. It is evident that by setting a first thickness region and a second thickness region, with the second thickness region being thinner, the transport distance of charge carriers from the second intrinsic passivation layer to the second doped layer is shortened, thereby further improving the photoelectric conversion efficiency of the heterojunction solar cell.

[0314] The heterojunction solar cell, its preparation method, and photovoltaic module disclosed in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the heterojunction solar cell, its preparation method, and photovoltaic module. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A heterojunction solar cell, characterized in that, The heterojunction solar cell includes: Silicon substrate; The first intrinsic passivation layer is disposed on the light-receiving surface of the silicon substrate, and the first intrinsic passivation layer is divided into a first region, a second region, and an isolation region located between the first region and the second region. A patterned first doped layer is disposed on the surface of the first intrinsic passivation layer away from the silicon substrate, and the position of the first doped layer corresponds to the first region; the first doped layer contains doping elements. A patterned antireflection layer is disposed on the surface of the first intrinsic passivation layer away from the silicon substrate, and the position of the antireflection layer corresponds to the second region. The first doped layer and the antireflection layer are separated by the isolation region. The antireflection layer has a specified element, which belongs to the same main group as the doping element of the first doped layer. A patterned first transparent conductive layer is disposed on the side surface of the first doped layer opposite to the silicon substrate.

2. The heterojunction solar cell according to claim 1, characterized in that, Along the thickness direction of the silicon substrate, the orthographic projection width of the isolation region is D, where D satisfies: 0 mm < D ≤ 0.26 mm.

3. The heterojunction solar cell according to claim 1, characterized in that, Along the thickness direction of the silicon substrate, the orthographic projection width of the first doped layer on the silicon substrate is 0.025 mm to 1.0 mm; and / or, Along the thickness direction of the silicon substrate, the width of the antireflection layer projected onto the silicon substrate is 0.5 mm to 1.1 mm; and / or, The antireflection layer is thicker than the first doped layer.

4. The heterojunction solar cell according to claim 1, characterized in that, The thickness of the antireflection layer is 75 nm to 100 nm.

5. The heterojunction solar cell according to claim 1, characterized in that, The specified element includes nitrogen, and the first doped layer is an N-type doped layer.

6. The heterojunction solar cell according to claim 5, characterized in that, Along the direction from the silicon substrate to the first intrinsic passivation layer, the antireflection layer sequentially includes a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer; Wherein, the thickness of the silicon nitride layer is 15 nm to 20 nm; and / or, The uniformity of the thickness of the silicon nitride layer is less than 4%; and / or, The refractive index of the silicon nitride layer is 1.9~1.95; and / or, The uniformity of the refractive index of the silicon nitride layer is less than 0.6%; and / or, The silicon nitride layer has an extinction coefficient of 1.2 × 10⁻⁶ at a wavelength of 250 nm. -13 ~5.0×10 -8 ; and / or, The thickness of the silicon oxynitride layer is 10 nm to 15 nm; and / or, The uniformity of the thickness of the silicon oxynitride layer is less than 4%; and / or, The refractive index of the silicon oxynitride layer is 1.7~1.75; and / or, The uniformity of the refractive index of the silicon oxynitride layer is less than 0.6%; and / or, The extinction coefficient of the silicon oxynitride layer at a wavelength of 250 nm is 0~1.56×10⁻⁶. -13 ; and / or, The thickness of the silicon oxide is 50 nm to 65 nm; and / or, The uniformity of the thickness of the silicon oxide is less than 4%; and / or, The refractive index of the silicon oxide layer is 1.5~1.55; and / or, The uniformity of the refractive index of the silicon oxide layer is less than 0.6%; and / or, The extinction coefficient of the silicon oxide layer is 0 at a wavelength of 250 nm.

7. The heterojunction solar cell according to claim 1, characterized in that, The first doped layer includes a first doped silicon layer near the silicon substrate and a second doped silicon layer on the side of the first doped silicon layer away from the silicon substrate; The doping concentration of the second doped silicon layer is higher than that of the first doped silicon layer.

8. The heterojunction solar cell according to any one of claims 1 to 7, characterized in that, The heterojunction solar cell also includes: The second intrinsic passivation layer is disposed on the back surface of the silicon substrate. The second intrinsic passivation layer includes a first thickness region and a second thickness region. The second thickness region is a thickness reduction region relative to the first thickness region, so that the second intrinsic passivation layer in the second thickness region forms a recessed structure. A patterned second doped layer is disposed on the surface of the second intrinsic passivation layer away from the silicon substrate, and the position of the second doped layer corresponds to the second thickness region. The second doped layer has an opposite conductivity type to the first doped layer. A patterned second transparent conductive layer is disposed on the side surface of the second doped layer opposite to the silicon substrate.

9. The heterojunction solar cell according to claim 8, characterized in that, The second intrinsic passivation layer includes a first passivation layer stacked together and a patterned second passivation layer. The first passivation layer is disposed on the back surface of the silicon substrate, and the second passivation layer is disposed on the side of the first passivation layer facing away from the silicon substrate, and the second passivation layer is located in the first thickness region. The thickness of the second passivation layer is 3 mm to 5 mm, and the thickness of the first passivation layer is 6 mm to 12.5 mm.

10. The heterojunction solar cell according to claim 9, characterized in that, Along the direction from the silicon substrate to the second intrinsic passivation layer, the first portion of the passivation layer sequentially includes a first passivation sublayer, a second passivation sublayer, and a third passivation sublayer; Wherein, the thickness of the first passivation sublayer is 1 nm to 2.5 nm; and / or, The structure factor of the first passivation sublayer is 65%~75%; and / or, The thickness of the second passivation sublayer is 2 nm to 4 nm; and / or, The structure factor of the second passivation sublayer is 30%~50%; and / or, The thickness of the third passivation sublayer is 3 nm to 6 nm; and / or, The structure factor of the third passivation sublayer is 5% to 25%.

11. The heterojunction solar cell according to claim 8, characterized in that, Along the thickness direction of the silicon substrate, the orthographic projection width of the first thickness region on the silicon substrate is 0.5 mm to 1.2 mm; and / or, Along the thickness direction of the silicon substrate, the width of the second doped layer projected onto the silicon substrate is 0.047 mm to 1.41 mm.

12. The heterojunction solar cell according to claim 8, characterized in that, The first doped layer is an N-type doped layer, and the second doped layer is a P-type doped layer. Along the thickness direction of the silicon substrate, the orthogonal projection width of the N-type doped layer on the silicon substrate is smaller than the orthogonal projection width of the P-type doped layer on the silicon substrate.

13. The heterojunction solar cell according to claim 12, characterized in that, Along the thickness direction of the silicon substrate, the orthographic projection pattern formed by the N-type doped layer and the isolation regions located on both sides of the N-type doped layer coincides with the orthographic projection pattern of the P-type doped layer.

14. The heterojunction solar cell according to claim 8, characterized in that, The second doped layer includes a third doped silicon layer near the silicon substrate and a fourth doped silicon layer disposed on the side of the third doped silicon layer away from the silicon substrate; wherein the doping concentration of the fourth doped silicon layer is higher than that of the third doped silicon layer.

15. A method for fabricating a heterojunction solar cell, characterized in that, The method for fabricating the heterojunction solar cell includes the following steps: A first intrinsic passivation layer is prepared on the light-receiving surface of a silicon substrate, wherein the first intrinsic passivation layer has a first region, a second region, and an isolation region located between the first region and the second region; A patterned first doped layer is prepared on the first intrinsic passivation layer in the first region, and the first doped layer contains doping elements; A patterned antireflection layer is fabricated on the first intrinsic passivation layer in the second region, the antireflection layer being separated from the first doped layer by the isolation region; the antireflection layer has a specified element, the specified element being an element belonging to the same main group as the doping element of the first doped layer; A patterned first transparent conductive layer is fabricated on the first doped layer; Post-processing yields the heterojunction solar cell.

16. The preparation method according to claim 15, characterized in that, The first doped layer includes a first doped silicon layer and a second doped silicon layer, and the steps for preparing the first doped layer include: The first doped silicon layer is prepared on the first intrinsic passivation layer in the first region; A second doped silicon layer is prepared on the first doped silicon layer, wherein the doping concentration of the second doped silicon layer is higher than that of the first doped silicon layer.

17. The preparation method according to claim 15, characterized in that, The antireflection layer comprises a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. The steps for preparing the antireflection layer using plate-type PECVD include: The silicon nitride layer is prepared on the first intrinsic passivation layer in the second region: The silicon oxynitride layer is prepared on the silicon nitride layer; The silicon oxide layer is prepared on the silicon oxynitride layer; The preparation parameters for the silicon nitride layer include: a SiH4 flow rate of 600 sccm~700 sccm, a H2 flow rate of 12000 sccm~14000 sccm, an NH3 flow rate of 1500 sccm~2100 sccm, a N2 flow rate of 1000 sccm~2000 sccm, a heating plate spacing of 35 mm~45 mm, a pressure of 300 Pa~400 Pa, a power of 10.0 kW~11.5 kW, an ignition time of 50 s~60 s, a heating plate temperature of 200 ℃~220 ℃, and a deposition rate of 1.0 A / s~1.5 A / s; and / or, The preparation parameters for the silicon oxynitride layer include: a SiH4 flow rate of 300 sccm to 400 sccm, a H2 flow rate of 6000 sccm to 8000 sccm, a NH3 flow rate of 1000 sccm to 1600 sccm, a N2O flow rate of 300 sccm to 400 sccm, a heating plate spacing of 35 mm to 45 mm, a pressure of 200 Pa to 350 Pa, a power of 9.0 kW to 10.5 kW, an ignition time of 20 s to 30 s, a heating plate temperature of 200 ℃ to 220 ℃, and a deposition rate of 1.0 A / s to 1.5 A / s; and / or, The preparation parameters for the silicon oxide layer include: a SiH4 flow rate of 200 sccm to 300 sccm, a H2 flow rate of 2000 sccm to 3000 sccm, a N2O flow rate of 200 sccm to 300 sccm, a heating plate spacing of 35 mm to 45 mm, a pressure of 100 Pa to 150 Pa, a power of 3.0 kW to 4.5 kW, an ignition time of 50 s to 60 s, a heating plate temperature of 200℃ to 220℃, and a deposition rate of 1.0 A / s to 1.5 A / s.

18. The preparation method according to any one of claims 15 to 17, characterized in that, The preparation method further includes: A first passivation layer and a patterned second passivation layer are prepared on the back surface of the silicon substrate to form a second intrinsic passivation layer with a thickness reduction region, wherein the thickness reduction region is a region without the second passivation layer. A patterned second doped layer is prepared on the first portion of the passivation layer in the thickness reduction region; The first passivation layer is prepared before the first doped layer is prepared. The fabrication of the patterned second portion of the passivation layer and the fabrication of the second doped layer are performed after the fabrication of the first doped layer and before the fabrication of the antireflection layer.

19. The preparation method according to claim 18, characterized in that, The first passivation layer includes a first passivation sublayer, a second passivation sublayer, and a third passivation sublayer. The steps for preparing the first passivation layer include: The first passivation sublayer is prepared on the backlight surface of the silicon substrate; The second passivation sublayer is prepared on the first passivation sublayer; The third passivation sublayer is prepared on the second passivation sublayer.

20. The preparation method according to claim 19, characterized in that, When preparing the first passivation sublayer, the preparation parameters include: the process gas includes SiH4 and N2O, and the flow ratio of SiH4 to N2O is 1:1 to 1:5; the gas pressure is 40 Pa to 90 Pa; the ignition power is 1200 W to 1600 W; and the ignition time is 2 s to 4 s; and / or, When preparing the second passivation sublayer, the preparation parameters include: the process gas includes SiH4 and H2, and the flow ratio of SiH4 to H2 is 1:1 to 1:5; the gas pressure is 40 Pa to 90 Pa; the ignition power is 800 W to 1200 W; and the ignition time is 4 s to 6 s; and / or, When preparing the third passivation sublayer, the preparation parameters include: the process gas includes SiH4 and H2, and the flow ratio of SiH4 and H2 is 1:1 to 1:5; the gas pressure is 40 Pa to 90 Pa; the ignition power is 600 W to 800 W; and the ignition time is 40 s to 60 s.

21. The preparation method according to claim 18, characterized in that, When preparing the second passivation layer, the preparation parameters include: the process gas includes SiH4 and H2, and the flow ratio of SiH4 and H2 is 1:1 to 1:5, the gas pressure is 40 Pa to 90 Pa, the ignition power is 600 W to 800 W, and the ignition time is 40 s to 60 s.

22. The preparation method according to claim 21, characterized in that, The second doped layer includes a third doped silicon layer and a fourth doped silicon layer, and the step of fabricating a patterned second doped layer on the first portion of the passivation layer in the thickness reduction region includes: The third doped silicon layer is prepared on the first portion of the passivation layer in the thickness reduction region; The fourth doped silicon layer is prepared on the third doped silicon layer, wherein the doping concentration of the fourth doped silicon layer is higher than that of the third doped silicon layer.

23. The preparation method according to claim 15, characterized in that, A second doped layer is disposed on the backlight surface of the silicon substrate, and the post-processing steps include: A patterned second transparent conductive layer is fabricated on the second doped layer; A first electrode is fabricated on the side of the first transparent conductive layer opposite to the silicon substrate; A second electrode is fabricated on the side of the second transparent conductive layer opposite to the silicon substrate.

24. A photovoltaic module, characterized in that, The photovoltaic module includes: a heterojunction solar cell according to any one of claims 1 to 14, or a heterojunction solar cell prepared by the preparation method according to any one of claims 15 to 23.

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