Back contact solar cells and cell assemblies

Abstract

The present disclosure relates to the technical field of solar cells, and discloses a back contact solar cell and a cell assembly. The cell comprises a cell base body having a light-receiving surface and a back surface, the back surface comprising first polarity regions and second polarity regions arranged alternately, and the first polarity regions and the second polarity regions having an isolation region therebetween, and the cell base body further comprises: a boss structure protruding from a surface of the first polarity regions and / or the second polarity regions towards the isolation region; and an interface optimization structure protruding from at least part of a side wall surface of the isolation region, comprising at least one optimization unit, one end of the optimization unit being connected to the boss structure, and the other end having a spacing distance from a bottom surface of the isolation region. The boss structure increases the effective printing area of the first polarity regions and the second polarity regions, and reduces the positioning difficulty of printing; and the interface optimization structure increases the area of the p-n junction and the efficiency of separating electron-hole pairs by built-in electric field, improves the carrier separation and transmission efficiency, and improves the current output efficiency and overall electrical performance.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of solar cells, in particular to a back contact solar cell and a cell assembly. BACKGROUND

[0002] A back contact solar cell (BC cell for short) is a new type of solar cell technology in which the positive and negative electrodes are both moved to the back of the cell sheet. It not only avoids the shading loss of the front grid lines, improving the optical performance, but also has good aesthetics, suitable for distributed scenarios. The positive and negative electrodes on the back of the back contact solar cell are distributed in a cross-finger shape. In order to prevent short circuit conduction between the positive and negative electrodes, an isolation region is usually provided between the n region and the p region with different polar structures. The rationality of the design of the isolation region is a key factor in determining the performance of the cell.

[0003] In the existing back contact solar cell, when the width of the isolation region is small, insufficient isolation often occurs, causing the interconnection of different polarity doped atoms and short circuit leakage. When the width of the isolation region is large, the effective area of the p region structure and the n region structure on both sides of the isolation region is narrowed, which reduces the efficiency of photon separation to form holes and electrons and weakens the carrier transport performance. At the same time, it also makes the effective contact area of the screen printing paste small when the electrode material is screen printed on the effective area, increases the difficulty of printing alignment, affects the performance of the subsequent passivation film and the conductive performance and service life of the electrode, and makes it difficult to guarantee the current output performance and power generation efficiency of the cell. SUMMARY

[0004] Therefore, the present disclosure provides a back contact solar cell and a cell assembly to solve the problem that the improper setting of the p region and the n region in the existing back contact solar cell easily affects the carrier transport performance, increases the difficulty of subsequent processes, and affects the current output performance and power generation efficiency of the cell.

[0005] In a first aspect, the present disclosure provides a back contact solar cell, comprising a cell substrate having a light-receiving surface and a back surface oppositely arranged, the back surface comprising first polarity regions and second polarity regions arranged alternately, and an isolation region formed by recessing inwardly from the back surface between the first polarity regions and the second polarity regions, the cell substrate further comprising: a boss structure formed by protruding the surface of the first polarity regions and / or the second polarity regions toward the isolation region; and an interface optimization structure protruding on at least part of the side wall surface of the isolation region and arranged close to the boss structure, the interface optimization structure comprising a plurality of optimization units stacked in sequence in a direction perpendicular to the side wall surface of the isolation region, one end of the optimization units being connected to the boss structure and the other end having a spacing distance from the bottom surface of the isolation region, the spacing distance between the plurality of optimization units and the bottom surface of the isolation region increasing in a stacking direction of the plurality of optimization units away from the side wall surface.

[0006] In an optional embodiment, the length of the interface optimization structure is less than or equal to 2 / 3 of the length of the side wall surface of the isolation region.

[0007] In an optional embodiment, the side wall surface of the isolation region is in a slope structure.

[0008] In an optional embodiment, in the arrangement direction of the first polarity regions and the second polarity regions, the width of the boss structure ranges from 0.1 to 50 μm, and the thickness of the boss structure ranges from 0.05 to 5.0 μm.

[0009] In an optional embodiment, further comprising: a buffer portion arranged between the boss structure and the interface optimization structure; and a cross-sectional dimension of the buffer portion gradually decreasing in a direction from the back surface toward the light-receiving surface.

[0010] In an optional embodiment, the width of the intersection plane of the buffer portion and the boss structure ranges from 0.1 to 10 μm, and the thickness of the buffer portion ranges from 0.05 to 5 μm.

[0011] In an optional embodiment, the surface of the buffer portion relatively close to the isolation region has a rough texture structure.

[0012] In an optional embodiment, the cell substrate comprises: a base layer and a passivation contact structure on one side surface of the base layer, the side on which the passivation contact structure is arranged being the back surface of the cell substrate.

[0013] In an optional embodiment, the passivation contact structure comprises a tunneling oxide layer and a doped layer arranged in layers, the tunneling oxide layer being relatively close to the base layer; and the base layer forms an inner extension layer in the surface connected to the passivation contact structure.

[0014] In an alternative embodiment, the thickness of the doped layer ranges from 100 nm to 300 nm, the thickness of the tunneling oxide layer ranges from 1 nm to 10 nm, and the thickness of the inner expansion layer ranges from 0.1 μm to 2 μm.

[0015] In an alternative embodiment, the boss structure is arranged in the doped layer, the tunneling oxide layer, and at least part of the inner expansion layer in the direction from the back surface to the light-receiving surface.

[0016] In an alternative embodiment, the boss structure is arranged in the doped layer and at least part of the tunneling oxide layer in the direction from the back surface to the light-receiving surface.

[0017] In an alternative embodiment, the boss structure is arranged in at least part of the doped layer in the direction from the back surface to the light-receiving surface.

[0018] In a second aspect, the disclosure also provides a battery assembly comprising a plurality of the back-contact solar cells described above.

[0019] Advantages: The back-contact solar cell of the disclosure, first, the upper surfaces of the first and second polarity regions form boss structures protruding from the main part of the polarity region towards the isolation region. On the one hand, the effective printing area of the first and second polarity regions is increased, which enables more metal paste to contact the polarity regions during subsequent screen printing, improves the carrier transport and collection performance, and further reduces the positioning difficulty of electrode printing and improves the printing yield.

[0020] Further, the interface optimization structure is arranged on the lower side of the boss structure, the interface optimization structure comprises one or more optimization units, and the interface optimization structure is arranged at one end of the side wall surface of the isolation region close to the boss structure. On the one hand, it ensures that the boss structure is connected to effectively support the boss structure and reduce the concentrated stress at the intersection of the boss structure and the polarity region, thereby improving the strength of the effective area of the first and second polarity regions for printing electrodes and ensuring the reliability of the printed electrodes. Moreover, the smooth side wall surface of the isolation region presents a textured structure, which reduces the light reflection on the side wall surface of the isolation region and improves the double-sided rate. On the other hand, the interface optimization structure is arranged on at least part of the side wall surface of the isolation region close to the boss structure, which further increases the area of the p-n junction during the diffusion process, thereby enhancing the efficiency of the built-in electric field in separating electron-hole pairs. That is, it helps to improve the carrier separation and transport efficiency, thereby improving the current output efficiency and overall electrical performance of the battery. Moreover, the boss structure and the interface optimization structure also help the doped atoms to diffuse uniformly from the outside to the inside during the diffusion process, reducing abnormal phenomena such as accumulation and clustering of local doped atoms at narrow corners, improving the battery yield and service life. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments or the prior art of the present disclosure, the drawings needed to be used in the description of the specific embodiments or the prior art will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present disclosure, and other drawings can be obtained by a person of ordinary skill in the art without creative effort based on these drawings.

[0022] Figure 1 is a structural schematic diagram of a back contact solar cell with a boss structure and an interface optimization structure with one optimization unit according to the present disclosure;

[0023] Figure 2 is a structural schematic diagram of a back contact solar cell with a boss structure and an interface optimization structure with two optimization units according to the present disclosure;

[0024] Figure 3 is a structural schematic diagram of a back contact solar cell with a boss structure, a buffer part and an interface optimization structure with one optimization unit according to the present disclosure;

[0025] Figure 4 is a structural schematic diagram of a back contact solar cell with a boss structure, a buffer part and an interface optimization structure with two optimization units according to the present disclosure;

[0026] Figure 5 is a curve diagram of the concentration of doped atoms with depth after boron diffusion according to the present disclosure;

[0027] Figures 6 to 16 is a structural schematic diagram of a boss structure, a buffer part and an interface optimization structure in different setting modes according to the present disclosure.

[0028] Explanation of reference signs:

[0029] 100, cell substrate; 101, light receiving surface; 102, back light surface; 103, first polarity region; 104, second polarity region; 105, isolation region; 1051, textured structure; 1052, slope structure; 106, boss structure; 107, buffer part; 108, interface optimization structure; 1081a, first optimization unit; 1081b, second optimization unit;

[0030] 1, base layer; 2, inner expansion layer; 3, tunneling oxide layer; 4, doped layer. DETAILED DESCRIPTION

[0031] The present disclosure will be further described below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present disclosure, but not to limit the present disclosure. In addition, it should be noted that, for the purpose of description, only the parts related to the present disclosure are shown in the drawings, but not all the structures. In the following description, the description of the well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present disclosure. In the drawings, various structural diagrams according to the embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which some details are exaggerated for the purpose of clear expression, and some details can be omitted. The shapes of various regions, layers, and the relative size and position relationship between them shown in the drawings are only exemplary, and in actuality, they can be deviated due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly located on the other layer / element, or there can be an intermediate layer / element between them. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0032] In a related back contact solar cell, if the width of the isolation region is set to be small, the isolation of the different polarity doping atoms is prone to be insufficient, causing short circuit and leakage; and if the width of the isolation region is set to be large, the effective area of the p region and the n region on both sides is narrowed, the efficiency of the photonic separation to form holes and electrons is reduced, the carrier transport performance is weakened, and meanwhile, the alignment difficulty in screen printing the electrode material on the effective area is increased, which is prone to affect the current output performance and the power generation efficiency of the cell.

[0033] Based on this, the present disclosure provides a back contact solar cell, by setting a boss structure to increase the surface printing area of the isolation between the first polarity region and the second polarity region, to reduce the electrode printing difficulty and ensure the electrode reliability; and by setting an interface optimization structure below the boss structure, on the one hand, the interface optimization structure helps to increase the effective area of the internal region of the back light first polarity region and the second polarity region, that is, to help to increase the p-n junction area at this position, thereby increasing the separation and transport efficiency of the carriers, and at the same time, since the doping concentration is lower closer to the light receiving surface, the interface optimization structure also optimizes the overall doping concentration gradient, reduces the occurrence of abnormal conditions such as accumulation and clustering of local doping atoms at narrow corners; on the other hand, the interface optimization structure is set on the isolation region side wall surface below the boss structure, which not only improves the full-angle light trapping performance of the cell, but also helps to enhance the strength performance of the boss structure, finally improving the overall performance of the cell.

[0034] Embodiment 1

[0035] ReferenceFigures 1 to 16 The back contact solar cell provided by the embodiment includes a cell substrate 100 having a light receiving surface 101 and a back surface 102 arranged oppositely, the back surface 102 includes first polarity regions 103 and second polarity regions 104 arranged alternately, and the first polarity regions 103 and the second polarity regions 104 have an isolation region 105 recessed inwardly from the back surface 102; the cell substrate 100 further includes a boss structure 106 and an interface optimization structure 108, the boss structure 106 is formed by the surfaces of the first polarity regions 103 and the second polarity regions 104 protruding towards the isolation region 105, and the interface optimization structure 108 is formed on at least part of the side wall surface of the isolation region 105 and arranged close to the boss structure 106, the interface optimization structure 108 includes at least one optimization unit, one end of the optimization unit is connected with the boss structure 106, and the other end has a distance from the bottom surface of the isolation region 105.

[0036] Specifically, the cell substrate 100 described above includes a silicon wafer and film layer structures formed on the silicon wafer, that is, the cell substrate 100 is a cell structure before printing the grid electrodes. Referring to Figure 1 and Figure 2 , the cell substrate 100 includes the light receiving surface 101 directly receiving sunlight and the back surface 102 opposite to the light receiving surface 101, the back surface 102 has the first polarity regions 103 and the second polarity regions 104 of different polarities, the first polarity regions 103 and the second polarity regions 104 are isolated by the isolation region 105, that is, the first polarity regions 103 and the second polarity regions 104 of different polarities are arranged alternately, for example, the first polarity regions 103 are n-type regions, and the second polarity regions 104 are p-type regions, or the first polarity regions 103 are p-type regions, and the second polarity regions 104 are n-type regions. On this basis, under the viewing angle shown in Figure 1 , the upper surfaces of the first polarity regions 103 and the second polarity regions 104 form the boss structure 106 protruding inwardly from the main parts of the polarity regions towards the isolation region 105. On one hand, the boss structure 106 increases the effective printing area of the first polarity regions 103 and the second polarity regions 104, and more metal paste can contact with the first polarity regions 103 and the second polarity regions 104 during subsequent screen printing, which improves the carrier transport and collection performance, and can further reduce the positioning difficulty of electrode printing and improve the printing yield. Further, the interface optimization structure 108 is arranged on the lower side of the boss structure 106, as shown in Figure 1 , the interface optimization structure 108 includes one optimization unit; as shown in Figure 2As shown, the interface optimization structure 108 can also include two or more optimization units, which can be arranged in a strip structure and completely adhere to the side wall surface of the isolation region 105 to reduce the generation of interface defects. One end of the optimization unit is connected to the boss structure 106, and the other end is spaced apart from the bottom surface of the isolation region 105, that is, the interface optimization structure 108 is arranged at one end of the side wall surface of the isolation region 105 close to the boss structure 106. On the one hand, it ensures the effective support of the connection with the boss structure 106, reduces the concentrated stress at the intersection of the boss structure 106 and the polar region, and further improves the strength of the effective area of the printed electrode in the first polar region 103 and the second polar region 104, ensuring the reliability of the printed electrode, and making the side wall surface of the smooth isolation region 105 present a textured structure, reducing the light reflection on the side wall surface of the isolation region 105, and improving the double-sided rate. On the other hand, during the forming process of the battery substrate 100, the back surface 102 side will be subjected to a diffusion process, and the doping concentration gradually decreases from the surface of the back surface 102 inward. Correspondingly, the efficiency of the p-n junction in the built-in electric field to separate electron-hole pairs is also reduced. Based on this, the interface optimization structure 108 is arranged on at least part of the side wall surface of the isolation region 105 close to the boss structure 106, further increasing the area of the p-n junction during the diffusion process, and further enhancing the efficiency of the built-in electric field to separate electron-hole pairs, that is, it helps to improve the carrier separation and transport efficiency, and further improve the current output efficiency and overall electrical performance of the battery. Moreover, the boss structure 106 and the interface optimization structure 108 also help the doping atoms to uniformly diffuse from the outside to the inside during the diffusion process, reduce the abnormal phenomena such as accumulation and clustering of local doping atoms at narrow corners, and improve the yield and service life of the battery.

[0037] On the other hand, the boss structure 106 and the interface optimization structure 108 can also form an isolation region 105 with a small opening and a large internal isolation space on the back surface 102 of the battery substrate 100, so that the exchange between plasma and the outside is reduced during the subsequent process of depositing and forming a passivation film layer on the back surface 102, the local distribution of the mobile hydrogen content of the passivation film layer is realized, the mobile hydrogen content of the passivation film layer in the isolation region 105 is reduced, and the related hydrogen defects formed by the excessive internal expansion of hydrogen atoms into the silicon wafer are reduced. The mobile hydrogen content of the passivation film layer on the remaining area is higher to achieve the best passivation effect.

[0038] In one embodiment, the interface optimization structure 108 includes a plurality of optimization units stacked in a direction perpendicular to the side wall surface of the isolation region 105; in the stacking direction of the plurality of optimization units away from the side wall surface, the spacing distance between the plurality of optimization units and the bottom surface of the isolation region 105 increases.

[0039] That is, the interface optimization structure 108 includes multiple optimization units stacked sequentially on the sidewall of the isolation region 105. Among the multiple optimization units, the closer the optimization unit is to the sidewall of the isolation region 105, the smaller its distance from the bottom surface of the isolation region 105. This arrangement makes the surface of the interface optimization structure 108 and the sidewall of the isolation region 105 present a smooth gradient change. In the direction from the backlight surface 102 to the light-receiving surface 101, that is... Figure 1 and Figure 2 As indicated by the middle arrow, the interface optimization structure 108 is positioned between the exposed sidewalls of the boss structure 106 and the isolation region 105, and it has multiple stacked optimization units. This causes the side surfaces of the first polar region 103 and the second polar region 104 to change from the abrupt transition from the boss structure 106 to the sidewall of the isolation region 105 to a smooth transition from the boss structure 106, the multiple optimization units, to the sidewall of the isolation region 105. Consequently, the polar regions on both sides of the isolation region 105 are located within the area containing the boss structure 106 and the interface optimization structure 108. The horizontal cross-section of the region gradually decreases, which matches the gradual decrease in dopant concentration in the first polar region 103 and the second polar region 104. The gradient change in the length of multiple optimized units further enhances the matching with the gradual decrease in dopant concentration, and also increases the pn junction area of ​​the polar region at this position, thereby improving the separation and transport efficiency of charge carriers. The overall polar region side surface presents a smooth transition, which also allows dopant atoms to diffuse uniformly and reduces the occurrence of abnormal phenomena such as local dopant atom accumulation and clustering in narrow corners.

[0040] For example, such as Figure 2 As shown, the interface optimization structure 108 includes a first optimization unit 1081a and a second optimization unit 1081b stacked sequentially in a direction perpendicular to the sidewall of the isolation region 105. The first optimization unit 1081a is disposed on the sidewall of the isolation region 105, and the second optimization unit 1081b is disposed on the first optimization unit 1081a. The distance between the second optimization unit 1081b and the bottom surface of the isolation region 105 is greater than the distance between the first optimization unit 1081a and the bottom surface of the isolation region 105. Compared with the first optimization unit 1081a, the second optimization unit 1081b is generally closer to the surface of the backlight 102, corresponding to a region with a higher doping atom concentration, while the first optimization unit 1081a corresponds to a region with a lower doping atom concentration. The pn junction area at the high concentration location is effectively increased, improving carrier separation and transport efficiency. In addition, the gradient structure helps to improve diffusion uniformity.

[0041] Furthermore, the length of the aforementioned interface optimization structure 108 is less than or equal to 2 / 3 of the sidewall length of the isolation region 105. (See reference) Figures 1 to 4The length of the side wall surface of the isolation region 105 is L, and the length of the interface optimization structure 108 is L1, and the following relationship is obtained: L1≤2L / 3, where the length L of the side wall surface of the isolation region 105 is the overall length from the surface of the backlight surface 102 to the bottom surface of the isolation region 105. The length of the interface optimization structure 108 accounts for a maximum proportion of 2 / 3 in the length of the side wall surface, so that the interface optimization structure 108 and the bottom surface of the isolation region 105 have a sufficient spacing to ensure the insulation effect while ensuring auxiliary support, light trapping, and improving the strength of the built-in electric field.

[0042] In addition, the bottom surface of the isolation region 105 is also provided with a textured structure 1051 to enhance the light trapping effect.

[0043] In one embodiment, referring to Figures 1 to 16 , the side wall surface of the isolation region 105 is a slope structure 1052, so that the initial shape of the isolation region 105 presents a groove with a large opening end and a small bottom surface, which helps to form subsequent structure topographies such as the boss structure 106 and the interface optimization structure 108 at the opening end of the isolation region 105, thereby flexibly adjusting the final shape of the isolation region 105. Compared with the initial side wall surface of the isolation region 105 being a vertical plane, the initial shape of the side wall surface of the isolation region 105 presents a slope structure 1052, which on the one hand keeps the distance between the first polarity region 103 and the second polarity region 104 on the bottom surface of the isolation region 105 unchanged, while further expanding the distance between the two at the top, which can more effectively prevent short circuit conduction between the first polarity region 103 and the second polarity region 104 and reduce the risk of electric leakage; on the other hand, this opening design is more conducive to the preparation of subsequent related structures and the uniform deposition of the passivation film. When the side wall surface of the isolation region 105 is a vertical plane, it is difficult for the passivation film to effectively and uniformly cover the corresponding position during the deposition process.

[0044] The inclination range of the above-mentioned slope structure 1052, i.e., the angle range between the vertical direction, is 20°-70°. Due to the inclination of the slope structure 1052, the p-n junction area formed during the diffusion process gradually decreases from the surface to the inside as the degree of internal diffusion decreases, i.e., the closer to the backlight surface 102, the smaller the area of the p-n junction, but the higher the doping concentration, which will lead to a mismatch between the structure parameters and the battery performance, so the interface optimization structure 108 and the boss structure 106 are set to gradually reduce the concentration and gradually reduce the corresponding junction area, which helps to ensure the strength of the built-in electric field, reduce the resistance of current transmission, and thus improve the current output effect and the overall performance of the battery.

[0045] The reason for forming the slope structure 1052 is that during the formation of the isolation region 105, the p-type structure is generally deposited at high temperature, then laser patterning is performed to form a groove, and finally wet cleaning is performed to form the groove surface morphology. Then the n-type structure is formed in the groove, the isolation region 105 is formed between the p-type structure and the n-type structure, and finally the wet cleaning is performed to form the final isolation region 105 morphology. During the wet cleaning process, the hydroxyl ions in the alkali solution do not only vertically corrode the laser grooving area, but also synchronously corrode horizontally, so that the final isolation region 105 sidewall is shaped into a slope structure 1052, and the entire isolation region 105 cross-section presents an "inverted ladder" structure.

[0046] Further, in the arrangement direction of the first polarity region 103 and the second polarity region 104, the width dimension of the boss structure 106 ranges from 0.1 to 50 μm; and the thickness of the boss structure 106 ranges from 0.05 to 5.0 μm.

[0047] Reference Figure 1 and Figure 2 Taking the right side area of the slope a as the main part of the first polarity region 103, and the left side area as the specific morphology structure formed in the embodiment, the width W1 of the boss structure 106 extending from the upper end of the main part of the first polarity region 103 to the isolation region 105 ranges from 0.1 to 50 μm. Within this width range, the boss structure 106 can effectively increase the printing area of the first polarity region 103, and ensure the size of the opening end of the isolation region 105 to achieve the isolation effect. The thickness H1 of the boss structure 106 ranges from 0.05 to 5.0 μm. According to different process requirements, the appropriate thickness of the boss structure 106 is determined within this range to ensure the strength performance of the boss structure 106.

[0048] Reference Figure 3 and Figure 4 In one embodiment, the back contact solar cell further comprises: a buffer portion 107 disposed between the boss structure 106 and the interface optimization structure 108; and in the direction from the back surface 102 to the light receiving surface 101, the cross-sectional dimension of the buffer portion 107 gradually decreases.

[0049] That is, in the direction of the arrow shown in Figure 3 and Figure 4 , the horizontal cross-sectional dimension of the buffer portion 107 gradually decreases, so that the buffer portion 107 forms a triangular stable support between the boss structure 106 and the sidewall of the isolation region 105, effectively relieving the concentrated stress of the boss structure 106 at the intersection line position with the sidewall of the isolation region 105, improving the reliability of the effective printing area of the upper surface of the boss structure 106 or even the entire first polarity region 103, and finally improving the battery performance and prolonging the battery service life. Exemplarily, in the embodiment, the buffer portion 107 is a triangular structure. Figure 3In the cross-sectional schematic view, the cross-sectional shape of the buffer portion 107 is a reverse triangle or a reverse trapezoid. When the sidewall surface of the isolation region 105 is a vertical surface, the cross-sectional shape of the buffer portion 107 is a reverse right-angled triangle or a reverse right-angled trapezoid. When the sidewall surface of the isolation region 105 is an inclined surface, the cross-sectional shape of the buffer portion 107 is a reverse ordinary triangle or a reverse ordinary trapezoid.

[0050] In some optional embodiments, the boss structure 106, the interface optimization structure 108, and the buffer portion 107 are only formed on the first polarity region 103, or the boss structure 106, the interface optimization structure 108, and the buffer portion 107 are only formed on the second polarity region 104, which can be set according to specific process requirements.

[0051] Reference is made to Figure 3 and Figure 4 On the basis of the above scheme, the width range of the intersection plane of the buffer portion 107 and the boss structure 106 is 0.1-10 μm, and the thickness range of the buffer portion 107 is 0.05-5 μm.

[0052] Specifically, the intersection plane of the buffer portion 107 and the boss structure 106 is the upper end surface of the buffer portion 107 shown in Figure 3 and Figure 4 In the buffer portion 107, the width of the upper end surface is the largest. Thus, the width W2 of the upper end surface of the buffer portion 107 ranges from 0.1 μm to 50 μm, and the thickness H2 of the buffer portion 107 ranges from 0.05 μm to 5 μm. That is, the maximum width W2 of the buffer portion 107 can be equal to or smaller than the width W1 of the boss structure 106, which can reasonably control the supporting effect on the boss structure 106 and ensure the isolation effect of the isolation region 105, thereby avoiding the problems such as fracture and collapse of the boss structure 106, which can affect the subsequent setting of the passivation film or the electrode and improve the battery performance.

[0053] In one embodiment, the surface of the buffer portion 107 in the above buffer portion 107 has a rough texture structure. That is, under the angles shown in Figure 3 and Figure 4 the surface of the buffer portion 107 has a rough texture structure, such as a strip shape from top to bottom or other topography, thereby increasing the light trapping effect of the surface of the buffer portion 107 and further enhancing the separation and transmission efficiency of the carriers in the polarity region beside the isolation region 105, thereby improving the battery performance.

[0054] In one embodiment, reference is made to Figures 6 to 16 Hereinafter, only the first polarity region 103 of the battery substrate 100 is shown, and the first polarity region 103 is taken as an example of a p region for description.

[0055] The back contact solar cell includes a base layer 1 and a passivation contact structure on one side surface of the base layer 1, and the side on which the passivation contact structure is located is the back light surface 102 of the cell base 100.

[0056] The base layer 1 can be a silicon substrate, and the passivation contact structure can be a combination of a tunneling oxide layer and a doped polysilicon layer, or a combination of an intrinsic amorphous silicon layer and a doped amorphous silicon layer, which is determined according to the design requirements of the cell.

[0057] Exemplarily, referring to Figures 6 to 16 In one embodiment, the passivation contact structure includes a tunneling oxide layer 3 and a doped layer 4 arranged in a stack, and the tunneling oxide layer 3 is relatively close to the base layer 1; and the base layer 1 forms an inner expansion layer 2 in the surface connected with the passivation contact structure.

[0058] That is, the inner expansion layer 2 is formed in the upper surface of the base layer 1, the tunneling oxide layer 3 is arranged on the inner expansion layer 2, and the doped layer 4 is arranged on the tunneling oxide layer 3; the tunneling oxide layer 3 is an ultra-thin silicon oxide, and the doped layer 4 is a p-type doped polysilicon.

[0059] The thickness of the doped layer 4 is in the range of 100-300 nm, the thickness of the tunneling oxide layer 3 is in the range of 1-10 nm, and the thickness of the inner expansion layer 2 is in the range of 0.1-2 μm.

[0060] The topography of the above-mentioned boss structure 106, the buffer part 107 and the interface optimization structure 108 can be formed by methods such as etching, and when formed on the p-side, it can also be formed by controlling the wet process. For example, the boss structure 106 is a boron-doped region, and the corresponding hole or positive charge concentration is relatively high. In the process of wet etching, that is, the process of redox reaction of electron gain and loss, the reaction rate of this region will be slower than that of the base layer 1 of silicon material, thereby forming the boss structure 106 on the surface. For the buffer part 107, the boron doping concentration during boron diffusion decreases from the surface layer to the inner layer, and the corresponding wet etching rate also decreases, thereby forming the buffer part 107 which is wide at the top and narrow at the bottom. The interface optimization structure 108 can also be formed by controlling the wet etching area.

[0061] Correspondingly, the boron doping process needs to be controlled, and in one embodiment, the following steps can be used:

[0062] S1, select a silicon wafer polished on both sides.

[0063] Specifically, the N-type single crystal silicon wafer cut by a diamond wire is placed in an alkali polishing tank for double-sided polishing, the temperature is maintained at 75-85 ℃, and the time is 6-8 min, to obtain the base layer 1.

[0064] S2, one-time boron diffusion, oxygen-free shallow pushing.

[0065] First, a first boron diffusion is performed on the side of the base layer 1 used as the back surface, so that a portion of the boron source is deposited on the surface of the base layer 1, and the conditions for the boron diffusion are: a temperature range of 800-950 ℃, a diffusion time range of 5-20 min, a boron chloride flow range of 10-50 sccm, and an oxygen flow range of 100-500 sccm; then, an oxygen-free shallow push is performed to slightly push the boron source into the base layer 1, so as to lay the foundation for the subsequent deposition of the high-quality tunnel oxide layer 3; if this step is not performed, a large number of boron atoms in the boron source will be "back-sucked" into the tunnel oxide layer 3 during the direct deposition of the tunnel oxide layer 3, and the conditions for the oxygen-free shallow push are: a temperature range of 900-1050 ℃, and a time range of 2-10 min.

[0066] S3, depositing a tunnel oxide layer 3 and an intrinsic polysilicon.

[0067] The deposition conditions for the tunnel oxide layer 3 are: an LPCVD method is used, an oxygen flow range of 10000-80000 sccm, a temperature range of 400-800 ℃, and a time range of 200-1000 s, and the thickness of the tunnel oxide layer 3 ranges from 1 nm to 10 nm. The deposition conditions for the intrinsic polysilicon are: an LPCVD method is used, a tetrahydrogen silane flow range of 300-2000 sccm, a temperature range of 500-700 ℃, a time range of 2-4 h, and a working pressure range of 100-500 mTorr, and the thickness of the intrinsic polysilicon ranges from 100 nm to 300 nm.

[0068] S4, a second boron diffusion and an oxidation deep push.

[0069] Finally, a second boron diffusion and an oxidation deep push are performed, since the initial first boron diffusion has already caused the boron source to exist on the surface of the base layer 1, the second boron diffusion performed in S4 can not greatly damage the tunnel oxide layer 3 formed in step S3, so as to ensure the passivation performance of the layer, and at the same time, enough boron atoms are internally diffused into the base layer 1 to form a gradually changing boron atom gradient doping, so as to further improve the film performance. The conditions for the second boron diffusion are: a boron diffusion temperature range of 800-950 ℃, a diffusion time range of 5-50 min, a boron chloride flow range of 20-100 sccm, and an oxygen flow range of 100-1000 sccm. Then, the temperature range for the oxidation deep push is 900-1050 ℃, the oxygen flow range is 5000-30000 sccm, and the push time range is 30-80 min, so as to obtain the doped layer 4 and the final internal diffusion layer 2. Then, the boron-silicon glass layer on the surface is removed for patterning treatment.

[0070] In summary, the first diffusion with the above-mentioned anaerobic shallow pushing and the second diffusion with the oxygen deep pushing, together with the wet cleaning process, form the interface optimization structure 108 with gradient variation on the sidewall surface of the isolation region 105, and thus realize the matching of the structure parameters and the cell performance. Referring to Figure 12 the curve diagram of the concentration of boron-doped atoms varying with depth after boron diffusion, the passivation contact structure, and the doping concentration variation of the inner expansion layer is relatively flat.

[0071] On this basis, in the stacking direction of the four-layer structure of the doped layer 4, the tunneling oxide layer 3, the inner expansion layer 2, and the base layer 1, for the convenience of description, the doped layer 4 is taken as the first layer, the tunneling oxide layer 3 as the second layer, the inner expansion layer 2 as the third layer, and the base layer 1 as the fourth layer. Taking the back contact solar cell including the above-mentioned boss structure 106, interface optimization structure 108, and buffer part 107 as an example, the structure composition of the three structures has multiple cases, which can be formed by methods such as etching. The following description is based on the composition of the boss structure 106. It should be understood that the base layer 1 here is the part other than the inner expansion layer 2.

[0072] Referring to Figure 6 In an alternative embodiment, the boss structure 106 can include a different three-layer structure, that is, in the direction from the back surface 102 to the light receiving surface 101, the boss structure 106 includes the doped layer 4, the tunneling oxide layer 3, and at least part of the inner expansion layer 2. In a specific embodiment, the boss structure 106 includes the entire thickness of the doped layer 4, the entire thickness of the tunneling oxide layer 3, the entire thickness of the inner expansion layer 2, and part of the thickness of the base layer 1.

[0073] In another specific embodiment, the boss structure 106 includes the entire thickness of the doped layer 4, the entire thickness of the tunneling oxide layer 3, and the entire thickness of the inner expansion layer 2.

[0074] In yet another specific embodiment, the boss structure 106 includes the entire thickness of the doped layer 4, the entire thickness of the tunneling oxide layer 3, and part of the thickness of the inner expansion layer 2, as shown in Figure 6

[0075] The third one is preferred in this embodiment, that is, the boss structure 106 includes the entire thickness of the doped layer 4, the entire thickness of the tunneling oxide layer 3, and part of the thickness of the inner expansion layer 2. The doped structure layer is easier to be patterned, which reduces the process difficulty of the boss structure 106, the buffer part 107, and the interface optimization structure 108, and facilitates the interface optimization structure 108 to better enhance the built-in electric field strength. Of course, when the interface optimization structure 108 corresponds to the base layer 1, it can also guide the separation and transmission of hole-electron pairs.

[0076] ​On this basis, the size of the buffer portion 107 and the interface optimization structure 108 under the boss structure 106 can be set according to process requirements, that is, the buffer portion 107 can include one layer, such as only the inner expansion layer 2 material; or two different layers, including the inner expansion layer 2 and the base layer 1. In this embodiment, the thickness of the buffer portion 107 only includes the thickness of the inner expansion layer 2 of the remaining portion, and the interface optimization structure 108 is formed on the base layer 1. Figure 6

[0077] Referring to Figures 7 to 9 , in another alternative embodiment, the boss structure 106 can include two different layers, and the second layer can be all or part, that is, in the direction from the backlight surface 102 towards the light receiving surface 101, the boss structure 106 includes the doped layer 4 and at least part of the tunneling oxide layer 3. On this basis, the size of the buffer portion 107 and the interface optimization structure 108 under the boss structure 106 can be set according to process requirements.

[0078] In a specific embodiment, the boss structure 106 includes the entire thickness of the doped layer 4 and the entire thickness of the tunneling oxide layer 3. At this time, the buffer portion 107 can include two different layers, that is, the entire inner expansion layer 2 and part of the base layer 1, and the interface optimization structure 108 only includes part of the base layer 1. Or the buffer portion 107 includes one layer structure, that is, it includes all or part of the third layer, such as Figure 7 for example, the buffer portion 107 includes part of the inner expansion layer 2, and the interface optimization structure 108 includes another part of the inner expansion layer 2 and part of the base layer 1; when the buffer portion 107 includes the entire inner expansion layer 2, the interface optimization structure 108 also only includes part of the base layer 1.

[0079] In another specific embodiment, the boss structure 106 includes the entire thickness of the doped layer 4 and part of the thickness of the tunneling oxide layer 3. At this time, the buffer portion 107 can include three different layers, that is, another part of the tunneling oxide layer 3, the entire inner expansion layer 2 and part of the base layer 1, and the interface optimization structure 108 includes part of the base layer 1. Or the buffer portion 107 includes two different layers, that is, it includes another part of the tunneling oxide layer 3 and all or part of the inner expansion layer 2, Figure 8 for example, the buffer portion 107 includes another part of the tunneling oxide layer 3 and part of the inner expansion layer 2, and the interface optimization structure 108 can include another part of the inner expansion layer 2 thickness and part of the base layer 1 thickness. Of course, the buffer portion 107 can only include another part of the tunneling oxide layer 3 layer structure, as Figure 9 shown.

[0080] Referring to Figures 10 to 16 ​In another alternative embodiment, the bump structure 106 includes the entire thickness of the doped layer 4. In this case, the buffer portion 107 can include a different three-layer structure, i.e., the entire tunneling oxide layer 3, the entire inner extension layer 2, and a portion of the base layer 1, and the interface optimization structure 108 includes a portion of the base layer 1. Alternatively, the buffer portion 107 can include a different two-layer structure, i.e., the entire tunneling oxide layer 3 and the entire or a portion of the inner extension layer 2,

[0081] In a specific embodiment, the bump structure 106 includes the entire thickness of the doped layer 4. In this case, the buffer portion 107 can include a different three-layer structure, i.e., the entire tunneling oxide layer 3, the entire inner extension layer 2, and a portion of the base layer 1, and the interface optimization structure 108 includes a portion of the base layer 1. Alternatively, the buffer portion 107 can include a different two-layer structure, i.e., the entire tunneling oxide layer 3 and the entire or a portion of the inner extension layer 2, Figure 10 A structure is shown in which the buffer portion 107 includes the entire tunneling oxide layer 3 and a portion of the inner extension layer 2. Alternatively, the buffer portion 107 can include only the entire or a portion of the tunneling oxide layer 3, Figure 11 A structure is shown in which the buffer portion 107 includes the entire tunneling oxide layer 3 and a portion of the inner extension layer 2. Alternatively, the buffer portion 107 can include only the entire or a portion of the tunneling oxide layer 3, Figure 12 A structure is shown in which the buffer portion 107 includes the entire tunneling oxide layer 3 and a portion of the inner extension layer 2. Alternatively, the buffer portion 107 can include only the entire or a portion of the tunneling oxide layer 3,

[0082] In another specific embodiment, the bump structure 106 includes a portion of the thickness of the doped layer 4. In this case, the buffer portion 107 can include a different four-layer structure, i.e., another portion of the doped layer 4, the entire tunneling oxide layer 3, the entire inner extension layer 2, and a portion of the base layer 1, and the interface optimization structure 108 includes a portion of the base layer 1. Alternatively, the buffer portion 107 can include a different three-layer structure, i.e., another portion of the doped layer 4, the entire tunneling oxide layer 3, and the entire or a portion of the inner extension layer 2, Figure 13 A structure is shown in which the buffer portion 107 includes another portion of the doped layer 4, the entire tunneling oxide layer 3, and a portion of the inner extension layer 2. Alternatively, the buffer portion 107 can include a different two-layer structure, i.e., another portion of the doped layer 4 and the entire or a portion of the tunneling oxide layer 3, Figure 14 A structure is shown in which the buffer portion 107 includes another portion of the doped layer 4 and the entire tunneling oxide layer 3. In this case, the interface optimization structure 108 can be a portion of the inner extension layer 2, or the entire inner extension layer 2, or the entire inner extension layer 2 and a portion of the base layer 1; Figure 15 A structure is shown in which the buffer portion 107 includes another portion of the doped layer 4 and a portion of the tunneling oxide layer 3. Alternatively, the buffer portion 107 can include only a portion of the doped layer 4, Figure 16 A structure is shown in which the buffer portion 107 includes only another portion of the doped layer 4. In this case, the interface optimization structure 108 is a two-layer structure, although in other cases the interface optimization structure 108 can be a three-layer structure or a one-layer structure.

[0083] In the above various embodiments, the interface optimization structure 108 preferably corresponds to at least part of the doped structure layer, i.e. the end of the interface optimization structure 108 close to the bottom surface of the isolation region 105 is higher than or equal to the interface between the inner extension layer 2 and the base layer 1.

[0084] The battery assembly of the present embodiment comprises a plurality of the above-mentioned back contact solar cells.

[0085] The battery assembly of the present embodiment comprises a plurality of the above-mentioned back contact solar cells, and the upper surfaces of the first polarity region 103 and the second polarity region 104 in the back contact solar cell form a boss structure 106 protruding from the main part of the polarity region towards the isolation region 105. On the one hand, the effective printing area of the first polarity region 103 and the second polarity region 104 is increased, so that more metal paste can be in contact with them during subsequent screen printing, improving the carrier transport and collection performance, and further reducing the positioning difficulty of electrode printing and improving the printing yield. Further, a support structure is arranged at the intersection position of the lower surface of the boss structure 106 and the side surface of the isolation region 105, reducing the cantilever size of the boss structure 106 and reducing the concentrated stress at the intersection of the boss structure 106 and the polarity region, thereby improving the strength of the effective area of the first polarity region 103 and the second polarity region 104 for printing electrodes, ensuring the reliability of the printed electrodes, and ultimately improving the output performance and power generation efficiency of the battery.

[0086] In summary, the electrical performance of the comparative example 1 battery, the example 1 battery and the example 2 battery are tested, and the three have the same film layers and boss structures 106 and buffer parts 107, but the comparative example 1 battery does not have the interface optimization structure 108, the interface optimization structure 108 of the example 1 battery comprises one optimization unit, and the interface optimization structure 108 of the example 2 battery comprises two optimization units. The data of the electrical performance test are shown in the following table:

[0087]

[0088] As can be seen from the above table, compared with the comparative example 1, the batteries of the example 1 and the example 2 are superior in terms of conversion efficiency ( η ), open circuit voltage ( V oc ), short circuit current density ( J sc ), fill factor ( FF ) and double-sided rate, etc. That is, the interface optimization structure 108 of the present embodiment 1 and the example 2 can effectively improve the performance of the back contact solar cell, and the battery performance is best when the interface optimization structure 108 is provided with two layers of optimization units, and has a better double-sided rate.

[0089] Further function description of each part is the same as the corresponding embodiment described above, and will not be described here.

[0090] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. of the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0091] Although the embodiments of the present disclosure are described in conjunction with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present disclosure, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A back contact solar cell, characterized by, The battery substrate has opposite light-receiving and back surfaces, the back surface comprising first and second polarity regions arranged alternately, and an isolation region recessed inward from the back surface between the first and second polarity regions. The battery substrate further comprises: a boss structure protruding from a surface of the first and / or second polarity region toward the isolation region; an interface optimization structure protruding from at least part of a sidewall surface of the isolation region and disposed close to the boss structure, the interface optimization structure comprising a plurality of optimization units stacked in sequence in a direction perpendicular to the sidewall surface of the isolation region, one end of each optimization unit being connected to the boss structure and the other end having a spacing distance from a bottom surface of the isolation region, the spacing distance between the plurality of optimization units and the bottom surface of the isolation region increasing in a stacking direction away from the sidewall surface. The length of the interface optimization structure is less than or equal to 2 / 3 of the length of the sidewall surface of the isolation region.

2. The back contact solar cell of claim 1, wherein, The sidewall surface of the isolation region has a slope structure.

3. The back contact solar cell of claim 1, wherein, In the arrangement direction of the first and second polarity regions, the width of the boss structure ranges from 0.1 to 50 μm, and the thickness of the boss structure ranges from 0.05 to 5.0 μm.

4. The back contact solar cell of claim 1, wherein, Further comprising:

5. The back contact solar cell of claim 1, wherein, a buffer portion disposed between the boss structure and the interface optimization structure, the horizontal width of the buffer portion gradually decreasing in a direction from the back surface toward the light-receiving surface. The end surface of the buffer portion close to the boss structure and connected to the boss structure has a width in the arrangement direction of the first and second polarity regions ranging from 0.1 to 10 μm, and a thickness in a direction perpendicular to the surface of the battery substrate ranging from 0.05 to 5 μm.

6. The back contact solar cell of claim 5, wherein, The surface of the buffer portion close to the isolation region has a rough texture structure.

7. The back contact solar cell of claim 6, wherein, The battery substrate comprises a substrate layer and a passivation contact structure on one side surface of the substrate layer, the side on which the passivation contact structure is located being the back surface of the battery substrate.

8. The back contact solar cell of claim 7, wherein, The passivation contact structure comprises a tunneling oxide layer and a doped layer stacked, the tunneling oxide layer being relatively close to the substrate layer, and the substrate layer forming an inner extension layer in the surface connected to the passivation contact structure.

9. The back contact solar cell of claim 8, wherein, The thickness of the doped layer ranges from 100 to 300 nm, the thickness of the tunneling oxide layer ranges from 1 to 10 nm, and the thickness of the inner extension layer ranges from 0.1 to 2 μm.

10. The back contact solar cell of claim 9, wherein, In a direction from the back surface toward the light-receiving surface, the boss structure is disposed corresponding to the doped layer, the tunneling oxide layer, and at least part of the inner extension layer.

11. The back contact solar cell of claim 10, wherein, In a direction from the back surface toward the light-receiving surface, the boss structure is disposed corresponding to the doped layer and at least part of the tunneling oxide layer.

12. The back contact solar cell of claim 10, wherein, In a direction from the back surface toward the light-receiving surface, the boss structure is disposed corresponding to at least part of the doped layer.

13. The back contact solar cell of claim 10, wherein, ​ 14. A battery assembly characterized by, ​ A plurality of back contact solar cells according to any one of claims 1-13.

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