Light emitting element and display device including the same

Abstract

Disclosed are a light emitting element and a display device including the same. A light-emitting element according to an embodiment of the present specification includes: a first semiconductor layer; a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer; a light emitting layer disposed on the first semiconductor layer and disposed between the plurality of first electrodes; a second semiconductor layer disposed on the light emitting layer; a second electrode disposed on the second semiconductor layer; and a passivation layer configured to cover at least a portion of the first semiconductor layer, at least a portion of the light emitting layer, and at least a portion of the second semiconductor layer, in which a plurality of first opening portions are provided on the passivation layer, the first opening portion exposes a portion of a top surface and a portion of a side surface of each of the plurality of first electrodes. Accordingly, a height of a top surface of the passivation layer disposed around the first electrode of the light emitting element may be reduced.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0028736 filed on February 28, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present specification relates to a light emitting element and a display device including the same, and more particularly, to a light emitting element capable of minimizing disconnection defects and a display device including the same. Background Art

[0004] As display devices used for computer monitors, televisions, mobile phones, and the like, there are organic light emitting displays (OLEDs) configured to emit light autonomously and liquid crystal displays (LCDs) requiring a separate light source.

[0005] Application ranges of display devices are diversified from monitors of computers and televisions to personal mobile devices, and research is being conducted on display devices having a wide display area and having reduced volume and weight.

[0006] Furthermore, display devices including light-emitting diodes (LEDs) have recently attracted attention as next-generation display devices. Because LEDs are made of inorganic rather than organic materials, they are more reliable and have a longer lifespan than liquid crystal displays or organic light-emitting displays. Furthermore, LEDs can be turned on and off quickly, have excellent luminous efficiency, high impact resistance, and high stability, and can display high-brightness images. Summary of the Invention

[0007] An object to be achieved by the present specification is to provide a light emitting element (light emitting diode) in which disconnection defects of electrodes are minimized.

[0008] Another object to be achieved by the present specification is to provide a display device in which a disconnection defect of a light emitting element is suppressed to thereby minimize pixel defects.

[0009] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0010] According to an embodiment of the present specification, a light-emitting element includes: a first semiconductor layer; a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer; a light-emitting layer disposed on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer disposed on the light-emitting layer; a second electrode disposed on the second semiconductor layer; and a passivation layer configured to cover at least a portion of the first semiconductor layer, at least a portion of the light-emitting layer, and at least a portion of the second semiconductor layer. The passivation layer includes a plurality of first openings that expose a portion of a top surface and a portion of a side surface of each of the plurality of first electrodes. Therefore, disconnection defects in the first electrodes of a display device can be minimized.

[0011] A display device according to another embodiment of the present specification includes: a substrate on which a pixel including a plurality of sub-pixels is defined; and a plurality of light-emitting elements arranged in the plurality of sub-pixels and including a plurality of first electrodes and a second electrode, wherein the light-emitting elements include: a first semiconductor layer; a plurality of first electrodes arranged on one side and the other side of the first semiconductor layer; a light-emitting layer arranged on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer arranged on the light-emitting layer; a second electrode arranged on the second semiconductor layer; and a passivation layer configured to cover at least a portion of the first semiconductor layer, at least a portion of the light-emitting layer, and at least a portion of the second semiconductor layer, wherein a plurality of first openings are provided in the passivation layer, the first openings exposing a portion of a top surface and a portion of a side surface of each of the plurality of first electrodes. Therefore, disconnection defects of the light-emitting elements can be minimized, thereby improving the luminous efficiency of the display device.

[0012] According to another embodiment of the present specification, a light-emitting element includes: a first semiconductor layer; a plurality of first electrodes arranged on one side and the other side of the first semiconductor layer; a light-emitting layer arranged on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer arranged on the light-emitting layer; a second electrode arranged on the second semiconductor layer; and a passivation layer configured to cover the first semiconductor layer, the plurality of first electrodes, the second semiconductor layer and the second electrode, the passivation layer including portions having different thicknesses.

[0013] Additional details of exemplary embodiments are included in the detailed description and drawings.

[0014] According to the present specification, a passivation layer is not provided on a portion of the top surface or a portion of the side surface of each of the multiple first electrodes provided on one side and the other side of the light-emitting element, which can reduce the height of the top surface of the passivation layer provided around the first electrode.

[0015] According to the present specification, the height of the top surface of the passivation layer on a portion of the top surface or a portion of the side surface of the first electrode is reduced, which can suppress the problem that the connection electrode provided on the passivation layer and connected to the first electrode is damaged during the manufacturing process.

[0016] According to the present specification, it is possible to suppress disconnection defects that occur between the first electrode and the connection electrode when the first electrode is etched.

[0017] According to the present specification, a light emitting element in which some of a plurality of first electrodes are exposed and a display device including the light emitting element can minimize the occurrence of pixel defects caused by disconnection of the first electrodes.

[0018] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a schematic top plan view of a light emitting element according to an embodiment of the present specification;

[0021] Figure 2 It is along Figure 1 A cross-sectional view taken along line II-II';

[0022] Figure 3 is a schematic configuration diagram of a display device according to an embodiment of this specification;

[0023] Figure 4A is a partial cross-sectional view of a display device according to an embodiment of the present specification;

[0024] Figure 4B is a perspective view of a tiled display device according to an embodiment of the present specification;

[0025] Figure 5 is a cross-sectional view of a sub-pixel of a display device according to an embodiment of this specification;

[0026] Figure 6A and Figure 6B is an SEM image of a light emitting element in a step of applying and etching a photoresist after providing a first connection line during a process of manufacturing a display device of a comparative example;

[0027] Figure 7 is a schematic top plan view of a light emitting element according to another embodiment of the present specification; and

[0028] Figure 8 It is along Figure 7 A cross-sectional view taken along line VIII-VIII'. DETAILED DESCRIPTION

[0029] The advantages and features of the present disclosure and methods for achieving these advantages and features will be apparent by reference to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure and scope of the present disclosure.

[0030] The shapes, sizes, ratios, angles, numbers, etc. used to describe the exemplary embodiments of the present disclosure shown in the accompanying drawings are merely examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used in this article are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Unless otherwise expressly stated, any reference to the singular may include the plural.

[0031] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0032] When terms such as "on," "above," "below," and "beside" are used to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used together with the terms "immediately" or "directly."

[0033] When an element or layer is referred to as being “on” another element or layer, the other layer or element can be directly on the other element or interposed therebetween.

[0034] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below may be the second component in the technical concept of the present disclosure.

[0035] Like reference numerals generally refer to like elements throughout the specification.

[0036] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0037] The features of the various embodiments of the present disclosure may be partially or completely dependent on or combined with each other, and may be technically interlocked and operated in various ways, and these embodiments may be performed independently of each other or in association with each other.

[0038] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 is a schematic top plan view of a light emitting element according to an embodiment of this specification. Figure 2 It is along Figure 1 A cross-sectional view taken along line II-II'.

[0040] Reference Figure 1 and Figure 2 The light emitting element LED according to the embodiment of this specification includes a first semiconductor layer NL, a plurality of first electrodes NE, a light emitting layer EL, a second semiconductor layer PL, a second electrode PE, and a passivation layer PAS.

[0041] The first semiconductor layer NL may be a layer formed by doping a specific material with n-type or p-type impurities. For example, the first semiconductor layer NL may be a layer formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) with n-type impurities. The n-type impurities may be silicon (Si), germanium, tin (Sn), or the like. However, the present invention is not limited thereto.

[0042] A plurality of first electrodes NE are provided on one side and the other side of the first semiconductor layer NL. For example, the plurality of first electrodes may be a plurality of n-type electrodes. The plurality of first electrodes may be electrodes for electrically connecting the drive transistor DT and the first semiconductor layer NL. The plurality of first electrodes NE are provided on the top surface of the first semiconductor layer NL on two opposing sides exposed by the light emitting layer EL and the second semiconductor layer PL.

[0043] Each of the plurality of first electrodes NE may have a fan-shaped planar shape. In this case, the pointed vertex of the planar shape of each of the plurality of first electrodes NE may be positioned adjacent to the light-emitting layer EL. The curved side surface of each of the plurality of first electrodes NE may be positioned away from the light-emitting layer EL. This specification is not limited thereto. The first electrode NE may have a circular, elliptical, or polygonal shape.

[0044] At least a portion of the side surface of each of the plurality of first electrodes NE and at least a portion of the top surface of each of the plurality of first electrodes NE may be covered by a passivation layer PAS, which will be described below. Furthermore, another portion of the side surface of each of the plurality of first electrodes NE and another portion of the top surface of each of the plurality of first electrodes NE may be exposed and not covered by the passivation layer PAS. Specifically, at least a portion of the side surface of each of the plurality of first electrodes NE and at least a portion of the top surface of each of the plurality of first electrodes NE—the portions adjacent to the light-emitting layer EL—may be covered by the passivation layer PAS. Therefore, another portion of the side surface of each of the plurality of first electrodes NE and another portion of the top surface of each of the plurality of first electrodes NE may be exposed and not covered by the passivation layer PAS.

[0045] The plurality of first electrodes NE may be arranged such that a distance between a side surface closest to the light-emitting layer EL and the light-emitting layer EL in a cross-sectional view may be shorter than a distance between a side surface farthest from the light-emitting layer EL and an end portion of the first semiconductor layer NL in a cross-sectional view. The plurality of first electrodes NE may be provided closer to the light-emitting layer EL than to the end portion of the first semiconductor layer NL.

[0046] The plurality of first electrodes NE may each be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, the present invention is not limited thereto.

[0047] The light-emitting layer EL is disposed on the first semiconductor layer NL and between the plurality of first electrodes NE. The light-emitting layer EL can emit light by receiving positive holes and electrons from the first semiconductor layer NL and the second semiconductor layer PL described below. The light-emitting layer EL can be configured as a single layer or a multiple quantum well (MQW) structure. For example, the light-emitting layer EL can be made of indium gallium nitride (InGaN), gallium arsenide (GaAs), gallium nitride (GaN), etc. However, this specification is not limited to this.

[0048] The second semiconductor layer PL is provided on the light-emitting layer EL. The second semiconductor layer PL can be formed by doping a specific material with p-type impurities. For example, the second semiconductor layer PL can be a layer formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) with p-type impurities. In this case, the p-type impurity can be magnesium, zinc (Zn), beryllium (Be), etc. However, this specification is not limited to this.

[0049] A second electrode PE is provided on the second semiconductor layer PL. The second electrode PE may be an electrode for electrically connecting the power line to the second semiconductor layer PL. The side surface of the second electrode PE may be covered by a passivation layer PAS, which will be described below. Furthermore, at least a portion of the top surface of the second electrode PE may be covered by the passivation layer PAS. Thus, another portion of the top surface of the second electrode PE may be exposed and not covered by the passivation layer PAS.

[0050] The planar shape of the second electrode PE may be a circle, an ellipse, or a polygon. The second electrode PE may be disposed on a central portion of the top surface of the second semiconductor layer PL.

[0051] The second electrode PE may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, the present invention is not limited thereto.

[0052] At the same time, either the first electrode NE or the second electrode PE of the light-emitting element LED may include a ferromagnetic material such as iron (Fe), cobalt (Co), or nickel (Ni). Therefore, the light-emitting element LED can be moved by a magnetic field. However, this specification is not limited to this. The passivation layer PAS covers at least a portion of the first semiconductor layer NL, at least a portion of the light-emitting layer EL, and at least a portion of the second semiconductor layer PL. The passivation layer PAS may cover the side surfaces of the first semiconductor layer NL. In addition, the passivation layer PAS may cover at least a portion of the top surface of the first semiconductor layer NL. The passivation layer PAS may include a first opening portion OA1 that exposes at least a portion of the top surface of the first semiconductor layer NL. Therefore, on the top surface of the first semiconductor layer NL, a portion of an end portion of the passivation layer PAS may be adjacent to the top surface of the first semiconductor layer NL. In addition, the exposed portion of the top surface of the first semiconductor layer NL may be located farther from the light-emitting layer EL than the first electrode NE. At least a portion of the end portion of the passivation layer PAS adjacent to the top surface of the first semiconductor layer NL may be spaced apart from the first electrode NE.

[0053] At least a portion of the planar shape of the first opening portion OA1 may include an arc or polygonal shape. In this case, the arc may be convex toward the side away from the light-emitting layer EL. The arcuate side surface of the first opening portion OA1 may be disposed outside the arcuate side surface of the first electrode NE. At least one of the ends of the first opening portion OA1 may be disposed outside at least one of the ends of the first electrode NE. Therefore, the exposed first semiconductor layer NL may be disposed between the arcuate side surface of the first opening portion OA1 and the arcuate side surface of the first electrode NE. Therefore, the planar shape of the top surface of the portion of the first semiconductor layer NL exposed by the first opening portion OA1 may include an arcuate shape on two opposing sides thereof.

[0054] The passivation layer PAS may expose a portion of the top surface of each of the plurality of first electrodes NE and a portion of the side surface of each of the plurality of first electrodes NE through the first opening portion OA1. Specifically, the passivation layer PAS may expose a portion of the curved side surface of the side surface of the first electrode NE. The passivation layer PAS may cover a portion of the top surface of the first electrode NE connected to the straight side surface of the first electrode NE. The passivation layer PAS may expose a portion of the top surface of the first electrode NE connected to the curved side surface of the first electrode NE. The area of ​​the exposed top surface of the first electrode NE may be greater than the area of ​​the exposed top surface of the first semiconductor layer NL.

[0055] The passivation layer PAS covers the side surfaces of the light-emitting layer EL. Furthermore, the passivation layer PAS covers the side surfaces and top surface of the second semiconductor layer PL. The passivation layer PAS, which covers the top and side surfaces of the second semiconductor layer PL and the side surface of the light-emitting layer EL, may be connected to a portion of the side surface and a portion of the top surface of the first electrode NE. Therefore, a portion of the side surface and a portion of the top surface of the first electrode NE—the portions adjacent to the light-emitting layer EL—may be covered by the passivation layer PAS. The passivation layer PAS may cover the straight side surfaces of the side surfaces of the first electrode NE and a portion of the top surface adjacent to the straight side surfaces. The side surface of the first electrode NE closest to the light-emitting layer EL may be arranged to be closer to the light-emitting layer EL than the side surface of the first opening portion OA1 closest to the light-emitting layer EL.

[0056] The passivation layer PAS may cover the side surface of the second electrode PE. Additionally, the passivation layer PAS may cover a portion of the top surface of the second electrode PE. Therefore, the passivation layer PAS may include a second opening portion OA2 that exposes a portion of the top surface of the second electrode PE. The second opening portion OA2 may be disposed at the center of the top surface of the second electrode PE. The planar shape of the second opening portion OA2 may be circular or elliptical. The planar shape of the second opening portion OA2 may correspond to the planar shape of the top surface of the second electrode PE. The planar area of ​​the second opening portion OA2 may be smaller than the planar area of ​​the second electrode PE. The passivation layer PAS may be disposed on the second electrode PE and surround the second opening portion OA2. The second opening portion OA2 may be disposed between the plurality of first opening portions OA1. The distances from the second opening portion OA2 to the plurality of first opening portions OA1 may be equal to each other.

[0057] In the following, reference will be made to Figure 3 6 describe a display device 100 including a light emitting element according to an embodiment of this specification.

[0058] Figure 3 is a schematic configuration diagram of a display device according to an embodiment of this specification.

[0059] For ease of description, Figure 3 Only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC among the various components of the display device 100 are shown. Figure 3 6 , the light emitting element LED and the display device 100 Figure 1 and Figure 2 The light-emitting elements in are the same, so repeated description thereof will be omitted.

[0060] Reference Figure 3 The display device 100 includes: a display panel PN, which includes a plurality of sub-pixels SP; a gate driver GD and a data driver DD, which are configured to supply various types of signals to the display panel PN; and a timing controller TC, which is configured to control the data driver DD and the gate driver GD.

[0061] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL in response to a plurality of gate control signals provided from the timing controller TC. Figure 1 It is shown that a single gate driver GD is disposed to be spaced apart from one side of the display panel PN. However, the number and arrangement of the gate drivers GD are not limited thereto.

[0062] The data driver DD converts image data input from the timing controller TC into data voltages using reference gamma voltages in response to a plurality of data control signals provided from the timing controller TC. The data driver DD may supply the converted data voltages to a plurality of data lines DL.

[0063] The timing controller TC aligns image data input from the outside and supplies the image data to the data driver DD. The timing controller TC can generate gate control signals and data control signals by using synchronization signals (i.e., dot clock signals, data enable signals, and horizontal / vertical synchronization signals) input from the outside. In addition, the timing controller TC can control the gate driver GD and the data driver DD by supplying the generated gate control signals and data control signals to the gate driver GD and the data driver DD.

[0064] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and each of the plurality of sub-pixels SP is connected to the scan line SL and the data line DL. In addition, although not shown in the drawings, the plurality of sub-pixels SP can be connected to a high-potential power line, a low-potential power line, a reference line, etc.

[0065] The display panel PN may have a display area AA and a non-display area NA configured to surround the display area AA.

[0066] The display area AA is an area of ​​the display device 100 that displays an image. The display area AA may include a plurality of sub-pixels SP constituting a plurality of pixels PX and a circuit configured to operate the plurality of sub-pixels SP. The plurality of sub-pixels SP is the smallest unit constituting the display area AA. N sub-pixels SP may constitute a single pixel PX. A light-emitting element LED, a thin film transistor for operating the light-emitting element LED, etc. may be provided in each of the plurality of sub-pixels SP. The plurality of light-emitting elements LED may be defined differently depending on the type of the display panel PN. For example, in the case where the display panel PN is an inorganic light-emitting display panel PN, the light-emitting element LED may be a light-emitting diode (LED) or a micro light-emitting diode (micro-LED).

[0067] A plurality of signal lines are provided in the display area AA for transmitting various types of signals to the plurality of sub-pixels SP. For example, the plurality of signal lines may include a plurality of data lines DL for supplying data voltages to the plurality of sub-pixels SP, and a plurality of scan lines SL for supplying gate voltages to the plurality of sub-pixels SP. The plurality of scan lines SL may extend in a single direction in the display area AA and may be connected to the plurality of sub-pixels SP. The plurality of data lines DL may extend in a direction different from the single direction in the display area AA and may be connected to the plurality of sub-pixels SP. Furthermore, low-potential power lines, high-potential power lines, and the like may also be provided in the display area AA. However, this specification is not limited thereto.

[0068] The non-display area NA may be defined as an area where no image is displayed, that is, an area extending from the display area AA. The non-display area NA may include link lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA. Alternatively, the non-display area NA may include driver ICs, such as a gate driver IC and a data driver IC.

[0069] Meanwhile, the non-display area NA may be positioned on the rear surface of the display panel PN (ie, the surface on which the sub-pixels SP do not exist). Alternatively, the non-display area NA may not be included. However, the present specification is not limited to the configuration shown in the drawings.

[0070] Meanwhile, drivers such as the gate driver GD, the data driver DD, and the timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-display area NA by a gate-in-panel (GIP) method, or may be installed between a plurality of sub-pixels SP in the display area AA by a gate-in-active-area (GIA) method. For example, the data driver DD and the timing controller TC may be formed on a separate flexible film and a printed circuit board, and may be electrically connected to the display panel PN by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN. In the case where the gate driver GD is installed by the GIP method and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrodes in the non-display area NA, it is necessary to ensure the area of ​​the non-display area NA in order to set the gate driver GD and the pad electrodes, which may increase the frame.

[0071] Alternatively, when the gate driver GD is installed in the display area AA by the GIA method and the side lines SRL connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN are formed to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-display area NA on the front surface of the display panel PN can be minimized. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN by the above method, a zero border in which there is substantially no border can be achieved. Figure 4A and Figure 4B To describe in more detail.

[0072] Figure 4A is a partial cross-sectional view of a display device according to an embodiment of this specification. Figure 4B is a perspective view of a tiled display device according to an embodiment of the present specification.

[0073] First, refer to Figure 4A A plurality of pad electrodes for transmitting various types of signals to the plurality of sub-pixels SP are provided in the non-display area NA of the display panel PN. For example, a first pad electrode PAD1 configured to transmit signals to the plurality of sub-pixels SP is provided in the non-display area NA on the front surface of the display panel PN. A second pad electrode PAD2 electrically connected to a driving component such as a flexible film and a printed circuit board is provided in the non-display area NA on the rear surface of the display panel PN.

[0074] In this case, although not shown in the drawings, various types of signal lines (eg, scan lines SL, data lines DL, etc.) connected to the plurality of sub-pixels SP may extend from the display area AA to the non-display area NA and be electrically connected to the first pad electrode PAD1.

[0075] Furthermore, side lines SRL are provided along the side surfaces of the display panel PN. The side lines SRL can electrically connect the first pad electrode PAD1 on the front surface of the display panel PN with the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, signals received from the driving components on the rear surface of the display panel PN can be transmitted to the plurality of sub-pixels SP via the second pad electrode PAD2, the side lines SRL, and the first pad electrode PAD1. This defines a signal transmission route from the front surface of the display panel PN to the side and rear surfaces, minimizing the area of ​​the non-display area NA of the display panel PN.

[0076] In addition, refer to Figure 4B , a tiled display device TD having a large screen can be realized by connecting a plurality of display devices 100. In this case, as Figure 4AAs shown, in the case of realizing the tiled display device TD by using the display device 100 with a minimized bezel, a seam area between the display devices 100 where no image is displayed may be minimized, thereby improving display quality.

[0077] For example, a plurality of sub-pixels SP may constitute a single pixel PX. The interval between the outermost pixels PX of one display device 100 and the outermost pixels PX of another display device 100 adjacent to the one display device 100 may be implemented to be equal to the interval between the pixels PX in the one display device 100. Therefore, since a constant interval between the pixels PX is achieved between the display devices 100 and the display devices 100, the seam area can be minimized.

[0078] However, if Figure 4A and Figure 4B As shown, the display device 100 according to the embodiment of the present specification may be a general display device 100 having a frame. However, the present specification is not limited thereto.

[0079] Figure 5 is a cross-sectional view of one sub-pixel of a display device according to an embodiment of this specification.

[0080] Reference Figure 5 , on each of the multiple sub-pixels SP of the display panel PN of the display device 100 according to the embodiment of the present specification, the following may be provided: a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarizing layer 115, a bonding layer 116, a second planarizing layer 117, a third planarizing layer 118, a driving transistor DT, a light emitting element LED, a plurality of reflective electrodes RE, a plurality of first connection electrodes CE1, a second connection electrode CE2, a light blocking layer LS, and an auxiliary electrode LE.

[0081] First, the substrate 110 is a component for supporting various components included in the display device 100 and can be made of an insulating material. For example, the substrate 110 can be made of glass, resin, etc. In addition, the substrate 110 can include plastic such as a polymer and can be made of a material having flexibility.

[0082] A light blocking layer LS may be disposed on each of the plurality of sub-pixels SP on the substrate 110. The light blocking layer LS blocks light from entering the active layer ACT of the driving transistor DT, which will be described below, from the lower side of the substrate 110. The light blocking layer LS may block light from entering the active layer ACT of the driving transistor DT, thereby minimizing leakage current.

[0083] A buffer layer 111 may be provided on the substrate 110 and the light blocking layer LS. The buffer layer 111 may reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present invention is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 may not be included. However, the present invention is not limited thereto.

[0084] The driving transistor DT is disposed on the buffer layer 111. The driving transistor DT may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0085] The active layer ACT may be disposed on the buffer layer 111. The active layer ACT may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the present invention is not limited thereto. The buffer layer 111 may include a contact hole for connecting the auxiliary electrode LE and the light blocking layer LS.

[0086] A gate insulating layer 112 may be provided on the active layer ACT. The gate insulating layer 112 is an insulating layer for insulating the active layer ACT from the gate electrode GE. The gate insulating layer 112 may include a contact hole for connecting the auxiliary electrode LE and the light blocking layer LS. In addition, the gate insulating layer 112 may also include a contact hole for connecting the source electrode SE and the active layer ACT. For example, the gate insulating layer 112 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this specification is not limited thereto.

[0087] A gate electrode GE may be disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present invention is not limited thereto.

[0088] An auxiliary electrode LE may be provided on the gate insulating layer 112. The auxiliary electrode LE electrically connects the light-blocking layer LS, disposed below the buffer layer 111, to either the source electrode SE or the drain electrode DE on the second interlayer insulating layer 114. For example, the light-blocking layer LS may be electrically connected to either the source electrode SE or the drain electrode DE via the auxiliary electrode LE so as not to operate as a floating gate, thereby minimizing changes in the threshold voltage of the drive transistor DT caused by the floating light-blocking layer LS. The figure illustrates that the light-blocking layer LS is connected to the source electrode SE. However, the light-blocking layer LS may be connected to the drain electrode DE. However, this specification is not limited thereto.

[0089] A first interlayer insulating layer 113 may be provided on the gate electrode GE and the auxiliary electrode LE. The first interlayer insulating layer 113 may include a contact hole for connecting the source electrode SE and the auxiliary electrode LE. In addition, the first interlayer insulating layer 113 may include a contact hole for connecting the source electrode SE and the active layer ACT. The first interlayer insulating layer 113 is an insulating layer for protecting components provided below the first interlayer insulating layer 113. The first interlayer insulating layer 113 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present specification is not limited thereto.

[0090] A conductive layer TM may be disposed on the first interlayer insulating layer 113. The conductive layer TM may be disposed on the gate electrode GE. The conductive layer TM and the gate electrode GE together may constitute a storage capacitor (not shown). However, depending on the embodiment, the conductive layer TM may not be included.

[0091] A second interlayer insulating layer 114 may be provided on the conductive layer TM. Contact holes may be formed in the second interlayer insulating layer 114, through which the source electrode SE and the drain electrode DE are connected to the active layer ACT. The second interlayer insulating layer 114 may be an insulating layer for protecting components disposed below the second interlayer insulating layer 114. The second interlayer insulating layer 114 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present specification is not limited thereto.

[0092] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT may be disposed on the second interlayer insulating layer 114. The source electrode SE may be connected to the active layer ACT and the auxiliary electrode LE through contact holes included in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. The drain electrode DE may be connected to the active layer ACT through contact holes included in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. The source electrode SE and the drain electrode DE may each be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present invention is not limited thereto.

[0093] A first planarization layer 115 may be provided on the drive transistor DT. The first planarization layer 115 may planarize the upper portion of the substrate 110 on which the drive transistor DT is provided. The first planarization layer 115 may include a contact hole for connecting the reflective electrode RE and the drain electrode DE. The first planarization layer 115 may be configured as a single layer or multiple layers and may be made of, for example, a photoresist or an acrylic-based organic material. However, the present invention is not limited thereto.

[0094] At least one reflective electrode RE may be disposed on the first planarization layer 115. The reflective electrode RE may be connected to the drain electrode DE of the drive transistor DT via a contact hole included in the first planarization layer 115. Furthermore, the plurality of reflective electrodes RE may electrically connect the light-emitting element LED to a power line (not shown). Furthermore, the reflective electrode RE may be disposed below the light-emitting element LED and function as a reflective plate configured to reflect light emitted from the light-emitting element LED toward the upper portion of the light-emitting element LED. The plurality of reflective electrodes RE may each be made of a conductive material having excellent reflective properties and reflect light emitted from the light-emitting element LED toward the upper portion of the light-emitting element LED.

[0095] A bonding layer 116 may be provided on the reflective electrode RE. The front surface of the substrate 110 may be coated with the bonding layer 116, and the bonding layer 116 may fix the light-emitting element LED provided on the bonding layer 116. The bonding layer 116 may include a contact hole for connecting the first connection electrode CE1 and the reflective electrode RE. The bonding layer 116 may be made of an organic material. For example, in this case, the bonding layer 116 may be made of any one material selected from an adhesive polymer, an epoxy resist, a UV resin, a polyimide-based material, an acrylate-based material, a polyurethane-based material, and polydimethylsiloxane (PDMS). However, this specification is not limited thereto.

[0096] A plurality of light-emitting element LEDs may be provided on the bonding layer 116 and on each of the plurality of sub-pixels SP. The plurality of light-emitting element LEDs may be elements configured to emit light by using an electric current, and include light-emitting element LEDs configured to emit red light, green light, blue light, and the like. The plurality of light-emitting element LEDs may be configured to emit light of various colors (including white) by using a combination of red light, green light, blue light, and the like. For example, the plurality of light-emitting element LEDs may each be a light-emitting diode (LED) or a micro-LED. However, the present invention is not limited thereto.

[0097] A second planarization layer 117 may be provided on the bonding layer 116. In this case, the second planarization layer 117 may be provided to surround the first semiconductor layer NL provided below the plurality of first electrodes NE of the plurality of light-emitting elements LED. This allows the plurality of light-emitting elements LED to be secured and protected. The second planarization layer 117 may expose the top surface of the first semiconductor layer NL. The second planarization layer 117 may include at least one contact hole for connecting the first connection electrode CE1 and the reflective electrode RE. For example, the second planarization layer 117 may be made of a photoresist or an acrylic-based organic material. However, this specification is not limited thereto.

[0098] A plurality of first connection electrodes CE1 may be disposed on the second planarization layer 117. The plurality of first connection electrodes CE1 are electrodes disposed on the plurality of sub-pixels SP and electrically connect the light-emitting element LED and the driving transistor DT. The plurality of first connection electrodes CE1 may be connected to the reflective electrode RE via contact holes formed in the second planarization layer 117 and the bonding layer 116. Therefore, the plurality of first connection electrodes CE1 may be electrically connected to any one of the source electrode SE and the drain electrode DE of the driving transistor DT via the reflective electrode RE. However, the present disclosure is not limited thereto. One first connection electrode CE1 may be directly electrically connected to any one of the source electrode SE and the drain electrode DE of the driving transistor DT.

[0099] The plurality of first connection electrodes CE1 may be respectively connected to the plurality of first electrodes NE of the plurality of light-emitting elements LED. The plurality of first connection electrodes CE1 may be formed to cover a portion of the side surface and the top surface of the first semiconductor layer NL. In this case, the plurality of first connection electrodes CE1 may abut a portion of the top surface of the first semiconductor layer NL through the plurality of first opening portions OA1 of the plurality of light-emitting elements LED. Furthermore, the plurality of first connection electrodes CE1 may cover an end portion of the passivation layer PAS that is located on a portion of the top surface of the first semiconductor layer NL. Therefore, the first connection electrode CE1 may be disposed outside the plurality of light-emitting elements LED and on a top surface of the passivation layer PAS that is located on the top surface of the first semiconductor layer NL. In other words, the first semiconductor layer NL, the passivation layer PAS, and the first connection electrode CE1 may be sequentially stacked outside the plurality of light-emitting elements LED. The first semiconductor layer NL and the first connection electrode CE1 may be sequentially stacked in an area adjacent to the plurality of light-emitting elements LED. Furthermore, the first connection electrode CE1 may be provided as a single first connection electrode CE1, and the single first connection electrode CE1 may be electrically connected to the plurality of first electrodes NE.

[0100] The plurality of first connection electrodes CE1 may be disposed inside the plurality of light emitting elements LED and cover the plurality of first electrodes NE. Specifically, the plurality of first connection electrodes CE1 may each be adjacent to a portion of the top surface and a portion of the side surface of each of the plurality of first electrodes NE exposed through the plurality of first opening portions OA1, and Figure 2The first semiconductor layer NL in the LED light emitting diode (LED) is directly adjacent to the top surface of the first semiconductor layer NL exposed through the first opening portion OA1. Furthermore, each of the plurality of first connection electrodes CE1 may be disposed on a passivation layer PAS disposed on a portion of the top surface of each of the plurality of first electrodes NE. In other words, the plurality of first electrodes NE, the passivation layer PAS, and the first connection electrodes CE1 may be sequentially stacked inside the plurality of light-emitting elements LED. Furthermore, the plurality of first electrodes NE and the plurality of first connection electrodes CE1 may be sequentially stacked in a region adjacent to the plurality of light-emitting elements LED.

[0101] The plurality of first connection electrodes CE1 may each be disposed on a portion of the top surface of the first semiconductor layer NL and a portion of the side surface of the second semiconductor layer PL. The plurality of first connection electrodes CE1 may be disposed at a position lower than the top surface of the second semiconductor layer PL. That is, the highest top surface among the top surfaces of the plurality of first connection electrodes CE1 may be located lower than the top surface of the second semiconductor layer PL.

[0102] Meanwhile, a first connection electrode CE1 may be independently provided on each of the plurality of sub-pixels SP, and the first connection electrode CE1 connects the driving transistor DT provided on each of the plurality of sub-pixels SP and the light emitting element LED.

[0103] A third planarization layer 118 may be provided on the plurality of first connection electrodes CE1 and the second planarization layer 117. The third planarization layer 118 may include contact holes for connecting the second connection electrodes CE2 to power lines (not shown). The third planarization layer 118 may expose at least a portion of the top surface of the second semiconductor layer PL of the plurality of light-emitting elements LED. Furthermore, the third planarization layer 118 may expose the second electrode PE by exposing the second opening portion OA2. The third planarization layer 118 may be provided to surround the side surface of the second semiconductor layer PL. The third planarization layer 118 may cover all of the plurality of first connection electrodes CE1. Therefore, the top surface of the third planarization layer 118 may be higher than the highest top surface among the top surfaces of the plurality of first connection electrodes CE1.

[0104] A second connection electrode CE2 may be provided on the third planarization layer 118. The second connection electrode CE2 may be connected to the second electrode PE of each light-emitting element in the plurality of light-emitting elements LED. Although not shown in the drawings, the second connection electrode CE2 may be electrically connected to a power line (not shown) via a reflective electrode RE. The second connection electrode CE2 may be provided on the plurality of light-emitting elements LED and cover the second opening portion OA2. Therefore, the second connection electrode CE2 may be adjacent to the top surface of the second electrode PE exposed by the second opening portion OA2. The second connection electrode CE2 may cover the top surface of the passivation layer PAS provided at the uppermost ends of the plurality of light-emitting elements LED. In addition, the second connection electrode CE2 may be formed to fill the second opening portion OA2. Therefore, the second connection electrode CE2 may be adjacent to the side surface of the passivation layer PAS adjacent to the second opening portion OA2.

[0105] The second connection electrode CE2 and the first connection electrode CE1 may be provided on different layers. The second connection electrode CE2 may be provided at a position higher than the first connection electrode CE1. Therefore, the position of the highest top surface among the top surfaces of the first connection electrode CE1 may be lower than the bottom surface of the second connection electrode CE2. The first connection electrode CE1 and the second connection electrode CE2 may be vertically spaced apart from each other.

[0106] A dam BB may be provided on the third planarization layer 118. The dam BB is a component for separating adjacent sub-pixels SP. The dam BB may be provided so as not to overlap with the light-emitting layer EL of each of the plurality of light-emitting elements LED. The dam BB may be provided on the plurality of first connection electrodes CE1 and partially overlap with the plurality of first connection electrodes CE1. In contrast, the dam BB may be provided so as to be spaced apart from the second connection electrode CE2. The dam BB may be made of an acrylic-based resin, a benzocyclobutene (BCB)-based resin, or a polyimide, and may also include a black component. However, the present specification is not limited thereto.

[0107] The light-emitting element may be a semiconductor light-emitting element that emits light when current is applied to the semiconductor. In this case, the light-emitting element may emit light when electrons and positive holes injected from different electrodes meet in the light-emitting layer. In this case, the different electrodes of the light-emitting element are connected to the driving transistor or the power line. For example, when one electrode of the light-emitting element is connected to the driving transistor, the other electrode is connected to the power line. As described above, the light-emitting element includes at least two different electrodes. In this case, the two different electrodes may sometimes be arranged on the same plane, but the two different electrodes may also be arranged on different planes. For example, one electrode may be arranged on a plane higher than the other electrode.

[0108] As described above, different electrodes of the light-emitting element can be connected to the driving transistor or the power line using separate connection electrodes. In this case, when the different electrodes of the light-emitting element are arranged on different planes, the connection electrodes connected to the different electrodes are also arranged at different positions. In this case, the connection electrodes may be damaged during the process of arranging the different connection electrodes on different electrodes.

[0109] In the following, reference will be made to Figure 6A and Figure 6B Describe the above problem in detail.

[0110] Figure 6A and Figure 6B is an SEM image of a light emitting element in the step of applying and etching a photoresist after providing a first connection line during a process of manufacturing a display device of a comparative example.

[0111] Reference Figure 6A and Figure 6B In the case where one electrode PE of a light-emitting element is disposed on a plane higher than the other electrode NE, the first connection electrode CE1 is preferably disposed on the electrode NE disposed on the lower plane, taking processing into consideration. In this case, the first connection electrode CE1 is disposed on a layer to cover the components disposed below the first connection electrode CE1. Therefore, in a light-emitting element in which both the different electrodes NE and PE are exposed, the first connection electrode CE1 is disposed not only on the electrode NE disposed on the lower plane, but also on the other electrode PE disposed on the higher plane.

[0112] However, as described above, since different voltages need to be applied to the two electrodes NE and PE of the light-emitting element, a common connection electrode is not required for the electrode NE located on the lower plane and the electrode PE located on the upper plane. Therefore, a separate connection electrode needs to be provided on the electrode PE located on the upper plane to apply a voltage different from that of the electrode PE located on the lower plane. Therefore, the following process is required: the connection electrode CE on the other electrode PE located on the upper plane, formed during the process of forming the first connection electrode CE1 on the electrode NE located on the lower plane of the light-emitting element, is removed. In this case, since the first connection electrode CE1 connected to the electrode NE located on the lower plane of the light-emitting element needs to be protected from damage, a photoresist PR is applied to the electrode NE and the first connection electrode CE1 connected to the electrode NE to protect them. The photoresist PR is initially applied to cover the entire light-emitting element. Subsequently, to remove the first connection electrode CE1 connected to the electrode PE located on the upper plane of the light-emitting element, the photoresist PR is etched until the first connection electrode CE1 is exposed.

[0113] At the same time, due to the material characteristics, the top surface of the photoresist PR is not applied flat. That is, when the height of the top surface of the photoresist PR applied on the high plane of the light emitting element and the height of the top surface of the photoresist PR applied on the low plane become different from each other, a predetermined level difference occurs. In this case, the height of the top surface of the photoresist PR decreases from the high plane to the low plane of the light emitting element, and decreases as the distance from the light emitting element increases. That is, as Figure 6A As shown, a height H1 between the top surface of the photoresist PR and the first connection electrode CE1 disposed on the lower plane of the light emitting element, which is disposed at a side adjacent to the upper plane, is higher than a height H2 between the top surface of the photoresist PR and the first connection electrode CE1 disposed at a side away from the upper plane of the light emitting element.

[0114] Therefore, if Figure 6B As shown, when the photoresist PR is etched, the height of the top surface of the photoresist PR gradually decreases depending on the position. Therefore, the height H2' of the top surface of the photoresist PR at the side away from the high plane of the light emitting element becomes lower than the height H1' of the top surface of the photoresist PR adjacent to the high plane of the light emitting element. Therefore, in the first connection electrode CE1 on the electrode NE provided on the low plane of the light emitting element, as the photoresist PR is etched, the first connection electrode CE1 at the side away from the high plane of the light emitting element may be exposed (A). Therefore, since a portion of the first connection electrode CE1 is exposed (A) by the photoresist PR, the following disconnection problem occurs: the first connection electrode CE1 is damaged by the continuous process of etching the photoresist PR and the process of removing unnecessary first connection electrode CE1 after the process of etching the photoresist PR.

[0115] Therefore, according to the light-emitting element LED and the display device 100 including the light-emitting element LED according to the embodiment of the present specification, the passivation layer PAS is not provided on a portion of the top surface and a portion of the side surface of the plurality of first electrodes NE provided on the lower plane of the light-emitting element LED. As described above, the passivation layer PAS is not provided on a portion of the top surface of the plurality of first electrodes NE, so that the height of a portion of the top surface of the passivation layer PAS can be reduced. Since the height of the top surface of the passivation layer PAS is reduced as described above, the distance between the top surface of the applied photoresist PR and the top surface of the passivation layer PAS can be increased in consideration of the processing. Therefore, it is possible to suppress the exposure of the lower components by the process of etching the photoresist PR during the process. In addition, it is possible to suppress damage to the lower components caused when the lower components are exposed.

[0116] In addition, according to the light emitting element LED and the display device 100 including the light emitting element LED according to the embodiment of the present specification, the plurality of first electrodes NE may be provided to be aligned with the end portion (eg, Figure 2 In other words, the plurality of first electrodes NE can be closer to the light-emitting layer EL than the ends in the horizontal direction of the first semiconductor layer NL shown in the figure, that is, the lateral or side ends) to the light-emitting layer EL. That is, the plurality of first electrodes NE can each be arranged inside the light-emitting element LED - where the photoresist PR is applied to have a relatively high height. Therefore, the plurality of first electrodes NE can be suppressed from being exposed by the process of etching the photoresist PR. Therefore, damage to the first electrodes NE can be suppressed. In addition, since the plurality of first electrodes NE are arranged inside the light-emitting element LED, it is possible to ensure a space in which the passivation layer PAS is directly arranged on the top surface of the first semiconductor layer NL adjacent to the end of the first semiconductor layer NL. Therefore, the passivation layer PAS and some of the plurality of first electrodes NE can be spaced apart from each other. Therefore, the height of a portion of the top surface of the passivation layer PAS can be more easily reduced.

[0117] Figure 7 is a schematic top plan view of a light emitting element according to another embodiment of the present specification. Figure 8 It is along Figure 7 A cross-sectional view taken along line VIII-VIII'. Figure 7 and Figure 8 The light emitting element LED' and Figure 1 and Figure 2 The light emitting elements LED in FIG. 1 are substantially the same in configuration, except for the configuration of the passivation layer PAS. Therefore, repeated descriptions of the same components will be omitted.

[0118] Reference Figure 7 and Figure 8 According to another embodiment of the present disclosure, a light-emitting element LED′ includes: a first semiconductor layer NL; a plurality of first electrodes NE disposed on one side and the other side of the first semiconductor layer NL; a light-emitting layer EL disposed on the first semiconductor layer NL and between the plurality of first electrodes NE; a second semiconductor layer PL disposed on the light-emitting layer EL; a second electrode PE disposed on the second semiconductor layer PL; and a passivation layer PAS configured to cover the first semiconductor layer NL, the plurality of first electrodes NE, the second semiconductor layer PL, and the second electrode PE. In other words, the passivation layer PAS may be disposed to cover all components disposed below the passivation layer PAS.

[0119] In addition, the passivation layer PAS includes at least one portion having different thicknesses. The passivation layer PAS may include three or more portions having different thicknesses. For example, the passivation layer PAS may include first portions T1-1, T1-2, and T1-3 having the smallest thicknesses, second portions T2-1 and T2-2 having medium thicknesses, and third portions T3-1, T3-2, T3-3, and T3-4 having the largest thicknesses. However, the present specification is not limited thereto. In addition to the above-mentioned portions, the passivation layer PAS may further include at least one portion having different thicknesses. Figure 8 This configuration is described in more detail. In the top surface of the first semiconductor layer NL, a passivation layer PAS is provided on the top surface of the first semiconductor layer NL provided outside the plurality of first electrodes NE. In this case, the passivation layer PAS may include at least one portion having different thicknesses. For example, the passivation layer PAS provided on the first semiconductor layer NL outside the plurality of first electrodes NE may include a first portion T1-1 having a small thickness and a third portion T3-1 having a large thickness; that is, the second portion having a medium thickness may be omitted. In addition, the first portion T1-1 having a small thickness may be provided adjacent to the first electrode NE, while the third portion T3-1 having a large thickness may be provided away from the first electrode NE. Therefore, the first portion T1-1 having a small thickness is provided away from the light-emitting layer EL, so that the first electrode NE exists between the first portion T1-1 and the light-emitting layer EL, so that the first portion T1-1 may be provided to surround at least a portion of the first electrode NE.

[0120] The passivation layer PAS disposed on the plurality of first electrodes NE may include at least one portion having different thicknesses. For example, the passivation layer PAS disposed on the plurality of first electrodes NE may include a first portion T1-2 having a smaller thickness and a third portion T3-2 having a larger thickness. In this case, the third portion T3-2 having the larger thickness may be disposed adjacent to the light-emitting layer EL. The first portion T1-2 having the smaller thickness may be disposed away from the light-emitting layer EL. The first portion T1-2 having the smaller thickness of the passivation layer PAS disposed on the plurality of first electrodes NE may extend to a portion of the side surface of each of the plurality of first electrodes NE and may be connected to the portion T1-1 having the smaller thickness of the passivation layer PAS disposed on the first semiconductor layer NL. Therefore, the thicknesses of the portions T1-1 and T1-2 having the smaller thickness of the passivation layer PAS disposed on the first semiconductor layer NL and each of the plurality of first electrodes NE may be substantially equal or similar to each other. However, this description is not limited to this. In addition, the thickness of the third portion T3-2 of the passivation layer PAS on the plurality of first electrodes NE and the thickness of the third portion T3-1 of the passivation layer PAS on the first semiconductor layer NL may be substantially equal to or similar to each other. However, the present specification is not limited thereto.

[0121] The passivation layer PAS disposed on the second electrode PE may include a first portion T1-3 having a small thickness and a third portion T3-4 having a large thickness. In this case, the first portion T1-3 having a small thickness may be disposed on the central portion of the second electrode PE, while the third portion T3-4 having a large thickness may be disposed on the second electrode PE and along the edge of the second electrode PE. The third portion T3-4 having a large thickness of the passivation layer PAS may be disposed on the second electrode PE and surround the first portion T1-3 having a small thickness. In the passivation layer PAS on the second electrode PE, the third portion T3-4 having a large thickness may extend to the outside of the second electrode PE and be connected to the passivation layer PAS on the second semiconductor layer PL. In addition, the passivation layer PAS on the second semiconductor layer PL may extend along the side surface of the second semiconductor layer PL and be connected to the thicker third portion T3-2 of the passivation layer PAS on the plurality of first electrodes NE. Therefore, the thickness of the thicker third portion T3-4 of the passivation layer PAS on the second electrode PE, the thickness of the thicker third portion T3-3 of the passivation layer PAS on the second semiconductor layer PL, and the thickness of the thicker third portion T3-2 of the passivation layer PAS on the plurality of first electrodes NE may be substantially equal to or similar to one another. However, the present specification is not limited thereto.

[0122] The thicknesses of the thin portions T1-1, T1-2, and T1-3 of the passivation layer PAS disposed on the first semiconductor layer NL, the first electrodes NE, and the second electrode PE outside the plurality of first electrodes NE may be substantially equal to or similar to each other. However, this specification is not limited to this. Furthermore, the thicknesses of the thin portions T1-1, T1-2, and T1-3 of the passivation layer PAS disposed on the first semiconductor layer NL, the first electrodes NE, and the second electrode PE outside the plurality of first electrodes NE may be smaller than the thicknesses of the portions T2-1 and T2-2 of the passivation layer PAS disposed on the side surfaces of the first semiconductor layer NL and the second semiconductor layer PL. Furthermore, the thicknesses of the thin portions T1-1, T1-2, and T1-3 of the passivation layer PAS disposed on the first semiconductor layer NL, the first electrodes NE, and the second electrode PE outside the plurality of first electrodes NE may be the smallest of the thicknesses of the entire passivation layer PAS. These components may serve to protect the plurality of first electrodes NE and the second electrode PE and may be removed as needed. For example, during the manufacturing process of the display device, the thin portions T1-1 and T1-2 of the passivation layer PAS on the plurality of first electrodes NE and the first semiconductor layer NL disposed outside the plurality of first electrodes NE may be removed as needed. Thus, a plurality of first opening portions OA1 may be formed from the removed portions T1-1 and T1-2. The plurality of first connection electrodes CE1 may be connected to the plurality of first electrodes NE through the first opening portions OA1 formed as described above. Furthermore, the thin portion T1-3 of the passivation layer PAS disposed on the second electrode PE may be removed as needed, thereby forming a second opening portion OA2. The second connection electrode CE2 may be connected to the second electrode PE through the second opening portion OA2 formed as described above.

[0123] At the same time, the thickness of the portions T3-1, T3-2 and T3-4 with large thickness of the passivation layer PAS arranged on the first semiconductor layer NL arranged outside the multiple first electrodes NE, on the multiple first electrodes NE and on the second electrode PE can be greater than the thickness of the portions T2-1 and T2-2 of the passivation layer PAS arranged on the side surface of the first semiconductor layer NL and the side surface of the second semiconductor layer PL.

[0124] The light-emitting element includes at least two distinct electrodes to be connected to a drive transistor or a power line. In this case, the two distinct electrodes may sometimes be arranged on the same plane, but the two distinct electrodes may also be arranged on different planes. Since the two distinct electrodes need to be electrically connected to the drive transistor or the power line as described above, the two distinct electrodes of the light-emitting element need to be at least partially exposed.

[0125] In this case, in the light-emitting element LED' according to another embodiment of the present disclosure, the passivation layer PAS on the plurality of first electrodes NE and the second electrode PE may include portions having different thicknesses. Therefore, the passivation layer PAS on the plurality of first electrodes NE and the second electrode PE includes portions T1-2 and T1-3 having smaller thicknesses, making it easier to remove the corresponding portions. Therefore, the plurality of first electrodes NE and the second electrode PE can be easily exposed at least partially.

[0126] In addition, in a light-emitting element LED' according to another embodiment of the present specification, the passivation layer PAS on the first semiconductor layer NL disposed outside the plurality of first electrodes NE may include portions having different thicknesses. Therefore, the portion T1-1 of the passivation layer PAS having a smaller thickness may be disposed on at least a portion of the first semiconductor layer NL disposed outside the plurality of first electrodes NE. Therefore, at least a portion of the first semiconductor layer NL disposed outside the plurality of first electrodes NE can be easily exposed.

[0127] Furthermore, a thin portion T1-1 of the passivation layer PAS may be disposed on the first semiconductor layer NL disposed outside the plurality of first electrodes NE, and this portion T1-1 may be disposed adjacent to the plurality of first electrodes NE. Therefore, by removing the thin portion T1-1 of the passivation layer PAS from the first semiconductor layer NL disposed outside the plurality of first electrodes NE, at least one side portion of each of the plurality of first electrodes NE and a distal end of the passivation layer PAS may be spaced apart from each other. Consequently, the plurality of first electrodes NE may be disposed inside the light-emitting element LED', adjacent to the light-emitting layer EL. Consequently, damage to the plurality of first electrodes NE can be suppressed.

[0128] Exemplary embodiments of the present disclosure may also be described as follows:

[0129] According to one aspect of the present disclosure, a light-emitting element includes: a first semiconductor layer; a plurality of first electrodes arranged on one side and the other side of the first semiconductor layer; a light-emitting layer arranged on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer arranged on the light-emitting layer; a second electrode arranged on the second semiconductor layer; and a passivation layer, which is configured to cover at least a portion of the first semiconductor layer, at least a portion of the light-emitting layer, and at least a portion of the second semiconductor layer, and a plurality of first opening portions are provided on the passivation layer, and the first opening portions expose a portion of a top surface and a portion of a side surface of each of the plurality of first electrodes.

[0130] A portion of a side surface of each of the plurality of first electrodes that is opposite to the light emitting layer is covered by the passivation layer, and the remaining portion of the side surface of each of the plurality of first electrodes may be exposed by the passivation layer.

[0131] A portion of the end portion of the passivation layer may be adjacent to the top surface of the first semiconductor layer.

[0132] A portion of the top surface of the first semiconductor layer may be exposed through the first opening portion.

[0133] The portion of the top surface of the first semiconductor layer exposed through the first opening may be disposed farther from the light emitting layer than the first electrode is from the light emitting layer.

[0134] The passivation layer may include a second opening portion configured to expose a portion of a top surface of the second electrode.

[0135] Each of the plurality of first electrodes may be provided closer to the light emitting layer than to the end portion of the first semiconductor layer.

[0136] According to another aspect of the present disclosure, a display device includes: a substrate on which pixels including a plurality of sub-pixels are defined; and a plurality of light-emitting elements, the plurality of light-emitting elements being arranged in the plurality of sub-pixels and including a plurality of first electrodes and a second electrode, each of the plurality of light-emitting elements including: a first semiconductor layer; a plurality of first electrodes arranged on one side and the other side of the first semiconductor layer; a light-emitting layer arranged on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer arranged on the light-emitting layer; a second electrode arranged on the second semiconductor layer; and a passivation layer configured to cover at least a portion of the first semiconductor layer, at least a portion of the light-emitting layer, and at least a portion of the second semiconductor layer, and a plurality of first opening portions being provided on the passivation layer, the first opening portions exposing a portion of a top surface and a portion of a side surface of each of the plurality of first electrodes.

[0137] The display device may further include: a plurality of first connection electrodes respectively connected to the plurality of first electrodes; and a second connection electrode connected to the second electrode.

[0138] The second connection electrode and the plurality of first connection electrodes may be provided on different layers.

[0139] The plurality of first connection electrodes may be disposed adjacent to top surfaces and side surfaces of the plurality of first electrodes exposed through the plurality of first opening portions.

[0140] The plurality of first connection electrodes may be disposed adjacent to a top surface of the first semiconductor layer exposed through the plurality of first opening portions.

[0141] A second opening portion exposing a portion of a top surface of the second electrode may be provided on the passivation layer, and the second connection electrode may be provided adjacent to the top surface of the second electrode exposed through the second opening portion.

[0142] According to another aspect of the present disclosure, a light-emitting element includes: a first semiconductor layer; a plurality of first electrodes arranged on one side and the other side of the first semiconductor layer; a light-emitting layer arranged on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer arranged on the light-emitting layer; a second electrode arranged on the second semiconductor layer; and a passivation layer configured to cover the first semiconductor layer, the plurality of first electrodes, the second semiconductor layer, and the second electrode, the passivation layer including portions having different thicknesses.

[0143] The portions having different thicknesses may be provided as three or more portions.

[0144] The passivation layers disposed on the first semiconductor layer disposed outside the plurality of first electrodes, on the plurality of first electrodes, and on the second electrode may respectively include at least one portion having a different thickness.

[0145] Among the portions of the passivation layer having different thicknesses, a portion having a large thickness may be disposed on the plurality of first electrodes and adjacent to the light emitting layer.

[0146] Among the portions of the passivation layer having different thicknesses, the portion having the large thickness may be disposed on the first semiconductor layer disposed outside the plurality of first electrodes and disposed away from the first electrodes.

[0147] Among the portions of the passivation layer having different thicknesses, the portion having a large thickness may be disposed on the second electrode along an edge of the second electrode.

[0148] Among the portions of the passivation layer having different thicknesses, the portion having the small thickness may be disposed adjacent to the plurality of first electrodes and disposed on the first semiconductor layer disposed outside the plurality of first electrodes.

[0149] Among the portions of the passivation layer having different thicknesses, a portion having a small thickness may be disposed on the plurality of first electrodes and disposed away from the light emitting layer.

[0150] Among the portions of the passivation layer having different thicknesses, the portion having a small thickness may be disposed on a central portion of the second electrode.

[0151] The thickness of the portion with a small thickness of the passivation layer arranged on the first semiconductor layer arranged outside the multiple first electrodes, on the multiple first electrodes, and on the second electrode can be smaller than the thickness of the passivation layer arranged on the side surface of the first semiconductor layer and the side surface of the second semiconductor layer.

[0152] The thickness of the portion with a large thickness of the passivation layer arranged on the first semiconductor layer arranged outside the multiple first electrodes, on the multiple first electrodes, and on the second electrode can be greater than the thickness of the passivation layer arranged on the side surface of the first semiconductor layer and the side surface of the second semiconductor layer.

[0153] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the following claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A light-emitting element, comprising: a first semiconductor layer; a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer; a light emitting layer disposed on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer disposed on the light-emitting layer; a second electrode disposed on the second semiconductor layer; as well as a passivation layer, the passivation layer being configured to cover at least a portion of the first semiconductor layer, at least a portion of the light emitting layer, and at least a portion of the second semiconductor layer, A plurality of first opening portions are provided on the passivation layer, wherein the first opening portions expose a portion of a top surface and a portion of a side surface of each of the plurality of first electrodes.

2. The light-emitting element according to claim 1, wherein A portion of a side surface of each of the plurality of first electrodes facing the light emitting layer is covered by the passivation layer, and the remaining portion of the side surface of each of the plurality of first electrodes is exposed by the passivation layer.

3. The light-emitting element according to claim 1, wherein A portion of an end portion of the passivation layer is adjacent to a top surface of the first semiconductor layer.

4. The light-emitting element according to claim 1, wherein A portion of a top surface of the first semiconductor layer is exposed through the first opening portion.

5. The light-emitting element according to claim 4, wherein The portion of the top surface of the first semiconductor layer exposed through the first opening is disposed farther from the light emitting layer than the first electrode is from the light emitting layer. The light-emitting element according to claim 1 , wherein The passivation layer includes a second opening portion configured to expose a portion of a top surface of the second electrode.

7. The light-emitting element according to claim 1, wherein Each of the plurality of first electrodes is disposed closer to the light emitting layer than an end portion of the first semiconductor layer is to the light emitting layer.

8. A display device comprising: a substrate, on which pixels including a plurality of sub-pixels are defined; as well as a plurality of light-emitting elements, each of which is provided in each of the plurality of sub-pixels and includes a plurality of first electrodes and a second electrode; Wherein, each of the plurality of light-emitting elements comprises: a first semiconductor layer; a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer; a light emitting layer disposed on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer disposed on the light-emitting layer; a second electrode disposed on the second semiconductor layer; and a passivation layer configured to cover at least a portion of the first semiconductor layer, at least a portion of the light emitting layer, and at least a portion of the second semiconductor layer, and A plurality of first opening portions are provided on the passivation layer, wherein the first opening portions expose a portion of a top surface and a portion of a side surface of each of the plurality of first electrodes.

9. The display device according to claim 8, further comprising: a plurality of first connection electrodes respectively connected to the plurality of first electrodes, and A second connection electrode is connected to the second electrode.

10. The display device according to claim 9, wherein The second connection electrode and the plurality of first connection electrodes are disposed on a different layer.

11. The display device according to claim 9, wherein The plurality of first connection electrodes are disposed adjacent to top surfaces and side surfaces of the plurality of first electrodes exposed through the plurality of first opening portions.

12. The display device according to claim 9, wherein The plurality of first connection electrodes are disposed adjacent to a top surface of the first semiconductor layer exposed through the plurality of first opening portions.

13. The display device according to claim 9, wherein: A second opening portion is provided on the passivation layer, the second opening portion exposing a portion of a top surface of the second electrode, and the second connection electrode is provided adjacent to the top surface of the second electrode exposed through the second opening portion.

14. A light-emitting element, comprising: a first semiconductor layer; a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer; a light emitting layer disposed on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer disposed on the light-emitting layer; a second electrode disposed on the second semiconductor layer; as well as a passivation layer, the passivation layer being configured to cover the first semiconductor layer, the plurality of first electrodes, the second semiconductor layer, and the second electrode, The passivation layer includes portions with different thicknesses.

15. The light-emitting element according to claim 14, wherein The portions having different thicknesses are provided in three or more portions.

16. The light-emitting element according to claim 14, wherein The passivation layer disposed on the first semiconductor layer disposed outside the plurality of first electrodes, on the plurality of first electrodes, and on the second electrode respectively includes at least one portion having a different thickness.

17. The light-emitting element according to claim 16, wherein Among the portions of the passivation layer having different thicknesses, a portion having a large thickness is disposed on the plurality of first electrodes and adjacent to the light emitting layer.

18. The light-emitting element according to claim 16, wherein Among the portions of the passivation layer having different thicknesses, the portion having a large thickness is disposed on the first semiconductor layer disposed outside the plurality of first electrodes and is disposed away from the first electrodes.

19. The light-emitting element according to claim 16, wherein Among the portions of the passivation layer having different thicknesses, the portion having a large thickness is disposed on the second electrode along an edge of the second electrode.

20. The light-emitting element according to claim 16, wherein Among the portions of the passivation layer having different thicknesses, a portion having a small thickness is disposed adjacent to the plurality of first electrodes and on the first semiconductor layer disposed outside the plurality of first electrodes.

21. The light-emitting element according to claim 16, wherein Among the portions of the passivation layer having different thicknesses, a portion having a small thickness is disposed on the plurality of first electrodes and is disposed away from the light emitting layer.

22. The light-emitting element according to claim 16, wherein Among the portions of the passivation layer having different thicknesses, the portion having a small thickness is disposed on a central portion of the second electrode.

23. The light-emitting element according to claim 16, wherein The thickness of the portion with a small thickness of the passivation layer arranged on the first semiconductor layer arranged outside the multiple first electrodes, on the multiple first electrodes, and on the second electrode is smaller than the thickness of the passivation layer arranged on the side surface of the first semiconductor layer and the side surface of the second semiconductor layer.

24. The light-emitting element according to claim 16, wherein The thickness of the portion with a large thickness of the passivation layer arranged on the first semiconductor layer arranged outside the multiple first electrodes, on the multiple first electrodes, and on the second electrode is greater than the thickness of the passivation layer arranged on the side surface of the first semiconductor layer and the side surface of the second semiconductor layer.

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