Display panel, preparation method thereof and display device
Through photolithography technology, pixel openings are formed on the display panel, and the maskless plate preparation method is adopted to solve the cathode sheath phenomenon and high cost problems caused by the mask plate, and the preparation of display panels with high yield, ultra-high PPI and improved luminous efficiency is achieved.
Patent Information
- Application Number
- CN202410232230.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-29
- Publication Date
- 2025-08-29
AI Technical Summary
In the prior art, the cathode sheath phenomenon occurs during chemical vapor deposition by using metal mask plates, resulting in thinning of the inorganic film, and the mask plate is expensive and cannot be generalized, which increases production costs.
A photolithography technology is used to form multiple pixel openings on the display panel, and the display panel is prepared by a maskless plate, and an inorganic protective layer is used to protect the anode and cathode to avoid the use of the mask panel.
The display panel is prepared without masks, which improves the yield of the display panel, reduces the mask board alignment accuracy and Shadow impact, realizes ultra-high PPI, and improves the device luminous efficiency, brightness and life.
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Figure CN120568985A_ABST
Abstract
Description
Technical Field
[0001] The present application generally relates to the field of display technology, and specifically relates to a display panel and a manufacturing method thereof, and a display device. Background Art
[0002] OLED devices are organic electroluminescent devices, and their materials are easily oxidized and become ineffective, so certain methods are needed to protect them. The current method used in the industry is: using chemical vapor deposition equipment to deposit a layer / multiple layers of inorganic thin film on the light-emitting device to isolate it from water and oxygen.
[0003] Due to the characteristics of chemical vapor deposition, all objects in the entire device space will be covered by the inorganic film layer, and the inorganic film layer does not have conductive properties, so a mask plate is needed to protect the area that requires external circuits. The setting method of the mask plate is as follows Figure 1 shown.
[0004] There are two problems with the use of mask plates: First, the mask plate is made of metal, and in the plasma environment of chemical atmospheric deposition, a "cathode sheath phenomenon" will occur. This phenomenon will cause the inorganic film near the mask plate area to become thinner, which is called Shadow in the industry, thereby reducing the packaging performance; second, the metal mask plate is made of Invar alloy, which is extremely expensive, and the mask plates of different products cannot be used interchangeably, which greatly increases the production cost. Summary of the Invention
[0005] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a display panel and a method for manufacturing the same, as well as a display device, which can realize maskless manufacturing of the display panel and improve the yield of the display panel.
[0006] In a first aspect, the present application provides a method for preparing a display panel, the method comprising:
[0007] providing a base substrate, and forming an anode layer on the base substrate;
[0008] forming a first protective layer, a cathode layer and a second protective layer in sequence on the anode layer;
[0009] forming a plurality of pixel openings, the pixel openings penetrating the first protective layer, the cathode layer, and the second protective layer and exposing a surface of the anode layer, the pixel openings including a first pixel opening for forming a first sub-pixel, a second pixel opening for forming a second sub-pixel, and a third pixel opening for forming a third sub-pixel;
[0010] forming a first photoresist layer on the second protective layer, wherein the first photoresist at least fills the pixel opening;
[0011] removing the first photoresist layer in the first pixel opening and forming a first sub-pixel in the first pixel opening, wherein the first sub-pixel includes a first light-emitting layer, a first cathode sub-layer, and a first protective sub-layer sequentially formed on the anode layer;
[0012] removing the first photoresist layer in the second pixel opening and forming a second sub-pixel in the second pixel opening, wherein the second sub-pixel includes a second light-emitting layer, a second cathode sub-layer, and a second protective sub-layer sequentially formed on the anode layer;
[0013] The first photoresist layer in the third pixel opening is removed and a third sub-pixel is formed in the third pixel opening. The third sub-pixel includes a third light-emitting layer, a third cathode sub-layer, and a third protective sub-layer sequentially formed on the anode layer.
[0014] Optionally, forming a first photoresist layer on the second protective layer, wherein the first photoresist at least fills the pixel opening, the method includes:
[0015] forming a first photoresist sublayer on the second protective layer, wherein the first photoresist sublayer is used to remove the first photoresist sublayer within the first pixel opening to form the first sub-pixel; and the first photoresist sublayer is further used to simultaneously etch and retain the first photoresist sublayer in the remaining area except for the first pixel opening during the process of forming the first sub-pixel;
[0016] forming a second photoresist sublayer on the second protective layer, wherein the second photoresist sublayer is used to remove the second photoresist sublayer within the second pixel opening to form the second sub-pixel; and the second photoresist sublayer is further used to simultaneously etch the second photoresist sublayer on the remaining area except for the second pixel opening during the formation of the second sub-pixel;
[0017] A third photoresist sublayer is formed on the second protective layer, and the third photoresist sublayer is used to remove the third photoresist sublayer within the third pixel opening to form the third sub-pixel; the third photoresist sublayer is also used to simultaneously etch and retain the third photoresist sublayer on the remaining area except for the corresponding third pixel opening during the process of forming the third sub-pixel.
[0018] Optionally, the heights of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer are less than or equal to the height of the first protective layer;
[0019] The surfaces of the first protective sublayer, the second protective sublayer, and the third protective sublayer on a side away from the base substrate are flush with the surface of the second protective layer.
[0020] Optionally, the cross-sectional shape of the pixel opening in a direction perpendicular to the substrate is a trapezoid, the trapezoid comprising a first side length close to the substrate and a second side length away from the substrate, the first side length being shorter than the second side length;
[0021] The trapezoid includes a hypotenuse connecting the first side length and the second side length, and the angle between the hypotenuse and the first side length is 60° to 89°.
[0022] Optionally, the method of forming a plurality of pixel openings includes:
[0023] forming a second photoresist layer on the anode layer and patterning the layer to form a shape-defining layer, wherein the cross-sectional shape of the shape-defining layer in a direction perpendicular to the substrate is the trapezoid;
[0024] forming the first protective layer, the cathode layer, and the second protective layer in sequence on the anode layer, wherein the first protective layer, the cathode layer, and the second protective layer all conformally cover a portion of the hypotenuse of the trapezoid;
[0025] The pixel opening is formed after the shape definition layer is removed by etching.
[0026] Optionally, the first protective layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride, and the second protective layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.
[0027] Optionally, a first wiring layer is provided on the base substrate, a first via hole is provided on the first protective layer, and the cathode layer contacts the first wiring layer through the first via hole.
[0028] Optionally, a second wiring layer is provided on a side of the second protective layer away from the base substrate, a second via hole is provided on the second protective layer, and the cathode layer contacts the second wiring layer through the second via hole.
[0029] In a second aspect, the present application provides a display panel, which is prepared using any of the above-described methods for preparing a display panel.
[0030] In a third aspect, the present application provides a display device comprising the display panel as described above.
[0031] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:
[0032] The display panel provided in the embodiment of the present application uses photolithography technology, and does not require the use of a metal mask plate to produce OLED devices. There is no mask plate alignment accuracy and shadow influence, the pixel spacing can be made very small, and the display panel can be prepared without a mask. It can achieve ultra-high PPI of the display panel, improve the luminous efficiency, brightness and life of the device, and increase the preparation yield of the dimming display panel. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:
[0034] Figure 1 A schematic diagram of a partial structure of a display panel after formation according to a method for manufacturing the display panel provided in an embodiment of the present application;
[0035] Figure 2 A schematic diagram of a partial structure of a display panel after formation according to a method for manufacturing the display panel provided in an embodiment of the present application;
[0036] Figure 3 A schematic diagram of a partial structure of a display panel after formation according to a method for manufacturing the display panel provided in an embodiment of the present application;
[0037] Figure 4 A schematic diagram of a partial structure of a display panel after formation according to a method for manufacturing the display panel provided in an embodiment of the present application;
[0038] Figure 5 A schematic diagram of a partial structure of a display panel after formation according to a method for manufacturing the display panel provided in an embodiment of the present application;
[0039] Figure 6 A schematic diagram of a partial structure of a display panel after formation according to a method for manufacturing the display panel provided in an embodiment of the present application;
[0040] Figure 7 A schematic diagram of a partial structure of a display panel after formation according to a method for manufacturing the display panel provided in an embodiment of the present application;
[0041] Figure 8 A schematic diagram of a portion of the structure of another method for manufacturing a display panel provided in an embodiment of the present application;
[0042] Figure 9 A schematic diagram of a portion of the structure of another method for manufacturing a display panel provided in an embodiment of the present application;
[0043] Figure 10 A schematic diagram of a partial structure of a display panel provided in an embodiment of the present application;
[0044] Figure 11A partial structural diagram of another display panel provided in an embodiment of the present application. DETAILED DESCRIPTION
[0045] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the invention are shown in the accompanying drawings.
[0046] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0047] The display panel provided in the embodiments of the present application may be an active light-emitting display panel, such as an organic light emitting diode (OLED) display panel, an active-matrix organic light emitting diode (AMOLED) display panel, a passive-matrix organic light emitting diode (PMOLED) display panel, a quantum dot organic light emitting diode (QLED) display panel, etc. In the embodiments of the present application, an OLED display panel is used as an example for exemplary description.
[0048] Please see Figure 1-7 , the present application provides a method for preparing a display panel, the method comprising:
[0049] S100, providing a base substrate 100, and forming an anode layer 200 on the base substrate 100;
[0050] In the embodiment of the present application, the substrate 100 may be a thin film transistor (TFT) array substrate. The substrate 100 may include an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, source and drain electrodes, and a planarization layer sequentially stacked on a substrate. As described above, the TFT structure is a top-gate type. However, the TFT structure in this embodiment may also be a bottom-gate type, which is not a limitation of this embodiment.
[0051] Those skilled in the art will appreciate that the above-mentioned thin-film transistor structure does not limit the thin-film transistor. A thin-film transistor may include more or fewer of the above-mentioned hierarchical structures, or a combination of certain hierarchical structures, or different hierarchical structures. This application is also applicable to thin-film transistor structures of other structures, which will not be described in detail here.
[0052] In the embodiments of the present application, the light-emitting elements in the OLED display panel can be top-emitting or bottom-emitting. In different embodiments, the top-emitting light-emitting element includes a light-emitting layer and a reflective anode and a transparent cathode disposed on both sides of the light-emitting layer. The bottom-emitting light-emitting element includes a light-emitting layer and a transparent anode and a reflective cathode disposed on both sides of the light-emitting layer. The device is selected according to the application scenario and other factors.
[0053] In this embodiment, when the anode layer 200 and / or the cathode layer 400 is a transparent electrode, the anode layer 200 and / or the cathode layer 400 may be formed of, for example, ITO, IZO, ZnO, or In2O3. When the anode layer 200 and / or the cathode layer 400 is a reflective electrode, the anode layer 200 and / or the cathode layer 400 may include, for example, a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a mixture thereof, and a transparent film formed of ITO, IZO, ZnO, or In2O3.
[0054] The light-emitting layer in this invention refers to a light-emitting layer within the organic compound layer disposed between the anode and cathode. The host in each light-emitting layer is the material that serves as the primary component of the materials contained within the light-emitting layer. The light-emitting layer can employ a variety of different hierarchical structures known in the art, and this application does not limit this.
[0055] Exemplarily, the light-emitting layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emitting prime layer (Emitting Prime Layer), an emitting functional layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL), which are arranged in sequence from the anode to the cathode.
[0056] S200, forming a first protective layer 300, a cathode layer 400 and a second protective layer 500 on the anode layer 200 in sequence; the structure after formation is as follows Figure 1 shown.
[0057] Optionally, the first protective layer 300 includes one or more of silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (SiOxNy), and the second protective layer 500 includes one or more of silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (SiOxNy).
[0058] In the embodiment of the present application, by arranging the first protective layer 300 and the second protective layer 500 on the anode layer 200, insulation between the anode layer 200, the cathode layer 400 and other conductive layers is achieved, and the water and oxygen resistance of the panel can be improved. By adopting the first protective layer 300 and the second protective layer 500 of inorganic materials, the subsequently formed light-emitting layer and cathode layer 400 can be reduced from being damaged by the developer and the etching material, thereby improving the preparation quality of the display panel.
[0059] S300, forming a plurality of pixel openings 600 by a patterning process, wherein the pixel openings 600 penetrate the first protective layer 300, the cathode layer 400 and the second protective layer 500 and expose the surface of the anode layer 200, and the pixel openings 600 include a first pixel opening 610 for forming the first sub-pixel 110, a second pixel opening 620 for forming the second sub-pixel 120 and a third pixel opening 630 for forming the third sub-pixel 130. The structure after formation is as follows Figure 2 shown.
[0060] In the embodiment of the present application, the display panel includes a plurality of sub-pixel units arranged in an array, wherein the sub-pixel units include a first sub-pixel 110 that emits a first color light (e.g., red light), a second sub-pixel 120 that emits a second color light (e.g., green light), and a third sub-pixel 130 that emits a third color light (e.g., blue light). In other embodiments, the sub-pixel units may also emit other colors of light, such as white light, and the types of sub-pixels are not limited herein.
[0061] Optionally, the cross-sectional shape of the first sub-pixel 110, the second sub-pixel 120, and the third sub-pixel 130 in a direction parallel to the base substrate 100 is any one of a triangle, a quadrilateral, a pentagon, a hexagon, or an octagon, and the shape of the pixel opening 600 is adapted to the shape of the sub-pixel. In actual applications, the cross-sectional shape can be flexibly set according to actual conditions such as the application of the display panel or the display effect requirements.
[0062] Optionally, the cross-sectional shape of the pixel opening 600 in a direction perpendicular to the base substrate 100 is a trapezoid, the trapezoid including a first side length close to the base substrate 100 and a second side length away from the base substrate 100, the length of the first side length being less than the length of the second side length; the trapezoid including a hypotenuse connecting the first side length and the second side length, the angle between the hypotenuse and the first side length being 60° to 89°.
[0063] It should be noted that the angle of the bevel is not limited in the embodiments of this application and can be adjusted as needed in different embodiments. In this embodiment, the trapezoidal cross-section of the pixel opening 600 can facilitate the subsequent formation of the light-emitting layer within the pixel opening 600 by evaporation or other methods, thereby preventing the vapor deposition material from adhering to the bevel and affecting the production effect. In practice, the angle of the bevel can be adjusted according to the evaporation angle.
[0064] The "patterning process" mentioned in the embodiments of the present application includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist, which is a known mature preparation process. Deposition can adopt known processes such as sputtering, evaporation, and chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not limited here. In the description of the embodiments of the present disclosure, a "thin film" refers to a thin film made by depositing or coating a certain material on a substrate. If the "thin film" does not require a patterning process or a photolithography process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".
[0065] S400 , forming a first photoresist layer on the second protection layer 500 , wherein the first photoresist at least fills the pixel opening 600 .
[0066] The photoresist layer may be formed of any photoresist (PR) material, including one or more of propylene glycol monomethyl ether (PGME), 1-methoxy-2-propyl acetate, propylene glycol methyl ether acetate, naphthoquinone diazide, and propylene glycol monomethyl ether acetate.
[0067] The first photoresist layer formed in step S400 is defined as a first photoresist sub-layer 710. The surface of the first photoresist sub-layer 710 is flush with the side away from the substrate 100. The structure after formation is as follows: Figure 3 shown.
[0068] S500, remove the first photoresist layer in the first pixel opening 610 and form a first sub-pixel 110 in the first pixel opening 610, wherein the first sub-pixel 110 includes a first light emitting layer 111, a first cathode sub-layer 112, and a first protective sub-layer 113 formed in sequence on the anode layer 200. The structure after formation is as follows Figure 4 shown.
[0069] In specific operation, the method includes:
[0070] A first photoresist sublayer 710 is formed on the second protective layer 500, and the first photoresist sublayer 710 is used to remove the first photoresist sublayer 710 within the first pixel opening 610 to form the first sub-pixel 110; the first photoresist sublayer 710 is also used to simultaneously etch and retain the first photoresist sublayer 710 on the remaining area except for the corresponding first pixel opening 610 during the process of forming the first sub-pixel 110.
[0071] In the embodiments of the present application, the photoresist layer can be removed by using processes such as exposure and development based on the distribution of the areas to be etched, and can be formed on an entire surface of the photoresist layer. For example, a mask having a pattern corresponding to the distribution of the areas to be etched can be used. In the embodiments of the present application, the method for removing the photoresist layer in a portion of the area can adopt various methods in the prior art, and the present application does not limit this. For example, the photoresist layer in a portion of the area can be removed by exposing and developing a positive photoresist, exposing and developing a negative photoresist, or other methods, which may all be applicable to the etching method of the present embodiment.
[0072] For example, the photoresist material can be a positive photoresist. After exposure and development through the mask, the photoresist layer in the exposed areas can be removed during the development process, while the photoresist layer in the unexposed areas is retained during the development process. Alternatively, a negative photoresist layer can be used, where the photoresist layer in the exposed areas is retained during the development process, while the photoresist layer in the unexposed areas is removed during the development process. The present invention is not limited to this. However, the following embodiments are all described using a positive photoresist as an example.
[0073] In an embodiment of the present application, each photoresist sublayer includes a removal area (for example, the first pixel opening 610 area) and a retained area (for example, the remaining area except for the area corresponding to the first pixel opening 610). The retained area is used to realize a masking effect to facilitate the subsequent removal of materials such as the first light-emitting layer 111 on the second sub-pixel 120 and the third sub-pixel 130 areas, so as to form the first sub-pixel 110 only within the first pixel opening 610.
[0074] In this embodiment, the first photoresist sub-layer 710 is further used to remove the first photoresist sub-layer 710 on the remaining area outside the first pixel opening 610 after forming the first sub-pixel 110 to expose the second protection layer 500 .
[0075] It should be noted that the embodiments of the present application do not limit the shapes and forms of the first light-emitting layer 111, the first cathode sublayer 112, and the first protective layer 300. Processes such as magnetron sputtering, evaporation, and plasma-enhanced chemical vapor deposition (PECVD) can be employed. For example, in forming the first subpixel 110, the first light-emitting layer 111 can be formed on the entire display panel by evaporation, the first cathode sublayer 112 can be formed on the entire display panel by PVD, and the first protective sublayer 113 can be formed on the entire display panel by PECVD.
[0076] During this process, the areas corresponding to the second pixel opening 620 and the third pixel opening 630 are reserved areas of the first photoresist sub-layer 710. The first light-emitting layer 111, the first cathode sub-layer 112, and the first protective sub-layer 113 are formed on top of the first photoresist sub-layer 710 in these reserved areas. In the embodiment of the present application, the excess film layers within the second pixel opening 620 and the third pixel opening 630 can be removed using various etching processes.
[0077] S600, remove the first photoresist layer in the second pixel opening 620 and form a second sub-pixel 120 in the second pixel opening 620, wherein the second sub-pixel 120 includes a second light-emitting layer 121, a second cathode sub-layer 122, and a second protective sub-layer 123 sequentially formed on the anode layer 200.
[0078] In specific operation, the method includes:
[0079] like Figure 5 As shown, a second photoresist sublayer 720 is formed on the second protective layer 500, and the second photoresist sublayer 720 is used to remove the second photoresist sublayer 720 within the second pixel opening 620 to form the second sub-pixel 120; the second photoresist sublayer 720 is also used to simultaneously etch and retain the second photoresist sublayer 720 on the remaining area except for the corresponding second pixel opening 620 during the process of forming the second sub-pixel 120.
[0080] S700, remove the first photoresist layer in the third pixel opening 630 and form a third sub-pixel 130 in the third pixel opening 630, wherein the third sub-pixel 130 includes a third light-emitting layer 131, a third cathode sub-layer 132, and a third protective sub-layer 133 sequentially formed on the anode layer 200.
[0081] In specific operation, the method includes:
[0082] like Figure 6As shown, a third photoresist sublayer 730 is formed on the second protective layer 500, and the third photoresist sublayer 730 is used to remove the third photoresist sublayer 730 within the third pixel opening 630 to form the third sub-pixel 130; the third photoresist sublayer 730 is also used to simultaneously etch and retain the third photoresist sublayer 730 on the remaining area except for the corresponding third pixel opening 630 during the process of forming the third sub-pixel 130.
[0083] It should be noted that, in the embodiment of the present application, the first light-emitting layer 111 is used to form the first sub-pixel 110 , the second light-emitting layer 121 is used to form the second sub-pixel 120 , and the third light-emitting layer 131 is used to form the third sub-pixel 130 .
[0084] The materials of the first cathode sublayer 112, the second cathode sublayer 122, and the third cathode sublayer 132 can be the same or different. The materials of the first protective sublayer 113, the second protective sublayer 123, and the third protective sublayer 133 can be the same or different from the materials of the first protective layer 300 and the second protective layer 500, which is not limited in the embodiments of the present application.
[0085] In steps S500, S600, and S700, the specific process can be performed as follows: Based on the structure formed in the previous step, a layer of photoresist is first applied to the second protective layer 500 by, for example, spin coating. The photoresist used can be, for example, a positive photoresist. Next, ultraviolet light can be used to illuminate the photoresist in all areas to be etched through the mask to fully expose the photoresist. The mask is then placed in a developer to completely remove the photoresist in the areas to be etched through development, and the remaining photoresist forms a photoresist sub-layer.
[0086] It should be further clarified that, in the embodiment of the present application, the second photoresist sublayer 720 in step S600 is formed after the first photoresist sublayer 710 is completely stripped in step S500, and the third photoresist sublayer 730 in step S700 is formed after the second photoresist sublayer 720 is completely stripped in step S600. The second protective layer 500, the first protective sublayer 113, the second protective sublayer 123, etc. in the embodiment of the present application can protect the lower film layer from being damaged by the developer and the etching material. The structure after formation is as follows Figure 7 shown.
[0087] Optionally, the heights of the first light-emitting layer 111, the second light-emitting layer 121, and the third light-emitting layer 131 are less than or equal to the height of the first protective layer 300; and the surfaces of the first protective sublayer 113, the second protective sublayer 123, and the third protective sublayer 133 on the side away from the base substrate 100 are flush with the surface of the second protective layer 500. These settings can be made as needed in specific applications.
[0088] In another embodiment of the present application, a method for forming a plurality of pixel openings 600 includes:
[0089] S310, forming a second photoresist layer on the anode layer 200, and patterning to form a shape definition layer 800, wherein the cross-sectional shape of the shape definition layer 800 in a direction perpendicular to the base substrate 100 is the trapezoidal shape; the structure after formation is as follows Figure 7 shown.
[0090] S320, forming the first protective layer 300, the cathode layer 400 and the second protective layer 500 on the anode layer 200 in sequence, wherein the first protective layer 300, the cathode layer 400 and the second protective layer 500 all cover part of the hypotenuse of the trapezoid; the structure after formation is as follows Figure 8 shown.
[0091] S330 , etching away the shape definition layer 800 to form the pixel opening 600 .
[0092] The method for forming the pixel opening 600 provided in this embodiment can further reduce the use of mask plates and save costs. In this embodiment, the second photoresist layer is patterned to form a shape definition layer 800 corresponding to the shape and position of the pixel opening 600. Then, the first protective layer 300, the cathode layer 400, and the second protective layer 500 are formed around the shape definition layer 800. After removing the photoresist from the shape definition layer 800, the pixel opening 600 is directly formed.
[0093] Alternatively, as Figure 10 As shown in , a first wiring layer 410 is provided on the base substrate 100 , a first via hole 420 is provided on the first protection layer 300 , and the cathode layer 400 is in contact with the first wiring layer 410 through the first via hole 420 .
[0094] Alternatively, as Figure 11 As shown in , a second wiring layer 430 is provided on the side of the second protective layer 500 away from the base substrate 100 , and a second via hole 440 is provided on the second protective layer 500 , and the cathode layer 400 is in contact with the second wiring layer 430 through the second via hole 440 .
[0095] In the embodiment of the present application, various signal routings can be arranged on the first routing layer 410 and the second routing layer 430. For example, a power signal VSS can be arranged. By overlapping the cathode layer 400 with VSS, voltage drop can be effectively reduced, thereby reducing the impact of IR drop. The positions of the first routing layer 410 and the second routing layer 430 can be set as needed in different embodiments, and this application does not limit this.
[0096] The present application also provides a display panel, which is prepared using any of the above-mentioned methods for preparing a display panel.
[0097] Based on the same inventive concept, the present application provides a display device including the display panel described above. The display device in the embodiments of the present invention may be a television, or may be a display device with a display function, such as a PC, a smartphone, a tablet computer, an e-book reader, an MP3 (Moving Picture Experts Group Audio Layer III) player, an MP4 (Moving Picture Experts Group Audio Layer IV) player, or a portable computer.
[0098] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.
[0099] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.
[0100] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present invention. The terms used herein are only for describing specific implementation purposes and are not intended to limit the present invention. Terms such as "setting" appearing in this article can mean that one component is directly attached to another component, or that one component is attached to another component through an intermediate component. Features described in this article in one embodiment can be applied to another embodiment alone or in combination with other features, unless the feature is not applicable in the other embodiment or otherwise specified.
[0101] The present invention has been described through the above embodiments, but it should be understood that the above embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. It will be understood by those skilled in the art that more variations and modifications can be made based on the teachings of the present invention, and these variations and modifications all fall within the scope of the second protection claimed by the present invention.
Claims
1. A method for preparing a display panel, characterized in that: The method comprises: providing a base substrate, and forming an anode layer on the base substrate; forming a first protective layer, a cathode layer and a second protective layer in sequence on the anode layer; forming a plurality of pixel openings, the pixel openings penetrating the first protective layer, the cathode layer, and the second protective layer and exposing a surface of the anode layer, the pixel openings including a first pixel opening for forming a first sub-pixel, a second pixel opening for forming a second sub-pixel, and a third pixel opening for forming a third sub-pixel; forming a first photoresist layer on the second protective layer, wherein the first photoresist at least fills the pixel opening; removing the first photoresist layer in the first pixel opening and forming a first sub-pixel in the first pixel opening, wherein the first sub-pixel includes a first light-emitting layer, a first cathode sub-layer, and a first protective sub-layer sequentially formed on the anode layer; removing the first photoresist layer in the second pixel opening and forming a second sub-pixel in the second pixel opening, wherein the second sub-pixel includes a second light-emitting layer, a second cathode sub-layer, and a second protective sub-layer sequentially formed on the anode layer; The first photoresist layer in the third pixel opening is removed and a third sub-pixel is formed in the third pixel opening. The third sub-pixel includes a third light-emitting layer, a third cathode sub-layer, and a third protective sub-layer sequentially formed on the anode layer.
2. The method for manufacturing a display panel according to claim 1, wherein: Forming a first photoresist layer on the second protective layer, wherein the first photoresist at least fills the pixel opening, the method comprising: forming a first photoresist sublayer on the second protective layer, wherein the first photoresist sublayer is used to remove the first photoresist sublayer within the first pixel opening to form the first sub-pixel; and the first photoresist sublayer is further used to simultaneously etch and retain the first photoresist sublayer in the remaining area except for the first pixel opening during the process of forming the first sub-pixel; forming a second photoresist sublayer on the second protective layer, wherein the second photoresist sublayer is used to remove the second photoresist sublayer within the second pixel opening to form the second sub-pixel; and the second photoresist sublayer is further used to simultaneously etch the second photoresist sublayer on the remaining area except for the second pixel opening during the formation of the second sub-pixel; A third photoresist sublayer is formed on the second protective layer, and the third photoresist sublayer is used to remove the third photoresist sublayer within the third pixel opening to form the third sub-pixel; the third photoresist sublayer is also used to simultaneously etch and retain the third photoresist sublayer on the remaining area except for the corresponding third pixel opening during the process of forming the third sub-pixel.
3. The method for manufacturing a display panel according to claim 1, wherein: The heights of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer are less than or equal to the height of the first protective layer; The surfaces of the first protective sublayer, the second protective sublayer, and the third protective sublayer on a side away from the base substrate are flush with the surface of the second protective layer.
4. The method for manufacturing a display panel according to claim 1, wherein: The cross-sectional shape of the pixel opening in a direction perpendicular to the substrate is a trapezoid, the trapezoid comprising a first side length close to the substrate and a second side length away from the substrate, the first side length being shorter than the second side length; The trapezoid includes a hypotenuse connecting the first side length and the second side length, and the angle between the hypotenuse and the first side length is 60° to 89°.
5. The method for manufacturing a display panel according to claim 4, wherein: The method of forming a plurality of pixel openings includes: forming a second photoresist layer on the anode layer and patterning the layer to form a shape-defining layer, wherein the cross-sectional shape of the shape-defining layer in a direction perpendicular to the substrate is the trapezoid; forming the first protective layer, the cathode layer, and the second protective layer in sequence on the anode layer, wherein the first protective layer, the cathode layer, and the second protective layer all conformally cover a portion of the hypotenuse of the trapezoid; The pixel opening is formed after the shape definition layer is removed by etching.
6. The method for manufacturing a display panel according to claim 1, wherein: The first protective layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride, and the second protective layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.
7. The method for manufacturing a display panel according to claim 1, wherein: A first wiring layer is provided on the base substrate, a first via hole is provided on the first protection layer, and the cathode layer contacts the first wiring layer through the first via hole.
8. The method for manufacturing a display panel according to claim 1, wherein: A second wiring layer is provided on a side of the second protection layer away from the base substrate. A second via hole is provided on the second protection layer. The cathode layer contacts the second wiring layer through the second via hole.
9. A display panel, characterized in that: The display panel is manufactured by the method for manufacturing the display panel according to any one of claims 1 to 8.
10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.