Display device

Abstract

Embodiments of the present disclosure relate to a display device with enhanced VACS, and may provide a display device including a sub-pixel, the sub-pixel includes a first region overlapping with the organic light emitting diode and a second region not overlapping with the organic light emitting diode and disposed to surround an outer periphery of the first region, a main emission region disposed in the first region, and a reflective light region provided to surround an outer periphery of the main emission region in the second region and having one side portion protruding outward to form a protruding region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2024-0030057, filed on February 29, 2024, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments of the present disclosure relate to a display device having enhanced visual angle color shift (VACS) characteristics. Background Art

[0004] In recent years, in the information age, the field of displays for visually representing electrical information signals has developed rapidly, and accordingly various display devices having excellent performance, such as more compact, lightweight, and low power consumption displays, have been developed.

[0005] Specific examples of the display device include a liquid crystal display (LCD), a field emission display (FED), and an organic light emitting display (OLED).

[0006] Meanwhile, a display device can display images by arranging red, green, and blue sub-pixels in a matrix. Because these sub-pixels each output different wavelengths depending on the color, the brightness decreases differently depending on the viewing angle. Consequently, the visual angle color shift (VACS) characteristics may deteriorate from the front to the side. Summary of the Invention

[0007] Embodiments of the present disclosure may provide a display device having enhanced visual color shift (VACS) characteristics by controlling the distance between the opening of the bank layer and the reflective electrode according to the wavelength of each sub-pixel.

[0008] Embodiments of the present disclosure may provide a display device capable of enhancing VACS without reducing an aperture ratio.

[0009] The embodiments of the present disclosure may provide a display device having enhanced brightness because light propagating from a light emitting layer to a side surface is reflected to the outside by a reflective electrode.

[0010] Embodiments of the present disclosure may provide a display device capable of reducing power consumption because light extraction efficiency is improved by a reflective electrode.

[0011] An embodiment of the present disclosure may provide a display device comprising a sub-pixel, the sub-pixel comprising a first region overlapping with an organic light-emitting diode and a second region not overlapping with the organic light-emitting diode and arranged to surround the periphery of the first region, a main emission region arranged in the first region, and a reflective light region arranged to surround the periphery of the main emission region in the second region and having a side portion protruding outward to form a protruding region.

[0012] According to an embodiment of the present disclosure, a display device having enhanced visual angle angular shift (VACS) characteristics by controlling the distance between the opening of the bank layer and the reflective electrode according to the wavelength of each sub-pixel may be provided.

[0013] According to an embodiment of the present disclosure, a display device capable of enhancing VACS without reducing an aperture ratio may be provided.

[0014] According to an embodiment of the present disclosure, a display device having enhanced brightness because light propagating from a light emitting layer to a side surface is reflected to the outside by a reflective electrode can be provided.

[0015] According to an embodiment of the present disclosure, a display device capable of reducing power consumption because light extraction efficiency is improved by a reflective electrode can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a diagram illustrating a system configuration of a display device according to an embodiment of the present disclosure;

[0018] Figure 2 It is intercepted along A-A' Figure 1 A plan view of a display device;

[0019] Figure 3 It is shown in Figure 2 A diagram of a light path generated in area "A" of a display device;

[0020] Figure 4 is a cross-sectional view illustrating a display device according to another embodiment of the present disclosure;

[0021] Figure 5 It is schematically shown Figure 2 and Figure 4 A plan view of adjacent sub-pixels in ;

[0022] Figure 6 It is shown from Figure 5A diagram showing a state in which a sub-pixel emits light;

[0023] Figure 7 is a plan view showing an arrangement of sub-pixels according to an embodiment of the present disclosure; and

[0024] Figure 8 is a plan view illustrating a data line overlapping a sub-pixel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings in which specific examples or embodiments that can be implemented are shown by way of illustration, and in the accompanying drawings, the same reference numerals and symbols may be used to represent the same or similar components even when the same or similar components are shown in different drawings. In addition, in the following description of examples or embodiments of the present disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter in some embodiments of the present disclosure unclear. Terms such as "including", "having", "containing", "consisting of", "consisting of", and "formed of" used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0026] Terms such as "first," "second," "A," "B," "(A)," or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, or quantity of the elements, but is only used to distinguish the corresponding element from other elements.

[0027] When referring to a first element being “connected or coupled”, “contacting or overlapping”, etc., with a second element, it should be understood that not only the first element may be “directly connected or coupled” or “directly contacting or overlapping” with the second element, but also a third element may be “interposed” between the first and second elements, or the first and second elements may be “connected or coupled”, “contacting or overlapping”, etc., with each other via a fourth element. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled”, “contacting or overlapping”, etc., with each other.

[0028] When time relative terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or method of manufacture, these terms may be used to describe non-sequential or non-sequential processes or operations unless used with the terms “directly” or “immediately.”

[0029] In addition, when any dimension, relative size, etc. is mentioned, even if no specific description is given, it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes tolerances or error ranges that may also be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all meanings of the term "can".

[0030] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0031] Figure 1 is a diagram illustrating a system configuration of a display device according to an embodiment of the present disclosure.

[0032] refer to Figure 1 The display driving system of the display device 100 according to an embodiment of the present disclosure may include a display panel 1 and a display driving circuit for driving the display panel 1 .

[0033] The display panel 1 may include a display area AA displaying an image and a non-display area NA not displaying an image. The display panel 1 may include a plurality of sub-pixels SP disposed on a base substrate 110 for image display.

[0034] The display panel 1 may include a plurality of signal lines disposed on the base substrate 110. For example, the plurality of signal lines may include data lines DL, gate lines GL, driving voltage lines DVL, and the like.

[0035] Each of the plurality of data lines DL is disposed while extending in a first direction (eg, a column direction or a row direction), and each of the plurality of gate lines GL is disposed while extending in a direction crossing the first direction.

[0036] The display driving circuit may include a data driving circuit 11 and a gate driving circuit 12 , and may further include a controller 13 for controlling the data driving circuit 11 and the gate driving circuit 12 .

[0037] The data driving circuit 11 may output data signals (also referred to as data voltages) corresponding to image signals to a plurality of data lines DL. The gate driving circuit 12 may generate gate signals and output the gate signals to a plurality of gate lines GL. The controller 13 may convert input image data input from an external host 14 to meet the data signal format used in the data driving circuit 11 and provide the converted image data to the data driving circuit 11.

[0038] The data driving circuit 11 may include one or more source driver integrated circuits. For example, each source driver integrated circuit may be connected to the display panel 1 by a tape automated bonding (TAB) method, or connected to a bonding pad of the display panel 1 by a chip on glass (COG) or chip on panel (COP) method, or may be implemented and connected to the display panel 1 by a chip on film (COF) method.

[0039] The gate driving circuit 12 can be connected to the display panel 1 through a tape automated bonding (TAB) method, connected to a bonding pad of the display panel 1 through a COG or COP method, connected to the display panel 1 through a COF method, or can be formed in the non-display area NA of the display panel 1 through a gate in panel (GIP) method.

[0040] refer to Figure 1 In the display device 100 according to an embodiment of the present disclosure, each sub-pixel SP may include a light emitting element ED and a pixel driving circuit SPC for driving the light emitting element ED. The pixel driving circuit SPC may include a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0041] The driving transistor DRT may control current flowing to the light emitting element ED to drive the light emitting element ED. The scanning transistor SCT may transmit the data voltage Vdata to the second node N2 which is the gate node of the driving transistor DRT. The storage capacitor Cst may be configured to maintain a voltage for a predetermined period of time.

[0042] The light-emitting element ED may include a first electrode 150, a second electrode 180, and a light-emitting layer 170 located between the first electrode 150 and the second electrode 180 to form a light-emitting diode. The first electrode 150 may be a pixel electrode involved in forming the light-emitting element ED of each sub-pixel SP and may be electrically connected to the first node N1 of the drive transistor DRT. The second electrode 180 may be a common electrode involved in forming the light-emitting elements ED of all sub-pixels SP and may be applied with a ground voltage EVSS.

[0043] For example, the light emitting element ED may be an organic light emitting diode OLED, an inorganic light emitting diode (LED), or a quantum dot light emitting element which is a self-luminous semiconductor crystal.

[0044] The driving transistor DRT is a transistor for driving the light-emitting element ED and may include a first node N1, a second node N2, and a third node N3. The first node N1 may be a source node or a drain node and may be electrically connected to the first electrode 150 of the light-emitting element ED. The second node N2 is a gate node and may be electrically connected to the source node or the drain node of the scan transistor SCT. The third node N3 may be a drain node or a source node and may be electrically connected to a driving voltage line DVL that provides a driving voltage EVDD. For ease of description, in the example described below, the first node N1 may be a source node, and the third node N3 may be a drain node.

[0045] The scan transistor SCT may switch the connection between the data line DL and the second node N2 of the drive transistor DRT. In response to a scan signal SCAN supplied from a scan line SCL, which is a type of gate line GL, the scan transistor SCT may control the connection between the second node N2 of the drive transistor DRT and a corresponding data line DL among the plurality of data lines DL.

[0046] The storage capacitor Cst may be configured between the first node N1 and the second node N2 of the driving transistor DRT.

[0047] Figure 1 The structure of the sub-pixel SP shown is merely an example of an illustration and may further include one or more transistors or one or more storage capacitors. The plurality of sub-pixels SP may have the same structure, or some of the plurality of sub-pixels SP may have different structures. Each of the drive transistor DRT and the scan transistor SCT may be an n-type transistor or a p-type transistor.

[0048] Figure 2 It is intercepted along A-A' Figure 1 A plan view of a display device.

[0049] refer to Figure 2 The display device 100 may include a base substrate 110 , a first planarization layer 120 , a second planarization layer 130 , a third planarization layer 140 , a first electrode 150 , a bank layer 160 , a light emitting layer 170 and a second electrode 180 .

[0050] The base substrate 110 is used to support various components of the display device 100 and may include a display area AA for displaying images and a non-display area NA for not displaying images. The display area AA may include a first area A1 and a second area A2. The first area A1 may be a main emission area MEA in which an organic light-emitting diode formed by the first electrode 150, the light-emitting layer 170, and the second electrode 180 is disposed, and the second area A2 may be an area that does not overlap with the organic light-emitting diode. In some embodiments, the light-emitting layer 170 may extend beyond the first area A1. In this case, the functional organic light-emitting diode may still be confined to the first area A1 where the first electrode 150, the light-emitting layer 170, and the second electrode 180 overlap and contact each other. Specifically, the second area A2 may be a region where the reflective light area REA and the non-emitting area NEA coexist. In the non-emitting area NEA, light in a waveguide mode propagating to the side of the light-emitting layer 170 is totally reflected by the first electrode 150 and emitted to the outside. The second area A2 may include a boundary between adjacent sub-pixels SP and / or the non-display area NA.

[0051] The base substrate 110 may be formed of two or more layers. For example, the base substrate 110 may include a first base substrate 111 , a second base substrate 112 , and an insulating layer 113 disposed between the first base substrate 111 and the second base substrate 112 .

[0052] The first base substrate 111 and the second base substrate 112 may be formed of polyimide (PI). Polyimide is a polymer having a relatively low crystallinity or a mostly amorphous structure and can be easily synthesized to prepare a thin film film, and has advantages such as transparency, heat resistance, and good mechanical properties. However, since polyimide has poor moisture permeability resistance, an insulating layer 113 formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) may be provided between the first base substrate 111 and the second base substrate 112 to ensure the moisture permeability resistance of the base substrate 110.

[0053] A plurality of buffer layers may be provided for blocking moisture and oxygen from flowing into the second base substrate 112. For example, the buffer layer may include a multi-buffer layer 114 and an active buffer layer 115.

[0054] The multi-buffer layer 114 serves to block moisture and oxygen introduced into the inside, and may be formed of an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0055] The first light shielding layer 10 may be disposed between the base substrate 110 and the multi-buffer layer 114 to prevent light from entering the driving transistor DRT from the outside. That is, the multi-buffer layer 114 may be formed to cover the first light shielding layer 10 on the base substrate 110 .

[0056] The active buffer layer 115 may be disposed on the multi-buffer layer 114. The active buffer layer 115 may be formed of an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0057] The driving transistor DRT may be disposed between the base substrate 110 and the first planarization layer 120. The driving transistor DRT serves to drive the light emitting element ED by controlling current flowing to the light emitting element ED, and may be electrically connected to the first electrode 150.

[0058] The driving transistor DRT may be disposed on the active buffer layer 115 and may include a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. A first light shielding layer 10 for protecting the first active layer ACT1 may be disposed under the first active layer ACT1.

[0059] A plurality of inorganic layers for forming each component of the driving transistor DRT may be formed on the active buffer layer 115. For example, the inorganic layers may include a gate insulating layer 116 and a plurality of interlayer insulating layers 117.

[0060] A gate insulating layer 116 may be disposed on the active buffer layer 115 to cover the first active layer ACT1 . A first gate electrode GE1 may be disposed on the gate insulating layer 116 .

[0061] A plurality of interlayer insulating layers 117 may be provided and disposed to cover the first gate electrode GE1 on the gate insulating layer 116. A first source electrode SE1 and a first drain electrode DE1 may be disposed on the interlayer insulating layer 117. In this case, contact holes through which the first source electrode SE1 and the first drain electrode DE1 pass may be formed in the gate insulating layer 116 and the interlayer insulating layer 117 so that the first source electrode SE1 and the first drain electrode DE1 can be connected to the first active layer ACT1 forming a channel when the drive transistor DRT is driven.

[0062] The interlayer insulating layer 117 may include first, second, third, and fourth interlayer insulating layers 117a, 117b, 117c, and 117d. A scan transistor SCT including a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2 may be disposed on the interlayer insulating layer 117.

[0063] For example, the second active layer ACT2 may be disposed on the second interlayer insulating layer 117b, and the third interlayer insulating layer 117c may be disposed to cover the second active layer ACT2. The second gate electrode GE2 may be disposed on the third interlayer insulating layer 117c, and the fourth interlayer insulating layer 117d may be disposed to cover the second gate electrode GE2 on the third interlayer insulating layer 117c. The first source electrode SE1 and the first drain electrode DE1 may be disposed on the fourth interlayer insulating layer 117d. In this case, contact holes through which the second source electrode SE2 and the second drain electrode DE2 pass may be formed in the third interlayer insulating layer 117c and the fourth interlayer insulating layer 117d, so that the second source electrode SE2 and the second drain electrode DE2 can be connected to the second active layer ACT2.

[0064] A second light shielding layer 20 for preventing light from being incident on the scanning transistor SCT may be provided below the scanning transistor SCT. For example, the second light shielding layer 20 may be provided between the first interlayer insulating layer 117a and the second interlayer insulating layer 117b.

[0065] The first planarization layer 120 may be provided on the base substrate 110. For example, the first planarization layer 120 may be formed of an organic material such as photo acrylic (PAC), and may be provided on the interlayer insulating layer 117 to cover the first source electrode SE1 and the first drain electrode DE1. Therefore, the first planarization layer 120 may reduce the step caused by the components of the first source electrode SE1 and the first drain electrode DE1.

[0066] The first planarization layer 120 may include a first contact hole 120a that overlaps with the hole 140a of the third planarization layer 140 and the driving transistor DRT. As described above, when the first contact hole 120a is formed in the first planarization layer 120, the driving transistor DRT and the first electrode 150 may be electrically connected via the connection electrode CE provided on the first planarization layer 120. For example, a lower portion of the connection electrode CE may be inserted into the first contact hole 120a so that the connection electrode CE may contact the driving transistor DRT.

[0067] The second planarization layer 130 may be provided to cover the connection electrode CE on the first planarization layer 120. The second planarization layer 130 may include a second contact hole 130a overlapping the first contact hole 120a.

[0068] As described above, when the second contact hole 130 a is formed in the second planarization layer 130 , a portion of the first electrode 150 may be inserted into the second contact hole 130 a so that the first electrode 150 may contact the connection electrode CE.

[0069] The third planarization layer 140 may be disposed on the second planarization layer 130 and may include a plurality of holes 140a that expose a portion of the second planarization layer 130. For example, the plurality of holes 140a formed in the third planarization layer 140 may be formed in the first area A1 and a portion of the second area A2 disposed around the periphery of the first area A1. The holes 140a may be formed to overlap with the first contact hole 120a and the second contact hole 130a. In other words, the holes 140a, the first contact hole 120a, and the second contact hole 130a may be disposed to overlap in the Z-axis direction in the drawing.

[0070] The first electrode 150 may be arranged to overlap with the hole 140a of the third planarization layer 140. For example, a plurality of first electrodes 150 may be provided, and each first electrode 150 may be independently arranged in a corresponding hole 140a. The first electrode 150 in this embodiment is an anode and may be a reflective electrode. To this end, the first electrode 150 may be formed of an opaque electrode formed of a metal material having good reflectivity such as aluminum (Al), copper (Cu), nickel (Ni), etc. In addition, the second electrode 180 may be formed in a structure in which a transparent electrode (such as indium tin oxide (ITO) and indium zinc oxide (IZO)) and an opaque electrode are stacked.

[0071] The bank layer 160 is used to separate the first area A1 and may have a plurality of openings 160a to expose a portion of the first electrode 150. For example, the bank layer 160 may be provided in the second area A2 and may be provided to cover a portion of the outer periphery of the first electrode 150 and the third planarization layer 140.

[0072] The bank layer 160 may have an opening 160a formed in a portion corresponding to the first area A1. For example, the opening 160a of the bank layer 160 may be arranged to overlap with the hole 140a without overlapping with the first contact hole 120a and the second contact hole 130a. With this structure, a portion of the first electrode 150 may be exposed to the outside through the opening 160a of the bank layer 160.

[0073] A plurality of light-emitting layers 170 may be provided and disposed in the openings 160a of the bank layer 160, respectively. That is, the light-emitting layers 170 may be independently disposed in the first region A1. In some embodiments, the light-emitting layers 170 may extend beyond the first region A1, for example, onto the side portions of the bank layer 160. The light-emitting layer 170 in this embodiment is an organic compound layer and may be an organic light-emitting layer including a hole injection layer (HIL), a hole transport layer (HTL), an active layer (a light-emitting material layer (EML)), an electron transport layer (ETL), and an electron injection layer (EIL).

[0074] The second electrode 180 may be disposed on the bank layer 160 and the light emitting layer 170. For example, the second electrode 180 is a cathode and may be disposed in the first region A1 and the second region A2. As a result, an organic light emitting diode may be formed in the first region A1 by the first electrode 150, the light emitting layer 170, and the second electrode 180.

[0075] The second electrode 180 may be formed of an opaque electrode such as aluminum (Al), copper (Cu), nickel (Ni) or a transparent electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). In addition, the second electrode 180 may be formed in a structure in which an opaque electrode and a transparent electrode are stacked.

[0076] Figure 3 It is shown in Figure 2 A diagram of the light paths generated in area 'A' of the display device.

[0077] refer to Figure 3 Light generated by the light-emitting layer 170 can be totally reflected at the interface with the underlying components and propagate to the side surfaces. This is known as a waveguide mode, which reduces light extraction efficiency. To address this issue, the waveguide mode light propagating to the side surfaces can be reflected to the outside by the first electrode 150. In other words, the first electrode 150 can function as a reflective electrode.

[0078] The first electrode 150 may include a first body portion 151 , a second body portion 152 , and a third body portion 153 .

[0079] The first body portion 151 may be disposed in the first area A1. For example, the first body portion 151 may be disposed on the second planarization layer 130 exposed to the outside of the hole 140a of the third planarization layer 140.

[0080] The second body portion 152 may extend from an end portion of the first body portion 151, and a portion thereof may be disposed on the second planarization layer 130, and the remaining portion thereof may be disposed on a side portion of the third planarization layer 140. As described above, when a portion of the second body portion 152 is formed on a side portion of the third planarization layer 140, light propagating from the interface between the light emitting layer 170 and the first body portion 151 to the side surface may be re-reflected by the second body portion 152 and emitted to the outside.

[0081] A portion of the second body portion 152 may be inserted into the second contact hole 130 a formed in the second planarization layer 130 to contact the connection electrode CE and thus may be electrically connected to the driving transistor DRT. In this case, the portion of the second body portion 152 inserted into the second contact hole 130 a may be recessed, thereby forming a step at an upper portion of the second body portion 152.

[0082] The second body portion 152 may be disposed to surround the outer circumference of the first body portion 151 in the second area A2, and may form a protrusion 150a protruding from one side of the first body portion 151 to overlap the second contact hole 130a. For example, the protrusion 150a may be formed by the second body portion 152 to overlap the second contact hole 130a in the second area A2.

[0083] The third body portion 153 may be disposed around the circumference of the second body portion 152 in the second area A2. For example, the third body portion 153 may extend from an end portion of the second body portion 152 and may be disposed on an upper portion of the third planarization layer 140.

[0084] As described above, since light propagating from the light emitting layer 170 to the side can be totally reflected by the second body portion 152 of the first electrode 150 serving as a reflective electrode and extracted to the outside, a display device 100 that can be used at low power by enhancing the light extraction efficiency of the display device 100 can be provided.

[0085] Meanwhile, when the first electrode 150 is formed to include the first main portion 151, the second main portion 152, and the third main portion 153, a step may be formed in the first electrode 150. Due to this step structure, the bank layer 160 disposed on the first electrode 150 and the third planarization layer 140 may have different heights at each location. For example, the height h1 of the bank layer 160 disposed between the second contact hole 130a and the first area A1 may be formed to be greater than the height h3 of the bank layer 160 overlapping the third planarization layer 140 and less than the height h2 of the bank layer 160 overlapping the second contact hole 130a.

[0086] The display device 100 according to this embodiment can output white light through red, green, and blue sub-pixels SP. Because the red, green, and blue sub-pixels SP each have a different wavelength, the brightness decreases differently from the front to the side, thereby deteriorating the visual angle color shift (VACS) characteristic. For example, as the brightness of blue light decreases more from the front to the side, the VACS characteristic may deteriorate.

[0087] To prevent degradation of the VACS characteristics, different spacing distances need to be provided in a horizontal direction parallel to the substrate between the portion of the second main portion 152 of the first electrode 150 formed on the side portion of the third planarization layer 140 and the opening 160a of the bank layer 160. Specifically, by providing different horizontal spacing distances between the portion of the second main portion 152 and the opening 160a where the light-emitting layer 170 is provided, depending on the wavelength of each sub-pixel SP, the reflection angle of light reflected from the second main portion 152 can be controlled, thereby enhancing the VACS characteristics.

[0088] Figure 4 is a cross-sectional view illustrating a display device according to another embodiment of the present disclosure.

[0089] refer to Figure 4 The display device 200 can control the horizontal separation distance between the portion of the second body portion 152 formed on the side portion of the third planarization layer 140 and the opening 160a of the bank layer 160 by placing a control member 141 formed of the same material as the third planarization layer 140 between the first body portion 151 of the first electrode 150 and the second contact hole 130a. For example, the horizontal separation distance can be controlled by shifting the placement of the control member 141 to the outside or inside according to the wavelength of each sub-pixel SP.

[0090] Figure 5 It is schematically shown Figure 2 and Figure 4 Planar diagram of adjacent sub-pixels in .

[0091] refer to Figure 5 , the adjacent first electrode 150 should minimize the process margin M. In this case, if the control member 141 moves to the region where the second contact hole 130a is placed, it may become difficult to minimize the process margin M. Therefore, Figure 4 The display device 200 ensures a horizontal spacing control distance between the portion of the second main body portion 152 formed on the side portion of the third planarization layer 140 and the opening 160a of the embankment layer 160 by reducing the width of the opening 160a, which may reduce the aperture ratio of the display device 200, thereby deteriorating the light extraction efficiency.

[0092] To prevent a reduction in aperture ratio, in the display device 100 according to this embodiment, the second body portion 152 disposed on the second planarizing layer 130 may be disposed so as not to overlap with the third planarizing layer 140. Specifically, in order to control the horizontal spacing distance between the portion of the second body portion 152 and the opening 160a formed in the bank layer 160 without changing the width of the opening 160a, the control member 141, which is part of the third planarizing layer 140, is not disposed between the second contact hole 130a and the first body portion 151. By doing so, the horizontal spacing distance between the portion of the second body portion 152 formed on the side portion of the third planarizing layer and the opening 160a of the bank layer 160 can be further increased / decreased by the width of the control member 141, and the horizontal spacing distance can be controlled without reducing the aperture ratio.

[0093] For example, the horizontal distance between the opening 160a and the first electrode 150 can be controlled by adjusting the size of the hole 140a formed in the third planarization layer 140. That is, when the size of the hole 140a of the third planarization layer 140 is formed to be large, the horizontal spacing distance between the opening 160a and the portion of the second body portion 152 formed on the side portion of the third planarization layer 140 may also increase, and when the size of the hole 140a is formed to be small, the horizontal spacing distance may also decrease.

[0094] refer to Figure 5 , the first electrode 150 of the display device 100 may include a first electrode region S1 overlapping with the second contact hole 130a and a second electrode region S2 extending from one side of the first electrode region S1 to overlap with the opening 160a. In addition, the hole 140a formed in the third planarization layer 140 may include a first hole region H1 and a second hole region H2. The first hole region H1 extends from the end portion of the second body portion 152 overlapping with the second contact hole 130a to the nearest side of the outer periphery of the second body portion 152 within the second electrode region S2. The second hole region H2 extends from one side of the first hole region H1 to the other side of the outer periphery of the second body portion 152, overlapping with the opening 160a.

[0095] With this structure, the distance L1 between the center of the opening 160a and the end portion of the second body portion 152 disposed in the first hole region H1 can be formed to be greater than the distance L2 between the center of the opening 160a and the end portion of the second body portion 152 disposed in the second hole region H2. Here, the periphery of the first hole region H1 and the second hole region H2 is a portion where the second body portion 152 as a reflective electrode is disposed in the first electrode 150, and when the width of the second hole region H2 formed in the third planarization layer 140 varies, as shown in FIG. Figure 5In the plan view shown in FIG. 1 , the spacing distance between the outer periphery of the second body portion 152 and the opening 160a can be controlled. Figure 3 In the cross-sectional view shown, the horizontal distance between the portion of the second body portion 152 formed on the side portion of the third planarization layer 140 and the opening 160a can increase or decrease in proportion to the change in the width of the second hole region H2. Here, the change in the width of the second hole region H2 refers to the change in length in the X-axis direction and the Y-axis direction in the drawing.

[0096] Therefore, when the width of the second hole region H2 increases or decreases according to the wavelength of each sub-pixel SP, the spacing distance between the outer periphery of the second body portion 152 and the opening 160a can be set to be different, which can enhance VACS. In addition, since the position of the second body portion 152 extends and moves the width of the first hole region H1, the spacing distance can be formed to widen the width of the first hole region H1, so that VACS can be enhanced without reducing the aperture ratio.

[0097] The second hole region H2 may be formed to extend up to a point before the second contact hole 130a. This is because when the second hole region H2 overlaps the second contact hole 130a, the size of the first electrode 150 covering the hole 140a also increases, making it difficult to ensure the minimum process margin M required between adjacent first electrodes 150.

[0098] Meanwhile, since the control member 141 is not disposed between the second contact hole 130a and the first body portion 151, the display device 100 according to this embodiment can increase the width of the opening 160a by the width of the control member 141. Therefore, light extraction efficiency can be increased by increasing the aperture ratio.

[0099] Figure 6 It is shown from Figure 5 Schematic diagram of a state where a sub-pixel emits light.

[0100] refer to Figure 6 The sub-pixel SP disposed in the display area AA may include an emission area EA including a main emission area MEA and a reflective light area REA, and a non-emission area NEA which is an area other than the emission area EA.

[0101] The main emission area MEA may be disposed in a first area A1 overlapping an organic light emitting diode formed by the first electrode 150, the light emitting layer 170, and the second electrode 180. That is, the main emission area MEA is a region in which light generated by the light emitting element ED is emitted through the opening 160a and may be a region having the highest brightness in the subpixel SP.

[0102] The reflective light area REA may be provided to surround the outer circumference of the main emission area MEA in the second area A2 and have one side portion protruding outward to form the protruding area PA. For example, the protruding area PA may protrude in a direction in which the second contact hole 130a is provided, and the first contact hole 120a and the second contact hole 130a may be located in the protruding area PA.

[0103] In this embodiment, the reflected light area REA may be a region where light in a waveguide mode propagating to the side portions of the light-emitting layer 170 is totally reflected by the second main portion 152 of the first electrode 150 and emitted to the outside. In this case, since the amount of light emitted in the waveguide mode is less than the amount of light emitted through the opening 160a, the reflected light area REA may have a lower brightness than the main emission area MEA. Since the area of ​​the second main portion 152 of the first electrode 150 that overlaps the bank layer 160 does not extend onto the side portions of the third planarization layer 140 but is instead located on the second planarization layer 130, it may be a region where total reflection is relatively unlikely to occur. Therefore, a side ring R may be formed between the main emission area MEA and the reflected light area REA. In other words, the side ring R may be the region with the lowest brightness in the emission area EA. Although not shown, when viewed in plan, the side ring R may have a protruding shape in accordance with the protruding area PA. Due to this protruding shape, the width of the side ring R may be greatest in the protruding area PA.

[0104] Figure 7 is a plan view illustrating the arrangement of sub-pixels according to an embodiment of the present disclosure.

[0105] refer to Figure 7 The sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4 that are adjacent to each other. For example, the first sub-pixel SP1 may be formed to emit red light, the second sub-pixel SP2 and the third sub-pixel SP3 may be formed to emit green light, and the fourth sub-pixel SP4 may be formed to emit blue light. Since the sub-pixels SP are formed in different structures and positions for each color, the intervals between the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 may be different. Therefore, the interval distance between the outer periphery of the second main portion 152 and the opening 160a may extend asymmetrically according to the interval between each sub-pixel SP.

[0106] According to this embodiment, the first and fourth subpixels SP1 and SP4 can be formed to have a square shape, and the second and third subpixels SP2 and SP3 can be formed to have an elliptical or rectangular shape. Furthermore, the protruding areas PA of the first and third subpixels SP1 and SP3 can protrude outward, while the protruding areas PA of the fourth and second subpixels SP4 and SP2 can protrude inward. This structure can improve luminous efficiency by maximizing the number of subpixels arranged on a plane. The protruding areas PA of the second and third subpixels SP2 and SP3 can point in a first direction, and the protruding areas PA of the first and fourth subpixels SP1 and SP4 can point in a second direction different from the first direction. The protruding areas PA of the fourth and second subpixels SP4 and SP2 can be formed to face each other more closely than the protruding areas PA of the first and third subpixels SP1 and SP3.

[0107] Figure 8 is a plan view illustrating a data line overlapping a sub-pixel according to an embodiment of the present disclosure.

[0108] refer to Figure 8 The display device 100 may further include data lines DL electrically connected to the sub-pixels SP disposed in the first area A1, and the data lines DL may be arranged in a row. When the data lines DL are arranged in a row as described above, more installation space can be secured than when a curved data line is provided, and the positions of the first contact hole 120a and the second contact hole 130a can be more easily designed.

[0109] According to this embodiment, a plurality of sub-pixels SP may be provided, and a data line DL may overlap at least two sub-pixels SP. Furthermore, the data line DL may overlap the light-reflecting area REA of at least one sub-pixel SP. With this structure, luminous efficiency can be improved by maximally arranging the plurality of sub-pixels SP on a plane.

[0110] refer to Figure 8 The display device 100 may further include a driving voltage line DVL for applying a driving voltage to the sub-pixel SP, and the protruding area PA may be provided between the driving voltage line DVL and the data line DL. Therefore, the first contact hole 120a and the second contact hole 130a formed in the protruding area PA can be easily formed.

[0111] The embodiments of the present disclosure described above are briefly described below.

[0112] According to an embodiment of the present disclosure, a display device can be provided, including a sub-pixel, the sub-pixel including a first area overlapping with an organic light-emitting diode and a second area not overlapping with the organic light-emitting diode and arranged to surround the periphery of the first area, a main emission area arranged in the first area, and a reflective light area arranged to surround the periphery of the main emission area in the second area and having a side portion protruding outward to form a protruding area.

[0113] According to an embodiment of the present disclosure, due to the difference in the amount of light in the main emission area and the reflected light area, a side ring can be formed between the main emission area and the reflected light area. According to an embodiment of the present disclosure, the side ring includes a protruding shape according to the protruding area. According to an embodiment of the present disclosure, the width of the side ring is thickest in the protruding area.

[0114] According to an embodiment of the present disclosure, a sub-pixel may include: a base substrate including a first region and a second region, a first planarization layer arranged on the base substrate and having a first contact hole, a second planarization layer arranged on the first planarization layer and having a second contact hole overlapping with the first contact hole, a third planarization layer arranged on the second planarization layer and having a hole overlapping with the first contact hole and the second contact hole, a first electrode overlapping with the hole of the third planarization layer, a dam layer having an opening formed to expose a portion of the first electrode, a light-emitting layer arranged in the opening of the dam layer, and a second electrode arranged on the dam layer and the light-emitting layer.

[0115] According to an embodiment of the present disclosure, the protruding region may protrude in a direction in which the second contact hole is provided.

[0116] According to an embodiment of the present disclosure, the first contact hole and the second contact hole may be located in the protrusion region.

[0117] According to an embodiment of the present disclosure, the first electrode may include a first main body portion arranged in the first area, a second main body portion arranged to surround the periphery of the first main body portion in the second area and having a protrusion protruding from one side of the first main body portion to overlap with the second contact hole, and a third main body portion arranged to surround the periphery of the second main body portion.

[0118] According to an embodiment of the present disclosure, the second body portion may totally reflect light propagating from the light emitting layer to the side portion toward the opening.

[0119] According to an embodiment of the present disclosure, the first body portion may be disposed on an upper portion of the second planarization layer. The second body portion may extend from the first body portion and be disposed on an upper portion of the second planarization layer and a side portion of the third planarization layer. The third body portion may extend from the second body portion and be disposed on an upper portion of the third planarization layer.

[0120] According to an embodiment of the present disclosure, no portion of the third planarization layer is provided between the second contact hole and the first body portion.

[0121] According to an embodiment of the present disclosure, the display device may further include a driving transistor disposed on the base substrate and a connection electrode disposed on the first planarization layer and having a portion inserted into the first contact hole to electrically connect the first electrode and the driving transistor.

[0122] According to an embodiment of the present disclosure, when a portion of the first electrode is inserted into the second contact hole, the first electrode may contact the connection electrode.

[0123] According to an embodiment of the present disclosure, a horizontal distance between the opening and a portion of the second body portion of the first electrode disposed on a side portion of the third planarization layer is controlled by adjusting a size of the hole of the third planarization layer.

[0124] According to an embodiment of the present disclosure, the height of the bank layer disposed between the second contact hole and the first region may be formed to be greater than the height of the bank layer overlapping the third planarization layer and less than the height of the bank layer overlapping the second contact hole.

[0125] According to an embodiment of the present disclosure, the opening may overlap with the hole of the third planarization layer and may not overlap with the first contact hole and the second contact hole.

[0126] According to an embodiment of the present disclosure, the first electrode may include a first electrode region overlapping the second contact hole and a second electrode region extending from one side of the first electrode region and overlapping the opening.

[0127] According to an embodiment of the present disclosure, the hole formed in the third planarization layer may include: a first hole region, which extends from an end portion of the second main body portion overlapping with the second contact hole to the nearest side of the periphery of the second main body portion within the second electrode region; and a second hole region, which extends from one side of the first hole region to the other side of the periphery of the second main body portion and overlaps with the opening.

[0128] According to an embodiment of the present disclosure, the spacing distance between the opening and the outer periphery of the second body portion may be controlled by changing the width of the second hole region.

[0129] According to an embodiment of the present disclosure, the second hole region may be formed to extend to a point before the second contact hole.

[0130] According to an embodiment of the present disclosure, the distance from the center of the opening to the end portion of the second body portion disposed in the first hole region may be formed to be greater than the straight-line distance from the center of the opening to the end portion of the second body portion disposed in the second hole region.

[0131] According to an embodiment of the present disclosure, the subpixels may include first, second, third, and fourth subpixels adjacent to each other. The first and fourth subpixels may be formed to have a rectangular shape, and the second and third subpixels may be formed to have an elliptical shape.

[0132] According to an embodiment of the present disclosure, the first sub-pixel and the fourth sub-pixel may be disposed to be symmetrical about the horizontal axis, and the second sub-pixel and the third sub-pixel may be disposed to be symmetrical about the vertical axis.

[0133] According to an embodiment of the present disclosure, the protruded areas of the first and third sub-pixels may protrude in an outward direction, and the protruded areas of the fourth and second sub-pixels may protrude in an inward direction.

[0134] According to an embodiment of the present disclosure, the display device may further include data lines electrically connected to the sub-pixels, wherein the data lines are arranged in rows.

[0135] According to an embodiment of the present disclosure, a plurality of sub-pixels may be provided, and a data line may overlap with at least two sub-pixels.

[0136] According to an embodiment of the present disclosure, a plurality of sub-pixels may be provided, and the data line may overlap with a light-reflecting region of at least one of the sub-pixels.

[0137] According to an embodiment of the present disclosure, the display device may further include a driving voltage line for applying a driving voltage to the sub-pixel. The protruding area may be provided between the driving voltage line and the data line.

[0138] The above description has been presented to enable any person skilled in the art to make and use the technical concepts of the present disclosure, and has been provided in the context of a specific application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical concepts of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the present disclosure.

[0139] [Description of Reference Signs]

[0140] 100: Display device

[0141] 110: Base substrate

[0142] 120: First planarization layer

[0143] 130: Second planarization layer

[0144] 140: Third planarization layer

[0145] 150: First electrode

[0146] 151: First main part

[0147] 152: Second main part

[0148] 153: The third main part

[0149] 160: Embankment layer

[0150] 170: Luminous layer

[0151] 180: Second electrode

Claims

1. A display device comprising: a sub-pixel, the sub-pixel including a first region and a second region, the first region overlapping with the organic light-emitting diode, the second region not overlapping with the organic light-emitting diode and disposed around a periphery of the first region; a main emission area, the main emission area being arranged in the first area; as well as A light reflecting area is provided to surround an outer periphery of the main emission area in the second area and has one side portion protruding outward to form a protruding area. 2 . The display device according to claim 1 , further comprising a side ring formed between the main emission area and the light reflection area.

3. The display device according to claim 2, wherein: The side ring includes a protruding shape according to the protruding area.

4. The display device according to claim 3, wherein The width of the side ring is thickest in the protruding area.

5. The display device according to claim 1, wherein The sub-pixel further includes: a base substrate, the base substrate comprising the first region and the second region; a first planarization layer disposed on the base substrate and having a first contact hole; A second planarization layer is disposed on the first planarization layer and has a second contact hole overlapping the first contact hole. The display device according to claim 5 , wherein: The sub-pixel further includes: a third planarization layer disposed on the second planarization layer and having a hole overlapping the first contact hole and the second contact hole; a first electrode, the first electrode overlapping the hole of the third planarization layer; a bank layer having an opening formed to expose a portion of the first electrode; a light emitting layer disposed in the opening of the bank layer; and A second electrode is provided on the bank layer and the light emitting layer.

7. The display device according to claim 5, wherein: The protruding region protrudes in a direction in which the second contact hole is provided.

8. The display device according to claim 5, wherein The first contact hole and the second contact hole are located in the protruding region.

9. The display device according to claim 6, wherein: The first electrode comprises: a first main body portion disposed in the first region; a second body portion provided to surround an outer circumference of the first body portion in the second region and having a protrusion protruding from one side of the first body portion to overlap with the second contact hole; and A third main body portion is provided to surround an outer periphery of the second main body portion.

10. The display device according to claim 9, wherein The second body portion totally reflects light propagating from the light emitting layer to the side portion toward the opening.

11. The display device according to claim 9, wherein The first body portion is disposed on an upper portion of the second planarization layer, wherein the second body portion extends from the first body portion and is disposed on an upper portion of the second planarization layer and a side portion of the third planarization layer, and The third body portion extends from the second body portion and is disposed on an upper portion of the third planarization layer.

12. The display device according to claim 11, wherein No portion of the third planarization layer is provided between the second contact hole and the first body portion.

13. The display device according to claim 6, further comprising: a driving transistor, the driving transistor being disposed on the base substrate; as well as A connection electrode is provided on the first planarization layer and has a portion inserted into the first contact hole to electrically connect the first electrode and the driving transistor.

14. The display device according to claim 13, wherein: When a portion of the first electrode is inserted into the second contact hole, the first electrode contacts the connection electrode.

15. The display device according to claim 11, wherein A horizontal distance between the opening and a portion of the second body portion of the first electrode disposed on a side portion of the third planarization layer is controlled by adjusting a size of the hole of the third planarization layer.

16. The display device according to claim 6, wherein: The height of the bank layer provided between the second contact hole and the first region is formed to be greater than the height of the bank layer overlapping the third planarization layer and smaller than the height of the bank layer overlapping the second contact hole.

17. The display device according to claim 6, wherein: The opening overlaps with the hole of the third planarization layer and does not overlap with the first contact hole and the second contact hole.

18. The display device according to claim 6, wherein The first electrode comprises: a first electrode region, the first electrode region overlapping the second contact hole; and A second electrode region extends from one side of the first electrode region and overlaps the opening.

19. The display device according to claim 18, wherein The hole formed in the third planarization layer includes: a first hole region extending from an end portion of the second body portion overlapping the second contact hole to a nearest side of an outer periphery of the second body portion within the second electrode region; and A second hole region extends from one side of the first hole region to the other side of the outer periphery of the second body portion and overlaps with the opening.

20. The display device according to claim 19, wherein The spacing distance between the opening and the outer periphery of the second body portion is controlled by varying the width of the second hole region.

21. The display device according to claim 19, wherein The second hole region is formed to be able to extend to a point before the second contact hole.

22. The display device according to claim 17, wherein A distance from a center of the opening to an end portion of the second body portion disposed in the first hole region is formed to be greater than a distance from the center of the opening to an end portion of the second body portion disposed in the second hole region.

23. The display device according to claim 1, wherein The sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel that are adjacent to each other, and The first and fourth sub-pixels are formed to have rectangular shapes, and the second and third sub-pixels are formed to have elliptical shapes.

24. The display device according to claim 23, wherein The first sub-pixel and the fourth sub-pixel are arranged symmetrically about a horizontal axis, and the second sub-pixel and the third sub-pixel are arranged symmetrically about a vertical axis.

25. The display device according to claim 23, wherein The protruding regions of the first and third sub-pixels protrude in an outward direction, and the protruding regions of the fourth and second sub-pixels protrude in an inward direction.

26. The display device according to claim 1, further comprising a data line electrically connected to the sub-pixel, wherein The data lines are arranged in rows.

27. The display device according to claim 26, wherein: A plurality of sub-pixels are provided, and wherein the data line overlaps at least two sub-pixels.

28. The display device according to claim 27, wherein: A plurality of sub-pixels are provided, and wherein the data line overlaps with a light reflecting area of ​​at least one of the sub-pixels.

29. The display device according to claim 26, further comprising a driving voltage line for applying a driving voltage to the sub-pixel, wherein The protruding area is disposed between the driving voltage line and the data line.

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