Light-emitting display device

Abstract

Disclosed is a light emitting display device including a substrate, a first metal layer on the substrate, a first insulating layer on the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer, and a second metal layer on the second insulating layer, in which at least one thin film transistor includes the semiconductor layer, the semiconductor layer is in contact with the first metal layer and is not in contact with the second metal layer.

Description

Technical Field

[0001] The present disclosure relates to a light-emitting display device, and more specifically, for example but not limited to, to a light-emitting display device in which contact holes are formed before an active layer, the light-emitting display device enabling a first metal layer to be connected to the active layer, and enabling a thin film transistor to be configured without a contact hole for connecting to a second metal layer, so that the number of contact holes can be reduced, thereby preventing contact defects caused by a low-reflective metal layer and improving the effective spatial arrangement and connection structure of the thin film transistor. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images in various forms has also increased. Therefore, display devices such as liquid crystal display (LCD) devices, organic light emitting display (OLED) devices, micro light emitting diode (LED) devices, and quantum dot display (QD) devices are used.

[0003] Among these display devices, organic light-emitting display devices, unlike liquid crystal displays (LCDs), use self-luminous light-emitting elements rather than separate light sources. Consequently, OLEDs have gained widespread adoption in the display industry due to their thin profiles and excellent image quality. In OLEDs, a low-reflective metal layer is applied to the metal layer used to connect the master node to prevent reflection of light emitted from internal pixels or incident light projected from the outside.

[0004] The description provided in the discussion of related art section should not be assumed to be prior art simply because it is mentioned in or related to that section. The discussion of related art section may include information describing one or more aspects of the subject technology, and the descriptions in this section do not limit the present invention. Summary of the Invention

[0005] The inventors of this application have discovered that a low-reflective metal layer may remain as a residual film during the process of forming a metal layer in a main node through an insulating layer or forming a large number of contact holes for connecting the metal layer and the semiconductor layer, which may cause contact failure. Therefore, there is an increasing demand for effective spatial arrangements and connection structures between components that can prevent contact failure caused by low-reflective metal layers.

[0006] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to provide a light-emitting display device in which a contact hole is formed before an active layer, which enables a first metal layer to be connected to the active layer, and enables a thin film transistor to be configured without a contact hole for connecting to a second metal layer, so that the number of contact holes can be reduced, thereby preventing contact defects caused by a low-reflective metal layer and improving the effective spatial arrangement and connection structure of the thin film transistor.

[0007] The objects of the present disclosure are not limited to the above contents, and other objects not described herein will be clearly understood by those skilled in the art from the following description.

[0008] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a light-emitting display device, which includes: a substrate; a first metal layer on the substrate; a first insulating layer on the first metal layer; a semiconductor layer on the first insulating layer; a second insulating layer on the semiconductor layer; and a second metal layer on the second insulating layer, wherein at least one thin film transistor includes the semiconductor layer, and the semiconductor layer is in contact with the first metal layer and not in contact with the second metal layer.

[0009] According to one or more embodiments of the present disclosure, the above-mentioned and other purposes can be achieved by providing a light-emitting display device, which includes: a substrate, which includes a plurality of sub-pixels; a first metal layer on the substrate; a first insulating layer on the first metal layer; a semiconductor layer on the first insulating layer; a planarization layer, which covers the first insulating layer and the semiconductor layer; and a light-emitting element on the planarization layer, wherein the semiconductor layer is connected to the first metal layer through at least one contact hole passing through the first insulating layer, and wherein the plurality of sub-pixels may include a driving transistor, and the pixel electrode of the light-emitting element is connected to the semiconductor layer of the driving transistor through a contact hole passing through the planarization layer.

[0010] According to one or more embodiments of the present disclosure, a light-emitting display device can be provided in which a contact hole is formed before an active layer, which enables a first metal layer to be connected to the active layer and enables a thin film transistor to be configured without a contact hole for connecting to a second metal layer, so that the number of contact holes can be reduced, thereby preventing contact defects caused by a low-reflective metal layer and improving the effective spatial arrangement and connection structure of the thin film transistor.

[0011] The light-emitting display device according to one or more embodiments of the present disclosure can reduce the number of contact holes, thereby preventing contact defects caused by the low-reflective metal layer, thereby improving the reliability of the manufacturing process and reducing the number of manufacturing processes used to manufacture the light-emitting display device. Therefore, environmental / social / governance (ESG) can be achieved by reducing the generation of greenhouse gases that may occur due to the manufacturing process.

[0012] Effects of the present disclosure are not limited to the above-described effects, and other effects not described herein will be clearly understood by those skilled in the art from the following description.

[0013] The details of the present disclosure described in the technical problems, technical solutions, and advantageous effects do not specify essential features of the claims, and therefore, the scope of the claims is not limited by the details described in the detailed embodiments of the present disclosure.

[0014] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain the principle of the disclosure.

[0016] Figure 1 A light emitting display device according to an exemplary embodiment of the present disclosure is shown.

[0017] Figure 2 is a block diagram illustrating a light emitting display device according to an exemplary embodiment of the present disclosure.

[0018] Figure 3 is a circuit diagram illustrating a sub-pixel of a light emitting display device according to an exemplary embodiment of the present disclosure.

[0019] Figure 4 is a plan view illustrating a sub-pixel of a light emitting display device according to an exemplary embodiment of the present disclosure.

[0020] Figure 5 According to an exemplary embodiment of the present disclosure Figure 4 Cross-sectional view along line II'.

[0021] Figure 6 According to an exemplary embodiment of the present disclosure Figure 4 The circuit diagram of the sub-pixel is shown.

[0022] Figure 7 An exemplary embodiment according to the present disclosure is shown. Figure 4 The node voltage of the driving transistor in the sub-pixel shown in .

[0023] Figures 8 to 11 The formation of an exemplary embodiment according to the present disclosure is shown Figure 4 The sub-pixel method is shown.

[0024] Figure 12 is a plan view illustrating a sub-pixel of a light-emitting display device according to another exemplary embodiment of the present disclosure.

[0025] Figure 13 According to another exemplary embodiment of the present disclosure, Figure 12 Cross-sectional view along line II-II'.

[0026] Figure 14 According to another exemplary embodiment of the present disclosure Figure 12 The circuit diagram of the sub-pixel is shown.

[0027] Figure 15 Another exemplary embodiment of the present disclosure is shown. Figure 12 The node voltage of the drive transistor in the shown sub-pixel.

[0028] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The size, length, thickness, and depiction of layers, regions, and elements may be exaggerated for clarity, illustration, and / or convenience. DETAILED DESCRIPTION

[0029] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. The progression of processing steps and / or operations described are examples; however, the order of the steps and / or operations is not limited to that set forth herein and may be varied as is known in the art, except that steps and / or operations must occur in a specific order. The names of the various elements used in the following description may have been selected solely for ease of writing the specification and, therefore, may differ from those used in an actual product.

[0030] The advantages and features of the present disclosure and their implementation methods are illustrated by the embodiments described with reference to the accompanying drawings. However, the present disclosure can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are examples and are provided to make the present disclosure thorough and complete, to help those skilled in the art understand the inventive concept without limiting the scope of protection of the present disclosure.

[0031] The shapes (e.g., size, length, width, height, thickness, position, radius, diameter, and area), ratios, angles, quantities, etc. disclosed herein (including those shown in the accompanying drawings) are examples only, and thus, the present disclosure is not limited to the details shown. Any implementation described herein as "example" is not necessarily to be construed as preferred or advantageous over other implementations. However, it should be noted that the relative sizes of components shown in the accompanying drawings are part of this disclosure.

[0032] When the terms "including," "having," "comprising," "containing," "consisting of," "made of," "formed of," etc. are used with respect to one or more elements, one or more other elements may be added unless terms such as "only" are used. When a component is described in the singular, the plural is also included unless otherwise clearly indicated. The terms used in this disclosure are only for describing example embodiments and are not intended to limit the scope of the disclosure. Terms in the singular may include plural forms unless the context clearly indicates otherwise.

[0033] The word "exemplary" is used to mean serving as an example or illustration. Aspects are example aspects. "Implementation," "example," "aspect," etc., should not be construed as preferred or advantageous over other implementations. Unless otherwise specified, references to exemplary implementations, examples, example implementations, aspects, etc., may refer to one or more implementations, one or more examples, one or more example implementations, one or more aspects, etc. Furthermore, the term "may" encompasses all meanings of the term "can."

[0034] When configuring an element, the element is interpreted as including an error region although there is no explicit description thereof.

[0035] When describing a positional relationship, for example, when the positional order is described as "on," "above," "below," "below," and "next to," a situation where there is no contact between them may be included unless "just" or "directly" is used. For example, when an element or layer is disposed "on" another element or layer, a third layer or element may be interposed therebetween.

[0036] If a first element is referred to as being "on" a second element, it does not mean that the first element is substantially above the second element in the drawings. The upper and lower portions of the objects involved may vary depending on the orientation of the objects. Therefore, a case where a first element is "on" a second element includes cases where the first element is "below" the second element as well as cases where the first element is "above" the second element in the drawings or in actual configuration.

[0037] When describing a temporal relationship, for example, when a temporal order is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "just" or "directly" is used.

[0038] It will be understood that although the terms "first," "second," "(A)," "(B)," "(a)," "(b)," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0039] When describing elements of the present disclosure, terms such as "first," "second," "A," "B," "(a)," "(b)," etc. may be used. These terms are intended to identify corresponding elements from other elements and are not used to limit the nature, basis, order, or number of the elements.

[0040] Unless otherwise specified, when an element is “connected,” “coupled,” “attached,” “bonded,” etc. to another element, the element may not only be directly connected, coupled, attached, bonded, etc. to the other element, but also may be indirectly connected, coupled, attached, bonded, etc. to the other element with one or more intermediate elements disposed or interposed between the elements.

[0041] Unless otherwise specified, when an element is stated to be “contacting,” “overlapping,” etc., another element, the element may not only be directly in contact with, overlapping, etc., but may also be indirectly in contact with, overlapping, etc., with one or more intermediate elements disposed or interposed between the elements.

[0042] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first, second, and third elements, as well as each of the first, second, and third elements.

[0043] The features of the various embodiments of the present disclosure may be partially or entirely coupled or combined with each other, may be technically associated with each other, and may interoperate, link, or drive together in various ways. The embodiments of the present disclosure may be implemented or executed independently of each other, or may be implemented or executed together in a mutually dependent or related relationship. In one or more aspects, the components of each device according to the various embodiments of the present disclosure may be operably coupled and configured.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, for example, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein. For example, the term "part" or "unit" may apply to, for example, a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function as would be understood by one of ordinary skill in the art.

[0045] In the following description, various example embodiments of the present disclosure are described in detail with reference to the accompanying drawings. With respect to the reference numerals of the elements of each drawing, the same elements may be shown in other drawings, and the same reference numerals may refer to the same elements, unless otherwise specified. The same or similar elements may be represented by the same reference numerals, even if they are shown in different drawings. In addition, for ease of description, the scale, size, size, and thickness of each element shown in the drawings may be different from the actual scale, size, size, and thickness, and therefore, the embodiments of the present disclosure are not limited to the scale, size, size, and thickness shown in the drawings.

[0046] Figure 1 A light emitting display device according to an exemplary embodiment of the present disclosure is shown. Figure 2 is a block diagram illustrating a light emitting display device according to an exemplary embodiment of the present disclosure.

[0047] The light-emitting display device 100 according to an exemplary embodiment of the present disclosure is implemented as an organic light-emitting display device, but may also be implemented as a liquid crystal display device, a quantum dot light-emitting diode display device, or an electrophoretic display device.

[0048] Reference Figure 1 and Figure 2 The light-emitting display device 100 according to an exemplary embodiment of the present disclosure may include a display panel 110, a scan driver 120 embedded in the display panel 110, a data driver 130 connected to the display panel 110, a timing controller 160 controlling the scan driver 120 and the data driver 130, and a power supply circuit 170.

[0049] The display panel 110 may include a substrate 111 and an opposing substrate 115. The opposing substrate 115 may be an encapsulation substrate. The substrate 111 may include a plastic film, a glass substrate or a flexible polymer film, but the embodiments of the present disclosure are not limited thereto. For example, the flexible polymer film may be made of any one of polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film and polystyrene (PS), which are only examples and are not necessarily limited thereto. For example, the substrate 111 may be formed of a semiconductor material such as a silicon wafer. The opposing substrate 115 may be a plastic film, a glass substrate or an encapsulation film (or protective film).

[0050] The display panel 110 includes a display area DA and a non-display area NDA surrounding the display area DA. The display panel 110 includes pixels P arranged in the display area DA to display images. Each pixel P may include multiple sub-pixels SP. The structure of the sub-pixels SP may vary depending on the type of light-emitting display device 100. For example, depending on the structure, the sub-pixels SP may be formed as a top-emission type, a bottom-emission type, or a dual-emission type, but embodiments of the present disclosure are not limited thereto. A sub-pixel SP refers to a unit capable of forming a specific type of color filter or capable of emitting its own color without forming a color filter. For example, the sub-pixels SP may include red, green, and blue sub-pixels, but embodiments of the present disclosure are not limited thereto. Sub-pixels of other colors (such as cyan, magenta, or yellow) are also possible. Alternatively, the sub-pixels SP may include red, blue, white, and green sub-pixels. Depending on the light-emitting characteristics, the sub-pixels SP may have one or more other light-emitting areas. For example, the multiple sub-pixels SP may be arranged in a quadrilateral or stripe shape, but embodiments of the present disclosure are not limited thereto. The color type, arrangement type, arrangement order, etc. of the sub-pixels SP may be configured in various forms according to light emission characteristics, lifespan of a device, specifications of a device, etc.

[0051] The display panel 110 may include data lines DL and scan lines SL connected to the sub-pixels SP. The data lines DL may be arranged to intersect the scan lines SL. Each of the plurality of data lines DL may be configured to extend in a first direction. Each of the plurality of gate lines GL may be configured to extend in a second direction different from the first direction. Each of the sub-pixels SP of the display panel 110 may be connected to any one of the data lines DL and any one of the scan lines SL. The data lines DL may supply a data voltage (which may be referred to as a data voltage or an image signal) supplied from the data driver 130 to each of the sub-pixels SP. The scan lines SL may supply a scan signal (which may be referred to as a gate signal) provided from the scan driver 120 to each of the sub-pixels SP.

[0052] Each sub-pixel SP is turned on by a scan signal. When the data voltage of the data line DL is supplied to the gate of the driving transistor, the light-emitting element can emit light according to the drain-source current of the driving transistor. The scan driver 120 can receive a scan control signal GCS from the timing controller 160. The scan driver 120 can supply a scan signal or a light-emitting control signal to the scan line SL using the scan control signal GCS.

[0053] The scan driver 120 can be configured in a gate-in-panel (GIP) manner in the non-display area NDA outside one or both sides of the display area DA, but is not limited thereto. Alternatively, the scan driver 120 can be provided in the display area DA of the display panel 110. Alternatively, the scan driver 120 can be manufactured as a driver chip, mounted on a flexible film, and attached to the non-display area NDA outside one or both sides of the display area DA using a tape automated bonding (TAB) method.

[0054] The data driver 130 may receive digital video data DATA and a data control signal DCS from the timing controller 160. The data driver 130 converts the digital video data DATA into analog positive / negative data voltages by using the data control signal DCS and supplies the analog positive / negative data voltages to the data lines DL.

[0055] The data driver 130 may include Figure 1 The plurality of data driver ICs 131 are shown. Each of the plurality of data driver ICs 131 may be mounted on a flexible film 140 by a chip on film (COF), a chip on plastic (COP), a flexible printed circuit (FPC), or a flexible flat cable (FFC). The flexible film 140 is attached to a pad provided in the non-display area (NDA) of the display panel 110 by using an anisotropic conductive film, whereby the plurality of data driver ICs 131 may be connected to the pad.

[0056] The circuit board 150 may be attached to the flexible film 140. A plurality of circuits implemented as a driving chip may be mounted on the circuit board 150. For example, the timing controller 160 may be mounted on the circuit board 150. The circuit board 150 may be a printed circuit board, a flexible printed circuit board, or the like.

[0057] Timing controller 160 receives digital video data DATA and timing signals from the host system. Timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a dot clock, and the like. The vertical synchronization signal defines a frame period. The horizontal synchronization signal defines a horizontal period required to supply data voltage to pixels in a horizontal row of display panel 110. The data enable signal defines the period during which valid data is input. The dot clock is a signal that repeats at a predetermined short period.

[0058] The timing controller 160 may generate a data control signal DCS for controlling the operation timing of the data driver 130 and a scan control signal GCS for controlling the operation timing of the scan driver 120 based on the timing signal. The timing controller 160 may output the scan control signal GCS to the scan driver 120 to control the scan driver 120, and output the digital video data DATA and the data control signal DCS to the data driver 130 to control the data driver 130.

[0059] The power supply circuit 170 can generate and supply a plurality of driving voltages required for the operation of all circuit configurations of the light-emitting display device 100 by using an input voltage. The power supply circuit 170 can generate a first power supply voltage EVDD (or pixel power supply voltage), a second power supply voltage EVSS (or common power supply voltage), and an initialization voltage Vref (or reference voltage), and supply the generated voltages to the display panel 110. The power supply circuit 170 can generate and supply various driving voltages required for the operation of the scan driver 120, the data driver 130, and the timing controller 160.

[0060] Figure 3 is a circuit diagram illustrating a sub-pixel of a light emitting display device according to an exemplary embodiment of the present disclosure.

[0061] Reference Figure 3 , each pixel includes a plurality of sub-pixels SP constituting a unit pixel. For example, the sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, but the embodiments of the present disclosure are not limited thereto. In each of the plurality of sub-pixels SP, there is a pixel circuit having a 3T (transistor) 1C (capacitor) including a drive transistor DR, a first switching transistor TR1, a second switching transistor TR2, and a storage capacitor Cst, as well as a light-emitting element ED, but is not limited thereto. Each sub-pixel SP may further include a compensation circuit. In this case, the sub-pixels SP may have various structures, such as 4T1C, 4T2C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C, etc., and may include more or fewer transistors and capacitors.

[0062] At least one thin film transistor DR, TR1, and TR2 of each sub-pixel SP may be implemented as an oxide thin film transistor TFT including an oxide semiconductor, a low-temperature polysilicon thin film transistor LTPS TFT including LTPS, etc., but is not limited thereto. In addition, each thin film transistor may be P-type or N-type, or P-type and N-type may be used interchangeably, but is not limited thereto.

[0063] At least one thin-film transistor DR, TR1, and TR2 is a three-electrode element comprising a gate, a source, and a drain. The source is an electrode for supplying carriers to the transistor. In at least one thin-film transistor DR, TR1, and TR2, carriers flow from the source. In at least one thin-film transistor DR, TR1, and TR2, carriers flow from the source to the drain. In an N-type transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, causing electrons to flow from the source to the drain. In an N-type transistor, current flows from the drain to the source. In a P-type transistor (PMOS), since the carriers are holes, the source voltage is higher than the drain voltage, causing holes to flow from the source to the drain. In a P-type transistor, since holes flow from the source to the drain, current flows from the source to the drain. The source and drain of at least one thin-film transistor DR, TR1, and TR2 are not fixed and may be changed depending on the applied voltage, but embodiments of the present disclosure are not limited to this. Either one of the source and the drain may be denoted as a first electrode, and the other may be denoted as a second electrode.

[0064] The selection signal can swing between a gate-on voltage and a gate-off voltage. The gate-on voltage can be set to a voltage higher than the threshold voltage of at least one thin film transistor DR, TR1, and TR2, and the gate-off voltage can be set to a voltage lower than the threshold voltage of at least one thin film transistor DR, TR1, and TR2. At least one thin film transistor DR, TR1, and TR2 can be turned on in response to the gate-on voltage, and at least one thin film transistor DR, TR1, and TR2 can be turned off in response to the gate-off voltage, but is not limited thereto. In the case of an N-type transistor, the gate-on voltage can be a gate high voltage VGH, and the gate-off voltage can be a gate low voltage VGL. In the case of a P-type transistor, the gate-on voltage can be a gate low voltage VGL, and the gate-off voltage can be a gate high voltage VGH.

[0065] The first switching transistor TR1 can be turned on or off in response to a scan signal Scan applied through the scan line SL (or gate line). When the first switching transistor TR1 is turned on in response to the scan signal Scan, the data voltage Vdata applied through the data line DL can be transmitted to one end of the storage capacitor Cst.

[0066] The second switching transistor TR2 can be turned on or off in response to a scan signal Scan applied via a scan line SL (or a gate line). When the second switching transistor TR2 is turned on in response to the scan signal Scan, the second switching transistor TR2 can be used to supply a reference voltage Vref provided from a reference line REFL to the drive transistor DR. For example, the gate of the second switching transistor TR2 can be connected to the scan line SL (or a gate line), and the first electrode of the second switching transistor TR2 can be connected to the reference line REFL. In addition, the second electrode of the second switching transistor TR2 can be connected to the first electrode of the drive transistor DR and the other end of the storage capacitor Cst.

[0067] For example, the second switching transistor TR2 can be turned on in response to a scan signal Scan applied via a scan line SL (or a gate line). When the second switching transistor TR2 is turned on, a reference voltage Vref applied via a reference line REFL can be transmitted to the other end of the storage capacitor Cst. In addition, the reference voltage Vref can also be applied to a first electrode of the drive transistor DR, such as a source electrode of the drive transistor DR.

[0068] The storage capacitor Cst holds the data voltage Vdata supplied to the drive transistor DR for one frame. For example, the storage capacitor Cst may have a first electrode connected to the gate of the drive transistor DR and a second electrode connected to the source of the drive transistor DR. The storage capacitor Cst may store a voltage corresponding to the data voltage Vdata transmitted by the first switching transistor TR1 and may use the stored voltage to turn on the drive transistor DR.

[0069] The drive transistor DR can be turned on or off in response to the voltage stored in the storage capacitor Cst. When the drive transistor DR is turned on, the drive transistor DR generates a data current from the first power supply voltage EVDD supplied from the pixel power supply line VDDL (or the first power supply line) and supplies the data current to the anode of the light-emitting element ED. For example, the gate electrode of the drive transistor DR is connected to one end of the storage capacitor Cst, and the first electrode of the drive transistor DR is connected to the pixel power supply line VDDL. In addition, the second electrode of the drive transistor DR is connected to the anode of the light-emitting element ED.

[0070] The light-emitting element ED may include an anode connected to the drive transistor DR, a cathode supplied with a second power supply voltage EVSS from a common power supply line VSSL (or a second power supply line), and a light-emitting layer between the anode and the cathode. For example, the light-emitting layer may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), but the present disclosure is not limited thereto. The anode is an independent electrode for each light-emitting element, but the cathode may be a common electrode shared by the entire light-emitting element. When a driving current is supplied from the drive transistor DR to the light-emitting element ED, electrons from the cathode are injected into the light-emitting layer, and holes from the anode are injected into the light-emitting layer, whereby the fluorescent or phosphorescent material emits light by recombination of electrons and holes in the light-emitting layer, thereby generating light with a brightness proportional to the current value of the driving current.

[0071] The anode of the light emitting element ED is connected to the second electrode of the driving transistor DR, and the cathode of the light emitting element ED is connected to the common power supply line VSSL. The light emitting element ED can emit light in response to the driving current generated by the driving transistor.

[0072] Figure 4 is a plan view illustrating a sub-pixel of a light emitting display device according to an exemplary embodiment of the present disclosure. Figure 5 According to an exemplary embodiment of the present disclosure Figure 4 Cross-sectional view along line II'. Figure 6 According to an exemplary embodiment of the present disclosure Figure 4 The circuit diagram of the sub-pixel is shown. Figure 7 An exemplary embodiment according to the present disclosure is shown. Figure 4 The node voltage of the driving transistor in the sub-pixel shown in .

[0073] Reference Figures 4 to 7According to an exemplary embodiment of the present disclosure, a subpixel SP may include a pixel circuit including at least one thin-film transistor DR, TR1, and TR2, and a storage capacitor Cst. For example, the at least one thin-film transistor DR, TR1, and TR2 may include a drive transistor DR, a first switching transistor TR1, and a second switching transistor TR2. The subpixel SP may include a light-emitting element ED for receiving a drive current from the pixel circuit and emitting light. For example, the light-emitting element ED may include a first electrode AND (or anode, pixel electrode), a light-emitting layer EL (or organic light-emitting layer), and a second electrode CE (or cathode, common electrode). At least one power line and at least one signal line may be provided in the subpixel SP. For example, the at least one power line may include a first power line VDDL (or pixel power line) and a second power line VSSL (or common power line) extending in a first direction (or Y-axis direction). The at least one signal line may include a data line DL and a reference line REFL extending in the first direction (or Y-axis direction), and a scan line SL and an auxiliary signal line VL extending in a second direction (or X-axis direction).

[0074] Reference Figure 5 In the display panel 110 according to an exemplary embodiment of the present disclosure, a first metal layer ML1 is provided on a substrate 111, a first insulating layer 112 is provided on the first metal layer ML1, an active layer ACT (or semiconductor layer) is provided on the first insulating layer 112, a second insulating layer 113 is provided on the active layer ACT, and a second metal layer ML2 may be provided on the second insulating layer 113, but is not limited thereto. At least one thin film transistor DR, TR1, and TR2 may be formed using the first metal layer ML1, the active layer ACT, and the second metal layer ML2. For example, the active layer ACT may be in contact with the first metal layer ML1 and may not be in contact with the second metal layer ML2, thereby forming the at least one thin film transistor DR, TR1, and TR2. For example, the second metal layer ML2 may not be in contact with the active layer ACT and the first metal layer ML1.

[0075] The first metal layer ML1 may be provided on the substrate 111. The first metal layer ML1 may be formed as a single layer or multilayer structure of any one of molybdenum Mo, aluminum Al, chromium Cr, tungsten W, gold Au, titanium Ti, nickel Ni, neodymium Nd, and copper Cu, or an alloy thereof, but is not limited thereto. The first metal layer ML1 may include a low-reflection material layer for low reflection of external light. For example, the low-reflection material layer may be provided on the lower portion of the first metal layer ML1, and the low-reflection material layer may include a metal oxide or an alloy oxide. For example, the low-reflection material layer may include copper oxide CuOx, nickel oxide NiOx, molybdenum oxide MoOx, or tungsten oxide WOx, but embodiments of the present disclosure are not limited thereto. For example, the first metal layer ML1 may have a double-layer structure including copper Cu and a metal oxide.

[0076] The first metal layer ML1 may include a first power line VDDL (or pixel power line), a second power line VSSL (or common power line), a data line DL, a reference line REFL, a gate DR_GE of the driving transistor DR, and a first electrode Cst_E1 of the storage capacitor Cst, but is not limited thereto. Figure 5 , the second power supply line VSSL and the reference line REFL are omitted.

[0077] The first power line VDDL, the second power line VSSL, the data line DL, and the reference line REFL constituting the first metal layer ML1 may extend in a first direction (or Y-axis direction) on the substrate 111. The gate electrode DR_GE of the drive transistor DR and the first electrode Cst_E1 of the storage capacitor Cst constituting the first metal layer ML1 may be configured as an integrated island pattern, but are not limited thereto.

[0078] The first insulating layer 112 may be provided on the substrate 111 and may be configured to cover the first metal layer ML1. That is, the first insulating layer 112 may be configured to cover the first metal layer ML1 and a portion of the substrate 111 exposed by the first metal layer ML1. The first insulating layer 112 prevents diffusion of impurity ions or penetration of moisture or external air and insulates the first metal layer ML1 and the active layer ACT from each other. The first insulating layer 112 may be configured to include a silicon oxide SiO X , silicon nitride SiN X , a single layer structure or a multilayer structure of inorganic insulating materials such as aluminum oxide Al2O3, but not limited thereto.

[0079] The first insulating layer 112 may include at least one contact hole CH1, CH2, and CH3 that exposes at least a portion of the first metal layer ML1. For example, the at least one contact hole CH1, CH2, and CH3 may include a first contact hole CH1, a second contact hole CH2, and a third contact hole CH3. The first contact hole CH1 may be configured to penetrate the first insulating layer 112 to expose at least a portion of the first metal layer ML1 constituting the first power line VDDL. The second contact hole CH2 may be configured to penetrate the first insulating layer 112 to expose at least a portion of the first metal layer ML1 constituting the gate electrode DR_GE of the drive transistor DR. The third contact hole CH3 may be configured to penetrate the first insulating layer 112 to expose at least a portion of the first metal layer ML1 constituting the data line DL.

[0080] The active layer ACT (or semiconductor layer) may be disposed on the first insulating layer 112. For example, the active layer ACT (or semiconductor layer) may be disposed on a portion of the first insulating layer 112. The active layer ACT may be formed of an oxide semiconductor material or a silicon-based semiconductor material, but is not limited thereto. For example, the active layer ACT may be formed of an oxide semiconductor, such as indium gallium zinc oxide IGZO, indium gallium oxide IGO, and indium tin zinc oxide ITZO. For example, the active layer ACT composed of an oxide semiconductor may have different conductive properties depending on the oxygen content. If the oxygen content decreases, the conductivity of the oxide semiconductor may increase and may be conductive, and if the oxygen content increases, the conductivity of the oxide semiconductor may decrease.

[0081] The active layer ACT may include a first semiconductor region and a second semiconductor region. The first semiconductor region of the active layer ACT is a non-conductive region that overlaps with the second metal layer ML2. The first semiconductor region may include a semiconductor channel (or channel region) DR_ACT_Ch that overlaps with the auxiliary signal line VL (or second gate line) of the second metal layer ML2 and a semiconductor channel (or channel region) TR1_ACT_Ch that overlaps with the gate TR1_GE of the first switching transistor TR1 of the second metal layer ML2 of at least one thin film transistor DR, TR1, and TR2. The second semiconductor region of the active layer ACT may include conductive regions ACT1_Co and ACT2_Co that become conductive, and may include source electrodes DR_SE and TR1_SE, drain electrodes DR_DE and TR1_DE of at least one thin film transistor DR, TR1, and TR2, and the second electrode Cst_E2 of the storage capacitor Cst. The conductive regions ACT1_Co and ACT2_Co of the active layer ACT are not covered by the second insulating layer 113 and the second metal layer ML2 , and upper portions of the conductive regions ACT1_Co and ACT2_Co are exposed from the second insulating layer 113 and the second metal layer ML2 in a conduction process of the active layer ACT.

[0082] The active layer ACT may include a first active layer ACT1 and a second active layer ACT2 spaced apart from each other on the first insulating layer 112 .

[0083] The first active layer ACT1 may include a semiconductor channel DR_ACT_Ch, a source DR_SE, and a drain DR_DE of the driving transistor DR. In addition, the first active layer ACT1 may include a second electrode Cst_E2 of the storage capacitor Cst and a semiconductor channel, a source, and a drain of the second switching transistor TR2. Figure 5The semiconductor channel, source, and drain of the second switching transistor TR2 are omitted. The conductive region ACT1_Co of the first active layer ACT1 may contact the first metal layer ML1 constituting the first power line VDDL through a first contact hole CH1 penetrating the first insulating layer 112 .

[0084] The second active layer ACT2 may include a semiconductor channel TR1_ACT_Ch, a source electrode TR1_SE, and a drain electrode TR1_DE of the first switching transistor TR1. The conductive region ACT2_Co of the second active layer ACT2 may contact the first metal layer ML1 constituting the gate electrode DR_GE of the drive transistor DR and the second electrode Cst_E2 of the storage capacitor Cst via a second contact hole CH2 penetrating the first insulating layer 112. Furthermore, the conductive region ACT2_Co of the second active layer ACT2 may contact the first metal layer ML1 constituting the data line DL via a third contact hole CH3 penetrating the first insulating layer 112.

[0085] The second insulating layer 113 may be disposed on the first insulating layer 112 to cover at least a portion of the active layer ACT. For example, the second insulating layer 113 may be configured to cover the semiconductor channel DR_ACT_Ch of the first active layer ACT1 and the semiconductor channel TR1_ACT_Ch of the second active layer ACT2. The second insulating layer 113 may be disposed between the active layer ACT and the second metal layer ML2. For example, the second insulating layer 113 may be disposed between the semiconductor channel DR_ACT_Ch of the first active layer ACT1 and the auxiliary signal line VL of the second metal layer ML2. In addition, the second insulating layer 113 may be disposed between the semiconductor channel TR1_ACT_Ch of the second active layer ACT2 and the gate TR1_GE of the first switching transistor TR1 of the second metal layer ML2. For example, in the process of patterning the second metal layer ML2, the second insulating layer 113 may be patterned to remain under the pattern of the second metal layer ML2. The second insulating layer 113 prevents the diffusion of impurity ions and insulates the active layer ACT and the second metal layer ML2 from each other. The second insulating layer 113 may be configured to include a material such as silicon oxide SiO X , silicon nitride SiN X , a single layer structure or a multilayer structure of inorganic insulating materials such as aluminum oxide Al2O3.

[0086] The second metal layer ML2 may be disposed on the second insulating layer 113. For example, the auxiliary signal line VL of the second metal layer ML2 may be disposed on the second insulating layer 113, and the gate TR1_GE of the first switching transistor TR1 of the second metal layer ML2 may be disposed on the second insulating layer 113. For example, the second metal layer ML2 may be disposed on the second insulating layer 113 and may be patterned together with the second insulating layer 113, but is not limited thereto. The second metal layer ML2 may be disposed so as to overlap at least a portion of the active layer ACT. The second metal layer ML2 may mask the active layer ACT during the conductive process of the active layer ACT. Therefore, the active layer ACT may not become conductive in the portion overlapping with the second metal layer ML2. The second metal layer ML2 may be formed as a single layer or multilayer structure of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof, but is not limited thereto. The second metal layer ML2 may include a low-reflection material layer for low reflection of external light. For example, a low-reflective material layer may be provided on the lower portion of the second metal layer ML2, and the low-reflective material layer may include a metal oxide or an alloy oxide. For example, the low-reflective material layer may include copper oxide CuOx, nickel oxide NiOx, molybdenum oxide MoOx, or tungsten oxide WOx, but embodiments of the present disclosure are not limited thereto. For example, the second metal layer ML2 may have a double-layer structure including copper Cu and a metal oxide.

[0087] The second metal layer ML2 may include a scan line (or a first gate line), an auxiliary signal line VL (or a second gate line), a gate TR1_GE of the first switching transistor TR1, and a gate of the second switching transistor TR2, but is not limited thereto. Figure 5 In FIG, the gate of the second switching transistor TR2 is omitted.

[0088] exist Figure 5 In the embodiment, the second metal layer ML2 does not contact the active layer ACT and the first metal layer ML1, so that the second metal layer ML2 can be used as a mask pattern for the conductive process of the active layer ACT of at least one thin film transistor DR, TR1 and TR2, and the second metal layer ML2 can be composed of the gate TR1_GE of the first switching transistor TR1 and the gate (not shown) of the second switching transistor TR2, but is not limited thereto. Alternatively, as Figure 13 As shown, the second metal layer ML2 does not contact the active layer ACT and the first metal layer ML1, so that the second metal layer ML2 can be used as a mask pattern for the conductive process of the active layer ACT of at least one thin film transistor DR, TR1, TR2 and TR3, and the second metal layer ML2 can be composed of the gate TR1_GE of the first switching transistor TR1, the gate (not shown) of the second switching transistor TR2 and the gate TR3_GE of the third switching transistor TR3.

[0089] The auxiliary signal lines VL and the scan lines SL formed of the second metal layer ML2 may extend along the second direction (or X-axis direction). The scan lines SL and the auxiliary signal lines VL are parallel to each other in the second direction (or X-axis direction) and spaced apart from each other in the first direction (or Y-axis direction), but are not limited thereto.

[0090] The scan line SL is applied with a scan signal Scan for controlling the first switching transistor TR1 and the second switching transistor TR2, and may be formed by a gate TR1_GE of each of the first switching transistor TR1 and the second switching transistor TR2. For example, the scan signal Scan may be applied to the gate TR1_GE of the first switching transistor TR1 and the gate of the second switching transistor TR2 to control the first switching transistor TR1 and the second switching transistor TR2.

[0091] The auxiliary signal line VL may be configured to be applied with a voltage different from the first power voltage EVDD (or driving voltage) applied by the first power line VDDL or to be electrically floating. For example, an auxiliary voltage having a voltage level lower than that of the first power voltage EVDD may be applied to the auxiliary signal line VL.

[0092] The planarization layer 114 may be disposed on the second metal layer ML2. The planarization layer 114 may be an organic insulating layer configured to cover the second metal layer ML2 and to planarize the step difference caused by at least one thin film transistor DR, TR1, and TR2 and the storage capacitor Cst. The planarization layer 114 may be configured to protect at least one thin film transistor DR, TR1, and TR2. For example, the planarization layer 114 may be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin, but is not limited thereto. According to an exemplary embodiment of the present disclosure, a passivation layer may be disposed between the planarization layer 114 and the second metal layer ML2. The passivation layer may be an inorganic insulating layer for protecting the lower structure. For example, a passivation layer as a dielectric (e.g., an inorganic dielectric) may be composed of a single layer made of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy) film, or a multilayer film thereof. According to an exemplary embodiment of the present disclosure, the passivation layer may be omitted. Depending on circumstances, the passivation layer may be omitted when the planarization layer 114 has the function of protecting at least one thin film transistor DR, TR1, and TR2. Furthermore, a plurality of color filters may be provided on the passivation layer in the light emitting region of each sub-pixel SP. For example, when the passivation layer is omitted, the plurality of color filters may be provided on the first insulating layer 112, but embodiments of the present disclosure are not limited thereto.

[0093] The planarization layer 114 may include a fourth contact hole CH4 for exposing at least a portion of the active layer ACT. The fourth contact hole CH4 may be configured to pass through the planarization layer 114 to expose at least a portion of the conductive region ACT1_Co of the first active layer ACT1.

[0094] A first electrode AND (or anode) of the light-emitting element ED, a light-emitting layer EL (or organic light-emitting layer), a second electrode CE (or cathode), and a bank layer BA may be disposed on the planarization layer 114. For example, the bank layer BA may be made of an organic material, such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and a polyimide resin. Alternatively, the bank layer BA may include an inorganic insulating material, such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide.

[0095] The first electrode AND of the light-emitting element ED can contact the conductive region ACT_Co of the first active layer ACT1 through the fourth contact hole CH4 that penetrates the planarization layer 114. For example, the first electrode AND provided in the pixel circuit can contact the conductive region ACT1_Co constituting the source electrode DR_SE of the drive transistor DR and the second electrode Cst_E2 of the storage capacitor Cst through the fourth contact hole CH4. In addition, the first electrode AND provided in the pixel circuit can be configured as the third electrode Cst_E3 of the storage capacitor Cst.

[0096] See also Figure 6 and Figure 7 The display panel 110 according to the exemplary embodiment of the present disclosure may include the auxiliary signal line VL of the second metal layer ML2 as the back gate of the driving transistor DR. For example, an auxiliary voltage V may be applied to the auxiliary signal line VL from the outside. VL , the auxiliary voltage V VL has a voltage V higher than the source voltage of the driving transistor DR. DR,S The voltage level is the low voltage level. Auxiliary voltage V VL During the first period t1 and the second period t2 of the operation of the sub-pixel SP, a constant fixed voltage may be applied. For example, the first period t1 may be an initialization period and a data programming period before the sub-pixel SP emits light, and the second period t2 may be a light-emitting period during which the sub-pixel SP emits light. For example, an auxiliary voltage V may be applied to the back gate of the driving transistor DR. VL , to compensate for the threshold voltage of the driving transistor DR.

[0097] Figures 8 to 11 The formation of an exemplary embodiment according to the present disclosure is shown Figure 4 The sub-pixel method is shown.

[0098] refer to Figure 8, a first metal layer ML1 may be formed on a substrate. The first metal layer ML1 may include a 1st metal pattern ML11 constituting a first power line VDDL (or a pixel power line), a 1st metal pattern ML12 constituting a gate electrode DR_GE of a drive transistor DR and a first electrode Cst_E1 of a storage capacitor Cst, and a 1st metal pattern ML13 constituting a data line DL. For example, the 1st metal pattern ML11 and the 1st metal pattern ML13 may be formed to extend in a first direction (or a Y-axis direction). The 1st metal pattern ML11 and the 1st metal pattern ML13 may be spaced apart from each other in a second direction (or an X-axis direction). The 1st metal pattern ML12 may be disposed between the 1st metal pattern ML11 and the 1st metal pattern ML13. For example, the 1st metal pattern ML12 may be formed as an island pattern between the 1st metal pattern ML11 and the 1st metal pattern ML13, but is not limited thereto.

[0099] like Figure 8 As shown, a first insulating layer may be formed on the substrate to cover the first metal layer ML1. In the first insulating layer, a first contact hole CH1 exposing at least a portion of the 1-1st metal pattern ML11 may be formed therein, a second contact hole CH2 exposing at least a portion of the 1-2nd metal pattern ML12 may be formed therein, and a third contact hole CH3 exposing at least a portion of the 1-3rd metal pattern ML13 may be formed therein.

[0100] Reference Figure 9 , an active layer ACT may be formed on the first insulating layer. The active layer ACT may include a first active layer ACT1 and a second active layer ACT2.

[0101] Reference Figure 9 , the first active layer ACT1 may be formed to overlap at least a portion of the 1-1st metal pattern ML11, the 1-2nd metal pattern ML12, and the 1-3rd metal pattern ML13. The first active layer ACT1 may contact the 1-1st metal pattern ML11 through the first contact hole CH1. In addition, the first active layer ACT1 may contact at least a portion of the 1-2nd metal pattern ML12 and the 1-3rd metal pattern ML13. The first active layer ACT1 may be composed of the semiconductor channel of the drive transistor DR and the semiconductor channel of the second switching transistor TR2. In addition, the first active layer ACT1 becomes conductive, so that the first active layer ACT1 may be composed of the source and drain of the drive transistor DR, the source and drain of the second switching transistor TR2, and the second electrode of the storage capacitor Cst.

[0102] Reference Figure 9The second active layer ACT2 may be formed to overlap at least a portion of the 1-2 metal pattern ML12 and the 1-3 metal pattern ML13. The second active layer ACT2 may contact the 1-2 metal pattern ML12 through the second contact hole CH2 and may contact the 1-3 metal pattern ML13 through the third contact hole CH3. The second active layer ACT2 may be configured as a semiconductor region of the first switching transistor TR1. Furthermore, the second active layer ACT2 becomes conductive, so that the second active layer ACT2 may be formed by the source and drain of the first switching transistor TR1.

[0103] Reference Figure 10 , a second insulating layer and a second metal layer ML2 may be formed on the active layer ACT. For example, the second insulating layer may be formed on the active layer ACT, and the second metal layer may be provided on the second insulating layer. That is, the second metal layer may not contact the active layer, wherein the second insulating layer is interposed between the second metal layer and the active layer. The second metal layer ML2 may include a 2-1st metal pattern ML21 constituting the auxiliary signal line VL (or the second gate line) and a 2-2nd metal pattern ML22 constituting the scan line SL (or the first gate line). For example, the 2-1st metal pattern ML21 and the 2-2nd metal pattern ML22 may be formed to extend in the second direction (or the X-axis direction). The 2-1st metal pattern ML21 and the 2-2nd metal pattern ML22 may be spaced apart from each other in the first direction (or the Y-axis direction).

[0104] The 2-1st metal pattern ML21 may be disposed to overlap at least a portion of the first active layer ACT1, and the 2-2nd metal pattern ML22 may be disposed to overlap at least a portion of the first active layer ACT1 and the second active layer ACT2. The 2-1st metal pattern ML21 and the 2-2nd metal pattern ML22 may be patterned together with the second insulating layer 113. Each of the 2-1st metal pattern ML21 and the 2-2nd metal pattern ML22 may not contact the active layers ACT1 and ACT2, with the second insulating layer interposed therebetween.

[0105] The 2-1st metal pattern ML21 can be used as a mask during the conductive process of the active layers ACT1 and ACT2, making the portion of the first active layer ACT1 overlapping with the 2-1st metal pattern ML21 non-conductive. The exposed portion of the first active layer ACT1 that does not overlap with the 2-1st metal pattern ML21 can be configured as a conductive region ACT1_Co. The portion of the first active layer ACT1 that overlaps with the 2-1st metal pattern ML21 can be configured as a semiconductor channel of the drive transistor DR.

[0106] The 2-2nd metal pattern ML22 can be used as a mask during the conductive process of the active layers ACT1 and ACT2, rendering the portions of the first and second active layers ACT1 and ACT2 overlapping with the 2-2nd metal pattern ML22 non-conductive. The exposed portions of the first and second active layers ACT1 and ACT2 that do not overlap with the 2-2nd metal pattern ML22 can be configured as conductive regions ACT1_Co and ACT2_Co. The first active layer ACT1 overlapping with the 2-2nd metal pattern ML22 can be configured as a semiconductor channel for the second switching transistor TR2. Furthermore, the second active layer ACT2 overlapping with the 2-2nd metal pattern ML22 can be configured as a semiconductor channel for the first switching transistor TR1.

[0107] The conductive process of the active layers ACT1 and ACT2 may use plasma treatment to reduce the oxygen content of the oxide semiconductors of the active layers ACT1 and ACT2, but is not limited thereto. For example, when the oxide semiconductors of the active layers ACT1 and ACT2 are exposed to plasma (conductive process), oxygen contained in the oxide semiconductors may be removed, thereby reducing the resistance of the oxide semiconductors, and thus the oxide semiconductors become conductive. For example, the plasma treatment may be a method of discharging plasma into helium He, hydrogen H2, or argon Ar gas. The exposed portions of the active layers ACT1 and ACT2 that do not overlap with the 2-1 metal pattern ML21 and the 2-2 metal pattern ML22 of the second metal layer ML2 become conductive.

[0108] A planarization layer may be formed on the conductive active layers ACT1_Co and ACT2_Co and the second metal layer ML2. The planarization layer may be formed to cover the conductive active layers ACT1_Co and ACT2_Co and the second metal layer ML2. A fourth contact hole CH4 exposing at least a portion of the first active layer ACT1 may be formed in the planarization layer.

[0109] Reference Figure 11 The first electrode AND (or anode) of the light-emitting element ED may be formed on the planarization layer. The first electrode AND may extend from the light-emitting region of each subpixel SP. The first electrode AND may be formed to overlap at least a portion of the first active layer ACT1 and the second active layer ACT2. The first electrode AND may contact at least a portion of the first active layer ACT1 through a fourth contact hole CH4 formed in the planarization layer. Furthermore, the first electrode AND may be configured by the third electrode Cst_E3 of the storage capacitor Cst.

[0110] Figure 12 is a plan view illustrating a sub-pixel of a light-emitting display device according to another exemplary embodiment of the present disclosure. Figure 13 According to another exemplary embodiment of the present disclosure, Figure 12Cross-sectional view along line II-II'. Figure 14 According to another exemplary embodiment of the present disclosure Figure 12 The circuit diagram of the sub-pixel is shown. Figure 15 Another exemplary embodiment of the present disclosure is shown. Figure 12 By changing the reference Figures 1 to 11 The configuration of the second metal layer in the display panel 110 is described to obtain Figures 12 to 15 In the following description, the same reference numerals are assigned to the same elements except for a modified configuration, and a repeated description thereof will be omitted or briefly described.

[0111] Reference Figures 12 to 15 According to another exemplary embodiment of the present disclosure, each of the plurality of sub-pixels SP1 and SP2 may include a pixel circuit including at least one thin film transistor DR, TR1, and TR2 and a storage capacitor Cst, but is not limited thereto. Alternatively, at least one of the plurality of sub-pixels SP1 and SP2 according to another exemplary embodiment of the present disclosure may further include a third switching transistor TR3. The plurality of sub-pixels SP1 and SP2 may include at least one signal line, and the at least one signal line may include a scan line SL (or a first gate line) and an emission control line EML (or a second gate line) extending in the second direction (or the X-axis direction).

[0112] refer to Figure 12 The display panel 110 according to another exemplary embodiment of the present disclosure may further include a protrusion pattern DP provided in at least one of the plurality of sub-pixels SP1 and SP2, and may further include a third switching transistor TR3 constituted by the protrusion pattern DP.

[0113] The plurality of sub-pixels SP1 and SP2 may be formed as conductive lines formed by extending a portion of the conductive region ACT_Co of the active layer ACT connected to the first power line VDDL in the second direction (or the X-axis direction). For example, the conductive line formed by the conductive region ACT_Co may be commonly connected to the drive transistor DR of each of the plurality of sub-pixels SP1 and SP2.

[0114] Reference Figure 13 The second metal layer ML2 according to another exemplary embodiment of the present disclosure may include a scan line SL (or a first gate line), an emission control line EML (or a second gate line), a protruding pattern DP, a gate TR1_GE of the first switching transistor TR1, a gate of the second switching transistor TR2, and a gate TR3_GE of the third switching transistor TR3, but is not limited thereto. Figure 13 In FIG, the gate of the second switching transistor TR2 is omitted.

[0115] The second metal layer ML2 does not contact the active layer ACT and the first metal layer ML1, so that the second metal layer ML2 can be used as a mask pattern for the conductive process of the active layer ACT of at least one thin film transistor DR, TR1, TR2, and TR3. The second metal layer ML2 can be composed of the gate electrode TR1_GE of the first switching transistor TR1, the gate electrode (not shown) of the second switching transistor TR2, and the gate electrode TR3_GE of the third switching transistor TR3, but is not limited thereto. For example, the gate electrode TR3_GE of the third switching transistor TR3 can be a protrusion pattern DP that protrudes from the emission control line EML.

[0116] The scan lines SL and the emission control lines EML formed of the second metal layer ML2 may extend in the second direction (or the X-axis direction). The scan lines SL and the emission control lines EML may be parallel to each other in the second direction (or the X-axis direction) and may be spaced apart from each other in the first direction (or the Y-axis direction).

[0117] The scan line SL may be applied with a scan signal Scan for controlling the first switching transistor TR1 and the second switching transistor TR2, and may be formed by a gate TR1_GE of each of the first switching transistor TR1 and the second switching transistor TR2. For example, the scan signal Scan may be applied to the gate TR1_GE of the first switching transistor TR1 and the gate of the second switching transistor TR2 to control the first switching transistor TR1 and the second switching transistor TR2.

[0118] A light emitting control signal (or light emitting signal) for controlling the third switching transistor TR3 may be applied to the light emitting control line EML. The protruding pattern DP of the light emitting control line EML may be configured as a gate TR3_GE of the third switching transistor TR3.

[0119] Reference Figure 14 and Figure 15 In the display panel 110 according to another exemplary embodiment of the present disclosure, the protruding pattern DP protruding from the emission control line EML of the second metal layer ML2 may be formed by the third switching transistor TR3. For example, the third switching transistor TR3 may be provided between the first power line VDDL and the driving transistor DT.

[0120] The third switching transistor TR3 can be turned on or off in response to a light emission control signal applied via the light emission control line EML. When the third switching transistor TR3 is turned on in response to the light emission control signal, the first power supply voltage EVDD applied via the first power supply line VDDL can be transmitted to the drain node D of the drive transistor DR. For example, the third switching transistor TR3 can be provided in the first subpixel SP1 among the plurality of subpixels SP1 and SP2. When the third switching transistor TR3 is turned on, the first power supply voltage EVDD applied via the first power supply line VDDL can be transmitted to the drain node D of the drive transistor DR in each of the plurality of subpixels SP1 and SP2.

[0121] The light emitting control signal may be applied to the light emitting control line EML from the scan driver 120. The voltage V EML It may be the gate-on voltage during the first period t1 and the second period t2 of the first period t1 to the third period t3 of the operation of the sub-pixel SP, and may be the gate-off voltage during the third period t3. For example, the first period t1 may be an initialization period and a data programming period before the sub-pixel SP emits light, the second period t2 may be a light-emitting period during which the sub-pixel SP emits light, and the third period t3 may be a period during which the light emission of the sub-pixel SP stops during the light-emitting period.

[0122] A light-emitting display device according to one or more embodiments of the present disclosure is described below.

[0123] According to one or more embodiments of the present disclosure, a light-emitting display device may include: a substrate; a first metal layer on the substrate; a first insulating layer on the first metal layer; a semiconductor layer on the first insulating layer; a second insulating layer on the semiconductor layer; and a second metal layer on the second insulating layer, wherein at least one thin film transistor may include the semiconductor layer, the semiconductor layer being in contact with the first metal layer and not in contact with the second metal layer.

[0124] According to one or more embodiments of the present disclosure, the second metal layer may not contact the semiconductor layer and the first metal layer.

[0125] According to one or more embodiments of the present disclosure, the semiconductor layer may include an oxide semiconductor.

[0126] According to one or more embodiments of the present disclosure, at least one of the first metal layer and the second metal layer may include a low-reflective material layer.

[0127] According to one or more embodiments of the present disclosure, the semiconductor layer may be connected to the first metal layer through at least one contact hole passing through the first insulating layer.

[0128] According to one or more embodiments of the present disclosure, the semiconductor layer may include a first semiconductor region and a second semiconductor region, the first semiconductor region overlaps the second metal layer, and the second semiconductor region does not overlap the second metal layer.

[0129] According to one or more embodiments of the present disclosure, the first semiconductor region may overlap with the second metal layer, with the second insulating layer interposed between the first semiconductor region and the second metal layer.

[0130] According to one or more embodiments of the present disclosure, the first semiconductor region may include a channel region of the at least one thin film transistor.

[0131] According to one or more embodiments of the present disclosure, the second semiconductor region may be exposed from the second insulating layer and the second metal layer.

[0132] According to one or more embodiments of the present disclosure, the second semiconductor region may include a conductive region.

[0133] According to one or more embodiments of the present disclosure, the second semiconductor region may include a source / drain of the at least one thin film transistor.

[0134] According to one or more embodiments of the present disclosure, the at least one thin film transistor may include: a driving transistor, the driving transistor including the semiconductor layer and the first metal layer; and a first switching transistor and a second switching transistor, each of the first switching transistor and the second switching transistor including the semiconductor layer and the second metal layer.

[0135] According to one or more embodiments of the present disclosure, a source / drain of each of the driving transistor, the first switching transistor, and the second switching transistor may include a conductive region of the semiconductor layer.

[0136] According to one or more embodiments of the present disclosure, the gate of the driving transistor may include the first metal layer, and the gate of each of the first switching transistor and the second switching transistor may include the second metal layer.

[0137] According to one or more embodiments of the present disclosure, a gate of the driving transistor may overlap with the second metal layer, and a gate of each of the first switching transistor and the second switching transistor may not overlap with the first metal layer.

[0138] According to one or more embodiments of the present disclosure, the second metal layer overlapping the gate of the driving transistor may be electrically floating.

[0139] The second metal layer overlapping the gate of the driving transistor may have a voltage level lower than a voltage level of a source voltage of the driving transistor.

[0140] According to one or more embodiments of the present disclosure, the light-emitting display device may further include: a light-emitting element electrically connected to the driving transistor; and a storage capacitor including the first metal layer, the semiconductor layer and a pixel electrode of the light-emitting element.

[0141] According to one or more embodiments of the present disclosure, the light-emitting display device may further include a planarization layer, which covers the first insulating layer, the semiconductor layer, the second insulating layer and the second metal layer. The light-emitting element may be located on the planarization layer, and the pixel electrode of the light-emitting element may be connected to the semiconductor layer of the driving transistor through a contact hole passing through the planarization layer.

[0142] The pixel electrode of the light emitting element may be connected to a conductive region constituting a source electrode of the driving transistor and a second electrode of the storage capacitor through a contact hole penetrating the planarization layer.

[0143] According to one or more embodiments of the present disclosure, the first metal layer may include at least one power line and at least one signal line, and the at least one power line and the at least one signal line extend along a first direction on the substrate, and the second metal layer may include a first gate line and a second gate line, and the first gate line and the second gate line extend along a second direction intersecting the first direction on the substrate.

[0144] According to one or more embodiments of the present disclosure, the first gate line and the second gate line may be parallel to each other in the second direction, and the first gate line and the second gate line may be spaced apart from each other in the first direction.

[0145] According to one or more embodiments of the present disclosure, the first gate line may be applied with a scan signal controlling the first and second switching transistors, and the first gate line may include a gate of each of the first and second switching transistors.

[0146] According to one or more embodiments of the present disclosure, a driving voltage may be applied to the at least one power line, and a voltage different from the driving voltage may be applied to the second gate line.

[0147] The second gate line may be applied with a voltage lower than the driving voltage applied to the at least one power line.

[0148] According to one or more embodiments of the present disclosure, the second gate line may be electrically floating.

[0149] According to one or more embodiments of the present disclosure, the second gate line may further include a protruding pattern protruding in the first direction, and the at least one thin film transistor may further include a third switching transistor including the semiconductor layer and the protruding pattern.

[0150] According to one or more embodiments of the present disclosure, the second gate line may be applied with a light emitting signal that controls the third switching transistor, and the protruding pattern of the second gate line may include a gate of the third switching transistor.

[0151] The voltage of the light-emitting signal may be a gate-on voltage during the first and second time periods, and may be a gate-off voltage during the third time period, and the first time period may be an initialization period and a data programming period before the sub-pixel emits light, the second time period may be a light-emitting period during which the sub-pixel emits light, and the third time period may be a period during which the light emission of the sub-pixel stops during the light-emitting period.

[0152] According to one or more embodiments of the present disclosure, the substrate may include a plurality of sub-pixels, the plurality of sub-pixels including the light-emitting element, the driving transistor, the storage capacitor, the first switching transistor and the second switching transistor, and the third switching transistor may be located in at least one sub-pixel of the plurality of sub-pixels arranged along the second direction.

[0153] According to one or more embodiments of the present disclosure, a light-emitting display device may include: a substrate including a plurality of sub-pixels; a first metal layer on the substrate; a first insulating layer on the first metal layer; a semiconductor layer on the first insulating layer; a planarization layer covering the first insulating layer and the semiconductor layer; and a light-emitting element on the planarization layer, the semiconductor layer may be connected to the first metal layer via at least one contact hole passing through the first insulating layer, and the plurality of sub-pixels may include a driving transistor, and a pixel electrode of the light-emitting element may be connected to the semiconductor layer of the driving transistor via a contact hole passing through the planarization layer.

[0154] It is obvious to those skilled in the art that various modifications and variations can be made to the device of the present disclosure without departing from the scope of the present disclosure. Therefore, the present disclosure is intended to cover the modifications and variations of the present disclosure as long as they are within the scope of the claims and their equivalents.

[0155] CROSS-REFERENCE TO RELATED APPLICATIONS

[0156] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0030282 filed in Korea on February 29, 2024, which is hereby expressly incorporated by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A light-emitting display device, comprising: substrate; a first metal layer on the substrate; a first insulating layer on the first metal layer; a semiconductor layer on the first insulating layer; a second insulating layer on the semiconductor layer; as well as a second metal layer on the second insulating layer, Wherein, at least one thin film transistor includes the semiconductor layer, and the semiconductor layer is in contact with the first metal layer and not in contact with the second metal layer.

2. The light-emitting display device according to claim 1, wherein The second metal layer does not contact the semiconductor layer and the first metal layer.

3. The light-emitting display device according to claim 1, wherein The semiconductor layer includes an oxide semiconductor.

4. The light-emitting display device according to claim 1, wherein At least one of the first metal layer and the second metal layer includes a low-reflective material layer.

5. The light-emitting display device according to claim 1, wherein The semiconductor layer is connected to the first metal layer through at least one contact hole passing through the first insulating layer. The light-emitting display device according to claim 1 , wherein: The semiconductor layer includes a first semiconductor region and a second semiconductor region, the first semiconductor region overlaps the second metal layer, and the second semiconductor region does not overlap the second metal layer.

7. The light-emitting display device according to claim 6, wherein The first semiconductor region overlaps the second metal layer, and the second insulating layer is interposed between the first semiconductor region and the second metal layer.

8. The light-emitting display device according to claim 6, wherein The first semiconductor region includes a channel region of the at least one thin film transistor.

9. The light emitting display device according to claim 6, wherein: The second semiconductor region is exposed from the second insulating layer and the second metal layer.

10. The light emitting display device according to claim 6, wherein The second semiconductor region includes a conductive region.

11. The light-emitting display device according to claim 6, wherein The second semiconductor region includes a source / drain of the at least one thin film transistor.

12. The light-emitting display device according to claim 1, wherein The at least one thin film transistor comprises: a driving transistor comprising the semiconductor layer and the first metal layer; and A first switching transistor and a second switching transistor, each of the first switching transistor and the second switching transistor includes the semiconductor layer and the second metal layer.

13. The light-emitting display device according to claim 12, wherein A source / drain of each of the driving transistor, the first switching transistor, and the second switching transistor includes a conductive region of the semiconductor layer.

14. The light-emitting display device according to claim 12, in, The gate of the driving transistor includes the first metal layer, and The gate of each of the first switch transistor and the second switch transistor includes the second metal layer.

15. The light-emitting display device according to claim 14, in, The gate of the driving transistor overlaps the second metal layer, and A gate of each of the first switch transistor and the second switch transistor does not overlap with the first metal layer.

16. The light-emitting display device according to claim 15, wherein The second metal layer overlapping the gate of the driving transistor is electrically floating.

17. The light-emitting display device according to claim 15, wherein The second metal layer overlapping the gate of the driving transistor has a voltage level lower than a voltage level of a source voltage of the driving transistor.

18. The light-emitting display device according to claim 12, further comprising: a light emitting element electrically connected to the driving transistor; as well as A storage capacitor includes the first metal layer, the semiconductor layer, and a pixel electrode of the light emitting element.

19. The light-emitting display device according to claim 18, further comprising a planarization layer covering the first insulating layer, the semiconductor layer, the second insulating layer, and the second metal layer. in, The light emitting element is located on the planarization layer, and The pixel electrode of the light emitting element is connected to the semiconductor layer of the driving transistor through a contact hole passing through the planarization layer.

20. The light-emitting display device according to claim 19, wherein The pixel electrode of the light emitting element is connected to a conductive region constituting a source electrode of the driving transistor and a second electrode of the storage capacitor through a contact hole penetrating the planarization layer.

21. The light-emitting display device according to claim 19, in, The first metal layer includes at least one power line and at least one signal line, the at least one power line and the at least one signal line extending along a first direction on the substrate, and The second metal layer includes a first gate line and a second gate line, and the first gate line and the second gate line extend on the substrate along a second direction crossing the first direction.

22. The light-emitting display device according to claim 21, wherein The first gate line and the second gate line are parallel to each other in the second direction, and the first gate line and the second gate line are spaced apart from each other in the first direction.

23. The light-emitting display device according to claim 22, in, The first gate line is applied with a scan signal controlling the first and second switching transistors, and includes a gate of each of the first and second switching transistors.

24. The light-emitting display device according to claim 22, wherein A driving voltage is applied to the at least one power supply line, and a voltage different from the driving voltage is applied to the second gate line.

25. The light-emitting display device according to claim 24, wherein The second gate line is applied with a voltage lower than the driving voltage applied to the at least one power line.

26. The light-emitting display device according to claim 22, wherein The second gate line is electrically floating.

27. The light-emitting display device according to claim 22, in, The second gate line further includes a protrusion pattern protruding along the first direction, and The at least one thin film transistor further includes a third switch transistor, and the third switch transistor includes the semiconductor layer and the protruding pattern.

28. The light-emitting display device according to claim 27, in, The second gate line is applied with a light emitting signal for controlling the third switching transistor, and The protruding pattern of the second gate line includes a gate of the third switch transistor.

29. The light-emitting display device according to claim 28, in, The voltage of the light emitting signal is a gate-on voltage during the first and second periods, and is a gate-off voltage during the third period, and The first period is an initialization period and a data programming period before the sub-pixel emits light, the second period is a light-emitting period during which the sub-pixel emits light, and the third period is a period during which the light-emitting of the sub-pixel stops during the light-emitting period.

30. The light-emitting display device according to claim 27, in, The substrate includes a plurality of sub-pixels, the plurality of sub-pixels including the light emitting element, the driving transistor, the storage capacitor, the first switching transistor, and the second switching transistor, and The third switch transistor is located in at least one sub-pixel among the plurality of sub-pixels arranged along the second direction.

31. A light-emitting display device, comprising: a substrate comprising a plurality of sub-pixels; a first metal layer on the substrate; a first insulating layer on the first metal layer; a semiconductor layer on the first insulating layer; a planarization layer, the planarization layer covering the first insulating layer and the semiconductor layer; and The light emitting element on the planarization layer, wherein the semiconductor layer is connected to the first metal layer via at least one contact hole passing through the first insulating layer, and The plurality of sub-pixels include a driving transistor, and the pixel electrode of the light-emitting element is connected to the semiconductor layer of the driving transistor via a contact hole passing through the planarization layer.

Images