Display device

Abstract

Disclosed is a display device including: a first sub-pixel and a second sub-pixel disposed adjacent to each other; a first light emitting element disposed in the first sub-pixel; a second light emitting element disposed in the second sub-pixel; a first driving transistor configured to supply a driving current to the first light emitting element; a second driving transistor configured to supply a driving current to the second light emitting element and disposed to at least partially overlap the first light emitting element; and a first metal layer disposed between the second driving transistor and the first light emitting element.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] With the development of the information society, there is an increasing demand for various types of display devices for displaying images, such as liquid crystal display (LCD), plasma display panel (PDP), quantum dot light emitting display (QLED), and organic light emitting display (OLED).

[0003] The description provided in this Background section should not be assumed to qualify as prior art merely because it is mentioned in or related to the Background section.The Background section may include information that describes one or more aspects of the subject technology. Summary of the Invention

[0004] In related art, a display device includes multiple sub-pixels positioned between two facing substrates to display an image. A light-emitting element and a circuit element may be provided in each of the multiple sub-pixels. The light-emitting element and the circuit element may be provided on different layers and may overlap in some areas. Parasitic capacitance may occur in the light-emitting element and the circuit element in the overlapping area, making it difficult to achieve the desired brightness due to increases or decreases in the brightness of the sub-pixels.

[0005] In the present disclosure, if the area of ​​a sub-pixel is reduced to achieve high resolution or high transmittance, circuit elements may overlap with the light-emitting elements of adjacent sub-pixels. Therefore, the inventors of the present application recognized the above-mentioned limitations and other limitations associated with the related art and conducted various experiments to realize a display device capable of reducing parasitic capacitance generated between circuit elements and light-emitting elements of adjacent sub-pixels.

[0006] Another object of the present disclosure is to provide a display device capable of achieving ESG (Environmental / Social / Governance) by reducing greenhouse gases that may occur due to a manufacturing process.

[0007] To achieve these and other aspects of the inventive concept, as implemented and broadly described herein, a display device may include: a first sub-pixel and a second sub-pixel adjacent to each other; a first light-emitting element disposed in the first sub-pixel; a second light-emitting element disposed in the second sub-pixel; a first driving transistor configured to provide a driving current to the first light-emitting element; a second driving transistor configured to provide a driving current to the second light-emitting element and disposed to at least partially overlap with the first light-emitting element; and a first metal layer disposed between the second driving transistor and the first light-emitting element.

[0008] According to another aspect of the present disclosure, a display device is provided, which includes: a display area, which includes a transmission area and a non-transmission area; a first light-emitting element and a second light-emitting element arranged adjacent to each other in the non-transmission area; a first circuit element, which is arranged in the non-transmission area and is configured to drive the first light-emitting element; and a second circuit element, which is arranged in the non-transmission area and is configured to drive the second light-emitting element, wherein at least a portion of the second circuit element overlaps with the first light-emitting element.

[0009] Other systems, methods, features, and advantages will be or will become apparent to those skilled in the art upon review of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included herein, be within the scope of the present disclosure, and be protected by the appended claims. Nothing in this section should be construed as limiting these claims. Additional aspects and advantages are discussed below in conjunction with the embodiments of the present disclosure.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which may be included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this disclosure, illustrate embodiments of the disclosure and together with the description serve to explain various principles of the disclosure.

[0012] The above and other objects, features and other advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a perspective view schematically illustrating a display device according to an exemplary embodiment of the present disclosure;

[0014] Figure 2 is a plan view schematically illustrating a display panel according to an exemplary embodiment of the present disclosure;

[0015] Figure 3 Schematically shows Figure 2 An example embodiment of a pixel arranged in area A;

[0016] Figure 4 It shows Figure 3 A circuit diagram showing an example of circuit elements of a sub-pixel;

[0017] Figure 5 schematically illustrates an example in which a pixel circuit is provided in a circuit region;

[0018] Figure 6A schematically illustrates an example in which a first metal layer is provided in a circuit region;

[0019] Figure 6B schematically illustrates an example in which a second metal layer is provided in a circuit region;

[0020] Figure 7 It is shown along Figure 6A and Figure 6B A cross-sectional view of an example embodiment of II';

[0021] Figure 8 is a cross-sectional view illustrating parasitic capacitance generated between a pixel circuit and a light-emitting element of an adjacent sub-pixel when the first metal layer and the second metal layer are not provided;

[0022] Figure 9 is a circuit diagram illustrating parasitic capacitance generated between a pixel circuit and a light-emitting element of an adjacent sub-pixel when the first metal layer and the second metal layer are not provided;

[0023] Figure 10 is a circuit diagram illustrating parasitic capacitance generated between a pixel circuit and a light-emitting element of an adjacent sub-pixel when a first metal layer and / or a second metal layer are provided;

[0024] Figure 11 schematically illustrates another example in which a first metal layer is provided in a circuit region;

[0025] Figure 12 schematically illustrates an example in which a shielding layer is provided in a circuit region;

[0026] Figure 13 Schematically shows the arrangement Figure 2 Another example embodiment of pixels in region A;

[0027] Figure 14 Schematically shows the Figure 13 An example of providing a pixel circuit in a circuit area;

[0028] Figure 15 schematically illustrates an example in which the size of the transmission area is reduced according to the pixel circuit arrangement;

[0029] Figure 16A Schematically shows the Figure 13 An example of providing a first metal layer in a circuit area;

[0030] Figure 16B Schematically shows the Figure 13 An example of providing a second metal layer in the circuit area;

[0031] Figure 17 It is shown along Figure 16A and Figure 16B II-II' is a cross-sectional view of an example embodiment;

[0032] Figure 18 Schematically shows the Figure 13 Another example of providing a first metal layer in the circuit area;

[0033] Figure 19 is a graph showing a driving current increase rate according to a driving voltage of an adjacent sub-pixel when the first metal layer and / or the second metal layer are not provided; and

[0034] Figure 20 is a graph showing a driving current increase rate according to driving voltages of adjacent sub-pixels when the first metal layer and / or the second metal layer are provided.

[0035] Throughout the drawings and the detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative size and depiction of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0036] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be shown in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations associated with this document will be omitted when they are determined to unnecessarily obscure the gist of the inventive concept. The described progression of processing steps and / or operations are examples; however, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as is known in the art, except for steps and / or operations that must occur in a particular order. Similar reference numerals designate similar elements throughout. The names of the corresponding elements used in the following description may be selected solely for ease of writing the specification and may therefore differ from the names used in the actual product.

[0037] The advantages and features of the present disclosure and their implementation methods will become clear through the example embodiments described below with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure is thorough and complete and fully conveys the scope of the present disclosure to those skilled in the art.

[0038] The shapes, sizes, areas, proportions, angles and quantities disclosed in the drawings used to describe example embodiments of the present disclosure are examples only, and the present disclosure is not limited to the details shown. Like reference numerals refer to like elements throughout. In the following description, when it is determined that a detailed description of related known functions or configurations would unnecessarily obscure the focus of the present disclosure, the detailed description will be omitted or briefly provided. Where "including," "having," "comprising," and "consisting of" are used in this specification, another component may also be present unless "only" is used. Unless otherwise specified, terms in the singular may include plural forms. Any implementation described herein as an "example" is not necessarily to be construed as being preferred or advantageous over other implementations.

[0039] When interpreting an element, the element is interpreted as including an error range or a tolerance range although not explicitly described.

[0040] When describing a positional relationship, for example, when using "up," "above," "below," "over," "under," "down," "adjacent," "near," or "adjacent," "next to," or "next to," etc. to describe the positional relationship between two components, one or more other components may be arranged between the two components, unless more restrictive terms such as "immediately," "directly," or "closely" are used. For example, when a structure is described as being located "up," "above," "below," "above," "under," "below," "adjacent" to another structure, "near" to another structure, or "adjacent to" another structure, "next to," or "next to" another structure, this description should be interpreted as including the case where the structures are in contact with each other and the case where a third structure is arranged or interposed therebetween. In addition, the terms "left," "right," "top," "bottom," "down," "up," "up," "up," "down," etc. refer to an arbitrary reference system.

[0041] When describing temporal relationships, for example, when a temporal sequence is described as "after," "subsequently," "next," and "before," discontinuities may be included unless more restrictive terms such as "just," "immediately," or "directly" are used.

[0042] It will be understood that although the terms "first," "second," "A," "B," "(a)," "(b)," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure. In addition, when an element or layer is described as being "connected," "coupled," or "adhered" to another element or layer, the element or layer may not only be directly connected or adhered to the other element or layer, but may also be indirectly connected or adhered to the other element or layer with one or more intermediate elements or layers "disposed" between the elements or layers, unless otherwise specified.

[0043] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include two or more elements selected from the first element, the second element, and the third element, and all combinations of each element in the first element, the second element, and the third element.

[0044] The features of the various embodiments of the present invention may be coupled or combined in part or in whole, and may be coordinated and technically driven in various ways that will be fully understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of one another or together in a mutually dependent relationship.

[0045] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, for example, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein. For example, the term "component" or "unit" may apply, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as would be understood by one of ordinary skill in the art.

[0046] The transistor used in the display device according to the exemplary embodiment of the present disclosure can be implemented as any one of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor can be implemented as an oxide semiconductor transistor having an oxide semiconductor as an active layer, or a low-temperature polysilicon (LTPS) transistor having LTPS as an active layer. The transistor may include at least a gate electrode, a source electrode, and a drain electrode. The transistor can be implemented as a thin film transistor (TFT) on a display panel. The carriers in the transistor flow from the source electrode to the drain electrode. In the case of an n-channel transistor (NMOS), since the carriers are electrons, the source voltage can be lower than the drain voltage, so that electrons can flow from the source electrode to the drain electrode. In an n-channel transistor (NMOS), current can flow from the drain electrode to the source electrode, and the source electrode can be an output terminal. In the case of a p-channel transistor (PMOS), since the carriers are holes, the source voltage can be higher than the drain voltage, so that holes can flow from the source electrode to the drain electrode. Since holes flow from the source electrode to the drain electrode in a p-channel transistor (PMOS), current can flow from the source electrode to the drain electrode, and the drain electrode can be an output terminal. Therefore, it should be noted that since the source and drain can change according to the applied voltage, the source and drain of the transistor are not fixed. In the present disclosure, the description is made by assuming that the transistor is an n-channel transistor (NMOS), but the present disclosure is not limited to this, and a p-channel transistor can be used, and the resulting circuit configuration can also be changed.

[0047] Various exemplary embodiments of the display device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In the accompanying drawings, the same or similar elements are denoted by the same reference numerals even if they are shown in different drawings. In addition, in the following description, when it is determined that a detailed description of a related known technology unnecessarily obscures the key points of the present disclosure, the detailed description will be omitted.

[0048] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0049] Figure 1 is a perspective view schematically showing a display device according to an embodiment of the present disclosure, and Figure 2 is a plan view schematically illustrating a display panel according to an embodiment of the present disclosure.

[0050] Hereinafter, the X axis represents a direction parallel to the scan lines, the Y axis represents a direction parallel to the data lines, and the Z axis represents a height direction of the display device 100 .

[0051] Although the display device 100 according to the embodiment of the present disclosure has been described as an organic light-emitting display device, the present disclosure is not limited thereto, and the display device of the present application may also be implemented as a liquid crystal display device, a quantum dot light-emitting display device, a micro LED display device, or an electrophoretic display device.

[0052] Reference Figure 1 and Figure 2 , a display device 100 according to an embodiment of the present disclosure includes a display panel 110 , a source driver integrated circuit (hereinafter referred to as “IC”) 210 , a flexible film 220 , a circuit board 230 , and a timing controller 240 .

[0053] The display panel 110 includes a first substrate 111 and a second substrate 112 facing each other. The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film. The first substrate 111 and the second substrate 112 may be formed of a transparent material. For example, the first substrate 111 or the second substrate 112 may include glass, plastic, or a flexible polymer film. For example, the flexible polymer film may be made of any of the following: polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), which are merely examples and are not necessarily limited thereto.

[0054] The display panel 110 may be divided into a display area DA in which pixels are formed to display an image and a non-display area NDA adjacent to the display area DA and not displaying an image.

[0055] The display area DA may be provided with first and second signal lines SL1 and SL2 and pixels, and the non-display area NDA may be provided with a pad area PA (in which pads are provided) and at least one scan driver 205 .

[0056] The first signal line SL1 may extend along a first direction (e.g., the Y-axis direction) and may intersect the second signal line SL2 in the display area DA. The second signal line SL2 may extend along a second direction (e.g., the X-axis direction) in the display area DA. Pixels are provided in an area where the first signal line SL1 is provided or in an area where the first signal line SL1 and the second signal line SL2 intersect, and emit predetermined light to display an image. The first signal line SL1 may include a gate line, and the second signal line SL2 may include the signal lines DL, VDDL, VSSL, and REFL to be described below.

[0057] A plurality of pads may be provided in the pad area PA. Since the size of the first substrate 111 is larger than the size of the second substrate 112, a portion of the first substrate 111 may be exposed without being covered by the second substrate 112. Pads such as power pads and data pads may be provided on the portion of the first substrate 111 that is exposed without being covered by the second substrate 112.

[0058] The scan driver 205 is connected to the scan lines and is configured to provide scan signals thereto. The scan driver 205 can be formed as a gate driver (GIP) in the panel in a non-display area (NDA) located on one or both sides of the display area DA of the display panel 110. Alternatively, the scan driver 205 can be fabricated as a driver chip and mounted on a flexible film, and then attached to the non-display area (NDA) located on one or both sides of the display area DA of the display panel 110 using a tape automated bonding (TAB) method.

[0059] The source driver IC 210 receives digital video data and data control signals from the timing controller 240. The source driver IC 210 converts the digital video data into analog data voltages based on the data control signals and supplies the analog data voltages to the data lines. When the source driver IC 210 is manufactured as a driver chip, the source driver IC 210 can be mounted on the flexible film 220 using a chip-on-film (COF) or chip-on-plastic (COP) method.

[0060] Wiring for connecting the pads to the source driver IC 210 and wiring for connecting the pads to the circuit board 230 may be formed on the flexible film 220. The flexible film 220 may be attached to the pads using an anisotropic conductive film so that the pads and wiring of the flexible film 220 can be connected to each other.

[0061] The circuit board 230 may be attached to the flexible film 220. A plurality of circuits implemented as a driving chip may be mounted on the circuit board 230. For example, the timing controller 240 may be mounted on the circuit board 230. The circuit board 230 may be a printed circuit board or a flexible printed circuit board.

[0062] The timing controller 240 receives digital video data and timing signals from an external system board (not shown). Based on the timing signals, the timing controller 240 generates a scan control signal for controlling the operation timing of the scan driver and a data control signal for controlling the source driver IC 210. The timing controller 240 provides the scan control signal to the scan driver 205 and provides the data control signal to the source driver IC 210.

[0063] Figure 3 Schematically shows Figure 2 In an embodiment of providing pixels in area A, Figure 4 It shows Figure 3 An example circuit diagram of a sub-pixel circuit element is shown in FIG. Figure 5 An example in which a pixel circuit is provided in the circuit region is schematically shown.

[0064] The display panel 110 according to an embodiment of the present disclosure may include a display area DA and a non-display area NDA (see Figure 2 ). Pixels P exist in the display area DA to display images.

[0065] Reference Figures 3 to 5 Each pixel P includes a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may be arranged in a matrix to emit predetermined light to display an image. The plurality of sub-pixels SP1, SP2, and SP3 may include a plurality of row lines and a plurality of column lines, the plurality of row lines including the sub-pixels SP1, SP2, and SP3 arranged along a first direction (e.g., an X-axis direction), and the plurality of column lines including the sub-pixels SP1, SP2, and SP3 arranged along a second direction (e.g., a Y-axis direction).

[0066] Each of the sub-pixels SP1, SP2, and SP3 may be any one of a first sub-pixel SP1 emitting red light, a second sub-pixel SP2 emitting green light, and a third sub-pixel SP3 emitting blue light, but is not limited thereto. The unit pixel P may include at least two sub-pixels SP1, SP2, and SP3. For example, Figure 3 As shown, the unit pixel P may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. The unit pixel P may also include a fourth subpixel for emitting white light. In addition, the emission colors, arrangement order, and direction of the subpixels SP1, SP2, and SP3 may be variously changed.

[0067] Each of the plurality of sub-pixels SP1, SP2, and SP3 may include a light emitting element and a circuit element for emitting light. Figure 4As shown, each of the plurality of sub-pixels SP1, SP2, and SP3 may include a circuit element having a 3T (transistor) 1C (capacitor) structure, including a first switching transistor SWT, a second switching transistor SWT', a driving transistor DT, a capacitor Cst, and a light-emitting element ED, but is not limited thereto. Each of the sub-pixels SP1, SP2, and SP3 may further include a compensation circuit. In this case, various structures such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C may be provided, and may include more or fewer transistors and capacitors.

[0068] Each of the transistors DT, SWT, and SWT' in each of the sub-pixels SP1, SP2, and SP3 may include a gate electrode, a source electrode, and a drain electrode. Since the source electrode and the drain electrode are not fixed and can change according to the voltage applied to the gate electrode and the direction of the current, either the source electrode or the drain electrode may be referred to as a first electrode, while the other may be referred to as a second electrode. The transistors DT, SWT, and SWT' in each of the sub-pixels SP1, SP2, and SP3 may be formed of at least one of a polycrystalline silicon semiconductor, an amorphous silicon semiconductor, and an oxide semiconductor. The transistors DT, SWT, and SWT' may be P-type transistors or N-type transistors, or the P-type and N-type transistors may be used interchangeably.

[0069] The first switching transistor SWT can provide a data voltage Vdata provided from the data line DL to the driving transistor DT. Specifically, the first switching transistor SWT can charge the capacitor Cst with the data voltage Vdata provided from the data line DL. In this case, the gate electrode of the first switching transistor SWT can be connected to the scan line SCANL, and the first electrode of the first switching transistor SWT can be connected to the data line DL. In addition, the second electrode of the first switching transistor SWT can be connected to one end of the capacitor Cst, for example, the gate electrode of the driving transistor DT.

[0070] The first switching transistor SWT may be turned on in response to a scan signal Scan applied through the scan line SCANL When the first switching transistor SWT is turned on, a data voltage Vdata applied through the data line DL may be transmitted to one end of the capacitor Cst.

[0071] The second switching transistor SWT' can provide a reference voltage Vref provided from a reference line REFL to the driving transistor DT. Specifically, a gate electrode of the second switching transistor SWT' can be connected to the scan line SCANL, and a first electrode of the second switching transistor SWT' can be connected to the reference line REFL. In addition, a second electrode of the second switching transistor SWT' can be connected to a second electrode (e.g., a source electrode) of the driving transistor DT and the other end of the capacitor Cst.

[0072] The second switching transistor SWT' can be turned on in response to the scan signal Scan applied through the scan line SCANL. When the second switching transistor SWT' is turned on, the reference voltage Vref applied through the reference line REFL can be transmitted to the other end of the capacitor Cst. In addition, the reference voltage Vref can also be applied to the source electrode of the driving transistor DT.

[0073] The capacitor Cst can maintain the data voltage Vdata supplied to the driving transistor DT for one frame. Specifically, a first electrode of the capacitor Cst can be connected to the gate electrode of the driving transistor DT, while a second electrode of the capacitor Cst can be connected to the source electrode of the driving transistor DT. The capacitor Cst can be charged with a driving voltage Vgs corresponding to the data voltage Vdata transmitted through the first switching transistor SWT, and the capacitor Cst can supply the charged driving voltage Vgs to the driving transistor DT.

[0074] The driving transistor DT can generate a driving current Ids from a first power source EVDD provided from a pixel power source line VDDL, and can provide the driving current Ids to the anode electrode of the light-emitting element ED. Specifically, a gate electrode of the driving transistor DT can be connected to one end of the capacitor Cst, and a first electrode of the driving transistor DT can be connected to the pixel power source line VDDL. In addition, a second electrode (e.g., a source electrode) of the driving transistor DT can be connected to the anode electrode of the light-emitting element ED.

[0075] The driving transistor DT can be turned on according to the driving voltage Vgs charged in the capacitor Cst. When the driving transistor DT is turned on, the first power EVDD applied via the pixel power line VDDL can be transmitted to the anode electrode of the light-emitting element ED. The driving transistor DT can control the luminous intensity of the light-emitting element ED by controlling the driving current Ids according to the driving voltage Vgs charged in the capacitor Cst.

[0076] The light-emitting element ED may include an anode electrode connected to the drive transistor DT, a cathode electrode supplied with a second power supply EVSS from a common power supply line VSSL, and a light-emitting layer located between the anode electrode and the cathode electrode. The anode electrode may be an independent electrode for each light-emitting element, and the cathode electrode may be a common electrode shared by all light-emitting elements. When a drive current Ids is supplied from the drive transistor DT to the light-emitting element ED, electrons from the cathode electrode are injected into the light-emitting layer, and holes from the anode electrode are injected into the light-emitting layer. As a result, the light-emitting layer emits fluorescence or phosphorescence through recombination of the electrons and holes, generating light with a brightness proportional to the current value of the drive current.

[0077] The anode electrode of the light emitting element ED may be connected to the second electrode of the driving transistor DT, and the cathode electrode of the light emitting element ED may be connected to the common power line VSSL. The light emitting element ED may emit light in response to the driving current Ids generated by the driving transistor DT.

[0078] The plurality of sub-pixels SP1, SP2, and SP3 may include light-emitting areas EA1, EA2, and EA3 in which light-emitting elements ED are disposed to emit light. In order to increase the aperture ratio, the display panel 110 may be configured such that the circuit elements DT, SWT, SWT', and Cst and the plurality of signal lines DL, VDDL, VSSL, and REFL overlap with the light-emitting areas EA1, EA2, and EA3. Figure 3 As shown, the light emitting area may overlap with a signal line area SLA in which a plurality of signal lines DL, VDDL, VSSL, and REFL are disposed and a circuit area CA in which circuit elements DT, SWT, SWT', and Cst are disposed.

[0079] In this case, the plurality of signal lines DL, VDDL, VSSL, and REFL provided in the signal line area SLA may include signal lines extending along the second direction (e.g., the Y-axis direction). For example, the plurality of signal lines DL, VDDL, VSSL, and REFL may include at least one of a plurality of data lines DL, a reference line REFL, a pixel power line VDDL, and a common power line VSSL corresponding to the plurality of sub-pixels SP1, SP2, and SP3, respectively.

[0080] Each of the data lines DL may provide a data voltage to the sub-pixels SP1, SP2, and SP3. For example, the first data line DL may provide a first data voltage to the first driving transistor of the first sub-pixel SP1, the second data line DL may provide a second data voltage to the second driving transistor of the second sub-pixel SP2, and the third data line DL may provide a third data voltage to the third driving transistor of the third sub-pixel SP3.

[0081] The reference line REFL may provide an initialization voltage (or a reference voltage) to the driving transistor DT of each of the sub-pixels SP1 , SP2 , and SP3 provided in the display area DA.

[0082] The pixel power line VDDL may provide a first power source to the driving transistor DT of each of the sub-pixels SP1 , SP2 , and SP3 provided in the display area DA.

[0083] The common power line VSSL may supply the second power source to cathode electrodes of the sub-pixels SP1, SP2, and SP3 disposed in the display area DA. In this case, the second power source may be a common power source commonly supplied to the sub-pixels SP1, SP2, and SP3.

[0084] In each of the plurality of column lines including sub-pixels SP1 , SP2 , and SP3 arranged along the second direction (eg, the Y-axis direction), a plurality of signal lines DL, VDDL, VSSL, REFL may be provided to form a signal line area SLA.

[0085] The circuit area CA may not overlap with the signal line area SL and may be disposed on one side of the signal line area SLA. For example, in the display panel 110 according to an embodiment of the present disclosure, the circuit elements DT, SWT, SWT', and Cst may be gathered and disposed on one side of the signal line area SLA. The circuit area CA may be disposed in one edge area of ​​each of the sub-pixels SP1, SP2, and SP3.

[0086] Specifically, the circuit element CE may include a first switching transistor SWT, a second switching transistor SWT', a driving transistor DT, and a capacitor Cst, and may be provided for each of the sub-pixels SP1, SP2, and SP3. For example, the circuit element may include a first circuit element CE1 connected to the first sub-pixel SP1 to drive the first sub-pixel SP1, a second circuit element CE2 connected to the second sub-pixel SP2 to drive the second sub-pixel SP2, and a third circuit element CE3 connected to the third sub-pixel SP3 to drive the third sub-pixel SP3.

[0087] like Figure 3 and Figure 5As shown, the plurality of sub-pixels SP1, SP2, and SP3 may be arranged in a line along a second direction (e.g., the Y-axis direction). The circuit elements CE1, CE2, and CE3 of each of the plurality of sub-pixels SP1, SP2, and SP3 may be arranged along an edge region of each of the plurality of sub-pixels SP1, SP2, and SP3 in the second direction (e.g., the Y-axis direction). In this case, at least some of the circuit elements CE1, CE2, and CE3 may partially overlap with adjacent sub-pixels SP1, SP2, and SP3, rather than partially overlapping with the corresponding sub-pixels SP1, SP2, and SP3.

[0088] For example, Figure 5 As shown, the second subpixel SP2 may include a second circuit element CE2, which includes a second drive transistor DT2 and a second capacitor Cst2. The second drive transistor DT2 of the second subpixel SP2 may at least partially overlap with the adjacent first subpixel SP1. The second drive transistor DT2 of the second subpixel SP2 may at least partially overlap with the first light-emitting element of the adjacent first subpixel SP1. In addition, the second capacitor Cst2 of the second subpixel SP2 may at least partially overlap with the second light-emitting element of the corresponding second subpixel SP2.

[0089] In the display panel 110 according to an embodiment of the present disclosure, the signal line area SLA and the circuit area CA are arranged so as not to overlap each other, thereby minimizing or reducing the area in which the plurality of signal lines DL, VDDL, VSSL, and REFL, as well as the circuit elements CE1, CE2, and CE3, are formed. If the circuit elements CE1, CE2, and CE3 are arranged between each of the plurality of signal lines DL, VDDL, VSSL, and REFL corresponding to one column line, the circuit elements CE1, CE2, and CE3 may require space to ensure a minimum spacing distance from the plurality of signal lines DL, VDDL, VSSL, and REFL on the upper, lower, left, and right sides. Therefore, the area in which the plurality of signal lines DL, VDDL, VSSL, and REFL, as well as the circuit elements CE1, CE2, and CE3, are formed may be increased.

[0090] In the display panel 110 according to an embodiment of the present disclosure, the circuit elements CE1, CE2, and CE3 may be gathered and disposed on one side of the signal line area SLA corresponding to one column line, thereby minimizing or reducing the space used to separate the circuit elements CE1, CE2, and CE3 and the plurality of signal lines DL, VDDL, VSSL, and REFL.

[0091] In addition, in the display panel 110 according to an embodiment of the present disclosure, the circuit elements CE1, CE2, and CE3 corresponding to the plurality of sub-pixels SP1, SP2, and SP3 may be arranged along an edge region of each of the plurality of sub-pixels SP1, SP2, and SP3 in the second direction (e.g., the Y-axis direction). In this case, some of the circuit elements CE1, CE2, and CE3 may be arranged to overlap with the corresponding sub-pixels SP1, SP2, and SP3. On the other hand, some of the circuit elements CE1, CE2, and CE3 may not be arranged to overlap with the corresponding sub-pixels SP1, SP2, and SP3, but may extend to and overlap with adjacent sub-pixels SP1, SP2, and SP3.

[0092] As the resolution of the display panel 110 increases, the area of ​​each of the sub-pixels SP1, SP2, and SP3 decreases. However, each of the sub-pixels SP1, SP2, and SP3 may have a minimum area required to arrange the circuit elements CE1, CE2, and CE3 in one edge region. Therefore, there is a limit to reducing the area of ​​each of the sub-pixels SP1, SP2, and SP3, which can be represented by a resolution limit.

[0093] The display panel 110 according to an embodiment of the present disclosure can be arranged so that the circuit elements CE1, CE2, and CE3 can partially overlap with the area in which the sub-pixels SP1, SP2, and SP3 are arranged, rather than being arranged to be included in the area in which the sub-pixels SP1, SP2, and SP3 are arranged. The display panel 110 according to an embodiment of the present disclosure can efficiently arrange the circuit elements CE1, CE2, and CE3, thereby minimizing or reducing the circuit area CA. Therefore, the display panel 110 according to an embodiment of the present disclosure can improve the resolution while reducing the area of ​​each of the sub-pixels SP1, SP2, and SP3.

[0094] In the display panel 110 according to an embodiment of the present disclosure, some of the circuit elements CE1, CE2, and CE3 may not be disposed in the region in which the corresponding sub-pixels SP1, SP2, and SP3 are formed, and some of the circuit elements CE1, CE2, and CE3 may overlap with the region in which the sub-pixels SP1, SP2, and SP3 are formed. The first to third sub-pixels SP1, SP2, and SP3 may have different areas. Each of the first to third sub-pixels SP1, SP2, and SP3 may have a different lifetime depending on the material of the light-emitting layer that emits light. In this case, the light-emitting area of ​​each of the first to third sub-pixels SP1, SP2, and SP3 may be designed to be the same as or different from the light-emitting area of ​​another of the first to third sub-pixels SP1, SP2, and SP3, so that the first to third sub-pixels SP1, SP2, and SP3 have the same or substantially similar lifetimes.

[0095] At least one of the first to third sub-pixels SP1, SP2, and SP3 may have a relatively larger or smaller area than the other sub-pixels. If there is an empty space between the adjacent sub-pixels SP1, SP2, SP3, and SP4, the circuit elements CE1, CE2, and CE3 corresponding to the sub-pixels SP1, SP2, and SP3 having relatively smaller areas may be formed to at least partially overlap with the adjacent sub-pixels SP1, SP2, and SP3.

[0096] For example, Figure 5 As shown, the areas of the second subpixel SP2 and the third subpixel SP3 can be smaller than the area of ​​the first subpixel SP1. In this case, the first subpixel SP1 can be a blue subpixel, and the second subpixel SP2 and the third subpixel SP3 can be red and green subpixels, respectively. For example, the areas of the red and green subpixels are smaller than those of the blue subpixel. A portion of the second circuit element CE2 corresponding to the second subpixel SP2 overlaps with the second subpixel SP2. However, due to the smaller area of ​​the second subpixel SP2, another portion of the second circuit element CE2 can be arranged not to overlap with the second subpixel SP2 but to extend to the first subpixel SP1. For example, the second capacitor Cst2 of the second circuit element CE2 overlaps with the second subpixel SP2, but the second drive transistor DT2 of the second circuit element CE2 can overlap with the first subpixel SP1.

[0097] In this case, the second driving transistor DT2 of the second circuit element CE2 may overlap with the light-emitting element of the first subpixel SP1, and parasitic capacitance may occur between the light-emitting elements of the first subpixel SP1. In the second driving transistor DT2 of the second circuit element CE2, the gate voltage may increase due to the parasitic capacitance generated when the adjacent first subpixel SP1 is driven, thereby increasing the brightness of the light-emitting element of the second subpixel SP2 connected to the second driving transistor DT2. Grayscale defects may occur in the second subpixel SP2.

[0098] The display panel 110 according to an embodiment of the present disclosure can reduce parasitic capacitance by setting a metal layer between the light emitting elements of adjacent sub-pixels SP1, SP2 and SP3 and the circuit element CE when the circuit element CE overlaps the adjacent sub-pixels SP1, SP2 and SP3 instead of overlapping the corresponding sub-pixels SP1, SP2 and SP3.

[0099] Below, we will refer to Figures 6A to 10 A structure for reducing parasitic capacitance generated when the circuit element CE overlaps the adjacent sub-pixels SP1 , SP2 , and SP3 is described in more detail.

[0100] Figure 6A schematically shows an example in which a first metal layer is provided in a circuit region, Figure 6B schematically shows an example in which a second metal layer is provided in the circuit region, Figure 7 It is shown along Figure 6A and Figure 6B 1-1' is a cross-sectional view of an embodiment of the present invention, and Figure 8 is a cross-sectional view illustrating parasitic capacitance generated between a pixel circuit and a light emitting element of an adjacent sub-pixel when the first metal layer and the second metal layer are not provided. Figure 9 is a circuit diagram illustrating parasitic capacitance generated between a pixel circuit and a light-emitting element of an adjacent sub-pixel when the first metal layer and the second metal layer are not provided. Figure 10 is a circuit diagram illustrating parasitic capacitance generated between a pixel circuit and a light emitting element of an adjacent sub-pixel when a first metal layer and / or a second metal layer are provided.

[0101] exist Figures 6A to 10 For ease of description, a portion of the second circuit element CE2 connected to the second subpixel SP2 overlaps the first subpixel SP1, but is not limited thereto. The following description can apply to all cases where a portion of a pixel circuit connected to one subpixel overlaps another adjacent subpixel.

[0102] Reference Figure 5 、 Figure 6A 、 Figure 6B and Figure 7The second sub-pixel SP2 may include a second circuit element CE2 including a second driving transistor DT2 and a second capacitor Cst2. The second driving transistor DT2 of the second sub-pixel SP2 may at least partially overlap the first light emitting element ED1 of the adjacent first sub-pixel SP1.

[0103] Specifically, a light shielding layer LS may be provided on the first substrate 111. The light shielding layer LS may be provided in the region where the drive transistor DT is formed to block external light from being incident on the active layer ACT of the drive transistor DT. The light shielding layer LS may be provided in the region where the second drive transistor DT2 is formed to block external light from being incident on the active layer ACT. The light shielding layer LS may be formed as a single layer or multiple layers including any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0104] A buffer layer BF may be provided on the light shielding layer LS. The buffer layer BF may be provided to protect the driving transistor DT from impurities such as hydrogen and moisture penetrating through the first substrate 111. The buffer layer BF may have a single-layer structure or a multi-layer structure including an inorganic insulating material such as silicon oxide SiOx, silicon nitride SiNx, and aluminum oxide Al2O3.

[0105] The driving transistor DT may be disposed on the buffer layer BF. The driving transistor DT may include an active layer ACT disposed on the buffer layer BF, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0106] A gate insulating layer GI may be provided between the active layer ACT and the gate electrode GE. Figure 7 As shown, the gate insulating layer GI may be patterned only on a region where the gate electrode GE is disposed, but is not limited thereto. In another embodiment, the gate insulating layer GI may be formed to cover the active layer ACT.

[0107] An interlayer insulating layer ILD may be disposed between the gate electrode GE and the source / drain electrodes SE / DE, and the source electrode SE and the drain electrode DE of the second driving transistor DT2 may be connected to the source region and the drain region of the active layer ACT through first contact holes CH1 penetrating the interlayer insulating layer ILD, respectively.

[0108] In addition, one of the source electrode SE and the drain electrode DE of the drive transistor DT can be connected to the light shielding layer LS via a contact hole extending through the interlayer insulating layer ILD and the buffer layer BF. The light shielding layer LS can be electrically connected to one of the source electrode SE and the drain electrode DE of the second drive transistor DT2 and does not operate as a floating gate. When the light shielding layer LS is floating and not connected to other electrodes, the threshold voltage of the drive transistor DT may change due to the floating light shielding layer LS. The display panel 110 according to an embodiment of the present disclosure can electrically connect the light shielding layer LS to one of the source electrode SE and the drain electrode DE of the drive transistor DT, thereby minimizing or reducing changes in the threshold voltage of the drive transistor DT.

[0109] The active layer ACT may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. The gate electrode GE, the source electrode SE, and the drain electrode DE may be formed as a single layer or multiple layers including any one of molybdenum Mo, aluminum Al, chromium Cr, gold Au, titanium Ti, nickel Ni, neodymium Nd, copper Cu, or ITO, and alloys thereof.

[0110] The gate insulating layer GI and the interlayer insulating layer ILD may have a single-layer or multi-layer structure including an inorganic insulating material such as silicon oxide SiOx, silicon nitride SiNx, or aluminum oxide Al2O3.

[0111] A first insulating layer PAS1 may be provided on the driving transistor DT, and a second insulating layer PAS2 may be provided on the first insulating layer PAS1. The first and second insulating layers PAS1 and PAS2 may have a single-layer or multi-layer structure including an inorganic insulating material such as silicon oxide SiOx, silicon nitride SiNx, or aluminum oxide Al2O3.

[0112] A first metal layer M1 may be disposed between the first insulating layer PAS1 and the second insulating layer PAS2. In a plan view, the first metal layer M1 may be disposed on the drive transistor DT and may be disposed to cover the gate electrode GE of the drive transistor DT. The first metal layer M1 may be electrically connected to one of the source electrode SE and the drain electrode DE of the drive transistor DT. For example, the first metal layer M1 may be electrically connected to the source electrode SE of the drive transistor DT via a second contact hole CH2 that penetrates the first insulating layer PAS1.

[0113] A planarization layer PLN for planarizing a step difference caused by the driving transistor DT may be provided on the second insulating layer PAS2 and may be formed of an organic layer such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0114] A second metal layer M2 may be disposed between the second insulating layer PAS2 and the planarization layer PLN. In a plan view, the second metal layer M2 may be disposed on the first metal layer M1 and may be disposed to cover a portion of the first metal layer M1. The second metal layer M2 may be disposed to cover an area where the first metal layer M1 overlaps with the first sub-pixel SP1. The second metal layer M2 may be in a floating state with no layer electrically connected thereto.

[0115] The first metal layer M1 and the second metal layer M2 may be formed as a single layer or multiple layers including any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and indium tin oxide (ITO), or alloys thereof, but are not limited thereto. For example, the first metal layer M1 or the second metal layer M2 may be formed as an alloy of molybdenum (Mo) and titanium (Ti), or a stacked structure of an alloy of molybdenum (Mo) and titanium (Ti) and indium tin oxide (ITO).

[0116] The light emitting element ED including the first electrode 120 , the light emitting layer 130 , the second electrode 140 , and the bank BN may be disposed on the planarization layer PLN.

[0117] A first electrode 120 may be provided on the planarization layer PLN for each of the sub-pixels SP1, SP2, and SP3. The first electrode 120 may include one first electrode 121 provided in the first sub-pixel SP1 and another first electrode 122 provided in the second sub-pixel SP2. Although not shown in the figure, the first electrode 120 may include another first electrode provided in the third sub-pixel SP3. The first electrodes 121 and 122 provided for each of the sub-pixels SP1, SP2, and SP3 may be spaced apart from each other to be electrically insulated from each other.

[0118] The first electrode 120 may be electrically connected to the driving transistor DT. Figure 7 As shown, the first electrode 122 of the second subpixel SP2 can be connected to the first metal layer M1 through the third contact hole CH3 penetrating the planarization layer PLN and the second insulating layer PAS2. The first metal layer M1 can be connected to one of the source electrode SE and the drain electrode DE of the drive transistor DT through the second contact hole CH2 penetrating the first insulating layer PAS1. As a result, the first electrode 122 of the second subpixel SP2 can be electrically connected to one of the source electrode SE and the drain electrode DE of the drive transistor DT through the first metal layer M1.

[0119] The first electrode 120 may be formed of a metal material having a high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), a stacked structure of an Ag alloy and ITO (ITO / Ag alloy / ITO), a MoTi alloy, a stacked structure of a MoTi alloy and ITO (ITO / MoTi alloy / ITO), etc. The silver alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). The MoTi alloy may be an alloy of molybdenum (Mo) and titanium (Ti). The first electrode 120 may be an anode electrode of the light-emitting element ED.

[0120] The bank BN may be provided on the planarization layer PLN. Alternatively, the bank BN may be provided between the first electrodes 121 and 122. Furthermore, the bank BN may be formed to cover the edge of each of the first electrodes 121 and 122 and to expose a portion of each of the first electrodes 121 and 122. Thus, the bank BN may prevent current from concentrating at the ends of each of the first electrodes 121 and 122, thereby preventing or reducing degradation of luminous efficiency.

[0121] The bank BN may define the emission area EA of each of the sub-pixels SP1, SP2, and SP3. The emission area EA of each of the sub-pixels SP1, SP2, and SP3 may be a region where the first electrode 120, the light-emitting layer 130, and the second electrode 140 are sequentially stacked to allow holes from the first electrode 120 and electrons from the second electrode 140 to recombine with each other in the light-emitting layer 130 to emit light. In this case, since the region where the bank BN is formed does not emit light, the region where the bank BN is formed becomes the non-emission area NEA, and the region where the first electrode 120 is exposed may be the emission area EA.

[0122] The bank BN may be formed of an organic layer such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0123] The light-emitting layer 130 may be provided on the first electrode 120. The light-emitting layer 130 may include a hole transport layer, a light-emitting material layer, and an electron transport layer. In this case, when a voltage is applied to the first electrode 120 and the second electrode 140, holes and electrons move to the light-emitting layer through the hole transport layer and the electron transport layer, respectively, and recombine with each other in the light-emitting layer to emit light.

[0124] In an embodiment, the light emitting layer 130 may be a common layer commonly formed in the sub-pixels SP1, SP2, and SP3. In this case, the light emitting layer may be a white light emitting layer for emitting white light.

[0125] In another embodiment, the light emitting layer 130 may include a light emitting material layer formed for each of the sub-pixels SP1, SP2, and SP3. For example, a red light emitting layer for emitting red light may be formed in the first sub-pixel SP1, a green light emitting layer for emitting green light may be formed in the second sub-pixel SP2, and a blue light emitting layer for emitting blue light may be formed in the third sub-pixel SP3.

[0126] The second electrode 140 may be disposed on the light emitting layer 130. The second electrode 140 may be a common layer commonly formed in the sub-pixels SP1, SP2, and SP3, and configured to apply the same voltage.

[0127] The second electrode 140 can be formed of a transparent conductive material that can transmit light, such as indium tin oxide (ITO) and indium zinc oxide (IZO), or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 140 is formed of a semi-transmissive metal material, the microcavity can improve the luminous efficiency. The second electrode 140 can be the cathode electrode of the light-emitting element ED.

[0128] An encapsulation layer 150 may be provided on the light-emitting element ED. The encapsulation layer 150 may be formed on the second electrode 140 and may be configured to cover the second electrode 140. The encapsulation layer 150 prevents or reduces the penetration of oxygen or moisture into the light-emitting layer 130 and the second electrode 140. For example, the encapsulation layer 150 may include at least one inorganic layer and may also include at least one organic layer. For example, the encapsulation layer 150 may include a structure in which at least one organic layer is provided between inorganic layers.

[0129] A color filter CF may be provided on one surface of the second substrate 112 facing the first substrate 111. The color filter CF may be patterned for each of the sub-pixels SP1, SP2, and SP3.

[0130] Specifically, the color filter CF may include a first color filter CF1, a second color filter CF2, and a third color filter (not shown). The first color filter CF1 may be arranged to correspond to the emission area EA1 of the first sub-pixel SP1 and may be a red color filter that transmits red light. The second color filter CF2 may be arranged to correspond to the emission area EA2 of the second sub-pixel SP2 and may be a green color filter that transmits green light. The third color filter may be arranged to correspond to the emission area EA3 of the third sub-pixel SP3 and may be a blue color filter that transmits blue light.

[0131] A black matrix BM may be provided between the color filters CF. The black matrix BM may be provided between the sub-pixels SP1, SP2, and SP3 to prevent or reduce color mixing between the sub-pixels SP1, SP2, and SP3. Furthermore, the black matrix BM may prevent or reduce externally incident light from being reflected from a plurality of signal lines provided between the sub-pixels SP1, SP2, and SP3, such as scan lines, data lines, pixel power lines, common power lines, reference lines, and the like.

[0132] The black matrix BM may include a light-absorbing material, such as a black dye that absorbs all light within the visible wavelength range.

[0133] A filler 160 may be provided between the first substrate 111 on which the light-emitting elements ED are provided and the second substrate 112 on which the color filters CF and the black matrix BM are provided. In this case, the filler 160 may be formed of a thermosetting resin or a UV curable resin and may be formed of an organic material having adhesive properties. In an embodiment, the filler 160 may include a material that absorbs hydrogen.

[0134] In the display panel 110, if there is free space between adjacent sub-pixels SP1, SP2, and SP3, the circuit elements CE1, CE2, and CE3 corresponding to the sub-pixels SP1, SP2, and SP3 having relatively smaller areas may be formed to at least partially overlap with the adjacent sub-pixels SP1, SP2, and SP3. For example, in the display panel 110, the area of ​​the second sub-pixel SP2 may be smaller than the area of ​​the first sub-pixel SP1. In this case, the display panel 110 may be configured such that at least a portion of the circuit element CE2 of the second sub-pixel SP2 overlaps with the adjacent first sub-pixel SP1. Figure 8 As shown, the display panel 110 may be arranged so that the second driving transistor DT2 of the second subpixel SP2 overlaps the first light emitting element ED1 of the first subpixel SP1. In this case, parasitic capacitance may occur between the second driving transistor DT2 of the second subpixel SP2 and the first light emitting element ED1 of the first subpixel SP1.

[0135] Specifically, if Figure 8 and Figure 9 As shown, a first parasitic capacitance C_DTG may appear between the gate electrode GE of the second driving transistor DT2 and the anode electrode 121 of the first light-emitting element ED1. When the first light-emitting element ED1 is driven, the voltage of the gate electrode GE of the second driving transistor DT2 may increase due to the first parasitic capacitance C_DTG. As the voltage of the gate electrode GE of the second driving transistor DT2 increases, the driving voltage Vgs of the second capacitor Cst2 may increase. In addition, the driving current Ids provided to the anode electrode 122 of the second light-emitting element ED2 may increase.

[0136] In addition, if Figure 8 and Figure 9 As shown, a second parasitic capacitance C_DTS is generated between the source electrode SE (or drain electrode) of the second driving transistor DT2 and the anode electrode 121 of the first light-emitting element ED1. When driving the first light-emitting element ED1, the voltage of the source electrode SE (or drain electrode) of the second driving transistor DT2 may increase due to the second parasitic capacitance C_DTS. As the voltage of the source electrode SE (or drain electrode) of the second driving transistor DT2 increases, the driving voltage Vgs of the second capacitor Cst2 may decrease. In addition, the driving current Ids provided to the anode electrode 122 of the second light-emitting element ED2 may decrease.

[0137] As described above, when the second driving transistor DT2 of the second subpixel SP2 overlaps the first light-emitting element ED1 of the first subpixel SP1, during the driving period of the first light-emitting element ED1, the second driving transistor DT2 may change due to the first parasitic capacitance C_DTG and the second parasitic capacitance C_DTS, and the driving current Ids supplied to the anode electrode 122 of the second light-emitting element ED2 may be increased or decreased. Therefore, while the brightness increases or decreases, the second subpixel SP2 may not emit light with the desired brightness. For example, a grayscale defect may occur in the second subpixel SP2.

[0138] The display panel 110 according to an embodiment of the present disclosure may remove the first parasitic capacitance C_DTG that may occur between the gate electrode GE of the second driving transistor DT2 and the anode electrode 121 of the first light emitting element ED1 by using the first metal layer M1 .

[0139] Specifically, in the display panel 110 according to an embodiment of the present disclosure, the first metal layer M1 may be provided between the second driving transistor DT2 of the second sub-pixel SP2 and the first light-emitting element ED1 of the first sub-pixel SP1. The first metal layer M1 may be provided above at least one of the source electrode SE and the drain electrode DE of the second driving transistor DT2, and may be electrically connected to one of the source electrode SE and the drain electrode DE of the second driving transistor DT2. For example, Figure 7 As shown, the first metal layer M1 may be disposed above the source electrode SE of the second driving transistor DT2 and may be electrically connected to the source electrode SE of the second driving transistor DT2 through the second contact hole CH2. Figure 7 As shown, the first metal layer M1 may be formed on the source electrode SE of the second driving transistor DT2 and configured to cover the source electrode SE of the second driving transistor DT2. Figure 7Although not shown in FIG. 1 , the first metal layer M1 may be formed to cover not only the source electrode SE but also the drain electrode DE of the second driving transistor DT2 .

[0140] The first metal layer M1 may be provided in a region where the second drive transistor DT2 of the second subpixel SP2 overlaps the first light-emitting element ED1 of the first subpixel SP1. The first metal layer M1 may extend from the region where the second light-emitting element ED2 of the second subpixel SP2 overlaps the first light-emitting element ED1 of the first subpixel SP1 and may be electrically connected to the anode electrode 122 of the second light-emitting element ED2. The anode electrode 122 of the second light-emitting element ED2 may be electrically connected to the source electrode SE of the second drive transistor DT2 through the first metal layer M1.

[0141] In a plan view, the first metal layer M1 may be formed to cover the gate electrode GE of the second driving transistor DT2 in a region where the second driving transistor DT2 and the first light emitting element ED1 overlap each other. Figure 4 ), the gate electrode GE of the second drive transistor DT2 may be in a floating state. The floating gate electrode GE may be affected by peripheral signals. Therefore, when a voltage is applied to the anode electrode 121 of the first light-emitting element ED1 disposed above the gate electrode GE, the voltage may also be applied to the floating gate electrode GE via the first parasitic capacitance C_DTG generated between the anode electrode 121 of the first light-emitting element ED1 and the gate electrode GE of the second drive transistor DT2. Therefore, the brightness of the second light-emitting element ED2, which is affected by the voltage level of the gate electrode GE, may also increase. In this case, while a voltage is applied to the floating gate electrode GE, the second light-emitting element ED2, which is affected by the voltage level of the gate electrode GE, may have a brightness increase rate greater than the desired brightness.

[0142] In the display panel 110 according to the embodiment of the present disclosure, the first metal layer M1 may be provided between the gate electrode GE of the second driving transistor DT2 and the anode electrode 121 of the first light emitting element ED1, and the first metal layer M1 may be electrically connected to the source electrode SE or the drain electrode DE of the second driving transistor DT2. Figure 4), during the period of , the source electrode SE or the drain electrode DE of the second driving transistor DT2 may also be fixed to the driving voltage Vgs. The first metal layer M1 may be connected to the source electrode SE or the drain electrode DE of the second driving transistor DT2 to be fixed to the driving voltage Vgs. In the display panel 110 according to the embodiment of the present disclosure, since the first metal layer M1 to which the driving voltage Vgs is not in a floating state is applied is provided between the gate electrode GE of the second driving transistor DT2 and the anode electrode 121 of the first light emitting element ED1, the first parasitic capacitance C_DTG that may be generated between the anode electrode 121 of the first light emitting element ED1 and the gate electrode GE of the second driving transistor DT2 may be removed, as shown in FIG. Figure 10 shown.

[0143] Furthermore, since the first metal layer M1 is connected to the source electrode SE or drain electrode DE of the second drive transistor DT2, a second parasitic capacitance C_DTS may be generated between the anode electrode 121 of the first light-emitting element ED1 and the source electrode or drain electrode. However, since the first metal layer M1 is applied with the driving voltage Vgs, it is less affected by external signals than the gate electrode GE. Therefore, even when a voltage is applied to the anode electrode 121 of the first light-emitting element ED1, the driving voltage Vgs is also applied to the first metal layer M1, and thus the rate of voltage change in the first metal layer M1 can be reduced.

[0144] Furthermore, parasitic capacitance may also occur between the gate electrode GE of the second drive transistor DT2 and the first metal layer M1. However, because the first metal layer M1 and the gate electrode GE of the second drive transistor DT2 are applied with a signal or drive voltage Vgs for the same sub-pixel SP2, the voltage may not change when the gate electrode GE of the second drive transistor DT2 is in a floating state. Therefore, even when a voltage is applied to the anode electrode 121 of the first light-emitting element ED1, the voltage of the gate electrode GE of the second drive transistor DT2 may not change in the display panel 110 according to an embodiment of the present disclosure. Furthermore, the parasitic capacitance occurring between the gate electrode GE of the second drive transistor DT2 and the first metal layer M1 may be part of the second capacitor Cst2, which can reduce the formation area of ​​the second capacitor Cst2.

[0145] In addition, in the display panel 110 according to an embodiment of the present disclosure, the second metal layer M2 may be disposed between the first metal layer M1 and the first light-emitting element ED1 of the first sub-pixel SP1. The second metal layer M2 may be disposed in a region where the first metal layer M1 overlaps with the first light-emitting element ED1 of the first sub-pixel SP1. In a plan view, the second metal layer M2 may be disposed to cover the portion of the first metal layer M1 that overlaps with the first light-emitting element ED1. The second metal layer M2 may be in a floating state without any layer electrically connected thereto.

[0146] The display panel 110 according to an embodiment of the present disclosure may arrange the second metal layer M2 in a floating state between the first metal layer M1 and the anode electrode 121 of the first light-emitting element ED1. In this case, the second metal layer M2 may overlap with the first subpixel SP1 and may not overlap with the second subpixel SP2. In addition, the second metal layer M2 may be formed over an area smaller than the area where the second drive transistor DT2 is provided. The display panel 110 according to an embodiment of the present disclosure may reduce the second parasitic capacitance C DTS by using the second metal layer M2.

[0147] The second metal layer M2 in the floating state may not completely eliminate the parasitic capacitance between the first metal layer M1 and the anode electrode 121 of the first light emitting element ED1. Herein, since the first metal layer M1 is electrically connected to the source electrode SE or the drain electrode DE of the second driving transistor DT2, the parasitic capacitance may correspond to the second parasitic capacitance C_DTS.

[0148] However, since the scanning signal Scan (see Figure 4 ), the source electrode SE or drain electrode DE of the second drive transistor DT2 is also fixed to the drive voltage Vgs during the period of 100°C (100°C). Therefore, the first metal layer M1 can be less affected by peripheral signals than the gate electrode GE in a floating state. When a voltage is applied to the anode electrode 121 of the first light-emitting element ED1 disposed above the source electrode SE or drain electrode DE, the voltage of the source electrode SE or drain electrode DE of the second drive transistor DT2 connected to the first metal layer M1 may also increase due to the second parasitic capacitance C_DTS. However, since the source electrode SE or drain electrode DE of the second drive transistor DT2 is not in a floating state but is applied with the drive voltage Vgs, the rate of voltage change of the source electrode SE or drain electrode DE can be smaller than that of the gate electrode GE.

[0149] Furthermore, when a floating second metal layer M2 is provided between the first metal layer M1 and the anode electrode 121 of the first light-emitting element ED1, a third parasitic capacitance may be generated between the first metal layer M1 and the second metal layer M2, and a fourth parasitic capacitance may be generated between the second metal layer M2 and the anode electrode 121 of the first light-emitting element ED1. In this case, the third and fourth parasitic capacitances may be connected in series. The second parasitic capacitance C_DTS obtained by combining the third and fourth parasitic capacitances connected in series can be expressed as the reciprocal of the value obtained by adding the reciprocal of the third and fourth parasitic capacitances. The second parasitic capacitance C_DTS obtained by combining the third and fourth parasitic capacitances connected in series when the second metal layer M2 is present can be smaller than the second parasitic capacitance C_DTS generated between the first metal layer M1 and the anode electrode 121 of the first light-emitting element ED1 when the second metal layer M2 is absent. Therefore, the display panel 110 according to an embodiment of the present disclosure can reduce the second parasitic capacitance C_DTS by using the second metal layer M2.

[0150] Therefore, the display panel 110 according to the embodiment of the present disclosure can remove the first parasitic capacitance C_DTG and also reduce the second parasitic capacitance C_DTS, thereby overcoming the grayscale defect of the second subpixel SP2 caused by driving of the adjacent first subpixel SP1.

[0151] Figure 11 Another example in which a first metal layer is provided in a circuit region is schematically shown, and Figure 12 An example in which a shielding layer is provided in a circuit region is schematically shown.

[0152] The second circuit element CE2 corresponding to the second subpixel SP2 may include a second driving transistor DT2, a second capacitor Cst2, and at least one second switching transistor SWT2 and SWT2'. The second driving transistor DT2 of the second subpixel SP2 may at least partially overlap with the first light emitting element ED1 of the first subpixel SP1, and the second capacitor Cst2 and the at least one second switching transistor SWT2 and SWT2' of the second subpixel SP2 may at least partially overlap with the second light emitting element ED2 of the second subpixel SP2.

[0153] Reference Figure 11 and Figure 12 , the first metal layer M1 may extend from a region where the first light-emitting element ED1 of the first subpixel SP1 is disposed to a region where the second light-emitting element ED2 of the second subpixel SP2 is disposed. In this case, the first metal layer M1 may extend to a region where the second capacitor Cst2 of the second subpixel SP2 is formed.

[0154] The first metal layer M1 may be disposed so as to overlap the gate electrode GE of the second driving transistor DT2 in the region where the first light emitting element ED1 of the first sub-pixel SP1 is disposed. In this case, the first metal layer M1 may remove the first parasitic capacitance C_DTG between the gate electrode GE of the second driving transistor DT2 and the anode electrode 121 of the first light emitting element ED1.

[0155] In addition, the first metal layer M1 may be disposed in a region where the second light emitting element ED2 of the second sub-pixel SP2 is disposed to overlap with the second capacitor Cst2. In this case, the first metal layer M1 may be a capacitor electrode CstE3 constituting the second capacitor Cst2 in the region overlapping with the second capacitor Cst2.

[0156] The second capacitor Cst2 may include at least two capacitor electrodes. For example, the second capacitor Cst2 may include a first capacitor electrode CstE1, a second capacitor electrode CstE2, and a third capacitor electrode CstE3. The first capacitor electrode CstE1 may be formed on the same layer and made of the same material as the light shielding layer LS, and the second capacitor electrode CstE2 may be formed on the same layer and made of the same material as the gate electrode GE. The third capacitor electrode CstE3 may be formed on the same layer and made of the same material as the first metal layer M1. In this example, the first capacitor electrode CstE1 may be connected to the light shielding layer LS, the second capacitor electrode CstE2 may be connected to the gate electrode GE, and the third capacitor electrode CstE3 may be connected to the first metal layer M1.

[0157] In the display panel 110 according to an embodiment of the present disclosure, the third capacitor electrode CstE3 is formed by extending the first metal layer M1 to a region where the second light emitting element ED2 of the second subpixel SP2 is provided, thereby increasing the capacity of the second capacitor Cst2 within a limited space.

[0158] In addition, the display panel 110 according to the exemplary embodiment of the present disclosure can simultaneously form the first metal layer M1 and the third capacitor electrode CstE3 by a simple process to remove the first parasitic capacitor C_DTG. Therefore, the display panel 110 according to the embodiment of the present disclosure can achieve process optimization and reduce production energy consumption.

[0159] In addition, the first metal layer M1 may be disposed so as not to overlap at least the second switching transistors SWT2 and SWT2' in the region where the second light emitting element ED2 of the second sub-pixel SP2 is disposed. Figure 11 As shown, in a plan view, the first metal layer M1 may be spaced apart from the at least one second switching transistor SWT2 and SWT2 ′ by a predetermined distance S1 .

[0160] As described above, the first metal layer M1 may be electrically connected to the source electrode SE or the drain electrode DE of the second drive transistor DT2. Therefore, when the first metal layer M1 overlaps the second switching transistors SWT2 and SWT2', the second switching transistors SWT2 and SWT2' may be affected by a signal applied to the source electrode SE or the drain electrode DE of the second drive transistor DT2. This may cause abnormal characteristics of the second switching transistors SWT2 and SWT2'. When the second subpixel SP2 is driven in black, a black lift defect may occur, in which the brightness increases.

[0161] In the display panel 110 according to an embodiment of the present disclosure, the first metal layer M1 is spaced apart from the at least one second switching transistor SWT2 and SWT2′, thereby preventing or reducing the signal applied to the source electrode SE or the drain electrode DE of the second driving transistor DT2 from affecting the at least one second switching transistor SWT2 and SWT2′. Therefore, the display panel 110 according to an embodiment of the present disclosure can prevent or reduce the occurrence of black lift defects.

[0162] like Figure 12 As shown, the display panel 110 according to an embodiment of the present disclosure may further include a shielding layer SD disposed on at least one second switching transistor SWT2 and SWT2′, thereby completely preventing or reducing a signal applied to the source electrode SE or drain electrode DE of the second drive transistor DT2 from affecting the at least one second switching transistor SWT2 and SWT2′. The shielding layer SD may be disposed on the same layer as the source electrode SE or drain electrode DE of the second drive transistor DT2. The shielding layer SD may be connected to the source region or drain region of the active layer ACT of the at least one second switching transistor SWT2 and SWT2′ via a fourth contact hole CH4 extending through the interlayer insulating layer ILD.

[0163] Figure 13 Schematically shows the arrangement Figure 2 Another embodiment of the pixels in area A, and Figure 14 Schematically shows the Figure 13 An example of setting a pixel circuit in a circuit area. Figure 15 An example in which the size of the transmission area is reduced according to the pixel circuit arrangement is schematically shown.

[0164] Figure 13 and Figure 14 The display panel 110 is shown with Figures 3 to 12 The difference between the display panel 110 shown is that a transmissive area TA is provided. The following mainly describes the differences, and substantially the same contents may be omitted or briefly provided.

[0165] The display panel 110 according to another embodiment of the present disclosure may include a display area DA and a non-display area NDA (see Figure 2 ).like Figure 13 As shown, the display area DA may include a first area NTA in which a plurality of sub-pixels SP1, SP2, SP3, and SP4 are arranged, and a second area TA in which the plurality of sub-pixels SP1, SP2, SP3, and SP4 are not arranged. The first area NTA may be a non-transmissive area that does not transmit most of the light incident from the outside. The second area TA may be a transmissive area that transmits most of the light incident from the outside. For example, the transmissive area TA may be an area with a light transmittance greater than α%, and the non-transmissive area NTA may be an area with a light transmittance less than β%. Here, "α" may be a value greater than "β". The display panel 110 according to another embodiment of the present disclosure can view an object or background located on the rear surface (or back) of the display panel 110 through the transmissive area TA.

[0166] The non-transmission area NTA may include light-emitting areas EA1, EA2, EA3, and EA4, each of which includes a plurality of light-emitting pixels P for emitting light, and a non-light-emitting area disposed between each light-emitting area. Each pixel P may include at least two sub-pixels SP. For example, each pixel P may include a first sub-pixel SP1 that emits red light, a second sub-pixel SP2 that emits green light, and a third sub-pixel SP3 that emits blue light, but is not limited thereto. Each pixel P may also include a fourth sub-pixel SP4 that emits white light.

[0167] The non-transmission area NTA may include a signal line area SLA and a circuit area CA. A plurality of signal lines DL, VDDL, VSSL, and REFL are provided in the signal line area SLA (see FIG. Figure 4 ), circuit elements DT, SWT, SWT' and Cst are provided in the circuit area CA (see Figure 4 In this case, the plurality of signal lines provided in the signal line area SLA may include signal lines extending along the second direction (eg, the Y-axis direction).

[0168] In the display panel 110 according to another embodiment of the present disclosure, since the transmissive area TA is disposed within the display area DA, the area of ​​the non-transmissive area NTA including the light-emitting areas EA1, EA2, EA3, and EA4 is reduced. Since the display panel 110 according to another embodiment of the present disclosure needs to include multiple light-emitting elements, multiple signal lines, and multiple circuit elements within the narrow non-transmissive area NTA, the multiple light-emitting elements can be formed to overlap with the multiple signal lines and the multiple circuit elements. Therefore, the display panel 110 according to another embodiment of the present disclosure can be configured so that the signal line area SLA in which the multiple signal lines DL, VDDL, VSSL, and REFL are disposed and the circuit area CA in which the circuit elements DT, SWT, SWT', and Cst are disposed can overlap with the light-emitting areas EA1, EA2, EA3, and EA4.

[0169] Furthermore, the display panel 110 according to another embodiment of the present disclosure may arrange the signal line area SLA and the circuit area CA so as not to overlap. When the circuit elements CE1, CE2, and CE3 are disposed between the plurality of signal lines DL, VDDL, VSSL, and REFL, the circuit elements CE1, CE2, and CE3 may need to have space on the upper, lower, left, and right sides to ensure a minimum separation distance from the plurality of signal lines DL, VDDL, VSSL, and REFL. Consequently, the area in which the plurality of signal lines DL, VDDL, VSSL, and REFL, as well as the circuit elements CE1, CE2, and CE3, are formed can be increased.

[0170] In the display panel 110 according to another embodiment, the circuit elements CE1, CE2, and CE3 may be gathered and disposed on one side of the signal line area SLA, thereby minimizing or at least reducing the space for separating the circuit elements CE1, CE2, and CE3 and the plurality of signal lines DL, VDDL, VSSL, and REFL.

[0171] In the display panel 110 according to another embodiment of the present disclosure, the circuit elements CE1, CE2, and CE3 corresponding to the plurality of sub-pixels SP1, SP2, SP3, and SP4 may be arranged along an edge region of each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 along a second direction (e.g., the Y-axis direction). In the display panel 110 according to another embodiment of the present disclosure, a certain region of the circuit elements CE1, CE2, and CE3 may be arranged to overlap with the corresponding sub-pixels SP1, SP2, SP3, and SP4, while other regions of the circuit elements CE1, CE2, and CE3 may be arranged to overlap with adjacent sub-pixels SP1, SP2, SP3, and SP4.

[0172] For example, Figure 14As shown, a portion of the second circuit element CE2 corresponding to the second sub-pixel SP2 may overlap with the second sub-pixel SP2, but another portion of the second circuit element CE2 may not overlap with the second sub-pixel SP2 but may overlap with the adjacent first sub-pixel SP1. For example, the second capacitor Cst2 of the second circuit element CE2 overlaps with the second sub-pixel SP2, while the second driving transistor DT2 of the second circuit element CE2 may overlap with the first sub-pixel SP1.

[0173] Therefore, the display panel 110 according to another embodiment of the present disclosure can minimize or at least reduce the area of ​​the circuit area CA. Figure 15 As shown, the display panel 110 may be arranged so that all circuit elements CE1, CE2, and CE3 overlap with corresponding sub-pixels SP1, SP2, SP3, and SP4. The first circuit element CE1 for driving the first sub-pixel SP1 may include a first driving transistor DT1, a first capacitor Cst1, and at least one first switching transistor SWT1 and SWT1' (see FIG. Figure 4 The first circuit element CE1 includes a first driving transistor DT1, a first capacitor Cst1, and at least one first switching transistor SWT1 and SWT1' (see Figure 4 ) may be disposed in an edge region of the first sub-pixel SP1 and may overlap with the first light emitting element of the first sub-pixel SP1. In addition, the second circuit element CE2 for driving the second sub-pixel SP2 may include a second driving transistor DT2, a second capacitor Cst2, and at least one second switching transistor SWT2 and SWT2′ (see Figure 4 The second circuit element CE2 includes a second driving transistor DT2, a second capacitor Cst2, and at least one second switching transistor SWT2 and SWT2' (see Figure 4 ) may be disposed at one edge region of the second sub-pixel SP2 and may overlap with the second light emitting element of the second sub-pixel SP2.

[0174] In this case, the first and second sub-pixels SP1 and SP2 need to ensure a minimum area required for arranging the first and second circuit elements CE1 and CE2 on one side. Therefore, there is a limit to reducing the area of ​​each of the first and second sub-pixels SP1 and SP2.

[0175] The display panel 110 according to another embodiment of the present disclosure can reduce Figure 15The circuit area CA in the pixel arrangement shown can be increased, and the transmission area TA therein can be increased. In the display panel 110 according to another embodiment of the present disclosure, the circuit elements CE1, CE2, and CE3 can be arranged in the circuit area CA that ensures the minimum. In this case, some of the circuit elements CE1, CE2, and CE3 may not be arranged in the area in which the corresponding sub-pixels SP1, SP2, SP3, and SP4 are formed, and some of the circuit elements CE1, CE2, and CE3 may overlap with the area in which the sub-pixels SP1, SP2, SP3, and SP4 are formed.

[0176] Sub-pixels SP1, SP2, SP3, and SP4 may have different areas. Depending on the material of the light-emitting layer used to emit light, each of sub-pixels SP1, SP2, SP3, and SP4 may have a different lifespan. In this case, the light-emitting areas of sub-pixels SP1, SP2, SP3, and SP4 may be designed to be the same as or different from each other, so that sub-pixels SP1, SP2, SP3, and SP4 may have the same or substantially similar lifespans.

[0177] At least one of the sub-pixels SP1, SP2, SP3, and SP4 may have an area that is relatively larger or smaller than that of the other sub-pixels. The circuit elements CE1, CE2, and CE3 corresponding to the sub-pixels SP1, SP2, SP3, and SP4 having relatively smaller areas may be formed so that at least a portion thereof overlaps with the adjacent sub-pixels SP1, SP2, SP3, and SP4 when there is a vacant space in the adjacent sub-pixels SP1, SP2, SP3, and SP4.

[0178] For example, Figure 14 As shown, the area of ​​the second sub-pixel SP2 may be smaller than that of the first sub-pixel SP1. The portion of the second circuit element CE2 corresponding to the second sub-pixel SP2 may overlap with the second sub-pixel SP2, and another portion of the second circuit element CE2 may overlap with the adjacent first sub-pixel SP1. For example, the second capacitor Cst2 of the second circuit element CE2 may overlap with the second sub-pixel SP2, and the second driving transistor DT2 of the second circuit element CE2 may overlap with the first sub-pixel SP1.

[0179] The display panel 110 according to another embodiment of the present disclosure can reduce the size of the circuit area CA and increase the size of the transmission area TA. The display panel 110 according to another embodiment of the present disclosure can improve light transmittance.

[0180] Figure 16A Schematically shows the Figure 13 An example of setting a first metal layer in a circuit area, Figure 16B Schematically shows the Figure 13An example of providing a second metal layer in the circuit area, and Figure 17 It is shown along Figure 16A and Figure 16B sectional view of an embodiment of II-II'. Figure 18 Schematically shows the Figure 13 Another example of setting the first metal layer in the circuit area.

[0181] Figure 16A 、 Figure 16B and Figure 17 The display panel 110 is shown with Figures 3 to 12 The display panel 110 shown is different in that a transmissive area TA is provided therein. The main differences will be described below, and substantially the same contents may be omitted or briefly provided.

[0182] exist Figure 16A 、 Figure 16B and Figure 17 For ease of description, a portion of the second circuit element CE2 connected to the second subpixel SP2 overlaps with the first subpixel SP1, but is not limited thereto. The following description can apply to all cases where a portion of a pixel circuit connected to one subpixel overlaps with another adjacent subpixel.

[0183] Reference Figure 16A 、 Figure 16B and Figure 17 The second sub-pixel SP2 may include a second circuit element CE2 including a second driving transistor DT2 and a second capacitor Cst2. The second driving transistor DT2 of the second sub-pixel SP2 may at least partially overlap the first light emitting element ED1 of the adjacent first sub-pixel SP1.

[0184] A light shielding layer LS may be disposed on the first substrate 111. The light shielding layer LS may be disposed in a region where the driving transistor DT is formed in the non-transmission area NTA to block external light incident on the active layer ACT of the driving transistor DT.

[0185] A buffer layer BF may be provided on the light shielding layer LS. The buffer layer BF may protect the driving transistor DT from the influence of impurities such as hydrogen or moisture penetrating through the first substrate 111. Figure 17 As shown, the buffer layer BF may be provided in both the non-transmission area NTA and the transmission area TA, but is not limited thereto. In another embodiment, the buffer layer BF may be provided only in the non-transmission area NTA and may not be provided in the transmission area TA.

[0186] The driving transistor DT may be disposed on the buffer layer BF. The driving transistor DT may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE disposed on the buffer layer BF in the non-transmission area NTA.

[0187] A gate insulating layer GI may be disposed between the active layer ACT and the gate electrode GE, and an interlayer insulating layer ILD may be disposed between the gate electrode GE and the source electrode SE / drain electrode DE.

[0188] A first insulating layer PAS1 may be provided on the driving transistor DT, and a second insulating layer PAS2 may be provided on the first insulating layer PAS1. The first insulating layer PAS1 and the second insulating layer PAS2 may be provided in the non-transmission area NTA and may not be provided in at least a portion of the transmission area TA. For example, the first insulating layer PAS1 and the second insulating layer PAS2 may include an opening area that overlaps with at least a portion of the transmission area TA. The first insulating layer PAS1 and the second insulating layer PAS2 may cause light refraction while transmitting light, thereby reducing transparency. Therefore, the display panel 110 according to another embodiment of the present disclosure can increase transparency by removing portions of the first insulating layer PAS1 and the second insulating layer PAS2 from the transmission area TA.

[0189] A first metal layer M1 may be disposed between the first insulating layer PAS1 and the second insulating layer PAS2. The first metal layer M1 may be disposed on the driving transistor DT in the non-transmission area NTA. In a plan view, the first metal layer M1 may be disposed to cover the gate electrode GE of the driving transistor D. The first metal layer M1 may be electrically connected to one of the source electrode SE and the drain electrode DE of the driving transistor DT.

[0190] A planarization layer PLN may be provided on the second insulating layer PAS2 to flatten the step difference caused by the driving transistor DT. The planarization layer PLN may be provided in the non-transmission area NTA and may not be provided in at least a portion of the transmission area TA. For example, the planarization layer PLN may include an opening area that overlaps with at least a portion of the transmission area TA. The planarization layer PLN may cause light refraction while transmitting light, thereby reducing transparency. Therefore, the display panel 110 according to another embodiment of the present disclosure can increase transparency by removing a portion of the planarization layer PLN in the transmission area TA.

[0191] A second metal layer M2 may be disposed between the second insulating layer PAS2 and the planarization layer PLN. The second metal layer M2 may be disposed on the first metal layer M1 in the non-transmission area NTA. In a plan view, the second metal layer M2 may be disposed to cover a portion of the first metal layer M1. The second metal layer M2 may be disposed to cover an area where the first metal layer M1 overlaps with the first sub-pixel SP1. The second metal layer M2 may be in a floating state with no layer electrically connected thereto.

[0192] A light emitting element ED including a first electrode 120 , a light emitting layer 130 , a second electrode 140 , and a bank BN may be disposed on the planarization layer PLN.

[0193] The first electrode 120 may be disposed on the planarization layer PLN in the non-transmission area NTA and may be disposed for each of the sub-pixels SP1, SP2, and SP3. The first electrode 120 may be electrically connected to one of the source electrode SE and the drain electrode DE of the driving transistor DT through the first metal layer M1. The first electrode 120 may be an anode electrode of the light-emitting element ED.

[0194] The bank BN may be disposed on the planarization layer PLN in the non-transmission area NTA. The bank BN may be formed to cover an edge of each of the first electrodes 120 and expose a portion of each of the first electrodes 120.

[0195] The bank BN may be provided in the non-transmission area NTA and may not be provided in at least a portion of the transmission area TA. For example, the bank BN may include an open area that overlaps at least a portion of the transmission area TA. The bank BN may cause light to refract while transmitting therethrough, thereby reducing transparency. Therefore, the display panel 110 according to another embodiment of the present disclosure may increase transparency by removing a portion of the bank BN from the transmission area TA.

[0196] The light emitting layer 130 may be provided on the first electrode 120. The light emitting layer 130 may include a hole transport layer, a light emitting material layer, and an electron transport layer.

[0197] In an embodiment, the light-emitting layer 130 may be a common layer commonly formed in the sub-pixels SP1, SP2, SP3, and SP4. In this case, the light-emitting layer 130 may be a white light-emitting layer that emits white light. In this case, the light-emitting layer 130 may be formed in the non-light-emitting area NEA between the sub-pixels SP1, SP2, SP3, and SP4, as well as in the sub-pixels SP1, SP2, SP3, and SP4. The light-emitting layer 130 may be formed in the sub-pixels SP1, SP2, SP3, and SP4, and may be formed continuously between the sub-pixels SP1, SP2, SP3, and SP4. Furthermore, the light-emitting layer 130 may be provided not only in the non-transmission area NTA including the light-emitting areas EA1, EA2, EA3, and EA4 and the non-light-emitting area NEA, but may also be provided in the transmissive area TA, but is not limited thereto. The light-emitting layer 130 may be patterned so as to be present only in the non-transmission area NTA including the light-emitting areas EA1, EA2, EA3, and EA4 and the non-light-emitting area NEA.

[0198] In another embodiment, the light-emitting layer 130 may be provided by forming a light-emitting material layer for each of the sub-pixels SP1, SP2, SP3, and SP4. For example, a red light-emitting layer for emitting red light may be formed in the first sub-pixel SP1, a green light-emitting layer for emitting green light may be formed in the second sub-pixel SP2, and a blue light-emitting layer for emitting blue light may be formed in the third sub-pixel SP3. In this case, the light-emitting material layer of the light-emitting layer 130 may not be formed in the transmission area TA. However, in addition to the light-emitting material layer, the hole injection layer HIL, the hole transport layer HTL, the electron transport layer ETL, and the electron injection layer EIL may be commonly formed in the sub-pixels SP1, SP2, SP3, and SP4, and may also be formed in the transmission area TA.

[0199] The second electrode 140 may be provided on the light-emitting layer 130. The second electrode 140 may be a common layer commonly formed in the sub-pixels SP1, SP2, SP3, and SP4. The second electrode 140 may be formed in the non-emission area NEA between the sub-pixels SP1, SP2, SP3, and SP4 and in the light-emitting areas EA1, EA2, EA3, and EA4 of the sub-pixels SP1, SP2, SP3, and SP4. The second electrode 140 may be formed in the sub-pixels SP1, SP2, SP3, and SP4 and may be continuously formed between the sub-pixels SP1, SP2, SP3, and SP4.

[0200] In addition, the second electrode 140 may be provided not only in the non-transmission area NTA including the emission areas EA1, EA2, EA3, and EA4 and the non-emission area NEA, but also in the transmission area TA, but is not limited thereto. The second electrode 140 may be patterned only in the non-transmission area NTA including the emission areas EA1, EA2, EA3, and EA4 and the non-emission area NEA.

[0201] An encapsulation layer 150 may be disposed on the light emitting element ED. The encapsulation layer 150 may be formed on the second electrode 140 and may be configured to cover the second electrode 140.

[0202] A color filter CF may be provided on one surface of the second substrate 112 facing the first substrate 111. The color filter CF may be patterned for each of the sub-pixels SP1, SP2, SP3, and SP4.

[0203] A black matrix BM may be provided between the color filters CF provided in each of the sub-pixels SP1, SP2, SP3, and SP4. The black matrix BM may be provided between the sub-pixels SP1, SP2, SP3, and SP4 to prevent or reduce color mixing between adjacent sub-pixels SP1, SP2, SP3, and SP4. In addition, the black matrix BM may prevent or reduce reflection of externally incident light onto the plurality of signal lines provided between the sub-pixels SP1, SP2, SP3, and SP4.

[0204] In addition, the black matrix BM may be disposed between the transmission area TA and the plurality of sub-pixels SP1, SP2, SP3, and SP4, and may prevent or reduce light emitted from each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 from propagating to the transmission area TA. Therefore, the black matrix BM may define a boundary between the transmission area TA and the non-transmission area NTA. Specifically, the black matrix BM may define a boundary between the non-transmission area NTA and the transmission area TA in the region between the emission area EA and the transmission area TA. In regions other than the emission area EA, the region in which the black matrix BM is formed may be the non-transmission region NT, while the region in which the black matrix BM is not formed may be the transmission area TA. For example, the region in which the emission area EA and the black matrix BM are formed may be the non-transmission region NTA, while the remaining region may be the transmission area TA.

[0205] A filler 160 may be provided between the first substrate 111 provided with the light emitting element ED and the second substrate 112 provided with the color filter CF and the black matrix BM.

[0206] Press and Figures 3 to 12In the same manner as the display panel 110 shown in FIG. 1 , the display panel 110 according to another embodiment of the present disclosure can remove the first parasitic capacitance C_DTG that may occur between the gate electrode GE of the second driving transistor DT2 and the anode electrode 121 of the first light emitting element ED1 by using the first metal layer M1 .

[0207] Specifically, in the display panel 110 according to another embodiment of the present disclosure, the first metal layer M1 may be provided between the second driving transistor DT2 of the second sub-pixel SP2 and the first light-emitting element ED1 of the first sub-pixel SP1. The first metal layer M1 may be provided above at least one of the source electrode SE and the drain electrode DE of the second driving transistor DT2, and may be electrically connected to one of the source electrode SE and the drain electrode DE of the second driving transistor DT2. For example, Figure 17 As shown, the first metal layer M1 may be disposed over the source electrode SE of the second driving transistor DT2 and may be electrically connected to the source electrode SE of the second driving transistor DT2 through the second contact hole CH2 .

[0208] The first metal layer M1 may be disposed in a region where the second drive transistor DT2 of the second subpixel SP2 overlaps with the first light-emitting element ED1 of the first subpixel SP1. The first metal layer M1 may extend from the region overlapping with the first light-emitting element ED1 of the first subpixel SP1 to a region where the second light-emitting element ED2 of the second subpixel SP2 is disposed, and may be electrically connected to the anode electrode 122 of the second light-emitting element ED2. The anode electrode 122 of the second light-emitting element ED2 may be electrically connected to the source electrode SE of the second drive transistor DT2 through the first metal layer M1. In this case, the first metal layer M1 may be referred to as an intermediate electrode, which is used to connect the source electrode SE of the second drive transistor DT2 and the anode electrode 122 of the second light-emitting element ED2, thereby reducing the contact resistance therebetween.

[0209] In a plan view, the first metal layer M1 may be formed to cover the gate electrode GE of the second driving transistor DT2 in a region where the second driving transistor DT2 and the first light emitting element ED1 overlap each other.

[0210] In the display panel 110 according to another embodiment of the present disclosure, the first metal layer M1 may be provided between the gate electrode GE of the second drive transistor DT2 and the anode electrode 121 of the first light-emitting element ED1. The first metal layer M1 may be electrically connected to the source electrode SE or the drain electrode DE of the second drive transistor DT2, thereby removing the first parasitic capacitance C_DTG. Therefore, even if a voltage is applied to the anode electrode 121 of the first light-emitting element ED1, the voltage of the gate electrode GE of the second drive transistor DT2 in the display panel 110 according to another embodiment of the present disclosure does not change.

[0211] Press and Figures 3 to 12 In a similar manner to the display panel 110 shown in FIG. 1 , a display panel 110 according to another embodiment of the present disclosure may include a second metal layer M2 disposed between the first metal layer M1 and the first light-emitting element ED1 of the first sub-pixel SP1. The second metal layer M2 may be disposed in a region where the first metal layer M1 overlaps with the first light-emitting element ED1 of the first sub-pixel SP1. In a plan view, the second metal layer M2 may be disposed to cover the portion of the first metal layer M1 that overlaps with the first light-emitting element ED1. The second metal layer M2 may be in a floating state with no layer electrically connected thereto.

[0212] The display panel 110 according to another embodiment of the present disclosure may arrange the second metal layer M2 in a floating state between the first metal layer M1 and the anode electrode 121 of the first light-emitting element ED1. In this case, the second metal layer M2 may overlap with the second sub-pixel SP2 and may not overlap with the first sub-pixel SP1. In addition, the second metal layer M2 may be formed over an area smaller than the area where the second drive transistor DT2 is provided. The display panel 110 according to another embodiment of the present disclosure may reduce the second parasitic capacitance C_DTS by using the second metal layer M2.

[0213] Since even when the scan signal Scan is not applied (see Figure 4 During the period of 100°C (100°C), the source electrode SE or drain electrode DE of the second drive transistor DT2 is also fixed to the drive voltage Vgs. Therefore, the first metal layer M1 can be less affected by peripheral signals than the gate electrode GE in a floating state. When a voltage is applied to the anode electrode 121 of the first light-emitting element ED1 disposed on the source electrode SE or drain electrode DE, the voltage of the source electrode SE or drain electrode DE of the second drive transistor DT2 connected to the first metal layer M1 may also increase due to the second parasitic capacitance C_DTS. However, since the source electrode SE or drain electrode DE of the second drive transistor DT2 is not in a floating state but is applied with the drive voltage Vgs, the voltage change rate of the source electrode SE or drain electrode DE can be smaller than that of the gate electrode GE. In the display panel 110 according to another embodiment of the present disclosure, even when a voltage is applied to the anode electrode 121 of the first light-emitting element ED1, the voltage change of the source electrode SE of the second drive transistor DT2 can be minimized or at least reduced.

[0214] Furthermore, when a floating second metal layer M2 is provided between the first metal layer M1 and the anode electrode 121 of the first light-emitting element ED1, a third parasitic capacitance may be generated between the first metal layer M1 and the second metal layer M2, and a fourth parasitic capacitance may be generated between the second metal layer M2 and the anode electrode 121 of the first light-emitting element ED1. In this case, the third and fourth parasitic capacitances may be connected in series. The second parasitic capacitance C_DTS obtained by combining the third and fourth parasitic capacitances connected in series can be expressed as the reciprocal of the value obtained by adding the reciprocal of the third and fourth parasitic capacitances. The second parasitic capacitance C_DTS obtained by combining the third and fourth parasitic capacitances connected in series when the second metal layer M2 is present can be smaller than the second parasitic capacitance C_DTS generated between the first metal layer M1 and the anode electrode 121 of the first light-emitting element ED1 when the second metal layer M2 is absent. Therefore, the display panel 110 according to another embodiment of the present disclosure can reduce the second parasitic capacitance C_DTS by using the second metal layer M2.

[0215] The display panel 110 according to another embodiment of the present disclosure can prevent or reduce the brightness of the second subpixel SP2 from increasing due to driving of the adjacent first subpixel SP1. The display panel 110 according to another embodiment of the present disclosure can improve the grayscale defect of the second subpixel SP2.

[0216] Figures 3 to 17 It is shown that one sub-pixel SP1 , SP2 , SP3 or SP4 includes one emission area EA1 , EA2 , EA3 or EA4 , but the present disclosure is not limited thereto.

[0217] like Figure 18 As shown, each of the sub-pixels SP1, SP2, SP3, and SP4 may include a plurality of divided light-emitting areas EA1, EA2, EA3, and EA4. For example, the first light-emitting area EA1 included in the first sub-pixel SP1 may include a first divided light-emitting area EA11 and a second divided light-emitting area EA12 divided into two. The second light-emitting area EA2 included in the second sub-pixel SP2 may include a first divided light-emitting area EA21 and a second divided light-emitting area EA22 divided into two. The third light-emitting area EA3 included in the third sub-pixel SP3 may include a first divided light-emitting area EA31 and a second divided light-emitting area EA32 divided into two. The fourth light-emitting area EA4 included in the fourth sub-pixel SP4 may include a first divided light-emitting area EA41 and a second divided light-emitting area EA42 divided into two.

[0218] In this case, a plurality of first electrodes 120 may be provided in each of the plurality of sub-pixels SP1, SP2, SP3, and SP4. The first electrodes 120 may include a first anode electrode and a second anode electrode. The first anode electrode may be provided in the first divided light-emitting areas EA11, EA21, EA31, and EA41, and the second anode electrode may be provided in the second divided light-emitting areas EA12, EA22, EA32, and EA42. The first anode electrode and the second anode electrode may be spaced apart from each other in the same layer.

[0219] The first anode electrode and the second anode electrode can be electrically connected to each other through an anode connecting electrode. One end of the anode connecting electrode can be electrically connected to the first anode electrode, and the other end of the anode connecting electrode can be electrically connected to the second anode electrode, thereby electrically connecting the first anode electrode and the second anode electrode.

[0220] For example, the first electrode 121 provided in the first subpixel SP1 may include a first anode electrode 1211 provided in the first divided light-emitting area EA11, a second anode electrode 1212 provided in the second divided light-emitting area EA12, and an anode connection electrode ACE1 electrically connecting the first anode electrode 1211 and the second anode electrode 1212. One end of the anode connection electrode ACE1 may be electrically connected to the first anode electrode 1211, and the other end of the anode connection electrode ACE1 may be electrically connected to the second anode electrode 1212, thereby electrically connecting the first anode electrode 1211 and the second anode electrode 1212 provided in the first subpixel SP1.

[0221] The first electrode 122 provided in the second subpixel SP2 may include a first anode electrode 1221 provided in the first divided light emitting area EA21 , a second anode electrode 1222 provided in the second divided light emitting area EA22 , and an anode connection electrode ACE2 electrically connecting the first anode electrode 1221 and the second anode electrode 1222 .

[0222] Anode connection electrodes ACE1 and ACE2 provided in the corresponding first and second subpixels SP1 and SP2 may be provided on the same layer as the first metal layer M1 and may be connected to the first metal layer M1. The anode connection electrode ACE1 provided in the first subpixel SP1 may be connected to the first metal layer M1 connected to the first drive transistor DT1, and the anode connection electrode ACE2 provided in the second subpixel SP2 may be connected to the first metal layer M1 connected to the second drive transistor DT2.

[0223] Reference Figure 14 、 Figure 16A 、 Figure 17 and Figure 18The first metal layer M1 connected to the source electrode SE of the second drive transistor DT2 may extend from the region where the second drive transistor DT2 overlaps with the first light-emitting element ED1 of the first subpixel SP1 to the region where the second light-emitting element ED2 of the second subpixel SP2 is disposed. The first metal layer M1 may extend to one side of the anode connection electrode ACE2 of the second subpixel SP2 and may be connected to the anode connection electrode ACE2 of the second subpixel SP2. The first metal layer M1 may be electrically connected to the first anode electrode 1221 and the second anode electrode 1222 of the second subpixel SP2 via the anode connection electrode ACE2.

[0224] Note that, although the description of the case where the driving transistor of one sub-pixel overlaps the light-emitting element of another adjacent sub-pixel is made with reference to Figures 5 to 18 For example, such parasitic capacitance may also occur when another element of a sub-pixel (such as a capacitor or a switching transistor) overlaps with the light-emitting element of another adjacent sub-pixel (which may also cause an undesirable increase or decrease in the brightness of the sub-pixel). Therefore, when another element of a sub-pixel (such as a capacitor or a switching transistor) overlaps with the light-emitting element of another adjacent sub-pixel, it may also overlap with the light-emitting element of the adjacent sub-pixel. Figures 5 to 18 The embodiment of the present invention similarly sets the first metal layer or the second metal layer to remove or reduce such parasitic capacitance.

[0225] Figure 19 is a graph showing a driving current increase rate according to a driving voltage of an adjacent sub-pixel when the first metal layer and the second metal layer are not provided, and Figure 20 is a graph showing a driving current increase rate according to driving voltages of adjacent sub-pixels when a first metal layer and a second metal layer are provided.

[0226] The display panel 110 may be arranged so that the driving transistor of a particular sub-pixel overlaps the light emitting element of an adjacent sub-pixel. In this case, parasitic capacitance may occur between the driving transistor of the particular sub-pixel and the light emitting element (specifically, anode electrode) of the adjacent sub-pixel.

[0227] A first parasitic capacitor may appear between the gate electrode of the driving transistor of a particular sub-pixel and the anode electrode of an adjacent sub-pixel. In addition, a second parasitic capacitor may appear between the source electrode of the driving transistor of the particular sub-pixel and the anode electrode of an adjacent sub-pixel.

[0228] In the driving transistor of a particular sub-pixel, e.g. Figure 19 As shown in FIG, when adjacent sub-pixels are driven, the driving current supplied to the anode electrode of a specific sub-pixel may increase due to the first parasitic capacitance and the second parasitic capacitance. Therefore, due to the increased brightness, the specific sub-pixel may not emit light with the desired brightness, and grayscale defects may occur.

[0229] from Figure 19 As can be seen, as the driving voltage applied to adjacent sub-pixels increases, the driving current increase rate for a particular sub-pixel may increase. Therefore, as the driving voltage applied to adjacent sub-pixels increases, the brightness increase rate of the particular sub-pixel also increases, which can be seen by the user's eyes.

[0230] On the other hand, the display panel 110 according to the present disclosure can remove the first parasitic capacitance by using the first metal layer, and can reduce the second parasitic capacitance by using the second metal layer. Figure 20 As shown, even when driving adjacent sub-pixels, the driving current supplied to the anode electrode of a specific sub-pixel does not vary significantly. For example, grayscale defects of sub-pixels do not occur in the display panel 110 according to the present disclosure.

[0231] In the display panel 110 according to the present disclosure, due to the reduction in product defect rate, the manufacturing process cost can be reduced, the manufacturing process time can be shortened, and the production energy can be reduced. In addition, the display panel 110 according to the present disclosure can reduce greenhouse gases generated by the manufacturing process, thereby achieving ESG (Environmental / Social / Governance).

[0232] In the present disclosure, a first metal layer can be provided between the gate electrode of the drive transistor of a particular sub-pixel and the anode electrode of an adjacent sub-pixel to remove the first parasitic capacitance. Furthermore, in the present disclosure, a second metal layer in a floating state can be provided between the first metal layer and the anode electrode of the adjacent sub-pixel to reduce the second parasitic capacitance.

[0233] Furthermore, in the present disclosure, even when driving adjacent sub-pixels, the driving current supplied to the anode electrode of a specific sub-pixel does not change significantly. For example, the present disclosure can prevent or reduce grayscale defects related to parasitic capacitance.

[0234] In addition, in the present disclosure, a portion of the first metal layer can be used as a capacitor electrode to increase the capacitance of the capacitor. The present disclosure can improve the brightness of the sub-pixel according to the increase in the capacitance of the capacitor.

[0235] In addition, the present disclosure can simultaneously form the first metal layer and the capacitor electrode through a simple process to remove the first parasitic capacitance. Therefore, the present disclosure can achieve process optimization and reduce production energy consumption.

[0236] Furthermore, the present disclosure can improve transparency by removing the insulating layer from the transmission area.

[0237] In addition, the present disclosure can reduce manufacturing process costs, shorten manufacturing process time, and reduce production energy consumption due to the reduction in product defect rates. In addition, the present disclosure can reduce greenhouse gases that may be generated during the manufacturing process, thereby achieving ESG (environmental, social, and governance) benefits.

[0238] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to the embodiments and various modifications can be made without departing from the spirit of the present disclosure. Therefore, the embodiments disclosed herein are intended to illustrate the scope of the technical ideas of the present disclosure, and the scope of the technical ideas of the present disclosure is not limited by the embodiments. Therefore, it should be understood that the above embodiments are illustrative and non-restrictive in all aspects.

[0239] CROSS-REFERENCE TO RELATED APPLICATIONS

[0240] This application claims the benefit of and priority to Korean Patent Application No. 10-2024-0030210 filed in Korea on February 29, 2024, which is hereby incorporated by reference for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: a first sub-pixel and a second sub-pixel, wherein the first sub-pixel and the second sub-pixel are adjacent to each other; a first light-emitting element, the first light-emitting element being in the first sub-pixel; a second light-emitting element, the second light-emitting element being in the second sub-pixel; a first driving transistor configured to provide a driving current to the first light emitting element; a second drive transistor configured to provide a drive current to the second light-emitting element, the second drive transistor at least partially overlapping the first light-emitting element; as well as A first metal layer is provided between the second driving transistor and the first light emitting element.

2. The display device according to claim 1, in, The second driving transistor includes an active layer, a gate electrode, a source electrode, and a drain electrode, and In a plan view of the display device, the first metal layer covers the gate electrode of the second driving transistor provided in a region where the second driving transistor and the first light emitting element overlap with each other.

3. The display device according to claim 2, in, The first metal layer is on either the source electrode or the drain electrode.

4. The display device according to claim 2, in, The first metal layer is electrically connected to one of the source electrode and the drain electrode.

5. The display device according to claim 4, in, The first metal layer extends from a region where the second driving transistor and the first light emitting element overlap to a region where the second light emitting element is provided, and the first metal layer is electrically connected to an anode electrode of the second light emitting element. 6 . The display device according to claim 1 , further comprising a second metal layer between the first metal layer and the first light emitting element.

7. The display device according to claim 6, wherein: The second metal layer is in a floating state.

8. The display device according to claim 6, wherein: In a plan view of the display device, the second metal layer covers a portion of the first metal layer overlapping the first light emitting element.

9. The display device according to claim 1, wherein The first sub-pixel and the second sub-pixel have different areas from each other.

10. The display device according to claim 1, wherein The second driving transistor is at one edge of the first sub-pixel.

11. The display device according to claim 1 , further comprising: A capacitor is provided at one edge of the second sub-pixel.

12. The display device according to claim 11, in, The capacitor includes a first capacitor electrode and a second capacitor electrode, The second driving transistor includes an active layer, a gate electrode, a source electrode, and a drain electrode, and One of the first capacitor electrode and the second capacitor electrode is on the same layer as the gate electrode of the second drive transistor and is connected to the gate electrode of the second drive transistor.

13. The display device according to claim 12, further comprising a light shielding layer provided below the second driving transistor and electrically connected to one of the source electrode and the drain electrode of the second driving transistor and to the other of the first capacitor electrode and the second capacitor electrode.

14. The display device according to claim 11, in, The capacitor further includes a third capacitor electrode, and The third capacitor electrode is on the same layer as the first metal layer and is connected to the first metal layer.

15. The display device according to claim 1, in, The second light emitting element includes an anode electrode, a light emitting layer and a cathode electrode, The anode electrode includes a first anode electrode, a second anode electrode, and an anode connecting electrode electrically connecting the first anode electrode and the second anode electrode to each other, and The anode connection electrode is on the same layer as the first metal layer.

16. The display device according to claim 15, wherein The first metal layer extends from a region where the second driving transistor and the first light emitting element overlap to a region where the second light emitting element is provided and is connected to the anode connection electrode. 17 . The display device according to claim 1 , further comprising at least one switching transistor in an edge region of one side of the second sub-pixel.

18. The display device according to claim 17, wherein: In a plan view of the display device, the first metal layer is spaced apart from the at least one switching transistor. 19 . The display device according to claim 17 , further comprising a shielding layer disposed on the at least one switching transistor.

20. A display device, comprising: Display area, the display device includes a transmissive area and a non-transmissive area; a first light-emitting element and a second light-emitting element, the first light-emitting element and the second light-emitting element being adjacent to each other in the non-transmitting region; a first circuit element, the first circuit element being located in the non-transmitting region and configured to drive the first light-emitting element; as well as a second circuit element, the second circuit element being in the non-transmitting region, the second circuit element being configured to drive the second light-emitting element; At least a portion of the second circuit element overlaps with the first light-emitting element.

21. The display device according to claim 20, in, The non-transmission area includes a signal line area in which a plurality of signal lines extending along a first direction are arranged, and The first circuit element and the second circuit element are between the signal line region and the transmission region.

22. The display device according to claim 20, wherein The second circuit element includes a driving transistor in a region overlapping with the first light emitting element and a capacitor in a region overlapping with the second light emitting element.

23. The display device according to claim 22, further comprising: A first metal layer is provided between the driving transistor of the second circuit element and the first light emitting element.

24. The display device according to claim 23, in, The non-transmission area includes a signal line area in which a plurality of signal lines extending along a first direction are arranged, and The first metal layer extends along the first direction between the signal line region and the transmission region.

25. The display device according to claim 23, in, The first metal layer extends from a region where the driving transistor of the second circuit element and the first light emitting element overlap to a region where the second light emitting element is provided and is electrically connected to the second light emitting element.

26. The display device according to claim 23, in, The driving transistor of the second circuit element includes an active layer, a gate electrode, a source electrode, and a drain electrode, and In a plan view of the display device, the first metal layer covers the gate electrode of the driving transistor.

27. The display device according to claim 26, wherein: The first metal layer is electrically connected to one of the source electrode and the drain electrode of the driving transistor.

28. The display device according to claim 23, further comprising: A second metal layer is between the first metal layer and the first light emitting element.

29. The display device according to claim 28, in, The non-transmission area includes a signal line area in which a plurality of signal lines extending along a first direction are arranged, and The second metal layer is between the signal line region and the transmission region.

30. The display device according to claim 28, wherein The second metal layer is in a floating state.

31. The display device according to claim 28, further comprising: a first insulating layer between the first metal layer and the driving transistor of the second circuit element; a second insulating layer, the second insulating layer being between the first metal layer and the second metal layer; as well as a planarization layer, the planarization layer being between the second metal layer and the first light emitting element, The first insulating layer, the second insulating layer and the planarization layer are removed from the transmission area.

32. A display device, comprising: a first light emitting element and a second light emitting element, wherein the first light emitting element and the second light emitting element are disposed adjacent to each other; a first circuit element configured to drive the first light-emitting element; a second circuit element configured to drive the second light-emitting element and disposed to at least partially overlap the first light-emitting element; as well as A first metal layer is provided between the second circuit element and the first light emitting element.

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