Display device having pad area

Abstract

The display device may include an active area in which a pixel area is disposed, and a bezel area disposed outside the active area. The pad region may be disposed in the bezel region. The pad region may include a plurality of voltage pads disposed side-by-side along an edge of the active region. A power voltage supply line surrounding the active area may be electrically connected to the plurality of voltage pads. The resistance of each voltage pad may decrease toward the center of the pad region. Accordingly, in the display device, heat generation due to a difference in a current path between the power voltage supply line and each of the voltage pads may be prevented or minimized.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0028329, filed on February 27, 2024, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a display device having a pad area. Background Art

[0004] Typically, a display device provides an image to a user. For example, a display device may include pixel regions on a device substrate. Each pixel region may be configured to produce a specific color. For example, a driver circuit electrically connected to a light-emitting device may be disposed within each pixel region.

[0005] Various signals may be applied to each pixel region via signal wiring. For example, the signal wiring may include a gate line for applying a gate signal, a data line for applying a data signal, and a power voltage supply line for supplying a power voltage. A power unit electrically connected to the power voltage supply line may be disposed outside the device substrate. For example, the device substrate may include an active area in which the pixel regions are disposed and a frame area disposed outside the active area, and a pad area including a voltage pad electrically connected to the power unit may be disposed within the frame area.

[0006] Each of the power voltage supply lines can be electrically connected to multiple voltage pads for stable connection. However, in a display device, the voltage pads electrically connected to each power voltage supply line may have different current paths. Therefore, in the display device, current may be concentrated on the voltage pads with relatively short current paths. In other words, in the display device, heat may be generated due to the difference in current paths. Therefore, in the display device, a light-emitting device arranged near the pad area may degrade due to the heat generated in one of the voltage pads. Summary of the Invention

[0007] Accordingly, the present disclosure is directed to a display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0008] An object of the present disclosure is to provide a display apparatus capable of reducing damage to a light emitting device due to heat.

[0009] Another object of the present disclosure is to provide a display device capable of preventing or minimizing heat generation due to a difference in current paths.

[0010] Additional advantages, objectives, and features of the present disclosure will be set forth in part in the following description and will become apparent to those skilled in the art upon examination of the following or may be learned from practice of the present disclosure. The objectives and other advantages of the present disclosure may be realized and obtained through the structures particularly pointed out in the written description and claims of the present disclosure and the accompanying drawings.

[0011] To achieve these objectives and other advantages and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a display device including a device substrate is provided. The device substrate includes an active area and a border area. The border area is disposed outside the active area. A pad area is disposed in the border area. The pad area includes a first voltage pad and a second voltage pad. The first voltage pad and the second voltage pad are disposed side by side along an edge of the active area. The first voltage pad and the second voltage pad are electrically connected to a power voltage supply line. The power voltage supply line extends along an edge of the device substrate. The first voltage pad is disposed between the second voltage pad and a side of the device substrate. The second voltage pad has a different resistance than the first voltage pad.

[0012] A distance between the power voltage supply line and a side of the device substrate outside the pad area may be smaller than a distance between the first voltage pad and the side of the device substrate outside the pad area.

[0013] The second voltage pad may have the same stack structure as the first voltage pad.

[0014] Each of the first voltage pad and the second voltage pad may include a first pad electrode and a second pad electrode. The second pad electrode may be disposed on the first pad electrode. The first pad electrode may include the same material as the power voltage supply line.

[0015] The horizontal width of the second voltage pad may be different from the horizontal width of the first voltage pad.

[0016] The second voltage pad may have the same length as the first voltage pad.

[0017] The pad area may include a third voltage pad. The third voltage pad may be electrically connected to a power voltage supply line. The second voltage pad may be disposed between the first voltage pad and the third voltage pad. The second voltage pad may have a resistance between the first voltage pad and the third voltage pad. The horizontal width of the second voltage pad may fall between the horizontal width of the first voltage pad and the horizontal width of the third voltage pad.

[0018] A distance between the second voltage pad and the third voltage pad may be different from a distance between the first voltage pad and the second voltage pad.

[0019] The signal applied to the power voltage supply line through the second voltage pad may be the same as the signal applied to the power voltage supply line through the first voltage pad.

[0020] The signal applied to the power voltage supply line through the first voltage pad and the second voltage pad may be a negative power voltage.

[0021] The pad area also includes a third voltage pad, a fourth voltage pad, a fifth voltage pad and a sixth voltage pad, which are arranged side by side in sequence near the second voltage pad and along the edge of the active area, the sixth voltage pad is connected to the first voltage pad, the fifth voltage pad is connected to the second voltage pad, and the fourth voltage pad is connected to the third voltage pad.

[0022] In another embodiment, a display device including a device substrate is provided. The device substrate includes an active area and a frame area. The frame area is disposed outside the active area. A pad area is disposed within the frame area. The pad area includes a plurality of voltage pads disposed side by side. The plurality of voltage pads are electrically connected to a power voltage supply line. The power voltage supply line extends along an edge of the device substrate. The area of ​​the region for connection between each voltage pad and the power voltage supply line increases toward the center of the pad area.

[0023] A plane of each voltage pad may have the same shape as a plane of an adjacent voltage pad.

[0024] Each of the plurality of voltage pads may include a lower pad electrode and an upper pad electrode. The upper pad electrode may be disposed on the lower pad electrode. A power voltage supply line may be electrically connected to the lower pad electrode of each voltage pad through at least one pad contact hole. The number of pad contact holes connected between the lower pad electrode of each voltage pad and the power voltage supply line may increase toward the center of the pad area.

[0025] Each of the plurality of voltage pads may include a first end and a second end. The first end of each voltage pad may face the power voltage supply line. The second end of each voltage pad may be opposite the first end of the corresponding voltage pad. A pad contact hole connected between the lower pad electrode of each voltage pad and the power voltage supply line may be provided near the second end of the corresponding voltage pad.

[0026] The connection electrode may be provided between the power voltage supply line and each of the voltage pads. Each of the plurality of voltage pads may be electrically connected to the power voltage supply line through one of the connection electrodes.

[0027] The connection electrode may be provided on a different layer from the power voltage supply line.

[0028] The driving circuit, the light-emitting device, and the light-blocking pattern may be disposed on the pixel region of the active area. The driving circuit may include at least one thin-film transistor. The light-emitting device may be electrically connected to the driving circuit. The light-blocking pattern may be disposed between the device substrate and the semiconductor pattern of the thin-film transistor. The connecting electrode may be disposed on the same layer as the light-blocking pattern.

[0029] Each of the plurality of voltage pads includes a lower pad electrode and an upper pad electrode disposed on the lower pad electrode, and an area of ​​the lower pad electrode of each voltage pad decreases toward an edge of the pad region. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0031] Figure 1 is a view schematically illustrating a display device according to an embodiment of the present disclosure;

[0032] Figure 2 is a diagram illustrating a circuit of a pixel region in a display device according to an embodiment of the present disclosure;

[0033] Figure 3 is a view showing a cross section of a pixel area in a display device according to an embodiment of the present disclosure;

[0034] Figure 4 yes Figure 1 A magnified view of the K1 region in Figure 1;

[0035] Figure 5 yes Figure 4 A magnified view of the K2 region in [Image file: 1];

[0036] Figure 6 It is along Figure 5 a view taken along line II' of FIG.

[0037] Figures 7 to 11 is a view illustrating a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] Hereinafter, details related to the above-mentioned objectives, technical configurations, and operational effects of the embodiments of the present disclosure will be clearly understood through the following detailed description with reference to the accompanying drawings showing some embodiments of the present disclosure. The embodiments of the present disclosure are provided here so that the technical spirit of the present disclosure can be satisfactorily conveyed to those skilled in the art, and therefore the present disclosure can be embodied in other forms and is not limited to the embodiments described below.

[0039] In addition, throughout the specification, the same or very similar elements may be represented by the same reference numerals, and in the drawings, the lengths and thicknesses of layers and regions may be exaggerated for convenience. It will be understood that when a first element is referred to as being "on" a second element, although the first element may be disposed on the second element to contact the second element, a third element may be interposed between the first and second elements.

[0040] Here, terms such as "first" and "second" may be used to distinguish any one element from another element. However, the first element and the second element may be arbitrarily named according to the convenience of those skilled in the art without departing from the technical spirit of the present disclosure.

[0041] The terms used in the specification of the present disclosure are only used to describe specific embodiments and are not intended to limit the scope of the present disclosure. For example, an element described in the singular is intended to include plural elements unless the context clearly indicates otherwise. In addition, in the specification of the present disclosure, it will be further understood that the terms "comprising" and "including" indicate the presence of claimed features, integers, steps, operations, elements, parts and / or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or combinations.

[0042] Also, unless “directly” is used, the terms “connected” and “coupled” may include two components being “connected” or “coupled” via one or more other components located between the two components.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the prior art and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0044] (Implementation Method)

[0045] Figure 1is a view schematically illustrating a display device according to an embodiment of the present disclosure. Figure 2 is a view illustrating a circuit of a pixel area in a display device according to an embodiment of the present disclosure. Figure 3 is a view illustrating a cross section of a pixel area in a display device according to an embodiment of the present disclosure.

[0046] Reference Figures 1 to 3 A display device according to an embodiment of the present disclosure may include a display panel DP. The display panel DP may generate an image provided to a user. For example, a pixel area PA may be provided in the display panel DP. Various signals may be applied to each pixel area PA via signal wirings GL, DL, and PL. For example, the signal wirings GL, DL, and PL may include a gate line GL for applying a gate signal, a data line DL for applying a data signal, and a first power voltage supply line PL for supplying a first power voltage.

[0047] Each of the pixel areas PA can emit light displaying a specific color according to the signal applied through the signal wiring GL, DL, and PL. For example, a drive circuit DC electrically connected to the light-emitting device 300 can be provided in each pixel area PA. The drive circuit DC of each pixel area PA can control the light-emitting device 300 of the corresponding pixel area PA by the signal applied through the signal wiring GL, DL, and PL. For example, the drive circuit DC of each pixel area PA can supply a drive current corresponding to the data signal to the light-emitting device 300 of the corresponding pixel area PA according to the gate signal. The drive current supplied by the drive circuit DC of each pixel area PA can be maintained for one frame. For example, the drive circuit DC of each pixel area PA may include a first thin film transistor TR1, a second thin film transistor TR2, and a storage capacitor Cst.

[0048] The first thin-film transistor TR1 of each pixel area PA can transmit a data signal to the second thin-film transistor TR2 of the corresponding pixel area PA according to a gate signal. For example, the first thin-film transistor TR1 of each pixel area PA can function as a switching thin-film transistor. The first thin-film transistor TR1 of each pixel area PA may include a first semiconductor pattern, a first gate electrode, a first drain electrode, and a first source electrode. The first semiconductor pattern may include a semiconductor material. The first semiconductor pattern may include a first drain region, a first channel region, and a first source region. The first gate electrode may overlap with the first channel region of the first semiconductor pattern. The first drain electrode and the first source electrode may be insulated from the first gate electrode. The first drain electrode may be electrically connected to the first drain region of the first semiconductor pattern. The first source electrode may be electrically connected to the first source region of the first semiconductor pattern. For example, the first gate electrode of each pixel area PA may be electrically connected to a corresponding gate line GL, and the first drain electrode of each pixel area PA may be electrically connected to a corresponding data line DL.

[0049] The second thin-film transistor TR2 of each pixel area PA can generate a driving current corresponding to the data signal. For example, the second thin-film transistor TR2 of each pixel area PA can function as a driving thin-film transistor. The second thin-film transistor TR2 of each pixel area PA may include a second semiconductor pattern 221, a second gate electrode 223, a second drain electrode 225, and a second source electrode 227. For example, the second gate electrode 223 of each pixel area PA may be electrically connected to the first source electrode of the corresponding pixel area PA, and the second drain electrode 225 of each pixel area PA may be electrically connected to the first power voltage supply line PL.

[0050] The second semiconductor pattern 221 may include a semiconductor material. For example, the second semiconductor pattern 221 may include low-temperature polysilicon (LPTS) or an oxide semiconductor, such as IGZO. The second semiconductor pattern 221 may include the same material as the first semiconductor pattern. The second semiconductor pattern 221 may be provided on the same layer as the first semiconductor pattern. The second semiconductor pattern 221 may be formed by the same process as the first semiconductor pattern. For example, the second semiconductor pattern 221 may be formed simultaneously with the first semiconductor pattern.

[0051] The second semiconductor pattern 221 may include a second drain region, a second channel region, and a second source region. The second channel region may be disposed between the second drain region and the second source region. The second drain region and the second source region may have a lower resistance than the second channel region. For example, the second drain region and the second source region may include a conductive region of an oxide semiconductor. The second channel region may be a non-conductive region of the oxide semiconductor.

[0052] The second gate electrode 223 may be disposed on a portion of the second semiconductor pattern. For example, the second gate electrode 223 may overlap the second channel region of the second semiconductor pattern 221. The second drain region and the second source region of the second semiconductor pattern 221 may be disposed outside the second gate electrode 223. The second gate electrode 223 may include a conductive material. For example, the second gate electrode 223 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second gate electrode 223 may be spaced apart from the second semiconductor pattern 221. The second gate electrode 223 may be insulated from the second semiconductor pattern 221. For example, the second channel region of the second semiconductor pattern 221 may have a conductivity corresponding to the voltage applied to the second gate electrode 223.

[0053] The second gate electrode 223 may include the same material as the first gate electrode. The second gate electrode 223 may be disposed on the same layer as the first gate electrode. The second gate electrode 223 may be formed by the same process as the first gate electrode. For example, the second gate electrode 223 may be formed simultaneously with the first gate electrode.

[0054] The second drain electrode 225 may include a conductive material. For example, the second drain electrode 225 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second drain electrode 225 may include the same material as the second gate electrode 223. The second drain electrode 225 may be provided on the same layer as the second gate electrode 223. The second drain electrode 225 may be formed by the same process as the second gate electrode 223. For example, the second drain electrode 225 may be formed simultaneously with the second gate electrode 223. The second drain electrode 225 may be electrically connected to the second drain region of the second semiconductor pattern 221. The second drain electrode 225 may be spaced apart from the second gate electrode 223.

[0055] The second source electrode 227 may include a conductive material. For example, the second source electrode 227 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second source electrode 227 may include the same material as the second gate electrode 223. The second source electrode 227 may be provided on the same layer as the second gate electrode 223. The second source electrode 227 may be formed by the same process as the second gate electrode 223. For example, the second source electrode 227 may be formed simultaneously with the second gate electrode 223. The second source electrode 227 may be electrically connected to the second source region of the second semiconductor pattern 221. The second source electrode 227 may be spaced apart from the second gate electrode 223 and the second drain electrode 225.

[0056] The storage capacitor Cst of each pixel area PA can maintain the voltage applied to the second gate electrode 223 of the corresponding pixel area PA for one frame. For example, the storage capacitor Cst of each pixel area PA can be electrically connected to the second gate electrode 223 and the second source electrode 227 of the corresponding pixel area PA. The storage capacitor Cst of each pixel area PA can have a stacked structure of capacitor electrodes. For example, the storage capacitor Cst of each pixel area PA includes a first capacitor electrode electrically connected to the second gate electrode 223 of the corresponding pixel area PA and a second capacitor electrode electrically connected to the second source electrode 227 of the corresponding pixel area PA. The first capacitor electrode or the second capacitor electrode of each pixel area PA can be formed using the same process as the first thin-film transistor TR1 and the second thin-film transistor TR2 of the corresponding pixel area PA. For example, the first capacitor electrode of each pixel area PA can be provided on the same layer as the second gate electrode 223 of the corresponding pixel area PA. The first capacitor electrode of each pixel area PA can be formed using the same process as the second gate electrode 223 of the corresponding pixel area PA. For example, the first capacitor electrode of each pixel area PA can be formed simultaneously with the second gate electrode 223 of the corresponding pixel area PA. Therefore, in the display device according to the embodiment of the present disclosure, the process of forming the driving circuit DC in each pixel area PA can be simplified.

[0057] The light emitting device 300 and the driving circuit DC of each pixel area PA may be supported by the device substrate 100. For example, the light emitting device 300 and the driving circuit DC of each pixel area PA may be disposed on the device substrate 100. The device substrate 100 may include an insulating material. For example, the device substrate 100 may include glass or plastic.

[0058] A plurality of insulating layers 110, 120, 130, 140, and 150 for avoiding unnecessary electrical connection may be provided on the device substrate 100. For example, a buffer insulating layer 110, a gate insulating layer 120, a device passivation layer 130, a planarization layer 140, and a bank insulating layer 150 may be provided on the device substrate 100.

[0059] The buffer insulating layer 110 may be provided on the device substrate 100. The buffer insulating layer 110 may prevent contamination caused by the device substrate 100 in the process of forming the driving circuit DC of each pixel area PA. For example, the buffer insulating layer 110 may extend along the upper surface of the device substrate 100 toward the driving circuit DC of each pixel area PA. The driving circuit DC of each pixel area PA may be provided on the buffer insulating layer 110. The buffer insulating layer 110 may include an insulating material. For example, the buffer insulating layer 110 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer insulating layer 110 may have a multilayer structure. For example, the buffer insulating layer 110 may have a structure in which an inorganic insulating layer made of silicon oxide (SiOx) and an inorganic insulating layer made of silicon nitride (SiNx) are stacked.

[0060] A light-blocking pattern 200 may be disposed between the device substrate 100 and the buffer insulating layer 110 of each pixel area PA. The light-blocking pattern 200 may include a material that reflects or absorbs light. For example, the light-blocking pattern 200 may include a metal. The light-blocking pattern 200 of each pixel area PA may overlap with the first and second semiconductor patterns 221 of the corresponding pixel area PA. Therefore, in a display device according to an embodiment of the present disclosure, light traveling toward the first and / or second semiconductor patterns 221 of each pixel area PA through the device substrate 100 may be blocked by the light-blocking pattern 200. Therefore, in a display device according to an embodiment of the present disclosure, changes in the characteristics of the first and second thin-film transistors TR1 and TR2 in each pixel area PA due to external light may be prevented.

[0061] The gate insulating layer 120 may be disposed on the buffer insulating layer 110. The first gate electrode of each pixel area PA may be insulated from the first semiconductor pattern of the corresponding pixel area PA by the gate insulating layer 120. The second gate electrode 223 of each pixel area PA may be insulated from the second semiconductor pattern 221 of the corresponding pixel area PA by the gate insulating layer 120. For example, the gate insulating layer 120 may cover the first and second semiconductor patterns 221 of each pixel area PA. The first and second gate electrodes 223 of each pixel area PA may be disposed on the gate insulating layer 120. The gate insulating layer 120 may include an insulating material. For example, the gate insulating layer 120 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0062] The device passivation layer 130 may be disposed on the gate insulating layer 120. The device passivation layer 130 may prevent damage to the driving circuit DC in each pixel area PA due to external impact and moisture. For example, the first gate electrode, the first drain electrode, the first source electrode, the second gate electrode 223, the second drain electrode 225, and the second source electrode 227 of each pixel area PA may be covered by the device passivation layer 130. The device passivation layer 130 may extend beyond the driving circuit DC of each pixel area PA. The device passivation layer 130 may include an insulating material. For example, the device passivation layer 130 may be a linear insulating layer made of an inorganic insulating material.

[0063] The planarization layer 140 may be disposed on the device passivation layer 130. The planarization layer 140 may eliminate thickness variations caused by the drive circuit DC of each pixel area PA. For example, the upper surface of the planarization layer 140 opposite the device substrate 100 may be flat. The upper surface of the planarization layer 140 may be parallel to the upper surface of the device substrate 100. The planarization layer 140 may include an insulating material. The planarization layer 140 may include a material different from that of the device passivation layer 130. The planarization layer 140 may include a material having relatively high fluidity. For example, the planarization layer 140 may include an organic insulating material.

[0064] The light emitting device 300 of each pixel area PA may be disposed on the planarization layer 140. The light emitting device 300 of each pixel area PA may emit light displaying a specific color. For example, the light emitting device 300 of each pixel area PA may include a first electrode 310, a light emitting layer 320, and a second electrode 330 sequentially stacked on the planarization layer 140 of the corresponding pixel area PA.

[0065] The first electrode 310 may include a conductive material. The first electrode 310 may include a material having a high reflectivity. For example, the first electrode 310 may include a metal such as aluminum (Al) and silver (Ag). The first electrode 310 may have a multilayer structure. For example, the first electrode 310 may have a structure in which a reflective electrode made of a metal is disposed between transparent electrodes made of a transparent conductive material such as ITO and IZO.

[0066] The light-emitting layer 320 may generate light having a brightness corresponding to the voltage difference between the first electrode 310 and the second electrode 330. For example, the light-emitting layer 320 may include at least one emission material layer (EML). The emission material layer may include an organic emission material, an inorganic emission material, or a hybrid emission material. For example, the display device according to an embodiment of the present disclosure may be an organic light-emitting display device including an organic light-emitting material.

[0067] The light-emitting layer 320 may have a multilayer structure. For example, the light-emitting layer 320 may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Therefore, in the display device according to the embodiment of the present disclosure, the emission efficiency of the light-emitting layer 320 can be improved.

[0068] The second electrode 330 may include a conductive material. The second electrode 330 may include a material different from that of the first electrode 310. The transmittance of the second electrode 330 may be higher than that of the first electrode 310. For example, the second electrode 330 may be a transparent electrode made of a transparent conductive material such as ITO and IZO. Therefore, in the display device according to an embodiment of the present disclosure, light generated by the light-emitting layer 320 can be emitted to the outside through the second electrode 330. The second electrode 330 may have a work function smaller than that of the first electrode 310. For example, the first electrode 310 may serve as an anode electrode, and the second electrode 330 may serve as a cathode electrode.

[0069] The bank insulation layer 150 may be disposed on the planarization layer 140. The bank insulation layer 150 may define an emission area in each pixel area PA. The first electrode 310 of each pixel area PA may be insulated from the first electrode 310 of an adjacent pixel area PA by the bank insulation layer 150. For example, the edge of the first electrode 310 in each pixel area PA may be covered by the bank insulation layer 150. The first electrode 310 of each pixel area PA may be partially exposed by the bank insulation layer 150. The light-emitting layer 320 and the second electrode 330 of each pixel area PA may be stacked on the portion of the corresponding first electrode 310 exposed by the bank insulation layer 150. For example, the light-emitting layer 320 may be in direct contact with the first electrode 310 and the second electrode 330 on the emission area EA defined by the bank insulation layer 150 in each pixel area PA. The bank insulation layer 150 may include an insulating material. For example, the bank insulation layer 150 may include an organic insulating material. The bank insulation layer 150 may include a material different from the planarization layer 140.

[0070] The first electrode 310 of each pixel area PA can be electrically connected to the driving circuit DC of the corresponding pixel area PA. For example, the first electrode 310 of each pixel area PA can directly contact the second source electrode 227 of the corresponding pixel area PA by penetrating the planarization layer 140. The planarization layer 140 may include a pixel contact hole that partially exposes the second source electrode 227 of each pixel area PA. The first electrode 310 of each pixel area PA can be connected to the second source electrode 227 of the corresponding pixel area PA through one of the pixel contact holes. The pixel contact hole may overlap with the bank insulation layer 150. Therefore, in the display device according to the embodiment of the present disclosure, the position of the first electrode 310 in the emission area EA of each pixel area PA can be minimized. For example, the portion of the first electrode 310 overlapping with the emission area EA of each pixel area PA can be in direct contact with the upper surface of the planarization layer 140. Therefore, in the display device according to the embodiment of the present disclosure, the brightness variation depending on the generation position of the light emitted from the emission area EA of each pixel area PA can be prevented.

[0071] The light emitted from the light emitting device 300 of each pixel area PA may display a different color from the light emitted from the light emitting device 300 of the adjacent pixel area PA. For example, the light emitting layer 320 of each pixel area PA may be spaced apart from the light emitting layer 320 of the adjacent pixel area PA. The light emitting layer 320 of each pixel area PA may include a different material from the light emitting layer 320 of the adjacent pixel area PA. For example, the light emitting layer 320 of each pixel area PA may have a different stacking structure from the light emitting layer 320 of the adjacent pixel area PA. The light emitting layer 320 of each pixel area PA may include an end portion disposed on the bank insulating layer 150.

[0072] The voltage applied to the second electrode 330 of each pixel area PA can be the same as the voltage applied to the second electrode 330 of an adjacent pixel area PA. For example, the second electrode 330 of each pixel area PA can be electrically connected to the second electrode 330 of an adjacent pixel area PA. The second electrode 330 of each pixel area PA can include the same material as the second electrode 330 of the adjacent pixel area PA. The second electrode 330 of each pixel area PA can be formed using the same process as the second electrode of the adjacent pixel area PA. For example, the second electrode 330 of each pixel area PA can be formed simultaneously with the second electrode 330 of the adjacent pixel area PA. The second electrode 330 of each pixel area PA can extend beyond the corresponding pixel area PA. For example, the second electrode 330 of each pixel area PA can be in direct contact with the second electrode 330 of the adjacent pixel area PA. Therefore, in the display device according to the embodiment of the present disclosure, the process of forming the second electrode 330 in each pixel area PA can be simplified. Furthermore, in the display device according to the embodiment of the present disclosure, the brightness of the light generated by the light emitting unit 320 of each pixel area PA can be adjusted by the data signal applied to the driving circuit DC of the corresponding pixel area PA.

[0073] The encapsulation structure 400 may be disposed on the light-emitting device 300 in each pixel area PA. The encapsulation structure 400 can prevent the light-emitting device 300 from being damaged by external impact and moisture. The encapsulation structure 400 may have a multilayer structure. For example, the encapsulation structure 400 may include a first encapsulation layer 410, a second encapsulation layer 420, and a third encapsulation layer 430 stacked in sequence. The first encapsulation layer 410, the second encapsulation layer 420, and the third encapsulation layer 430 may include insulating materials. The second encapsulation layer 420 may include a different material from the first encapsulation layer 410 and the third encapsulation layer 430. For example, the first encapsulation layer 410 and the third encapsulation layer 430 may include an inorganic insulating material, and the second encapsulation layer 420 may include an organic insulating material. Therefore, in the display device according to an embodiment of the present disclosure, the light-emitting device 300 can be effectively prevented from being damaged by external impact and moisture. The thickness difference caused by the light-emitting device 300 in each pixel area PA can be eliminated by the second encapsulation layer 420. The second encapsulation layer 420 may have a greater thickness than the first encapsulation layer 410 and the third encapsulation layer 430. For example, an upper surface of the package structure 400 opposite to the device substrate 100 may be a flat surface. The upper surface of the package structure 400 may be parallel to the upper surface of the device substrate 100.

[0074] The display panel DP may include an active area AA in which a pixel area PA is provided and a border area BZ provided outside the active area AA. The border area BZ may be provided outside the pixel area PA. For example, the active area AA may be surrounded by the border area BZ. A gate driver GD electrically connected to the gate line GL, a data driver electrically connected to the data line DL, and a power unit electrically connected to the first power voltage supply line PL may be provided outside the active area AA. For example, each of the signal wirings GL, DL, and PL may include an area provided on the border area BZ. At least one of the gate driver GD, the data driver, and the power unit may be provided on the border area BZ of the display panel DP. For example, a display device according to an embodiment of the present disclosure may be a GIP (gate in panel) type display device in which the gate driver GD is formed on the border area BZ.

[0075] A pad region PAD for applying external signals may be provided within the bezel region BZ. A data driver and a power unit provided outside the display panel DP may apply signals via the pad region PAD. For example, a data line DL may be electrically connected to the data driver via the pad region PAD, and a first power voltage supply line PL may be electrically connected to the power unit via the pad region PAD.

[0076] The second power voltage supply line VSL may be provided on the border area BZ. The second power voltage supply line VSL may supply a second voltage to the gate driver GD and the active area AA. The second power voltage may be different from the first power voltage. For example, the first power voltage may be a positive power voltage (VDD), and the second power voltage may be a negative power voltage (VSS). The second power voltage supply line VSL may extend along the edge of the device substrate 100. For example, the second electrode 330 of each pixel area PA may be electrically connected to the second power voltage supply line VSL on the border area BZ. The side of the active area AA that does not face the pad area PAD may be surrounded by the second power voltage supply line VSL. The second power voltage supply line VSL may be provided close to the side 100s at the outside of the pad area PAD of the device substrate 100, as shown in FIG. Figure 1 As shown. For example, the distance L1 between the second power voltage supply line VSL outside the pad area PAD and the side 100s of the device substrate 100 can be smaller than the distance L2 between the side 100s of the device substrate 100 and the side of the pad area PAD. The gate driver GD can be provided between the active area AA and the second power voltage supply line VSL. The second power voltage supply line VSL can be electrically connected to the pad area PAD.

[0077] Figure 4 yes Figure 1 A magnified view of the K1 region in Figure 2. Figure 5 yes Figure 4 A magnified view of the K2 region in Figure 1. Figure 6 It is along Figure 5 A view taken along line II'.

[0078] Reference Figures 1 to 6 , the second power voltage supply line VSL can be formed using the same process as the drive circuit DC of each pixel area PA. For example, the second power voltage supply line VSL may include the same material as the second gate electrode 223 of each pixel area PA. The second power voltage supply line VSL may be provided on the same layer as the second gate electrode 223 of each pixel area PA. For example, the second power voltage supply line VSL may be provided between the gate insulation layer 120 and the device passivation layer 130 of the border area BZ. The second power voltage supply line VSL may be formed using the same process as the second gate electrode 223 of each pixel area PA. For example, the second power voltage supply line VSL may be formed simultaneously with the second gate electrode 223 of each pixel area PA.

[0079] The pad area PAD may include a plurality of voltage pads VSP electrically connected to the second power voltage supply line VSL. The signal supplied to the second power voltage supply line VSL through each voltage pad VSP may be the same as the signal supplied to the second power voltage supply line VSL through the adjacent voltage pad VSP. For example, a negative power voltage may be supplied to the second power voltage supply line VSL through each voltage pad VSP. The plurality of voltage pads VSP may be arranged at the edge of the pad area PAD. For example, the second power voltage supply line VSL may be electrically connected to the pad area PAD outside the data line DL. The plurality of voltage pads VSP may be arranged side by side. For example, the plurality of voltage pads VSP may include a first voltage pad VP1, a second voltage pad VP2, a third voltage pad VP3, a fourth voltage pad VP4, a fifth voltage pad VP5, and a sixth voltage pad VP6 arranged side by side along the edge of the active area AA. The second power voltage supply line VSL may be electrically connected to the first voltage pad VP1, the second voltage pad VP2, the third voltage pad VP3, the fourth voltage pad VP4, the fifth voltage pad VP5, and the sixth voltage pad VP6. Therefore, in the display device according to an embodiment of the present disclosure, the second power voltage supply line VSL may be stably connected to the power unit.

[0080] The first voltage pad VP1 may be positioned near an edge of the pad area PAD. The sixth voltage pad VP6 may be positioned near the center of the pad area PAD. For example, the first voltage pad VP1 may be positioned between the second voltage pad VP2 and a side of the device substrate 100, the third voltage pad VP3 may be positioned between the second voltage pad VP2 and the fourth voltage pad VP4, and the fifth voltage pad VP5 may be positioned between the fourth voltage pad VP4 and the sixth voltage pad VP6. The distance between the second power voltage supply line VSL and the side of the device substrate 100 outside the pad area PAD may be smaller than the distance between the pad area PAD and the side of the device substrate 100. For example, the distance between the second power voltage supply line VSL and the side of the device substrate 100 outside the pad area PAD may be smaller than the distance between the first voltage pad VP1 and the side of the device substrate 100. Therefore, in a display device according to an embodiment of the present disclosure, the current path between each voltage pad VSP and the second power voltage supply line VSL may have different lengths depending on the position of the corresponding voltage pad VSP. For example, in a display device according to an embodiment of the present disclosure, a current path between the second voltage pad VP2 and the second power voltage supply line VSL may be longer than a current path between the first voltage pad VP1 and the second power voltage supply line VSL, and a current path between the third voltage pad VP3 and the second power voltage supply line VSL may be longer than a current path between the second voltage pad VP2 and the second power voltage supply line VSL. Furthermore, in a display device according to an embodiment of the present disclosure, a current path between the fifth voltage pad VP5 and the second power voltage supply line VSL may be shorter than a current path between the sixth voltage pad VP6 and the second power voltage supply line VSL, a current path between the fourth voltage pad VP4 and the second power voltage supply line VSL may be shorter than a current path between the fifth voltage pad VP5 and the second power voltage supply line VSL, and a current path between the third voltage pad VP3 and the second power voltage supply line VSL may be shorter than a current path between the fourth voltage pad VP4 and the second power voltage supply line VSL.

[0081] The resistance of each voltage pad VSP can decrease as it moves away from the edge of the pad area PAD. For example, the resistance of the second voltage pad VP2 can be less than the resistance of the first voltage pad VP1, the resistance of the third voltage pad VP3 can be less than the resistance of the second voltage pad VP2, and the resistance of the fourth voltage pad VP4 can be less than the resistance of the third voltage pad VP3. Moreover, the resistance of the fifth voltage pad VP5 can be greater than the resistance of the sixth voltage pad VP6, and the resistance of the fourth voltage pad VP4 can be greater than the resistance of the fifth voltage pad VP5. Therefore, in the display device according to an embodiment of the present disclosure, the current flowing between the voltage pad VSP and the second power voltage supply line VSL can be distributed to the first voltage pad VP1, the second voltage pad VP2, the third voltage pad VP3, the fourth voltage pad VP4, the fifth voltage pad VP5, and the sixth voltage pad VP6. For example, in a display device according to an embodiment of the present disclosure, the current flowing between the sixth voltage pad VP6 and the second power voltage supply line VSL can be greater than the current flowing between the first voltage pad VP1 and the second power voltage supply line VSL. Therefore, in a display device according to an embodiment of the present disclosure, current concentration caused by the difference in current paths of the voltage pad VSP can be reduced by the difference in resistance of the voltage pad VSP. In other words, in a display device according to an embodiment of the present disclosure, heat generation caused by current concentration between the voltage pad VSP and the second power voltage supply line VSL can be reduced.

[0082] Each of the voltage pads VSP may have the same stacked structure. For example, each of the voltage pads may have a stacked structure of a lower pad electrode P1 and an upper pad electrode P2. The upper pad electrode P2 of each voltage pad VSP may be disposed on the lower pad electrode P1 of the corresponding voltage pad VSP. The upper pad electrode P2 of each voltage pad VSP may be electrically connected to the lower pad electrode P1 of the corresponding voltage pad VSP. For example, the upper pad electrode P2 of each voltage pad VSP may be in direct contact with the lower pad electrode P1 of the corresponding voltage pad VSP.

[0083] The lower pad electrode P1 and upper pad electrode P2 of each voltage pad VSP can be formed using the same process used to form the driving circuit DC and light-emitting device 300 of each pixel area PA. For example, the lower pad electrode P1 of each voltage pad VSP can include the same material as the second gate electrode 223 of each pixel area PA, and the upper pad electrode P2 of each voltage pad VSP can include the same material as the first electrode 310 of each pixel area PA. The lower pad electrode P1 of each voltage pad VSP can be disposed on the same layer as the second gate electrode 223 of each pixel area PA. For example, the lower pad electrode P1 of each voltage pad VSP can be disposed between the gate insulating layer 120 and the device passivation layer 130 of the pad area PAD. The upper pad electrode P2 of each voltage pad VSP can be disposed on the same layer as the first electrode 310 of each pixel area PA. For example, the upper pad electrode P2 of each voltage pad VSP can be disposed on the planarization layer 140 of the pad area PAD. The device passivation layer 130 and the planarization layer 140 of the pad area PAD may include pad contact holes that partially expose the lower pad electrode P1 of each voltage pad VSP. The upper pad electrode P2 of each voltage pad VSP may directly contact the lower pad electrode P1 of the corresponding voltage pad VSP through one of the pad contact holes. The lower pad electrode P1 of each voltage pad VSP may be formed using the same process as the second gate electrode 223 of each pixel area PA, and the upper pad electrode P2 of each voltage pad VSP may be formed using the same process as the first electrode 310 of each pixel area PA. For example, the lower pad electrode P1 of each voltage pad VSP may be formed simultaneously with the second gate electrode 223 of each pixel area PA, and the upper pad electrode P2 of each voltage pad VSP may be formed simultaneously with the first electrode 310 of each pixel area PA.

[0084] The lower pad electrode P1 of each voltage pad VSP may be provided on the same layer as the second power voltage supply line VSL. The second power voltage supply line VSL may be electrically connected to the lower pad electrode P1 of each voltage pad VSP. For example, the second power voltage supply line VSL may be in direct contact with the lower pad electrode P1 of each voltage pad VSP. The second power voltage supply line VSL may include the same material as the lower pad electrode P1 of each voltage pad VSP. For example, the boundary between the lower pad electrode P1 of each voltage pad VSP and the second power voltage supply line VSL may not be discernible.

[0085] Each of the voltage pads VSP may have the same length. The horizontal width of each voltage pad VSP may be different. For example, the horizontal width W2 of the second voltage pad VP2 may be greater than the horizontal width W1 of the first voltage pad VP1, and the horizontal width W3 of the third voltage pad VP3 may be greater than the horizontal width W2 of the second voltage pad VP2. The fifth voltage pad VP5 may have a smaller horizontal width than the sixth voltage pad VP6, the fourth voltage pad VP4 may have a smaller horizontal width than the fifth voltage pad VP5, and the third voltage pad VP3 may have a smaller horizontal width than the fourth voltage pad VP4. That is, in a display device according to an embodiment of the present disclosure, the resistance of each voltage pad VSP can be adjusted by the horizontal width of the corresponding voltage pad VSP. Therefore, in a display device according to an embodiment of the present disclosure, a reduction in process efficiency caused by the process of forming voltage pads VSP with different resistances can be prevented.

[0086] The voltage pads VSP may be formed at a constant pitch. The voltage pads VSP may also be formed at a variable pitch. For example, the distance d2 between the second voltage pad VP2 and the third voltage pad VP3 may be less than the distance d1 between the first voltage pad VP1 and the second voltage pad VP2. The distance between the third voltage pad VP3 and the fourth voltage pad VP4 may be less than the distance d2 between the second voltage pad VP2 and the third voltage pad VP3, the distance between the fourth voltage pad VP4 and the fifth voltage pad VP5 may be less than the distance between the third voltage pad VP3 and the fourth voltage pad VP4, and the distance between the fifth voltage pad VP5 and the sixth voltage pad VP6 may be less than the distance between the fourth voltage pad VP4 and the fifth voltage pad VP5. The sum of the horizontal width W1 of the first voltage pad VP1 and the distance d1 between the first voltage pad VP1 and the second voltage pad VP2 may be the same as the sum of the horizontal width W2 of the second voltage pad VP2 and the distance between the second voltage pad VP2 and the third voltage pad VP3.

[0087] Therefore, a display device according to an embodiment of the present disclosure may include a pad area PAD disposed outside the active area AA, wherein the pad area PAD may include a plurality of voltage pads VSP electrically connected to a second power voltage supply line VSL extending along an edge of the device substrate 100, wherein the resistance of each voltage pad VSP may decrease toward the center of the pad area PAD. Therefore, in the display device according to an embodiment of the present disclosure, the current flowing between the pad area PAD and the second power voltage supply line VSL may be distributed to the plurality of voltage pads VSP. Therefore, in the display device according to an embodiment of the present disclosure, heat generation caused by current concentration between the pad area PAD and the second power voltage supply line VSL may be reduced. That is, in the display device according to an embodiment of the present disclosure, degradation of the light-emitting device 300 due to heat may be prevented.

[0088] Furthermore, in the display device according to an embodiment of the present disclosure, the resistance of each voltage pad VSP can be adjusted by the horizontal width of the corresponding voltage pad VSP. Therefore, in the display device according to an embodiment of the present disclosure, the current flowing between the pad area PAD and the second power voltage supply line VSL can be distributed without reducing process efficiency. Therefore, in the display device according to an embodiment of the present disclosure, production energy consumption can be reduced through process optimization.

[0089] The display device according to an embodiment of the present disclosure is described as including a drive circuit DC for each pixel area PA that may include a first thin-film transistor TR1, a second thin-film transistor TR2, and a storage capacitor Cst. However, in a display device according to another embodiment of the present disclosure, the drive circuit DC for each pixel area PA may include a drive thin-film transistor and at least one switching thin-film transistor. For example, in a display device according to another embodiment of the present disclosure, the drive circuit DC for each pixel area PA may further include a third thin-film transistor for initializing the storage capacitor Cst of the corresponding pixel area PA based on a gate signal. The third thin-film transistor in each pixel area PA may include a third semiconductor pattern, a third gate electrode, a third drain electrode, and a third source electrode. The third semiconductor pattern may include a semiconductor material. The third gate electrode of each pixel area PA may be electrically connected to the corresponding gate line GL. The third drain electrode of each pixel area PA may be electrically connected to an initialization line that applies an initialization signal. The third source electrode of each pixel area PA may be electrically connected to the storage capacitor Cst of the corresponding pixel area PA. Therefore, in the display device according to another embodiment of the present disclosure, the degree of freedom in configuring each drive circuit DC may be increased.

[0090] In a display device according to an embodiment of the present disclosure, the positions and electrical connections of the first drain electrode, first source electrode, second drain electrode 225, and second source electrode 227 in each drive circuit DC can vary depending on the configuration of the corresponding drive circuit DC and / or the type of the corresponding thin-film transistors TR1 and TR2. For example, in a display device according to another embodiment of the present disclosure, the second gate electrode 223 of each drive circuit DC can be electrically connected to the first drain region of the corresponding drive circuit DC. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of each drive circuit DC and the type of each thin-film transistor TR1 and TR2 can be increased.

[0091] The display device according to an embodiment of the present disclosure is described as the first drain electrode and the first source electrode of each pixel area PA can be provided on the same layer as the first gate electrode of the corresponding pixel area PA, and the second drain electrode 225 and the second source electrode 227 of each pixel area PA can be provided on the same layer as the second gate electrode 223 of the corresponding pixel area PA. However, in a display device according to another embodiment of the present disclosure, the first thin film transistor TR1 and the second thin film transistor TR2 of each pixel area PA can have various structures. For example, in a display device according to an embodiment of the present disclosure, the second drain electrode 225 and the second source electrode 227 of each pixel area PA can be provided on a different layer from the second gate electrode 223 of the corresponding pixel area PA, such as Figure 7 shown.

[0092] The interlayer insulating layer 160 may be disposed between the gate insulating layer 120 and the device passivation layer 130 of the device substrate 100. The second drain electrode 225 and the second source electrode 227 of each pixel area PA may be insulated from the second gate electrode 223 of the corresponding pixel area PA by the interlayer insulating layer 160. For example, the interlayer insulating layer 160 may cover the second gate electrode 223 of each pixel area PA. The second drain electrode 225 and the second source electrode 227 of each pixel area PA may be disposed on the interlayer insulating layer 160. The interlayer insulating layer 160 may include an insulating material. For example, the interlayer insulating layer 160 may include an inorganic insulating material. Therefore, in a display device according to another embodiment of the present disclosure, the degree of freedom in the configuration of the second thin film transistor TR2 in each pixel area PA may be increased.

[0093] The display device according to an embodiment of the present disclosure is described as the second power voltage supply line VSL can be in direct contact with the lower pad electrode P1 of each voltage pad VSP. However, in a display device according to another embodiment of the present disclosure, each of the voltage pads VSP can be connected to the second power voltage supply line VSL in various ways. For example, in a display device according to another embodiment of the present disclosure, the connection electrode CL can be provided between the buffer insulating layer 110 of the pad area PAD and the device substrate 100, and each of the voltage pads VSP can be electrically connected to the second power voltage supply line VSL through one of the connection electrodes CL, such as Figure 8 and Figure 9 As shown. The connection electrode CL may include a conductive material. For example, the connection electrode CL may include metal.

[0094] The connection electrode CL may be provided on the same layer as the light-blocking pattern in each pixel area PA. The connection electrode CL may include the same material as the light-blocking pattern in each pixel area PA. The connection electrode CL may be formed using the same process as the light-blocking pattern in each pixel area PA. For example, the connection electrode CL may be formed simultaneously with the light-blocking pattern in each pixel area PA. Therefore, in a display device according to another embodiment of the present disclosure, a reduction in process efficiency caused by the process of forming the connection electrode CL may be prevented.

[0095] The lower pad electrode P1 of each voltage pad VSP may be disposed on the same layer as the second power voltage supply line VSL. For example, the lower pad electrode P1 of each voltage pad VSP may be electrically connected to the corresponding connection electrode CL via at least one pad contact hole Ph. The pad contact hole Ph may penetrate the buffer insulating layer 110 and the gate insulating layer 120 of the pad area PAD. The number of pad contact holes Ph electrically connecting the lower pad electrode P1 of each voltage pad VSP to the second power voltage supply line VSL may increase toward the center of the pad area PAD. For example, in a display device according to another embodiment of the present disclosure, the number of pad contact holes Ph connected between the lower pad electrode P1 of the second voltage pad VP2 and the corresponding connection electrode CL may be greater than the number of pad contact holes Ph connected between the lower pad electrode P1 of the first voltage pad VP1 and the corresponding connection electrode CL, and the number of pad contact holes Ph connected between the lower pad electrode P1 of the third voltage pad VP3 and the corresponding connection electrode CL may be greater than the number of pad contact holes Ph connected between the lower pad electrode P1 of the second voltage pad VP2 and the corresponding connection electrode CL. Furthermore, in a display device according to another embodiment of the present disclosure, the number of pad contact holes Ph connected between the lower pad electrode P1 of the fourth voltage pad VP4 and the corresponding connection electrode CL may be greater than the number of pad contact holes Ph connected between the lower pad electrode P1 of the third voltage pad VP3 and the corresponding connection electrode CL, the number of pad contact holes Ph connected between the lower pad electrode P1 of the fifth voltage pad VP5 and the corresponding connection electrode CL may be greater than the number of pad contact holes Ph connected between the lower pad electrode P1 of the fourth voltage pad VP4 and the corresponding connection electrode CL, and the number of pad contact holes Ph connected between the lower pad electrode P1 of the sixth voltage pad VP6 and the corresponding connection electrode CL may be greater than the number of pad contact holes Ph connected between the lower pad electrode P1 of the fifth voltage pad VP5 and the corresponding connection electrode CL. Therefore, in a display device according to another embodiment of the present disclosure, the area of ​​the region for connection between each voltage pad VSP and the second power voltage supply line VSL may increase toward the center of the pad area PAD. That is, in the display device according to another embodiment of the present disclosure, the resistance of each voltage pad VSP can be determined by the number of pad contact holes Ph overlapping with the corresponding voltage pad VSP. Therefore, in the display device according to another embodiment of the present disclosure, the degree of freedom of configuration of each voltage pad VSP can be increased without reducing process efficiency.

[0096] In a display device according to another embodiment of the present disclosure, each of the voltage pads VSP may include a first end Pe1 facing the second power voltage supply line VSL and a second end Pe2 opposite the first end Pe1, and a pad contact hole Ph for connecting each voltage pad VSP to the second power voltage supply line VSL may be located near the second end Pe2 of the corresponding voltage pad VSP. Therefore, in the display device according to another embodiment of the present disclosure, the current path between each voltage pad VSP and the second power voltage supply line VSL can be increased by the location of the pad contact hole Ph. That is, in the display device according to another embodiment of the present disclosure, the deviation of the current path caused by the difference in the location of the voltage pad VSP can be reduced by the location of the pad contact hole Ph. Therefore, in the display device according to another embodiment of the present disclosure, the current flowing between the pad area PAD and the second power voltage supply line VSL can be efficiently distributed to the multiple voltage pads VSP without reducing process efficiency.

[0097] In a display device according to another embodiment of the present disclosure, the lower pad electrode P1 of each voltage pad VSP may have different sizes. For example, in a display device according to another embodiment of the present disclosure, the area of ​​the lower pad electrode P1 of each voltage pad VP1, VP2, VP3, VP4, VP5, and VP6 may decrease toward the edge of the pad area PAD, as shown in FIG. Figure 10 As shown. The lower pad electrode P1 of the first voltage pad VP1 may have a smaller size than the lower pad electrode P1 of the second voltage pad VP2, the lower pad electrode P1 of the second voltage pad VP2 may have a smaller size than the lower pad electrode P1 of the third voltage pad VP3, and the lower pad electrode P1 of the third voltage pad VP3 may have a smaller size than the lower pad electrode P1 of the fourth voltage pad VP4. The lower pad electrode P1 of the sixth voltage pad VP6 may have a larger size than the lower pad electrode P1 of the fifth voltage pad VP5, and the lower pad electrode P1 of the fifth voltage pad VP5 may have a larger size than the lower pad electrode P1 of the fourth voltage pad VP4. Therefore, in a display device according to another embodiment of the present disclosure, the resistance between the upper pad electrode P2 of each voltage pad VP1, VP2, VP3, VP4, VP5 and VP6 and the corresponding connection electrode CL may decrease toward the center of the pad area PAD. Therefore, in the display device according to another embodiment of the present disclosure, heat generation due to current concentration between the pad area PAD and the second power voltage supply line VSL may be effectively reduced without reducing process efficiency.

[0098] The display device according to an embodiment of the present disclosure is described as a device in which the resistance of the voltage pad VSP can decrease toward the center of the pad area PAD. However, in a display device according to another embodiment of the present disclosure, various structures can be used to reduce heat generation due to current concentration between the pad area PAD and the second power voltage supply line VSL. For example, in a display device according to another embodiment of the present disclosure, the sixth voltage pad VP6 can be connected to the first voltage pad VP1, the fifth voltage pad VP5 can be connected to the second voltage pad VP2, and the fourth voltage pad VP4 can be connected to the third voltage pad VP3, as shown in FIG. Figure 11 As shown. Therefore, in the display device according to another embodiment of the present disclosure, the third voltage pad VP3 and the fourth voltage pad VP4 can have a relatively small resistance, and the first voltage pad VP1 and the sixth voltage pad VP6 can have a relatively large resistance. That is, in the display device according to another embodiment of the present disclosure, the current flowing between the pad area PAD and the second power voltage supply line VSL can be distributed around the third voltage pad VP3 and the fourth voltage pad VP4. Therefore, in the display device according to another embodiment of the present disclosure, the degree of freedom of arrangement and shape of the voltage pads VP1, VP2, VP3, VP4, VP5 and VP6 in the pad area PAD can be improved.

[0099] In the result, a display device according to an embodiment of the present disclosure may include a pad area and a power voltage supply line arranged outside the active area, wherein the power voltage supply line may extend along an edge of the device substrate, wherein the pad area may include voltage pads electrically connected to the power voltage supply line, and wherein each of the voltage pads may have a different resistance from adjacent voltage pads.

[0100] Therefore, in a display device according to an embodiment of the present disclosure, the current flowing between the power voltage supply line and the voltage pad can be distributed. That is, in a display device according to an embodiment of the present disclosure, heat generation due to current concentration can be prevented or minimized. Therefore, in a display device according to an embodiment of the present disclosure, heat generation due to differences in current paths in the pad region can be prevented or minimized, and degradation of the light-emitting device can be reduced or prevented. Furthermore, in a display device according to an embodiment of the present disclosure, production energy consumption can be reduced through process optimization.

[0101] The disclosure being thus described, it will be obvious that the disclosure may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the disclosure, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the appended claims.

Claims

1. A display device, comprising: a device substrate including a frame region disposed outside the active region; a pad region disposed in the frame region, the pad region comprising a first voltage pad and a second voltage pad disposed side by side along an edge of the active region; and a power voltage supply line extending along an edge of the device substrate, the power voltage supply line being electrically connected to the first voltage pad and the second voltage pad, wherein the first voltage pad is disposed between the second voltage pad and a side portion of the device substrate, and The second voltage pad has a resistance different from that of the first voltage pad.

2. The display device according to claim 1, wherein A distance between the power voltage supply line and a side of the device substrate outside the pad area is smaller than a distance between the first voltage pad and a side of the device substrate outside the pad area.

3. The display device according to claim 1, wherein The second voltage pad has the same stacking structure as the first voltage pad.

4. The display device according to claim 3, wherein Each of the first voltage pad and the second voltage pad includes a first pad electrode and a second pad electrode disposed on the first pad electrode, and The first pad electrode includes the same material as the power voltage supply line.

5. The display device according to claim 1, wherein The horizontal width of the second voltage pad is different from the horizontal width of the first voltage pad. The display device according to claim 5 , wherein: The second voltage pad has the same length as the first voltage pad.

7. The display device according to claim 5, wherein the pad area including a third voltage pad electrically connected to the power voltage supply line, Wherein, the second voltage pad is arranged between the first voltage pad and the third voltage pad, wherein the second voltage pad has a resistance between the first voltage pad and the third voltage pad, and The horizontal width of the second voltage pad falls between the horizontal width of the first voltage pad and the horizontal width of the third voltage pad.

8. The display device according to claim 7, wherein A distance between the second voltage pad and the third voltage pad is different from a distance between the first voltage pad and the second voltage pad.

9. The display device according to claim 1, wherein The signal applied to the power voltage supply line through the second voltage pad is the same as the signal applied to the power voltage supply line through the first voltage pad.

10. The display device according to claim 9, wherein The signal applied to the power voltage supply line through the first voltage pad and the second voltage pad is a negative power voltage.

11. The display device according to claim 1, wherein The pad area also includes a third voltage pad, a fourth voltage pad, a fifth voltage pad and a sixth voltage pad, which are arranged side by side in sequence near the second voltage pad and along the edge of the active area, the sixth voltage pad is connected to the first voltage pad, the fifth voltage pad is connected to the second voltage pad, and the fourth voltage pad is connected to the third voltage pad.

12. A display device comprising: a device substrate including a frame region disposed outside the active region; a pad area, which is arranged in the frame area, and the pad area includes a plurality of voltage pads arranged side by side; as well as a power voltage supply line extending along an edge of the device substrate, the power voltage supply line being electrically connected to the plurality of voltage pads, The area of ​​the region used for connection between each voltage pad and the power voltage supply line increases toward the center of the pad region.

13. The display device according to claim 12, wherein The plane of each voltage pad has the same shape as the plane of an adjacent voltage pad.

14. The display device according to claim 12, wherein Each of the plurality of voltage pads includes a lower pad electrode and an upper pad electrode disposed on the lower pad electrode. wherein the power voltage supply line is electrically connected to the lower pad electrode of each voltage pad through at least one pad contact hole, and The number of the at least one pad contact hole connected between the lower pad electrode of each voltage pad and the power voltage supply line increases toward the center of the pad area.

15. The display device according to claim 14, wherein Each of the plurality of voltage pads includes a first end facing the power voltage supply line and a second end opposite to the first end, and The at least one pad contact hole connected between the lower pad electrode of each voltage pad and the power voltage supply line is disposed close to the second end of the corresponding voltage pad.

16. The display device according to claim 14, further comprising a connection electrode provided between the power voltage supply line and each voltage pad, in, Each of the plurality of voltage pads is electrically connected to the power voltage supply line through one of the connection electrodes.

17. The display device according to claim 16, wherein The connection electrode is provided on a different layer from the power voltage supply line.

18. The display device according to claim 16, further comprising: a driving circuit, which is disposed on a pixel region of the active region, the driving circuit comprising at least one thin film transistor; a light emitting device, which is disposed on a pixel region of the active region, the light emitting device being electrically connected to the driving circuit; as well as a light blocking pattern disposed on a pixel region of the active region, the light blocking pattern being disposed between the device substrate and the semiconductor pattern of the at least one thin film transistor, Wherein, the connecting electrode is provided on the same layer as the light blocking pattern.

19. The display device according to claim 12, wherein Each of the plurality of voltage pads includes a lower pad electrode and an upper pad electrode disposed on the lower pad electrode, and The area of ​​the lower pad electrode of each voltage pad decreases toward the edge of the pad region.

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