Display device

Abstract

A display device according to an exemplary embodiment of the present disclosure includes: a substrate including an active area having a profiled edge, a non-active area surrounding the active area, and a notch area defined by a shape of the profiled edge of the active area; a gate driver including a plurality of gate blocks disposed to be distributed in the active area and outputting gate signals; a plurality of gate lines connected to the plurality of gate blocks to transmit gate signals; and a first compensation pattern disposed in at least one of the plurality of gate blocks and overlapping the plurality of gate lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0030316 filed on February 29, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device with a reduced or minimized bezel. Background Art

[0004] With the development of technology in modern society, display devices are used to provide information to users in various ways. Display devices are not only included in electronic signs that transmit visual information in one direction, but also in various electronic devices that require higher-level technology to detect user input and provide information in response to the detected input.

[0005] For example, display devices are included in vehicles to provide various information to the driver and passengers. However, vehicle display devices must appropriately display content without disrupting vehicle operation. For example, while the vehicle is in operation, the display device must limit the display of content that might distract from the driver's focus. Summary of the Invention

[0006] An object to be achieved by the present disclosure is to provide a display device with a special-shaped structure that compensates for signal output according to position.

[0007] Another object to be achieved by the present disclosure is to provide a display device with a reduced frame.

[0008] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0009] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate, the substrate including an active area having a special-shaped edge, an inactive area surrounding the active area, and a gap area defined by the shape of the special-shaped edge of the active area; a gate driver, the gate driver including a plurality of gate blocks arranged to be distributed in the active area and output gate signals; a plurality of gate lines, the plurality of gate lines being connected to the plurality of gate blocks to transmit the gate signals; and a first compensation pattern, the first compensation pattern being arranged in at least one of the plurality of gate blocks and overlapping with the plurality of gate lines.

[0010] Additional details of illustrative embodiments are included in the detailed description and accompanying drawings.

[0011] According to the present disclosure, it is possible to compensate for outputs of gate signals and clock signals that differ according to positions due to a profiled structure.

[0012] According to the present disclosure, a gate driver outputting a gate signal is disposed in an active area and a compensation pattern compensating for a gate signal and a clock signal is disposed in the active area to reduce or minimize a bezel area.

[0013] Effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is an exemplary plan view of a display device according to an exemplary embodiment of the present disclosure;

[0016] Figure 2 is an exemplary plan view of a display device according to an exemplary embodiment of the present disclosure;

[0017] Figure 3 is an exemplary circuit diagram of a pixel circuit of a display device according to an exemplary embodiment of the present disclosure;

[0018] Figure 4 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 5 is an enlarged plan view of one pixel of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 6 Is used to illustrate Figure 1 A schematic diagram of the first region;

[0021] Figure 7 yes Figure 6 an enlarged plan view of one of the gate drivers;

[0022] Figure 8 Is used to illustrate Figure 1 A schematic diagram of the second region;

[0023] Figure 9 yes Figure 8 an enlarged plan view of one of the gate blocks;

[0024] Figure 10 It is along Figure 9 A cross-sectional view taken along line VIII-VIII';

[0025] Figure 11 is an enlarged plan view of one of the gate blocks of a display device according to another exemplary embodiment of the present disclosure;

[0026] Figure 12 is an enlarged plan view of one of the gate blocks of a display device according to still another exemplary embodiment of the present disclosure;

[0027] Figure 13 is a cross-sectional view of a display device according to yet another exemplary embodiment of the present disclosure;

[0028] Figure 14 is a cross-sectional view of one of the gate blocks of a display device according to still another exemplary embodiment of the present disclosure;

[0029] Figure 15 is an exemplary plan view of a display device according to yet another exemplary embodiment of the present disclosure;

[0030] Figure 16 yes Figure 15 a plan view of one of the gate blocks of the fourth region;

[0031] Figure 17 It is along Figure 16 A cross-sectional view taken along line XV-XV';

[0032] Figure 18 is a cross-sectional view of one of the gate blocks of a display device according to still another exemplary embodiment of the present disclosure; and

[0033] Figure 19 is a cross-sectional view of one of the gate blocks of a display device according to still another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The advantages and features of the present disclosure and the methods for achieving these advantages and features are described in detail below and in the accompanying drawings. Figure 1 The following detailed description of the exemplary embodiments will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but may be implemented in various forms. The exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of the present disclosure. Therefore, the present disclosure will be limited only by the scope of the appended claims.

[0035] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for the purpose of describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. The same reference numerals generally represent the same elements throughout the application. In addition, in the description below the present disclosure, detailed explanations of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of..." used herein are generally intended to allow the addition of other components, unless the term "only" is used in these terms. Any reference in the singular may include the plural form, unless otherwise expressly stated.

[0036] When terms such as "on," "above," "below," and "next" are used to describe the positional relationship between two parts, one or more other parts may be set between the two parts unless these terms are used together with the term "immediately" or "directly."

[0037] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component mentioned below may be the second component.

[0038] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may be interlocked and operated in various technical ways, and the embodiments may be performed independently of or in association with each other.

[0039] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 is an exemplary plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 2 is an exemplary plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 1 and Figure 2 , among various components of the display device 100 , only the substrate 110 and a plurality of flexible films COFs are shown.

[0041] The substrate 110 is a base member supporting various components of the display device 100 and may be formed of an insulating material. For example, the substrate 110 may be formed of a plastic material such as polyimide (PI) or glass, but is not limited thereto.

[0042] The substrate 110 includes an active area AA and a non-active area NA.

[0043] The active area AA is an area where an image is displayed. In the active area AA, a pixel formed by multiple sub-pixels can be set to display an image. For example, a pixel is composed of multiple sub-pixels including a light-emitting diode and a driving circuit to display an image.

[0044] In the active area AA, one of the four sides forming the active area AA may be a heterogeneous side having a heterogeneous structure. Figure 1 , the active area AA has a first side FS, a second side SS, a third side TS and a fourth side HTRS (also referred to as a special-shaped side HTRS). The second side SS faces the third side TS and is opposite thereto, and the first side FS is between the second side SS and the third side TS. The special-shaped side HTRS faces the first side FS and is opposite thereto. Unlike the first side FS, the special-shaped side HTRS has a convex shape. However, excluding the traditional straight edge design (e.g., a straight-sided shape), the special-shaped side HTRS may have various shapes (e.g., a curved shape, a triangle, a circle, a non-linear shape, a polygon, etc.). For example, referring to Figure 1 , among the four sides of the active area AA, the side located on the lower side may be a special-shaped side HTRS. That is, the special-shaped side HTRS located on the lower side of the active area AA is concave inwardly toward the upward direction of the active area AA, so that a special-shaped structure having a concave shape corresponding to the special-shaped side can be defined. Even in Figure 1 The irregular structure is shown as a rectangular concave structure, but is not limited to this. Therefore, the irregular structure is a structure resulting from an irregular edge and is formed by modifying polygons such as circles, triangles, rectangles, rhombuses, pentagons, and hexagons, making it difficult to define as a polygon. In the position where the irregular edge is concave, no pixels are provided, so that no image is displayed, and this can be defined as a notch area NTA.

[0045] The active area AA may include a plurality of first areas A1 and at least one second area A2 divided into a grid shape. Each of the plurality of first areas A1 and the at least one second area A2 may be an area in which the gate driver is distributed. All of the plurality of first areas A1 have an area of ​​a predetermined size, and at least one second area A2 is set to correspond to the notch area NTA and may be an area smaller than the plurality of first areas A1. At this time, for ease of design, the second area A2 may be set at a position adjacent to the notch area NTA. In addition, although in Figure 1 The effective area AA is shown to include one second area A2, but is not limited thereto. Two or more second areas may be provided according to the shape, position and size of the notch area. Figure 2, a plurality of first regions A1 and a plurality of second regions A2 may be provided in the active area AA. For example, in the row area corresponding to the notch area NTA, one first region A1 and a plurality of second regions A2 may be provided, but is not limited thereto.

[0046] The non-active area NA is an area where no image is displayed and various wirings for driving sub-pixels provided in the active area AA are provided. The non-active area may be referred to as a bezel area.

[0047] A plurality of flexible films COF are provided at one end of the substrate 110. The plurality of flexible films COF can be electrically connected to one end of the substrate 110. The plurality of flexible films COF is a film in which various components are provided on a base film having ductility to provide signals to the plurality of sub-pixels in the active area AA. One end of the plurality of flexible films COF is provided in the non-active area NA of the substrate 110 to provide data voltages, etc. to the plurality of sub-pixels in the active area AA. In addition, although Figure 1 The plurality of flexible film COFs shown in FIG. 5 are four, but the number of flexible film COFs may vary according to design, but is not limited thereto.

[0048] Furthermore, driver ICs, such as data driver ICs, can be mounted on multiple flexible film COFs. Driver ICs process the data used to display images and the drive signals used to process this data. Depending on the mounting method, driver ICs can be mounted in chip-on-glass (COG), chip-on-film (COF), or tape carrier package (TCP). For ease of description, this disclosure describes mounting driver ICs on multiple flexible film COFs using chip-on-film technology, but is not limited to this.

[0049] Figure 3 2 is an exemplary circuit diagram of a pixel circuit of a display device according to an exemplary embodiment of the present disclosure. A pixel PX may include a plurality of sub-pixels representing different colors and pixel circuits corresponding to the plurality of sub-pixels, respectively. Figure 3 An example of a pixel circuit provided for one sub-pixel in a pixel PX is illustrated.

[0050] Reference Figure 3 , the pixel circuit may include eight transistors and one capacitor.

[0051] The pixel circuit may include a driving transistor DT, a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 , and a capacitor Cstg.

[0052] The eight transistors included in the pixel circuit can be n-type transistors or p-type transistors. In the case of p-type transistors, the low-level voltage of each drive signal can represent the voltage that turns on the TFT, and the high-level voltage of each drive signal can represent the voltage that turns off the TFT.

[0053] Here, the low-level voltage may correspond to a predetermined voltage lower than the high-level voltage. For example, the low-level voltage may include a voltage corresponding to a range of -8V to -12V. The high-level voltage may correspond to a predetermined voltage higher than the low-level voltage. For example, the high-level voltage may include a voltage corresponding to a range of 12V to 16V. According to an exemplary embodiment, the low-level voltage may be referred to as a first voltage and the high-level voltage may be referred to as a second voltage. In this case, the first voltage may be lower than the second voltage. However, the ranges of the low-level voltage and the high-level voltage are illustrative and not limited thereto.

[0054] Here, the first electrode or the second electrode of the transistor described below may refer to the source electrode or the drain electrode. However, the terms first electrode and second electrode are terms used to distinguish the electrodes, but do not limit what corresponds to each electrode. In addition, in each electrode, the first electrode may not refer to the same electrode. For example, the first electrode of the first transistor T1 may represent the source electrode of the first transistor T1, and the first electrode of the sixth transistor T6 may represent the drain electrode of the sixth transistor T6.

[0055] The driving transistor DT may be connected to the first transistor T1 connected to the first light emitting diode ED1 and the second transistor T2 connected to the second light emitting diode ED2. For example, the second electrode of the driving transistor DT may be connected to the first transistor T1 and the second transistor T2.

[0056] The driving transistor DT may be connected to a high-potential power line that provides a high-potential power voltage ELVDD. For example, a first electrode of the driving transistor DT may be connected to the high-potential power line. When the driving transistor DT is turned on, the high-potential power voltage ELVDD provided by the high-potential power line may be transmitted from the first electrode of the driving transistor DT to the second electrode.

[0057] The first transistor T1 may be connected to at least one of the first light emitting diode ED1 , the second transistor T2 , the fourth transistor T4 , and the fifth transistor T5 .

[0058] For example, the first electrode of the first transistor T1 may be connected to the second transistor T2 and the fourth transistor T4. The second electrode of the first transistor T1 may be connected to the first light-emitting diode ED1 and the fifth transistor T5. The gate electrode of the first transistor T1 may be connected to a wide-field-of-view signal line to which the wide-field-of-view signal CS1 is applied. The first transistor T1 may be turned on or off by the wide-field-of-view signal CS1 provided via the wide-field-of-view signal line. When the first transistor T1 is turned on, the voltage through the driving transistor DT may be applied to the first light-emitting diode ED1 (e.g., the anode electrode of the first light-emitting diode ED1).

[0059] Here, the wide field signal CS1 is provided by a mode controller (or a mode control circuit) and may control driving (or light emission) of the first light emitting diode ED1 in which the first lens is disposed.

[0060] The second transistor T2 may be connected to at least one of the second light emitting diode ED2 , the first transistor T1 , the fourth transistor T4 , and the sixth transistor T6 .

[0061] For example, the first electrode of the second transistor T2 may be connected to the first transistor T1 and the fourth transistor T4. The second electrode of the second transistor T2 may be connected to the sixth transistor T6 and the second light-emitting diode ED2. The gate electrode of the second transistor T2 may be connected to a narrow field of view signal line to which the narrow field of view signal CS2 is applied. The second transistor T2 may be turned on or off by the narrow field of view signal CS2 provided via the narrow field of view signal line. Therefore, when the second transistor T2 is turned on, the voltage across the drive transistor DT may be applied to the second light-emitting diode ED2 (e.g., the anode electrode of the second light-emitting diode ED2).

[0062] Here, the narrow field of view signal CS2 is provided by a mode controller (or a mode control circuit) and may control driving (or light emission) of the second light emitting diode ED2 in which the second lens is disposed.

[0063] In an exemplary embodiment, a first lens may be provided over the first light-emitting diode ED1. The first lens may allow the viewing angle of the region where the first light-emitting diode ED1 is provided to correspond to a first value. For example, the viewing angle of the region where the first light-emitting diode ED1 is provided may be equal to or greater than the first value. A second lens may be provided over the second light-emitting diode ED2. The second lens may allow the viewing angle of the region where the second light-emitting diode ED2 is provided to correspond to a second value. The second value may be smaller than the first value. For example, the viewing angle of the region where the second light-emitting diode ED2 is provided may be equal to or less than the second value.

[0064] In an exemplary embodiment, the area where the first light emitting diode ED1 of the pixel PX is provided may have a first viewing angle to provide light to a range corresponding to the front passenger seat and the driver's seat next to the front passenger seat. The area where the second light emitting diode ED2 is provided may have a second viewing angle to provide light to a range corresponding to the front passenger seat.

[0065] For example, the content (or image) provided by the first light-emitting diode ED1 of a pixel PX can be shared with people nearby the user in a first direction. When providing content via the first light-emitting diode ED1, the content is provided within a first viewing angle range that is wider than the second viewing angle range provided by the second light-emitting diode ED2. This can be referred to as a first mode. Furthermore, the content provided by the second light-emitting diode ED2 cannot be shared with people nearby the user. When providing content via the second light-emitting diode ED2, the content is provided within a second viewing angle range that is narrower than the first viewing angle range provided by the first light-emitting diode ED1. This can be referred to as a second mode.

[0066] The third transistor T3 may be connected to at least one of the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the capacitor Cstg.

[0067] For example, the first electrode of the third transistor T3 may be connected to a reference voltage line that provides a reference voltage Vref. Furthermore, the first electrode of the third transistor T3 may be connected to a fifth transistor T5 and a sixth transistor T6. The second electrode of the third transistor T3 may be connected to the sixth transistor T6 and the capacitor Cstg. The gate electrode of the third transistor T3 may be connected to a light emitting signal line that provides a light emitting signal EM. The third transistor T3 may be turned on or off by the light emitting signal EM. Therefore, when the third transistor T3 is turned on, the reference voltage Vref may be applied to the first electrode of the capacitor Cstg.

[0068] The fourth transistor T4 may be connected to at least one of the driving transistor DT, the first transistor T1 , the second transistor T2 , and the capacitor Cstg.

[0069] For example, the first electrode of the fourth transistor T4 may be connected to the driving transistor DT and the capacitor Cstg. The second electrode of the fourth transistor T4 may be connected to the driving transistor DT, the first transistor T1, and the second transistor T2. The gate electrode of the fourth transistor T4 may be connected to the second scan line providing the second scan signal SCAN2. The fourth transistor T4 may be provided with the second scan signal SCAN2 and may be turned on or off by the second scan signal SCAN2. Therefore, when the fourth transistor T4 is turned on, the gate electrode and the second electrode of the driving transistor DT may be diode-connected, thereby functioning as a diode connection.

[0070] The fifth transistor T5 may be connected to at least one of the first transistor T1 , the third transistor T3 , and the first light emitting diode ED1 .

[0071] For example, a first electrode of the fifth transistor T5 may be connected to the third transistor T3 and a reference voltage line providing a reference voltage Vref. A second electrode of the fifth transistor T5 may be connected to the first transistor T1 and the first light-emitting diode ED1. A gate electrode of the fifth transistor T5 may be connected to the second scan line. Therefore, the fifth transistor T5 may be provided with the second scan signal SCAN2 and may be turned on or off by the second scan signal SCAN2. Therefore, when the fifth transistor T5 is turned on, the reference voltage Vref may be applied to the first light-emitting diode ED1 (e.g., the anode electrode of the first light-emitting diode ED1).

[0072] The sixth transistor T6 may be connected to at least one of the second transistor T2 , the third transistor T3 , and the second light emitting diode ED2 .

[0073] For example, a first electrode of the sixth transistor T6 may be connected to the third transistor T3 and a reference voltage line providing a reference voltage Vref. A second electrode of the sixth transistor T6 may be connected to the second transistor T2 and the second light-emitting diode ED2. A gate electrode of the sixth transistor T6 may be connected to a second scan line. Therefore, the sixth transistor T6 may be provided with a second scan signal SCAN2 and may be turned on or off by the second scan signal SCAN2. Therefore, when the sixth transistor T6 is turned on, the reference voltage Vref may be applied to the second light-emitting diode ED2 (e.g., the anode electrode of the second light-emitting diode ED2).

[0074] The seventh transistor T7 may be connected to at least one of the third transistor T3 and the capacitor Cstg.

[0075] For example, a first electrode of the seventh transistor T7 may be connected to a data line providing a data voltage Vdata. A second electrode of the seventh transistor T7 may be connected to the third transistor T3 and the capacitor Cstg. A gate electrode of the seventh transistor T7 may be connected to a first scan line providing a first scan signal SCAN1. The seventh transistor T7 may be provided with the first scan signal SCAN1 and may be turned on or off by the first scan signal SCAN1. Therefore, when the seventh transistor T7 is turned on, the data voltage Vdata may be applied to the first electrode of the capacitor Cstg.

[0076] The first light-emitting diode ED1 and the second light-emitting diode ED2 may be connected to a low-potential power line that provides a low-potential power voltage ELVSS. For example, the cathode electrodes of the first light-emitting diode ED1 and the second light-emitting diode ED2 may be connected to the low-potential power line to provide the low-potential power voltage ELVSS. The low-potential power voltage may be a ground voltage (e.g., 0V). For example, a voltage corresponding to the ground voltage may be provided to the cathode electrodes of the first light-emitting diode ED1 and the second light-emitting diode ED2, but the present invention is not limited thereto.

[0077] Figure 4 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 4 , for ease of description, among the various components of the display device 100 according to an exemplary embodiment of the present disclosure, only the substrate 110, the first transistor T1, the storage capacitor Cst, the buffer layer 111, the gate insulating layer 112, the first interlayer insulating layer 113, the second interlayer insulating layer 114, the first planarizing layer 115, the second planarizing layer 116, the connecting electrode CE, the light emitting diode 120, the embankment layer 117, and the spacer 117a are shown.

[0078] Reference Figure 4 The display device 100 according to an exemplary embodiment of the present disclosure includes a substrate 110, a first transistor T1, a storage capacitor Cst, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarizing layer 115, a second planarizing layer 116, a light emitting diode 120, and a bank layer 117.

[0079] The substrate 110 is a base member that supports various components of the display device 100 and may be made of an insulating material. For example, the substrate may be formed of glass or a plastic material, but is not limited thereto.

[0080] A buffer layer 111 may be provided on the substrate 110. The buffer layer 111 may be formed over the entire surface of the substrate 110. The buffer layer 111 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. The buffer layer 111 may enhance adhesion between layers formed on the buffer layer 111 and the substrate 110. The buffer layer 111 is not a required component and may be omitted based on the type or material of the substrate 110 and the structure and type of the transistor.

[0081] The first transistor T1 may be disposed on the buffer layer 111 . The first transistor T1 may include a first active layer ACT1 , a first gate electrode GE1 , a first source electrode SE1 , and a first drain electrode DE1 . The first active layer ACT1 of the first transistor T1 may be disposed on the buffer layer 111 .

[0082] The first active layer ACT1 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0083] A gate insulating layer 112 may be provided on the first active layer ACT1 of the first transistor T1. The gate insulating layer 112 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. A contact hole may be formed in the gate insulating layer 112, through which each of the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1 is connected to the first active layer ACT1 of the first transistor T1.

[0084] The first gate electrode GE1 of the first transistor T1 may be disposed on the gate insulating layer 112. The first gate electrode GE1 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof. The first gate electrode GE1 may be formed on the gate insulating layer 112 to overlap with the first active layer ACT1 of the first transistor T1.

[0085] A first interlayer insulating layer 113 may be disposed on the gate insulating layer 112 and the first gate electrode GE1. The first interlayer insulating layer 113 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. A contact hole may be formed in the first interlayer insulating layer 113 to expose the first active layer ACT1 of the first transistor T1.

[0086] A second interlayer insulating layer 114 may be disposed on the first interlayer insulating layer 113. A contact hole may be formed in the second interlayer insulating layer 114 to expose the first active layer ACT1 of the first transistor T1. The second interlayer insulating layer 114 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0087] A first source electrode SE1 and a first drain electrode DE1 of the first transistor T1 may be disposed on the second interlayer insulating layer 114 .

[0088] The first source electrode SE1 and the first drain electrode DE1 of the first transistor T1 may be connected to the first active layer ACT1 of the first transistor T1 through contact holes formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. Therefore, the first source electrode SE1 of the first transistor T1 may be connected to the first source region of the first active layer ACT1 through the contact holes formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. The first drain electrode DE1 of the first transistor T1 may be connected to the first drain region of the first active layer ACT1 through the contact holes formed in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114.

[0089] The storage capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2 .

[0090] The first capacitor electrode Cst1 may be disposed on the gate insulating layer 112. The first capacitor electrode Cst1 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof. The first capacitor electrode Cst1 may be formed of the same material as the first gate electrode GE1, but is not limited thereto.

[0091] The second capacitor electrode Cst2 may be provided on the first interlayer insulating layer 113. The second capacitor electrode Cst2 may be provided on the first interlayer insulating layer 113 to overlap with the first capacitor electrode Cst1. For example, the second capacitor electrode Cst2 may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0092] A passivation layer may be disposed on the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1 and the second interlayer insulating layer 114. The passivation layer is an insulating layer that protects elements thereunder and may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0093] A first planarization layer 115 may be provided on the second interlayer insulating layer 114. The first planarization layer 115 is provided to reduce steps of the lower structure. The first planarization layer may be formed of an organic material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, or photoresist.

[0094] A connection electrode CE may be provided on the first planarization layer 115. The connection electrode CE may be electrically connected to the first drain electrode DE1 of the first transistor T1 through a contact hole formed in the first planarization layer 115. The connection electrode CE may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0095] A second planarization layer 116 may be provided on the connection electrode CE and the first planarization layer 115. The second planarization layer 116 is provided to reduce the step of the lower structure. The second planarization layer may be formed of an organic material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, or photoresist.

[0096] A light emitting diode 120 may be disposed on the second planarization layer 116. The light emitting diode 120 may include a first electrode 121, a light emitting structure 122, and a second electrode 123.

[0097] The first electrode 121 may be disposed on the second planarization layer 116. The first electrode 121 is an anode electrode and may be electrically connected to the first drain electrode DE1 of the first transistor T1 through a contact hole.

[0098] Since the display device 100 according to the exemplary embodiment of the present disclosure is a top-emitting display device, the first electrode 121 may be formed into a dual-layer structure including a transparent conductive layer and a reflective layer with high reflection efficiency. The transparent conductive layer may be formed of a material with a relatively high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The reflective layer may be formed into a single-layer or multi-layer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. For example, the first electrode 121 may be formed into a structure having a transparent conductive layer, a reflective layer, and a transparent conductive layer laminated in sequence. However, the first electrode 121 is not limited thereto and may also be formed into a structure having a transparent conductive layer and a reflective layer laminated in sequence.

[0099] A bank layer 117 may be disposed on the first electrode 121 and the second planarization layer 116 .

[0100] An opening may be formed in the bank layer 117 to expose the first electrode 121. Since the bank layer 117 defines the light-emitting area of ​​the display device 100, the bank layer 117 may also be referred to as a pixel defining layer. The bank layer 117 may be formed of an organic material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, or photoresist.

[0101] A spacer 117 a may be further disposed on the bank layer 117 .

[0102] The spacer 117a may be used to support the mask when aligning the mask on the bank layer 117 during the process of depositing the first electrode 121. The spacer 117a may be integrally formed with the bank layer 117. The spacer 117a may be formed of an organic material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, or photoresist.

[0103] A light-emitting structure 122 may be disposed on the first electrode 121. The light-emitting structure 122 may include a material that emits light of a specific color. For example, the light-emitting structure 122 may include a light-emitting material that emits any one of red, green, and blue light. Specifically, the light-emitting structure 122 may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). Depending on the structure or characteristics of the display device 100, some components of the light-emitting structure 122 may be omitted.

[0104] A second electrode 123 may be further disposed on the light emitting structure 122, the bank layer 117, and the spacer 117a. The second electrode 123 is a cathode electrode and may be disposed on the light emitting structure 122 so as to oppose the first electrode 121 with the light emitting structure 122 interposed therebetween. The second electrode 123 provides electrons to the light emitting structure 122. For example, the second electrode 123 may be formed of a conductive material having a low work function. When the display device 100 is a top-emission display device, the second electrode 123 may be formed of a transparent conductive oxide such as indium tin oxide or indium zinc oxide, or a transparent conductive material such as ytterbium (Yb), but is not limited thereto.

[0105] Figure 5 is an enlarged plan view of one pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 5 : is an enlarged plan view of the red sub-pixel SPR, the green sub-pixel SPG, and the blue sub-pixel SPB constituting one pixel PX. Figure 5, for the convenience of description, only the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the driving transistor DT, the storage capacitor Cst, the data line DL, the high potential power line VDDL, the reference voltage line RL, the first scan signal line SL1, the second scan signal line SL2, the emission signal line EML, the first wide field of view signal line SHL1, the second wide field of view signal line SHL2, the first narrow field of view signal line PRL1, the second narrow field of view signal line PRL2, the clock line CLKL, the gate high voltage line VGHL and the gate low voltage line VGLL are shown.

[0106] Reference Figure 5 , the display device 100 may include a plurality of red sub-pixels SPR, a plurality of green sub-pixels SPG, a plurality of blue sub-pixels SPB, and a plurality of gate blocks GB.

[0107] The plurality of gate blocks GB may include a plurality of first gate blocks GB1 and a plurality of second gate blocks GB2. The plurality of gate blocks GB1 and GB2 may be disposed on one side of one of the red subpixel SPR, the green subpixel SPG, and the blue subpixel SPB. For example, when the red subpixel SPR, the green subpixel SPG, and the blue subpixel SPB are arranged sequentially along a row direction, the first gate block GB1 may be disposed on the right side of the blue subpixel SPB, and the second gate block GB2 may be disposed on the left side of the red subpixel SPR. However, the placement order of the red subpixel SPR, the green subpixel SPG, the blue subpixel SPB, and the gate blocks GB1 and GB2 is not limited to this. The configuration of the gate driver may be separately disposed in the first gate block GB1 and the second gate block GB2. For example, the first gate block GB1 may include a clock line CLKL that provides a clock signal to the gate driver, a gate high voltage line VGHL that provides a gate high voltage, and a gate low voltage line VGLL that provides a gate low voltage. In the second gate block GB2, a first narrow field of view signal line PRL1 extending along the column direction and providing a narrow field of view mode signal, a first wide field of view signal line SHL1 providing a wide field of view mode signal, a high potential power line VDDL providing a high potential power supply, and a low potential power line VSSL providing a low potential power supply can be set.

[0108] Reference Figure 5Data lines DL, high-potential power lines VDDL, and reference voltage lines RL may be arranged on the substrate 110 along the column direction. For example, the data lines DL, high-potential power lines VDDL, and reference voltage lines RL may be arranged in this order from the left. The data lines DL, high-potential power lines VDDL, and reference voltage lines RL are arranged on the same layer of the substrate 110 and may be formed of the same material. For example, the data lines DL, high-potential power lines VDDL, and reference voltage lines RL may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0109] The data lines DL extend in a column direction on the substrate 110 to transmit a data voltage provided from the data driver to each sub-pixel SPR, SPG, SPB.

[0110] The high potential power line VDDL extends along a column direction on the substrate 110 to transmit a high potential voltage for driving the light emitting diode to each sub-pixel SPR, SPG, SPB.

[0111] The reference voltage line RL extends along a column direction on the substrate 110 to transmit a reference voltage to each sub-pixel SPR, SPG, SPB.

[0112] Reference Figure 5 A plurality of gate lines GL extending in a row direction may be provided on the substrate 110. The plurality of gate lines GL may include a first scan signal line SL1, a second scan signal line SL2, a light emission signal line EML, a second wide field of view signal line SHL2, and a second narrow field of view signal line PRL2. The first scan signal line SL1, the second scan signal line SL2, the light emission signal line EML, the second wide field of view signal line SHL2, and the second narrow field of view signal line PRL2 are spaced apart from each other and arranged in parallel. The first scan signal line SL1, the second scan signal line SL2, the light emission signal line EML, the second wide field of view signal line SHL2, and the second narrow field of view signal line PRL2 are provided on the same layer on the substrate 110 and may be formed of the same material. For example, the first scan signal line SL1, the second scan signal line SL2, the light emission signal line EML, the second wide field of view signal line SHL2, and the second narrow field of view signal line PRL2 may be formed of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0113] The first scan signal line SL1 extends in the row direction on the substrate 110 to intersect the data line DL, the high potential power line VDDL, and the reference voltage line RL extending in the column direction. The first scan signal line SL1 can transmit the first scan signal provided by the gate driver to each subpixel SPR, SPG, SPB.

[0114] The second scan signal line SL2 extends in the row direction on the substrate 110 to intersect the data line DL, the high potential power line VDDL, and the reference voltage line RL extending in the column direction. The second scan signal line SL2 can transmit the second scan signal provided by the gate driver to each sub-pixel SPR, SPG, SPB. Figure 3 FIG. 2 shows two second scan signal lines SL2 configured to transmit the second scan signal, but is not limited thereto. According to design, one second scan signal line SL2 may be provided.

[0115] The light emitting signal line EML extends in the row direction on the substrate 110 to intersect the data line DL, the high potential power line VDDL, and the reference voltage line RL extending in the column direction. The light emitting signal line EML can transmit the light emitting signal provided by the gate driver to each sub-pixel SPR, SPG, SPB. Figure 4 , two light emitting signal lines EML are shown configured to transmit light emitting signals, but the present invention is not limited thereto. According to design, one light emitting signal line EML may be provided.

[0116] The second wide-view signal line SHL2 extends along the row direction on the substrate 110 and is electrically connected to the first wide-view signal line SHL1 extending along the column direction through a contact hole. The second wide-view signal line SHL2 can transmit a wide-view mode signal to each sub-pixel SPR, SPG, SPB.

[0117] The second narrow field of view signal line PRL2 extends along the row direction on the substrate 110 to be electrically connected to the first narrow field of view signal line PRL1 extending along the column direction through the contact hole. The second narrow field of view signal line PRL2 can transmit the narrow field of view mode signal to each sub-pixel SPR, SPG, SPB.

[0118] Figure 6 Is used to illustrate Figure 1 Schematic diagram of the first region. Figure 6 , for convenience of description, only the first scan driver area SDA1, the second scan driver area SDA2, the light emitting driver area EMA, and the plurality of gate blocks GB provided in the first area A1 are shown.

[0119] The display device 100 according to an exemplary embodiment of the present disclosure includes a gate driver.

[0120] The gate driver includes a first scan driver, a second scan driver, and a light-emitting driver, which output scan signals and light-emitting signals in response to gate timing control signals. The gate driver receives a clock signal and a gate control signal to generate and output signals that turn on or off transistors disposed on substrate 110. Specifically, the first scan driver, the second scan driver, and the light-emitting driver can output a low-level voltage or a high-level voltage of a scan signal or light-emitting signal to the transistor disposed in each subpixel. For example, the first scan driver can output a first scan signal SCAN1 to a first scan signal line SL1 connected to the first scan driver in response to a gate control signal from a timing controller. The second scan driver can output a second scan signal SCAN2 to a second scan signal line SL2 connected to the second scan driver in response to a gate control signal from the timing controller. The light-emitting driver can output a light-emitting signal EM to a light-emitting signal line EML connected to the light-emitting driver in response to a gate control signal from the timing controller.

[0121] Reference Figure 6 In the first area A1, a first scan driver area SDA1, a second scan driver area SDA2, and a light emitting driver area EMA may be disposed.

[0122] The first scan driver area SDA1 is an area where the first scan driver is provided, the second scan driver area SDA2 is an area where the second scan driver is provided, and the light emitting driver area EMA is an area where the light emitting driver is provided. Each of the first scan driver area SDA1, the second scan driver area SDA2, and the light emitting driver area EMA includes a plurality of first gate blocks GB1 and a plurality of second gate blocks GB2.

[0123] Multiple first gate blocks GB1 and multiple second gate blocks GB2 may be arranged along the column direction in the active area AA. For example, in each of the first scan driver area SDA1, the second scan driver area SDA2, and the light emitting driver area EMA, three first gate blocks GB1 and two second gate blocks GB2 may be arranged extending along the column direction. In each of the first scan driver area SDA1, the second scan driver area SDA2, and the light emitting driver area EMA, the multiple first gate blocks GB1 and the multiple second gate blocks GB2 may be arranged alternately along the row direction. However, this is not limiting, and the number and placement of the multiple first gate blocks GB1 and the multiple second gate blocks GB2 may vary depending on the design.

[0124] The first scan driver, the second scan driver, and the light-emitting driver can be separately disposed in a plurality of first gate blocks GB1. The plurality of second gate blocks GB2 can include a plurality of power lines that transmit a constant voltage to the subpixels SPR, SPG, and SPB, a plurality of first narrow field of view signal lines PRL1 that provide narrow field of view mode signals, and a plurality of first wide field of view signal lines SHL1 that provide wide field of view mode signals. For example, the plurality of power lines can include a high potential power line VDDL and a low potential power line VSSL.

[0125] Figure 7 yes Figure 6 An enlarged plan view of one of the gate drivers. Figure 7 , only some of the gate blocks GB1 and GB2 provided in the first scan driver area SDA1 are shown.

[0126] Reference Figure 7 The plurality of first gate blocks GB1 may include a 1-1th gate block GB1-1, a 1-2th gate block GB1-2, and a 1-3th gate block GB1-3. The configuration of the first scan driver may be separately provided in the 1-1th gate block GB1-1, the 1-2nd gate block GB1-2, and the 1-3rd gate block GB1-3.

[0127] The 1-1th gate block GB1 - 1 may include a 1-1th transistor T1 - 1 , a 1-2th transistor T1 - 2 , a 1-3th transistor T1 - 3 , and a first capacitor CB.

[0128] The 1st transistor T1-1 may include a 1st source electrode SE1-1, a 1st drain electrode DE1-1, a 1st gate electrode GE1-1, and a 1st active layer ACT1-1. The 1st source electrode SE1-1 may be electrically connected to a gate low voltage line VGLL to which a gate low voltage is applied. The 1st drain electrode DE1-1 may be electrically connected to a 1st gate electrode GE1-2 of a 1st transistor T1-2 and a 1st gate electrode GE1-3 of a 1st transistor T1-3. The 1st gate electrode GE1-1 may be electrically connected to a clock line CLKL to which a clock signal is applied. The 1st active layer ACT1-1 may overlap the 1st gate electrode GE1-1 below the 1st gate electrode GE1-1.

[0129] The 1-2 transistor T1-2 may include a 1-2 source electrode SE1-2, a 1-2 drain electrode DE1-2, a 1-2 gate electrode GE1-2, and a 1-2 active layer ACT1-2. The 1-2 source electrode SE1-2 may be electrically connected to a gate high voltage line VGHL to which a gate high voltage is applied. The 1-2 drain electrode DE1-2 may be electrically connected to a 1-2 gate block GB1-2. The 1-2 gate electrode GE1-2 may be electrically connected to the drain electrode DE1-1 of the 1-1 transistor T1-1 and the 1-3 gate electrode G1-3 of the 1-3 transistor T1-3. The 1-2 active layer ACT1-2 may overlap with the 1-2 gate electrode GE1-2 below the 1-2 gate electrode GE1-2.

[0130] The 1-3rd transistor T1-3 may include a 1-3rd source electrode SE1-3, a 1-3rd drain electrode DE1-3, a 1-3rd gate electrode GE1-3, and a 1-3rd active layer ACT1-3. The 1-3rd source electrode SE1-3 may be electrically connected to a gate high voltage line VGHL. The 1-3rd drain electrode DE1-3 may be electrically connected to a first scan signal line SL1 that transmits a first scan signal. The 1-3rd gate electrode GE1-3 may be electrically connected to the drain electrode DE1-1 of the 1-1st transistor T1-1 and the 1-2nd gate electrode G1-2 of the 1-2nd transistor T1-2. The 1-3rd active layer ACT1-3 may overlap the 1-3rd gate electrode GE1-3 below the 1-3rd gate electrode GE1-3.

[0131] The first capacitor CB may be electrically connected to the 1-3 gate electrode GE1-3 of the 1-3 transistor T1-3 and the gate high voltage line VGHL.

[0132] The 1-2 th gate block GB1 - 2 may include a 1-4 th transistor T1 - 4 , a 1-5 th transistor T1 - 5 , and a 1-6 th transistor T1 - 6 .

[0133] The 1-4th transistor T1-4 may include a 1-4th source electrode SE1-4, a 1-4th drain electrode DE1-4, a 1-4th gate electrode GE1-4, and a 1-4th active layer ACT1-4. The 1-4th source electrode SE1-4 may be electrically connected to a gate low voltage line VGLL to which a gate low voltage is applied. The 1-4th drain electrode DE1-4 may be electrically connected to the 1-2nd drain electrode DE1-2 of the 1-2nd transistor T1-2, the 1-7th transistor T1-7 of the 1-3rd gate block GB1-3, and the 1-6th gate electrode GE1-6 of the 1-6th transistor T1-6. The 1-4th gate electrode GE1-4 may be electrically connected to the 1-5th gate electrode GE1-5 of the 1-5th transistor T1-5. The 1-4th active layer ACT1-4 may overlap with the 1-4th gate electrode GE1-4 below the 1-4th gate electrode GE1-4.

[0134] The 1-5th transistor T1-5 may include a 1-5th source electrode SE1-5, a 1-5th drain electrode DE1-5, a 1-5th gate electrode GE1-5, and a 1-5th active layer ACT1-5. The 1-5th source electrode SE1-5 may be electrically connected to the 1-6th source electrode SE1-6 of the 1-6th transistor T1-6, the first capacitor CB, and the 1-3rd gate electrode GE1-3 of the 1-3rd transistor T1-3. The 1-5th drain electrode DE1-5 may be electrically connected to a gate high voltage line VGHL to which a gate high voltage is applied. The 1-5th gate electrode GE1-5 may be electrically connected to the 1-4th gate electrode GE1-4 of the 1-4th transistor T1-4. The 1-5th active layer ACT1-5 may overlap the 1-5th gate electrode GE1-5 below the 1-5th gate electrode GE1-5.

[0135] The 1-6th transistor T1-6 may include a 1-6th source electrode SE1-6, a 1-6th drain electrode DE1-6, a 1-6th gate electrode GE1-6, and a 1-6th active layer ACT1-6. The 1-6th source electrode SE1-6 may be electrically connected to the 1-5th source electrode SE1-5 of the 1-5th transistor T1-5, the first capacitor CB, and the 1-3rd gate electrode GE1-3 of the 1-3rd transistor T1-3. The 1-6th drain electrode DE1-6 may be electrically connected to a gate high voltage line VGHL to which a gate high voltage is applied. The 1-6th gate electrode GE1-6 may be electrically connected to the 1-4th drain electrode DE1-4 of the 1-4th transistor T1-4. The 1-6th active layer ACT1-6 may overlap with the 1-6th gate electrode GE1-6 below the 1-6th gate electrode GE1-6.

[0136] The 1-3 th gate block GB1 - 3 may include a 1-7 th transistor T1 - 7 , a 1-8 th transistor T1 - 8 , and a second capacitor CQ.

[0137] The 1-7th transistor T1-7 may include a 1-7th source electrode SE1-7, a 1-7th drain electrode DE1-7, a 1-7th gate electrode GE1-7, and a 1-7th active layer ACT1-7. The 1-7th source electrode SE1-7 may be electrically connected to the 1-1st drain electrode DE1-4 of the 1-4th transistor T1-4 and the 1-2nd drain electrode DE1-2 of the 1-2nd transistor T1-2. The 1-7th drain electrode DE1-7 may be electrically connected to the 1-8th gate electrode GE1-8 of the 1-8th transistor T1-8. The 1-7th gate electrode GE1-7 may be electrically connected to a gate low voltage line VGLL to which a gate low voltage is applied. The 1-7th active layer ACT1-7 may overlap the 1-7th gate electrode GE1-7 below the 1-7th gate electrode GE1-7.

[0138] The 1-8th transistor T1-8 may include an 1-8th source electrode SE1-8, an 1-8th drain electrode DE1-8, an 1-8th gate electrode GE1-8, and an 1-8th active layer ACT1-8. The 1-8th source electrode SE1-8 may be electrically connected to a gate high voltage line VGHL to which a gate high voltage is applied. The 1-8th drain electrode DE1-8 may be electrically connected to a second capacitor CQ. The 1-8th gate electrode GE1-8 may be electrically connected to the 1-7th drain electrode DE1-7 of the 1-7th transistor T1-7 and the second capacitor CQ. The 1-8th active layer ACT1-8 may overlap the 1-8th gate electrode GE1-8 below the 1-8th gate electrode GE1-8.

[0139] The second capacitor CQ may be electrically connected to the 1-8th gate electrode GE1-8 of the 1-8th transistor T1-8, the 1-8th drain electrode DE1-8 of the 1-8th transistor T1-8, and the first scan signal line SL1 to which the first scan signal is transmitted.

[0140] In the plurality of second gate blocks GB2 , a plurality of gate lines GL extending in a row direction and a power supply line VDDL extending in a column direction so as to cross the plurality of gate lines GL may be disposed.

[0141] Figure 8 Is used to illustrate Figure 1 Schematic diagram of the second region. Figure 8 In order to facilitate the description, only the Figure 1 The first scanning driver area SDA1, the second scanning driver area SDA2, the light emitting driver area EMA and the plurality of gate blocks GB in the second area A2. Hereinafter, the remaining configuration except the plurality of gate blocks GB is the same as Figure 6 The configuration is the same, so the description will be omitted.

[0142] Reference Figure 8 Due to the notch area NTA, the second area A2 can be an area smaller than the plurality of first areas A1. Therefore, the number of the plurality of gate blocks GB provided in each of the first scan driver area SDA1, the second scan driver area SDA2, and the light emitting driver area EMA can be smaller than that in the first area A1. For example, in each of the first scan driver area SDA1, the second scan driver area SDA2, and the light emitting driver area EMA provided in the second area A2, two first gate blocks GB1 and two second gate blocks GB2 can be provided extending along the column direction. Although Figure 6 In, with Figure 4 In comparison, one first gate block GB1 is omitted, but the number of the first gate blocks GB1 and the second gate blocks GB2 provided in the second area A2 may vary according to areas and designs, but is not limited thereto.

[0143] Figure 9 yes Figure 8 An enlarged plan view of one of the gate blocks. Figure 9 middle, Figure 8 A portion of the second gate block GB2 among the plurality of gate blocks GB is enlarged.

[0144] Reference Figure 9 In the second gate block GB2 disposed in the second area A2, a plurality of gate lines GL, a high potential power line VDDL, and a first compensation pattern 130 may be disposed.

[0145] A plurality of gate lines GL extend in a row direction in the second gate block GB2 and are spaced apart from each other in a column direction to be disposed in parallel.

[0146] The high potential power line VDDL extends in the column direction in the second gate block GB2 to intersect the plurality of gate lines GL.

[0147] The first compensation pattern 130 extends in the column direction in the second gate block GB2 to overlap with the plurality of gate lines GL. The first compensation pattern 130 may extend from the high-potential power line VDDL in the row direction and may be integrally formed with the high-potential power line VDDL. Therefore, the first compensation pattern can function as the high-potential power line, and the high-potential power line can also function as the first compensation pattern.

[0148] The first compensation pattern 130 may be formed to have a constant width from the upper end to the lower end of the second gate block GB2. The width of the high-potential power line VDDL and the first compensation pattern 130 in the second gate block GB2 of the second area A2 may be greater than the width of the high-potential power line VDDL in the second gate block GB2 of the first area A1. In other words, the area where the high-potential power line VDDL and the first compensation pattern 130 in the second gate block GB2 of the second area A2 overlap with the plurality of gate lines GL may be greater than the area where the high-potential power line VDDL in the second gate block GB2 of the first area A1 overlaps with the plurality of gate lines GL.

[0149] Figure 10 It is along Figure 9 A cross-sectional view taken along line VIII-VIII'. Figure 10 In the embodiment, for the convenience of description, only the substrate 110, the buffer layer 111, the gate insulating layer 112, the gate line GL, the first interlayer insulating layer 113, the second interlayer insulating layer 114, the first compensation pattern 130, the first planarization layer 115 and the second planarization layer 116 are shown. Hereinafter, the remaining configuration except for the gate line GL and the first compensation pattern 130 is the same as Figure 4 The configuration is the same as that of , so detailed description will be omitted.

[0150] Reference Figure 10 , the gate line GL may be disposed on the gate insulating layer 112 .

[0151] The gate line GL may be formed on the same layer and with the same material as the first gate electrode GE1 of the first transistor T1. For example, the gate line GL may be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0152] The first compensation pattern 130 may be disposed on the second interlayer insulating layer 114 .

[0153] The first compensation pattern 130 may be disposed on the second interlayer insulating layer 114 so as to overlap the gate line GL. The first compensation pattern 130 may be formed on the same layer using the same material as the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1. For example, the first compensation pattern 130 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0154] In related-art display devices, the substrate is configured as a rectangular substrate without a side having a special-shaped structure, so that the output characteristics of the gate signal outputted from the gate driver are the same at all locations in the active area. However, in the case of a special-shaped display device in which at least one or more of the four sides of the substrate have a special-shaped structure rather than a rectangular substrate, the output characteristics of the gate signal are the same in the areas without the special-shaped structure. However, in the areas with the special-shaped structure, the output characteristics of the gate signal vary compared to the areas without the special-shaped structure, resulting in uneven brightness.

[0155] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the active area AA is divided into a plurality of first areas A1 and at least one second area A2, which is arranged to correspond to the notch area. In each of the first and second areas A1 and A2, a plurality of gate blocks GB1 and GB2 are provided, each of which has a gate driver separately provided. In the second area A2, which is smaller than the first area A1 due to the notch area, a smaller number of gate blocks GB1 and GB2 are provided than in the first area A1, resulting in different gate signal output characteristics. Therefore, a first compensation pattern 130 is provided in at least one of the plurality of gate blocks GB1 and GB2 provided in the second area A2, so that the first compensation pattern 130 overlaps with the gate line GL, forming a capacitor between the gate line GL and the first compensation pattern 130. This compensates for the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 provided in the second area A2. That is, the output characteristics of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second area A2 can be equal to the output characteristics of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the first area A1. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the RC delay of the gate signal that is changed due to the profiled structure is compensated to be equal to the RC delay in the area without the profiled structure, thereby reducing brightness unevenness and improving display quality.

[0156] Furthermore, when a compensation pattern for compensating for RC delay deviation caused by a gate driver outputting a gate signal and a special-shaped structure is provided in the inactive region, there is a problem of increasing the area of ​​the inactive region, thereby increasing the border region.

[0157] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, a plurality of gate blocks GB1 and GB2, in which the gate driver is separately provided, are distributed in the active area AA. Furthermore, a first compensation pattern 130 for compensating for RC delay deviation is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 provided in the second area A2, thereby reducing or minimizing the area of ​​the non-active area NA. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the gate driver and the first compensation pattern 130 are provided in the active area to reduce or minimize the border area.

[0158] Figure 11 FIG. 1 is an enlarged plan view of one of the gate blocks of a display device according to another exemplary embodiment of the present disclosure. Figure 11 , a portion of a second gate block GB2 among a plurality of gate blocks GB of a display device 200 according to another exemplary embodiment of the present disclosure is enlarged.

[0159] Reference Figure 11 In the second gate block GB2 disposed in the second area A2, a high potential power line VDDL, a first compensation pattern 230, and a plurality of gate lines GL may be disposed.

[0160] The high potential power line VDDL extends in the column direction in the second gate block GB2 to intersect the plurality of gate lines GL.

[0161] The first compensation pattern 230 extends in the column direction in the second gate block GB2 to overlap with the plurality of gate lines GL. The first compensation pattern 230 may extend from the high-potential power line VDDL in the row direction and may be integrally formed with the high-potential power line VDDL. Therefore, the first compensation pattern can function as the high-potential power line, and the high-potential power line can also function as the first compensation pattern.

[0162] The first compensation pattern 230 may be formed to have a constant width from the upper end to the lower end of the second gate block GB2. The width of the high-potential power line VDDL and the first compensation pattern 230 in the second gate block GB2 of the second area A2 may be greater than the width of the high-potential power line VDDL in the second gate block GB2 of the first area A1. In other words, the area where the high-potential power line VDDL and the first compensation pattern 230 overlap with the plurality of gate lines GL in the second gate block GB2 of the second area A2 may be greater than the area where the high-potential power line VDDL and the first compensation pattern 230 overlap with the plurality of gate lines GL in the second gate block GB2 of the first area A1.

[0163] A plurality of gate lines GL extend in the row direction in the second gate block GB2 and are spaced apart from each other in the column direction so as to be arranged in parallel. The width of the portions of the plurality of gate lines GL that overlap with the first compensation pattern 230 may be greater than the width of the portions of the plurality of gate lines GL that do not overlap with the first compensation pattern 230. For example, the width of the portions of the plurality of gate lines GL that overlap with the high-potential power supply line VDDL and the first compensation pattern 230 may be greater than the width of the portions that do not overlap with the high-potential power supply line VDDL and the first compensation pattern 230. For example, the portions of the plurality of gate lines GL that have a larger width may be portions formed by extending the portions of the plurality of gate lines GL that overlap with the high-potential power supply line VDDL and the first compensation pattern 230 in the column direction.

[0164] In addition, the portions of the plurality of gate lines GL having a larger width may vary depending on the output of the gate driver connected to each gate line GL. For example, when the output of the gate driver connected to one gate line GL is greater than the output of the gate driver connected to another gate line GL, the width of the portion of the one gate line GL that overlaps the high-potential power line VDDL and the first compensation pattern 230 may be greater than the width of the portion of the other gate line GL that overlaps the high-potential power line VDDL and the first compensation pattern 230.

[0165] In a display device 200 according to another exemplary embodiment of the present disclosure, a first compensation pattern 230 is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 disposed in a second area A2, such that the first compensation pattern 230 overlaps the gate line GL. Consequently, a capacitor is formed between the gate line GL and the first compensation pattern 230 to compensate for the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second area A2. Therefore, in the display device 200 according to another exemplary embodiment of the present disclosure, the RC delay of the gate signal, which is altered by the profiled structure, is compensated to be equal to the RC delay in an area without the profiled structure, thereby reducing brightness unevenness and improving display quality.

[0166] Therefore, in a display device 200 according to another exemplary embodiment of the present disclosure, a plurality of gate blocks GB1 and GB2, in which a gate driver is separately provided, are distributed in the active area AA. Furthermore, a first compensation pattern 230 for compensating for RC delay deviation is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 provided in the second area A2, thereby reducing or minimizing the area of ​​the non-active area NA. Therefore, in a display device 200 according to another exemplary embodiment of the present disclosure, the gate driver and the first compensation pattern 230 are provided in the active area to reduce or minimize the border area.

[0167] In a display device 200 according to another exemplary embodiment of the present disclosure, the width of the portion of the plurality of gate lines GL that overlaps with the first compensation pattern 230 can be greater than the width of the portion of the plurality of gate lines GL that does not overlap with the first compensation pattern 230. In this case, the width of the portion overlapping with the first compensation pattern 230 can be designed differently depending on the output of the gate driver to which the gate lines GL are connected. Therefore, RC delay can be compensated based on the output characteristics of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second area A2. Therefore, in the display device 200 according to another exemplary embodiment of the present disclosure, RC delay can be compensated based on the output of the gate driver to which the gate lines GL are connected, thereby increasing design freedom and improving display quality.

[0168] Figure 12 is an enlarged plan view of one of the gate blocks of a display device according to still another exemplary embodiment of the present disclosure.

[0169] exist Figure 12 , a portion of the second gate block GB2 among the plurality of gate blocks GB of the display device 300 according to still another exemplary embodiment of the present disclosure is enlarged.

[0170] Reference Figure 12 In the second gate block GB2 disposed in the second area A2, a high potential power line VDDL, a first compensation pattern 230, and a plurality of gate lines GL may be disposed.

[0171] The plurality of gate lines GL extend in a row direction in the second gate block GB2 and are spaced apart from each other in a column direction to be disposed in parallel. The plurality of gate lines GL may have a constant width.

[0172] The high potential power line VDDL extends in the column direction in the second gate block GB2 to intersect the plurality of gate lines GL. The high potential power line VDDL may be formed to have a constant width from the upper end to the lower end of the second gate block GB2.

[0173] The first compensation pattern 330 extends in the column direction in the second gate block GB2 to overlap the plurality of gate lines GL. The first compensation pattern 330 may extend in the row direction from the high potential power line VDDL and may be integrally formed with the high potential power line VDDL.

[0174] The widths of the high-potential power line VDDL and the first compensation pattern 230 disposed in the second gate block GB2 of the second area A2 may be greater than the widths of the high-potential power line VDDL disposed in the second gate block GB2 of the first area A1. That is, the area over which the high-potential power line VDDL and the first compensation pattern 230 disposed in the second gate block GB2 of the second area A2 overlap with the plurality of gate lines GL may be greater than the area over which the high-potential power line VDDL and the first compensation pattern 230 disposed in the second gate block GB2 of the second area A2 overlap with the plurality of gate lines GL.

[0175] In addition, the width of the first compensation pattern 330 may vary depending on the position. The high potential power line VDDL is constant, so that the total width of the high potential power line VDDL and the first compensation pattern 330 may vary depending on the position. The width of the first compensation pattern 330 may vary according to the output of the gate driver to which each gate line GL is connected. For example, when the output of the gate driver connected to one gate line GL is greater than the output of the gate driver connected to another gate line GL, the width of the first compensation pattern 330 overlapping with the corresponding gate line GL may be greater than the width of the first compensation pattern 330 overlapping with the other gate line GL. Although in Figure 12 3 shows that the widths of the high potential power line VDDL and the first compensation pattern 330 are narrower toward the bottom and toward the center, but is not limited thereto.

[0176] Therefore, in a display device 300 according to another exemplary embodiment of the present disclosure, a first compensation pattern 330 is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 disposed in the second area A2, so that the first compensation pattern 330 overlaps with the gate line GL to form a capacitor between the gate line GL and the first compensation pattern 330. Therefore, the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second area A2 can be compensated. Therefore, in the display device 300 according to another exemplary embodiment of the present disclosure, the RC delay of the gate signal, which is changed due to the profiled structure, is compensated to be equal to the RC delay in an area without the profiled structure, thereby reducing brightness unevenness and improving display quality.

[0177] Therefore, in a display device 300 according to another exemplary embodiment of the present disclosure, a plurality of gate blocks GB1 and GB2, in which a gate driver is separately provided, are distributed in the active area AA. Furthermore, a first compensation pattern 330 for compensating for RC delay deviation is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 provided in the second area A2, thereby reducing or minimizing the area of ​​the non-active area NA. Therefore, in a display device 300 according to another exemplary embodiment of the present disclosure, the gate driver and the first compensation pattern 330 are provided in the active area to reduce or minimize the border area.

[0178] In a display device 300 according to another exemplary embodiment of the present disclosure, the plurality of gate lines GL have a constant width, and the width of the first compensation pattern 330 overlapping the plurality of gate lines GL can vary depending on the position. Therefore, capacitors can be formed in various forms between the gate lines GL and the first compensation pattern 330, thereby compensating for RC delay based on the output characteristics of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second area A2. Therefore, in the display device 300 according to another exemplary embodiment of the present disclosure, RC delay can be compensated based on the output of the gate driver to which the gate lines GL are connected, thereby increasing design freedom and improving display quality.

[0179] Figure 13 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figure 13, for the convenience of description, among the various components of the display device 400 according to the exemplary embodiment of the present disclosure, only the substrate 410, the first transistor T1, the storage capacitor Cst, the first buffer layer 411, the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second transistor T2, the second gate insulating layer 415, the second interlayer insulating layer 416, the first planarization layer 417, the connecting electrode CE, the second planarization layer 418, the light emitting diode 420, the embankment layer 419 and the spacer 419a are shown.

[0180] Reference Figure 13 According to another exemplary embodiment of the present disclosure, a display device 400 includes a substrate 410, a first transistor T1, a storage capacitor Cst, a first buffer layer 411, a first gate insulating layer 412, a first interlayer insulating layer 413, a second buffer layer 414, a second transistor T2, a second gate insulating layer 415, a second interlayer insulating layer 416, a first planarization layer 417, a connecting electrode CE, a second planarization layer 418, a light emitting diode 420 and a dam layer 419.

[0181] The substrate 410 is a base member that supports various components of the display device 400 and may be made of an insulating material. For example, the substrate may be formed of glass or a plastic material, but is not limited thereto.

[0182] A first buffer layer 411 may be provided on the substrate 410. The first buffer layer 411 may be formed over the entire surface of the substrate 410. The first buffer layer 411 may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The first buffer layer 411 may enhance adhesion between layers formed on the first buffer layer 411 and the substrate 410. The first buffer layer 411 is not a required component and may be omitted based on the type or material of the substrate 410 and the structure and type of the transistor.

[0183] The first transistor T1 may be disposed on the first buffer layer 411 . The first transistor T1 may include a first active layer ACT1 , a first gate electrode GE1 , a first source electrode SE1 , and a first drain electrode DE1 . The first active layer ACT1 of the first transistor T1 may be disposed on the first buffer layer 411 .

[0184] The first active layer ACT1 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0185] A first gate insulating layer 412 may be provided on the first active layer ACT1 of the first transistor T1. The first gate insulating layer 412 may be configured as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. A contact hole may be formed in the first gate insulating layer 412, through which each of the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1 is connected to the first active layer ACT1 of the first transistor T1.

[0186] The first gate electrode GE1 of the first transistor T1 may be disposed on the first gate insulating layer 412. The first gate electrode GE1 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof. The first gate electrode GE1 may be formed on the first gate insulating layer 412 to overlap with the first active layer ACT1 of the first transistor T1.

[0187] A first interlayer insulating layer 413 may be disposed on the first gate insulating layer 412 and the first gate electrode GE1. The first interlayer insulating layer 413 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. A contact hole may be formed in the first interlayer insulating layer 413 to expose the first active layer ACT1 of the first transistor T1.

[0188] A second buffer layer 414 may be provided on the first interlayer insulating layer 413. The second buffer layer 414 may be formed over the entire surface of the substrate 410. The second buffer layer 414 may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). A contact hole may be formed in the second buffer layer 414 to expose the first active layer ACT1 of the first transistor T1.

[0189] The second transistor T2 may be disposed on the second buffer layer 414 . The second transistor T2 may include a second active layer ACT2 , a second gate electrode GE2 , a second source electrode SE2 , and a second drain electrode DE2 . The second active layer ACT2 of the second transistor T2 may be disposed on the second buffer layer 414 .

[0190] The second active layer ACT2 may be formed of an oxide semiconductor. For example, the second active layer ACT2 may be formed of a metal oxide, such as various metal oxides such as indium gallium zinc oxide (IGZO). While the second active layer ACT2 of the second transistor T2 is formed of IGZO, among various metal oxides, the active layer is described as being formed based on an IGZO layer, but the present invention is not limited thereto. Therefore, in addition to IGZO, the active layer may be formed of other metal oxides such as indium zinc oxide (IZO), indium gallium tin oxide (IGTO), or indium gallium oxide (IGO).

[0191] A second gate insulating layer 415 may be provided on the second active layer ACT2 of the second transistor T2. The second gate insulating layer 415 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. A contact hole may be formed in the second gate insulating layer 415, through which each of the second source electrode SE2 and the second drain electrode DE2 of the second transistor T2 is connected to the second active layer ACT2 of the second transistor T2.

[0192] The second gate electrode GE2 of the second transistor T2 may be disposed on the second gate insulating layer 415. The second gate electrode GE2 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof. The second gate electrode GE2 may be formed on the second gate insulating layer 415 to overlap with the second active layer ACT2 of the second transistor T2. Contact holes may be formed in the second gate insulating layer 415 to expose the first active layer ACT1 of the first transistor T1 and the second active layer ACT2 of the second transistor T2.

[0193] A second interlayer insulating layer 416 may be disposed on the second gate insulating layer 415 and the second gate electrode GE2. The second interlayer insulating layer 416 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. Contact holes may be formed in the second interlayer insulating layer 416 to expose the first active layer ACT1 of the first transistor T1 and the second active layer ACT2 of the second transistor T2.

[0194] A first source electrode SE1 and a first drain electrode DE1 of the first transistor T1 and a second source electrode SE2 and a second drain electrode DE2 of the second transistor T2 may be disposed on the second interlayer insulating layer 416 .

[0195] The first source electrode SE1 and the first drain electrode DE1 of the first transistor T1 may be connected to the first active layer ACT1 of the first transistor T1 through contact holes formed in the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second gate insulating layer 415, and the second interlayer insulating layer 416. Therefore, the first source electrode SE1 of the first transistor T1 may be connected to the first source region of the first active layer ACT1 through the contact hole formed in the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second gate insulating layer 415, and the second interlayer insulating layer 416. The first drain electrode DE1 of the first transistor T1 may be connected to the first drain region of the first active layer ACT1 through the contact hole formed in the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second gate insulating layer 415, and the second interlayer insulating layer 416.

[0196] The second source electrode SE2 and the second drain electrode DE2 of the second transistor T2 may be connected to the second active layer ACT2 of the second transistor T2 through contact holes formed in the second gate insulating layer 415 and the second interlayer insulating layer 416. Therefore, the second source electrode SE2 of the second transistor T2 may be connected to the second source region of the second active layer ACT2 through the contact holes formed in the second gate insulating layer 415 and the second interlayer insulating layer 416. Furthermore, the second drain electrode DE2 of the second transistor T2 may be connected to the second drain region of the second active layer ACT2 through contact holes formed in the second gate insulating layer 415 and the second interlayer insulating layer 416.

[0197] The storage capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2 .

[0198] The first capacitor electrode Cst1 may be disposed on the gate insulating layer 112. The first capacitor electrode Cst1 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof. The first capacitor electrode Cst1 may be formed of the same material as the first gate electrode GE1, but is not limited thereto.

[0199] The second capacitor electrode Cst2 may be provided on the first interlayer insulating layer 113. The second capacitor electrode Cst2 may be provided on the first interlayer insulating layer 113 to overlap with the first capacitor electrode Cst1. For example, the second capacitor electrode Cst2 may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0200] A passivation layer may be provided on the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1, the second source electrode SE2 and the second drain electrode DE2 of the second transistor T2, and the second interlayer insulating layer 416. The passivation layer is an insulating layer that protects the elements thereunder and may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0201] A first planarization layer 417 may be provided on the second interlayer insulating layer 416. The first planarization layer 417 is provided to reduce steps of the lower structure. The first planarization layer may be formed of an organic material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, or photoresist.

[0202] A connection electrode CE may be provided on the first planarization layer 417. The connection electrode CE may be electrically connected to each of the first drain electrode DE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2 through a contact hole formed in the first planarization layer 417. The connection electrode CE may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0203] A second planarization layer 418 may be provided on the connection electrode CE and the first planarization layer 417. The second planarization layer 418 is provided to reduce the step of the lower structure. The second planarization layer may be formed of an organic material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, or photoresist.

[0204] A light emitting diode 420 may be disposed on the second planarization layer 418. The light emitting diode 420 may include a first electrode 421, a light emitting structure 422, and a second electrode 423.

[0205] The first electrode 421 may be disposed on the second planarization layer 418. The first electrode 421 is an anode electrode and may be electrically connected to the first drain electrode DE1 of the first transistor T1 through a contact hole.

[0206] A bank layer 419 may be disposed on the first electrode 421 and the second planarization layer 418 .

[0207] An opening may be formed in the bank layer 419 to expose the first electrode 421. Since the bank layer 419 may define the light-emitting region of the display device 400, the bank layer 419 may also be referred to as a pixel-defining layer. The bank layer 419 may be formed of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0208] A spacer 419a may be further provided on the bank layer 419. The spacer 419a may be used to support the mask when aligning the mask on the bank layer 419 during the process of depositing the first electrode 421. The spacer 419a may be integrally formed with the bank layer 419. The spacer 419a may be formed of an organic material such as, but not limited to, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, benzocyclobutene, or a photoresist.

[0209] A light-emitting structure 422 may be disposed on the first electrode 421. The light-emitting structure 422 may include a material that emits light of a specific color. For example, the light-emitting structure 422 may include a light-emitting material that emits any one of red, green, and blue light. Specifically, the light-emitting structure 422 may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). Depending on the structure or characteristics of the display device 400, some components of the light-emitting structure 422 may be omitted.

[0210] A second electrode 423 may be further provided on the light emitting structure 422, the bank layer 419, and the spacer 419a. The second electrode 423 is a cathode electrode and may be provided on the light emitting structure 422 to face the first electrode 421 with the light emitting structure 422 interposed therebetween. The second electrode 423 provides electrons to the light emitting structure 422. The second electrode 423 may be formed of a transparent conductive oxide such as indium tin oxide or indium zinc oxide, or a transparent conductive material such as ytterbium (Yb), but is not limited thereto.

[0211] Figure 14 is a cross-sectional view of one of the gate blocks of a display device according to still another exemplary embodiment of the present disclosure. Figure 14 is a cross-sectional view of a second gate block GB2 among the gate blocks GB of a display device 400 according to still another exemplary embodiment of the present disclosure. Figure 14 Is along with Figure 10 Cross-section at the same location.

[0212] exist Figure 14, for the convenience of description, only the substrate 410, the first buffer layer 411, the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second gate insulating layer 415, the gate line GL, the second interlayer insulating layer 416, the first compensation pattern 430, the first planarization layer 417 and the second planarization layer 418 are shown. Hereinafter, the remaining configuration except for the gate line GL and the first compensation pattern 430 is the same as Figure 11 The configuration is the same as that of , so detailed description will be omitted.

[0213] Reference Figure 14 , the gate line GL may be disposed on the second gate insulating layer 415 .

[0214] The gate line GL may be formed on the same layer and with the same material as the second gate electrode GE2 of the second transistor T2. For example, the gate line GL may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0215] The first compensation pattern 430 may be disposed on the second interlayer insulating layer 416 .

[0216] The first compensation pattern 430 may be disposed on the second interlayer insulating layer 416 so as to overlap the gate line GL. The first compensation pattern 430 overlaps the gate line GL to form a capacitor between the gate line GL and the first compensation pattern. The first compensation pattern 430 may be formed on the same layer using the same material as the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1, and the second source electrode SE2 and the second drain electrode DE2 of the second transistor T2. For example, the first compensation pattern 430 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0217] Therefore, in a display device 400 according to another exemplary embodiment of the present disclosure, a first compensation pattern 430 is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 disposed in the second area A2, so that the first compensation pattern 430 overlaps with the gate line GL to form a capacitor between the gate line GL and the first compensation pattern 430. Therefore, the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second area A2 can be compensated. Therefore, in the display device 400 according to another exemplary embodiment of the present disclosure, the RC delay of the gate signal, which is changed due to the profiled structure, is compensated to be equal to the RC delay in the area without the profiled structure, thereby reducing brightness unevenness and improving display quality.

[0218] Therefore, in a display device 400 according to another exemplary embodiment of the present disclosure, a plurality of gate blocks GB1 and GB2, in which a gate driver is separately provided, are distributed in the active area AA. Furthermore, a first compensation pattern 430 for compensating for RC delay deviation is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 provided in the second area A2, thereby reducing or minimizing the area of ​​the non-active area NA. Therefore, in a display device 400 according to another exemplary embodiment of the present disclosure, the gate driver and the first compensation pattern 430 are provided in the active area to reduce or minimize the border area.

[0219] Figure 15 is an exemplary plan view of a display device according to yet another exemplary embodiment of the present disclosure, and Figure 16 yes Figure 15 A plan view of one of the gate blocks in the fourth region. Figure 17 It is along Figure 16 A cross-sectional view taken along line XV-XV'.

[0220] For ease of description, Figure 15 , among the various components of the display device 500, only the substrate 110 and the plurality of flexible films COF are shown. Figure 15 In addition to the plurality of third areas A3 and the plurality of fourth areas A4 of the effective area AA, the remaining configuration is the same as in Figure 1 The configuration is the same as in , so the detailed description will be omitted.

[0221] Reference Figure 15 , the active area AA may include multiple third areas A3 and multiple fourth areas A4. Each of the multiple third areas A3 and the multiple fourth areas A4 may be an area where gate drivers are distributed. The multiple third areas A3 are areas having a first width in the column direction, and the multiple fourth areas A4 are areas arranged to correspond to the notch areas NTA and having a second width that is smaller than the first width of the multiple third areas A3. For example, the fourth area A4 may be an area having a width in the column direction that is smaller than the width of the third area A3 in the column direction. The multiple third areas A3 may be the remaining areas excluding the fourth areas A4.

[0222] exist Figure 16 In FIG. 1 , only the 1-1 gate block GB1 - 1 among the plurality of gate blocks GB provided in the fourth area A4 is shown. Figure 16 In addition to the clock line CLKL and the second compensation pattern 540, the rest of the configuration is the same as Figure 5 The configuration is the same as in , so the detailed description will be omitted.

[0223] Reference Figure 16The clock line CLKL may be connected to the plurality of gate blocks GB. In the 1-1 gate block GB1-1 among the plurality of gate blocks GB, a clock line CLKL extending in the column direction to transmit a clock signal may be provided. The clock line CLKL may be provided to intersect with the plurality of gate lines GL provided in the row direction.

[0224] The second compensation pattern 540 may overlap the clock line CLKL. The second compensation pattern 540 may be disposed between the plurality of gate lines GL of the 1-1 gate block GB1-1. The second compensation pattern 540 may be disposed below the clock line CLKL and may be disposed to overlap the clock line CLKL. Figure 16 , the second compensation pattern 540 is shown as being positioned below the clock line, but the present invention is not limited thereto. The second compensation pattern 540 may be positioned above the clock line CLKL to overlap the clock line CLKL. For ease of design, the second compensation pattern 540 may be positioned adjacent to the notch area NTA. A constant voltage may be applied to the second compensation pattern 540. For example, the second compensation pattern 540 may be electrically connected to one of the low-potential power supply line VSSL to which a low-potential power supply is applied and the high-potential power supply line VDDL to which a high-potential power supply is applied, thereby receiving either the low-potential power supply or the high-potential power supply.

[0225] In addition, the second compensation pattern 540 has a constant width and the length of the clock line CLKL overlapped with the second compensation pattern may vary according to the position. The second compensation pattern 540 is disposed between the plurality of gate lines GL, the gate low voltage line VGLL, and the gate high voltage line VGHL to have a constant width.

[0226] The length of the clock lines CLKL arranged in the fourth area A4 may be equal to the length of the clock lines CLKL arranged in the third area A3. For example, the clock lines CLKL arranged in the area adjacent to the notch area NTA among the clock lines CLKL arranged in the fourth area A4 may have a zigzag pattern. For example, the portion of the clock lines CLKL arranged in the fourth area A4 that overlaps with the second compensation pattern 540 may have a zigzag pattern. Therefore, even if the width of the fourth area A4 is smaller than the width of the third area A3, the total length of the clock lines CLKL arranged in the fourth area A4 may be equal to the total length of the clock lines CLKL arranged in the third area A3.

[0227] exist Figure 17, for the convenience of description, only the substrate 110, the buffer layer 111, the gate insulating layer 112, the first interlayer insulating layer 113, the second compensation pattern 540, the second interlayer insulating layer 114, the clock line CLKL, the intermediate electrode CEE, the first planarization layer 115 and the third compensation pattern 550 are shown. Hereinafter, the remaining configuration except the second compensation pattern 540, the clock line CLKL, the intermediate electrode CEE and the third compensation pattern 550 is the same as Figure 4 The configuration is the same as in , so the detailed description will be omitted.

[0228] Reference Figure 17 , the second compensation pattern 540 may be disposed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114 .

[0229] The second compensation pattern 540 may be formed on the same layer using the same material as the second capacitor electrode Cst2. For example, the second compensation pattern 540 may be formed as a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0230] A clock line CLKL may be disposed on the second interlayer insulating layer 114 .

[0231] The clock line CLKL may be disposed on the second interlayer insulating layer 114 so as to overlap the second compensation pattern 540. The clock line CLKL may be formed on the same layer using the same material as the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1. For example, the clock line CLKL may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0232] An intermediate electrode CEE may be disposed on the second interlayer insulating layer 114 .

[0233] The intermediate electrode CEE may be disposed on the same layer as the clock line CLKL and may be formed of the same material. The intermediate electrode CEE may be electrically connected to the second compensation pattern 540 through a contact hole formed in the second interlayer insulating layer 114 .

[0234] A third compensation pattern 550 may be disposed on the first planarization layer 115 .

[0235] The third compensation pattern 550 may overlap the clock line CLKL. The third compensation pattern 550 may be electrically connected to the intermediate electrode CEE via a contact hole formed in the first planarization layer 115. The third compensation pattern 550 may be provided on the same layer as the connection electrode CE and may be formed from the same material. For example, the third compensation pattern 550 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0236] That is, the clock line CLKL overlaps the second compensation pattern 540 and the third compensation pattern 550, and the third compensation pattern 550, to which a constant voltage is applied, can be electrically connected to the second compensation pattern 540 through the contact hole and the intermediate electrode CEE. Therefore, a capacitor is formed between the clock line CLKL and the second compensation pattern 540, and a capacitor is formed between the clock line CLKL and the third compensation pattern 550 to delay the clock signal applied to the clock line CLKL.

[0237] Therefore, in a display device 500 according to another exemplary embodiment of the present disclosure, a first compensation pattern 230 is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 disposed in the second area A2, so that the first compensation pattern 230 overlaps with the gate line GL to form a capacitor between the gate line GL and the first compensation pattern 230. Therefore, the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second area A2 can be compensated. Therefore, in the display device 500 according to another exemplary embodiment of the present disclosure, the RC delay of the gate signal, which is changed due to the profiled structure, is compensated to be equal to the RC delay in the area without the profiled structure, thereby reducing brightness unevenness and improving display quality.

[0238] Therefore, in a display device 500 according to another exemplary embodiment of the present disclosure, a plurality of gate blocks GB1 and GB2, in which a gate driver is separately provided, are distributed in the active area AA. Furthermore, a first compensation pattern 230 for compensating for RC delay deviation is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 provided in the second area A2, thereby reducing or minimizing the area of ​​the non-active area NA. Therefore, in a display device 500 according to another exemplary embodiment of the present disclosure, the gate driver and the first compensation pattern 230 are provided in the active area to reduce or minimize the border area.

[0239] In related-art display devices, the substrate is configured as a rectangular substrate without a side having a special-shaped structure, so that the same clock signal is supplied to the gate driver located at the lowest end of the active area. However, in the case of a non-rectangular display device where one or more of the four sides of the substrate have a special-shaped structure, the timing at which the clock signal is supplied to the gate driver located at the lowest end of the third area A3 without the special-shaped structure differs from the timing at which the clock signal is supplied to the gate driver located at the lowest end of the fourth area A3 with the special-shaped structure. Consequently, the problem of uneven brightness arises.

[0240] Therefore, in a display device 500 according to another exemplary embodiment of the present disclosure, the second compensation pattern 540 and the third compensation pattern 550 are arranged to overlap with the clock line CLKL in at least one gate block GB1-1 among the plurality of gate blocks GB located in the fourth area A4. Consequently, a capacitor is formed between the clock line CLKL and the second compensation pattern 540, and a capacitor is formed between the clock line CLKL and the third compensation pattern 550, compensating for the RC delay of the clock signal transmitted via the clock line CLKL located in the fourth area A4. In other words, the clock signal transmitted via the clock line CLKL located in the fourth area A4 and the clock signal transmitted via the clock line CLKL located in the third area A3 can be transmitted equally to the respective gate drivers. Therefore, in the display device 500 according to another exemplary embodiment of the present disclosure, the RC delay differences of the clock signals according to the regions caused by the heterogeneous structure are compensated to be equal, thereby reducing brightness unevenness and improving display quality.

[0241] Figure 18 is a cross-sectional view of one of the gate blocks of a display device according to still another exemplary embodiment of the present disclosure.

[0242] Figure 18 is a cross-sectional view of a 1-1th gate block GB1 - 1 among the gate blocks GB of a display device 600 according to yet another exemplary embodiment of the present disclosure. Figure 18 Is along with Figure 17 Cross-section view of the same location.

[0243] exist Figure 18 , for ease of description, only the substrate 410, the first buffer layer 411, the first gate insulating layer 412, the first interlayer insulating layer 413, the second buffer layer 414, the second gate insulating layer 415, the second compensation pattern 640, the second interlayer insulating layer 416, the clock line CLKL, the intermediate electrode CEE, the first planarization layer 417, and the third compensation pattern 650 are shown. Hereinafter, the remaining configuration except for the second compensation pattern 640, the clock line CLKL, the intermediate electrode CEE, and the third compensation pattern 650 is the same as Figure 11The configuration is the same as in , so the detailed description will be omitted.

[0244] Reference Figure 18 , the second compensation pattern 640 may be disposed on the second gate insulating layer 415 .

[0245] The second compensation pattern 640 may be provided on the same layer as the second gate electrode GE2 of the second transistor T2 and may be formed of the same material. For example, the second compensation pattern 640 may be formed as a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0246] A clock line CLKL and an intermediate electrode CEE may be disposed on the second interlayer insulating layer 416 .

[0247] The clock line CLKL may be disposed on the second interlayer insulating layer 416 so as to overlap with the second compensation pattern 640. The clock line CLKL overlaps with the second compensation pattern 640 to form a capacitor between the second compensation pattern 640 and the clock line CLKL. The clock line CLKL may be disposed on the same layer as the first source electrode SE1 and the first drain electrode DE1 of the first transistor T1, and the second source electrode SE2 and the second drain electrode DE2 of the second transistor T2, and may be formed of the same material. For example, the clock line CLKL may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0248] The intermediate electrode CEE may be disposed on the same layer as the clock line CLKL and may be formed of the same material. The intermediate electrode CEE may be electrically connected to the second compensation pattern 640 through a contact hole formed in the second interlayer insulating layer 416 .

[0249] A third compensation pattern 650 may be disposed on the first planarization layer 417 .

[0250] The third compensation pattern 650 may overlap the clock line CLKL. The third compensation pattern 650 may be electrically connected to the intermediate electrode CEE via a contact hole formed in the first planarization layer 417. The third compensation pattern 650 may be provided on the same layer as the connection electrode CE and may be formed from the same material. For example, the third compensation pattern 650 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0251] That is, the clock line CLKL overlaps the second compensation pattern 640 and the third compensation pattern 650, and the third compensation pattern 650, to which a constant voltage is applied, can be electrically connected to the second compensation pattern 640 through the contact hole and the intermediate electrode CEE. Therefore, a capacitor is formed between the clock line CLKL and the second compensation pattern 640, and a capacitor is formed between the clock line CLKL and the third compensation pattern 650 to delay the clock signal applied through the clock line CLKL.

[0252] Therefore, in a display device 600 according to another exemplary embodiment of the present disclosure, a first compensation pattern 230 is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 disposed in the second area A2, so that the first compensation pattern 230 overlaps with the gate line GL to form a capacitor between the gate line GL and the first compensation pattern 230. Therefore, the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second area A2 can be compensated. Therefore, in the display device 600 according to another exemplary embodiment of the present disclosure, the RC delay of the gate signal, which is changed due to the profiled structure, is compensated to be equal to the RC delay in the area without the profiled structure, thereby reducing brightness unevenness and improving display quality.

[0253] Therefore, in a display device 600 according to another exemplary embodiment of the present disclosure, a plurality of gate blocks GB1 and GB2, in which a gate driver is separately provided, are distributed in the active area AA. Furthermore, a first compensation pattern 230 for compensating for RC delay deviation is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 provided in the second area A2, thereby reducing or minimizing the area of ​​the non-active area NA. Therefore, in a display device 600 according to another exemplary embodiment of the present disclosure, the gate driver and the first compensation pattern 230 are provided in the active area to reduce or minimize the border area.

[0254] Therefore, in a display device 600 according to another exemplary embodiment of the present disclosure, the second compensation pattern 640 and the third compensation pattern 650 are arranged to overlap with the clock line CLKL in at least one gate block GB1-1 among the plurality of gate blocks GB located in the fourth area A4. Consequently, a capacitor is formed between the clock line CLKL and the second compensation pattern 640, and a capacitor is formed between the clock line CLKL and the third compensation pattern 650, compensating for the RC delay of the clock signal transmitted via the clock line CLKL located in the fourth area A4. In other words, the clock signal transmitted via the clock line CLKL located in the fourth area A4 and the clock signal transmitted via the clock line CLKL located in the third area A3 can be equally transmitted to the respective gate drivers. Therefore, in the display device 600 according to another exemplary embodiment of the present disclosure, the RC delay differences of the clock signals according to the regions due to the heterogeneous structure are compensated to be equal, thereby reducing brightness unevenness and improving display quality.

[0255] Figure 19 is a cross-sectional view of one of the gate blocks of a display device according to still another exemplary embodiment of the present disclosure.

[0256] Figure 19 is a cross-sectional view of a 1-1th gate block GB1 - 1 among the gate blocks GB of a display device 700 according to yet another exemplary embodiment of the present disclosure. Figure 19 Is along with Figure 17 Cross-section view of the same location.

[0257] exist Figure 19 , for ease of description, only the substrate 410, the first buffer layer 411, the first gate insulating layer 412, the first interlayer insulating layer 413, the fourth compensation pattern 760, the second buffer layer 414, the second gate insulating layer 415, the second compensation pattern 640, the second interlayer insulating layer 416, the clock line CLKL, the middle electrode CEE, the first planarization layer 417, and the third compensation pattern 650 are shown. Hereinafter, the remaining configuration except for the fourth compensation pattern 760 is the same as that in Figure 16 The configuration is the same as in , so detailed description is omitted.

[0258] Reference Figure 19 , the fourth compensation pattern 760 may be disposed between the first interlayer insulating layer 413 and the second compensation pattern 640 .

[0259] The fourth compensation pattern 760 may be disposed between the first interlayer insulating layer 413 and the second buffer layer 414. The fourth compensation pattern 760 may be disposed to overlap the second compensation pattern 640. The fourth compensation pattern 760 may be electrically connected to the second compensation pattern 640 through a contact hole formed in the second buffer layer 414.

[0260] The fourth compensation pattern 760 may be provided on the same layer as the second capacitor electrode Cst2 of the storage capacitor Cst and may be formed of the same material. For example, the second capacitor electrode Cst2 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0261] That is, the clock line CLKL may overlap with the second compensation pattern 640, the third compensation pattern 650, and the fourth compensation pattern 760. The third compensation pattern 650, to which a constant voltage is applied, may be electrically connected to the fourth compensation pattern 760 through the contact hole, the intermediate electrode CEE, and the second compensation pattern 640. Therefore, a capacitor is formed between the clock line CLKL and the second compensation pattern 640, a capacitor is formed between the clock line CLKL and the third compensation pattern 650, and a capacitor is formed between the clock line CLKL and the fourth compensation pattern 760 to delay the clock signal applied through the clock line CLKL.

[0262] Therefore, in a display device 700 according to another exemplary embodiment of the present disclosure, a first compensation pattern 230 is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 disposed in the second area A2, so that the first compensation pattern 230 overlaps with the gate line GL to form a capacitor between the gate line GL and the first compensation pattern 230. Therefore, the RC delay of the gate signals output from the plurality of gate blocks GB1 and GB2 disposed in the second area A2 can be compensated. Therefore, in the display device 700 according to another exemplary embodiment of the present disclosure, the RC delay of the gate signal, which is changed due to the profiled structure, is compensated to be equal to the RC delay in the area without the profiled structure, thereby reducing brightness unevenness and improving display quality.

[0263] Therefore, in a display device 700 according to another exemplary embodiment of the present disclosure, a plurality of gate blocks GB1 and GB2, in which a gate driver is separately provided, are distributed in the active area AA. Furthermore, a first compensation pattern 230 for compensating for RC delay deviation is provided in at least one gate block GB2 among the plurality of gate blocks GB1 and GB2 provided in the second area A2, thereby reducing or minimizing the area of ​​the non-active area NA. Therefore, in a display device 700 according to another exemplary embodiment of the present disclosure, the gate driver and the first compensation pattern 230 are provided in the active area to reduce or minimize the border area.

[0264] Therefore, in a display device 700 according to another exemplary embodiment of the present disclosure, the second compensation pattern 640, the third compensation pattern 650, and the fourth compensation pattern 760 are arranged to overlap with the clock line CLKL in at least one gate block GB1-1 among the plurality of gate blocks GB located in the fourth area A4. Consequently, a capacitor is formed between the clock line CLKL and the second compensation pattern 640, between the clock line CLKL and the third compensation pattern 650, and between the clock line CLKL and the fourth compensation pattern 760. Consequently, the RC delay of the clock signal transmitted via the clock line CLKL located in the fourth area A4 can be compensated. That is, the clock signal transmitted via the clock line CLKL located in the fourth area A4 and the clock signal transmitted via the clock line CLKL located in the third area A3 can be equally transmitted to the respective gate drivers. Therefore, in the display device 700 according to another exemplary embodiment of the present disclosure, the RC delay differences of the clock signals according to the regions caused by the heterogeneous structure are compensated to be equal, thereby reducing brightness unevenness and improving display quality.

[0265] The display device according to the exemplary embodiment of the present disclosure may also be described as follows:

[0266] According to an exemplary embodiment of the present disclosure, a display device includes: a substrate, the substrate including an active area having a special-shaped edge, an inactive area surrounding the active area, and a gap area defined by the shape of the special-shaped edge of the active area; a gate driver, the gate driver including a plurality of gate blocks arranged to be distributed in the active area and output gate signals; a plurality of gate lines, the plurality of gate lines being connected to the plurality of gate blocks to transmit the gate signals; and a first compensation pattern, the first compensation pattern being arranged in at least one of the plurality of gate blocks and overlapping with the plurality of gate lines.

[0267] The active area may include: a plurality of first areas; and at least one second area having a smaller area than the plurality of first areas and disposed to correspond to the notch area, and the first compensation pattern is disposed in the at least one second area.

[0268] The number of the plurality of gate blocks disposed in the at least one second region may be smaller than the number of the plurality of gate blocks disposed in the plurality of first regions.

[0269] The at least one second region may be disposed adjacent to at least the notch region.

[0270] The display device may further include: a plurality of power lines disposed to intersect the plurality of gate lines, the first compensation pattern extending from the plurality of power lines while being integral with at least one power line of the plurality of power lines.

[0271] Widths of the plurality of power lines and the first compensation pattern in the at least one second region may be greater than widths of the plurality of power lines in the plurality of first regions.

[0272] A width of the first compensation pattern may be constant.

[0273] The width of the first compensation pattern may vary according to location.

[0274] Widths of portions of the plurality of gate lines overlapping the first compensation pattern may be greater than widths of portions of the plurality of gate lines not overlapping the first compensation pattern.

[0275] The display device may further include: an active layer, which is located on the substrate; a gate insulating layer, which is located on the active layer; a gate electrode, which overlaps with the active layer on the gate insulating layer; a first interlayer insulating layer, which is located on the gate electrode; a second interlayer insulating layer, which is located on the first interlayer insulating layer; a source electrode and a drain electrode, which are arranged on the second interlayer insulating layer and electrically connected to the active layer; a first planarization layer, which is located on the source electrode and the drain electrode; a connecting electrode, which is arranged on the first planarization layer and electrically connected to one of the source electrode and the drain electrode; a second planarization layer, which is located on the connecting electrode; and a light-emitting diode, which is arranged on the second planarization layer, the multiple gate lines and the gate electrode are arranged on the same layer, and the first compensation pattern and the source electrode and the drain electrode are arranged on the same layer.

[0276] The display device may further include: a first active layer, the first active layer being located on the substrate; a first gate insulating layer, the first gate insulating layer being located on the first active layer; a first gate electrode, the first gate electrode being overlapped with the first active layer on the first gate insulating layer; a first interlayer insulating layer, the first interlayer insulating layer being located on the first gate electrode; a second active layer, the second active layer being located on the first interlayer insulating layer; a second gate insulating layer, the second gate insulating layer being located on the second active layer; a second gate electrode, the second gate electrode being overlapped with the second active layer on the second gate insulating layer; a second interlayer insulating layer, the second interlayer insulating layer being located on the second gate electrode; a first source electrode and a first drain electrode, the first source electrode and the first drain electrode being arranged on the second interlayer insulating layer and electrically connected to the first active layer An active layer; a second source electrode and a second drain electrode, the second source electrode and the second drain electrode are arranged on the second interlayer insulating layer and electrically connected to the second active layer; a first planarization layer, the first planarization layer is located on the first source electrode, the first drain electrode, the second source electrode and the second drain electrode; a connecting electrode, the connecting electrode is arranged on the first planarization layer and electrically connected to one of the first source electrode and the first drain electrode; a second planarization layer, the second planarization layer is located on the connecting electrode; and a light-emitting diode, the light-emitting diode is arranged on the second planarization layer, the multiple gate lines and the second gate electrode are arranged on the same layer, and the first compensation pattern and the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are arranged on the same layer.

[0277] The active area may include: a third area having a first width in a column direction; and a fourth area having a second width smaller than the first width in the column direction, and the display device may further include a second compensation pattern disposed in the fourth area.

[0278] The display device may further include a clock line connected to the plurality of gate blocks and intersecting the plurality of gate lines, the second compensation pattern overlapping the clock line.

[0279] The display device may further include: a third compensation pattern overlapping the clock line.

[0280] A width of the second compensation pattern may be constant, and a length of the clock line may differ according to a location.

[0281] The clock line may have a zigzag pattern.

[0282] The display device may further include: an active layer, which is located on the substrate; a gate insulating layer, which is located on the active layer; a gate electrode, which overlaps with the active layer on the gate insulating layer; a first interlayer insulating layer, which is located on the gate electrode; a second interlayer insulating layer, which is located on the first interlayer insulating layer; a source electrode and a drain electrode, which are arranged on the second interlayer insulating layer and electrically connected to the active layer; a first planarization layer, which is located on the source electrode and the drain electrode; a connecting electrode, which is arranged on the first planarization layer and electrically connected to one of the source electrode and the drain electrode; a second planarization layer, which is located on the connecting electrode; and a light-emitting diode, which is arranged on the second planarization layer, the second compensation pattern is arranged between the first interlayer insulating layer and the second interlayer insulating layer, and the third compensation pattern is arranged on the same layer as the connecting electrode.

[0283] The display device may further include: a first active layer, the first active layer being located on the substrate; a first gate insulating layer, the first gate insulating layer being located on the first active layer; a first gate electrode, the first gate electrode being on the first gate insulating layer and overlapping with the first active layer; a first interlayer insulating layer, the first interlayer insulating layer being located on the first gate electrode; a second active layer, the second active layer being on the first interlayer insulating layer; a second gate insulating layer, the second gate insulating layer being located on the second active layer; a second gate electrode, the second gate electrode being on the second gate insulating layer and overlapping with the second active layer; a second interlayer insulating layer, the second interlayer insulating layer being located on the second gate electrode; a first source electrode and a first drain electrode, the first source electrode and the first drain electrode being disposed on the second interlayer insulating layer on and electrically connected to the first active layer; a second source electrode and a second drain electrode, the second source electrode and the second drain electrode are arranged on the second interlayer insulating layer and electrically connected to the second active layer; a first planarization layer, the first planarization layer is located on the first source electrode, the first drain electrode, the second source electrode and the second drain electrode; a connecting electrode, the connecting electrode is arranged on the first planarization layer and electrically connected to one of the first source electrode and the first drain electrode; a second planarization layer, the second planarization layer is located on the connecting electrode; and a light emitting diode, the light emitting diode is arranged on the second planarization layer, the second compensation pattern is arranged between the first interlayer insulating layer and the second interlayer insulating layer, and the third compensation pattern is arranged on the same layer as the connecting electrode.

[0284] The display device may further include a fourth compensation pattern overlapping the second compensation pattern and disposed between the first interlayer insulating layer and the second compensation pattern.

[0285] Capacitors may be formed between the first compensation pattern and the plurality of gate lines.

[0286] An area where the plurality of power lines and the first compensation pattern overlap with the plurality of gate lines in the at least one second region may be greater than an area where the plurality of power lines overlap with the plurality of gate lines in the plurality of first regions.

[0287] The second compensation pattern may be electrically connected to one of the plurality of power lines.

[0288] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided only for illustrative purposes and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the following claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: a substrate comprising an active area having a special-shaped edge, a non-active area surrounding the active area, and a notch area defined by the shape of the special-shaped edge of the active area; a gate driver including a plurality of gate blocks arranged to be distributed in the active area and output gate signals; a plurality of gate lines connected to the plurality of gate blocks to transmit the gate signals; as well as A first compensation pattern is disposed in at least one of the plurality of gate blocks and overlaps the plurality of gate lines.

2. The display device according to claim 1, wherein the active area comprises: a plurality of first regions; and at least one second region having an area smaller than that of the plurality of first regions and disposed to correspond to the notch region, and The first compensation pattern is disposed in the at least one second region. 3 . The display device according to claim 2 , wherein the number of the plurality of gate blocks disposed in the at least one second region is smaller than the number of the plurality of gate blocks disposed in the plurality of first regions. The display device according to claim 2 , wherein the at least one second region is disposed adjacent to at least the notch region.

5. The display device according to claim 2, further comprising: a plurality of power lines, the plurality of power lines being arranged to intersect the plurality of gate lines, The first compensation pattern extends from the plurality of power lines while being integral with at least one of the plurality of power lines. 6 . The display device of claim 5 , wherein widths of the plurality of power lines and the first compensation pattern in the at least one second region are greater than widths of the plurality of power lines in the plurality of first regions. The display device of claim 5 , wherein a width of the first compensation pattern is constant. 8 . The display apparatus of claim 5 , wherein a width of the first compensation pattern varies according to a position. 9 . The display device of claim 5 , wherein widths of portions of the plurality of gate lines overlapping the first compensation pattern are greater than widths of portions of the plurality of gate lines not overlapping the first compensation pattern.

10. The display device according to claim 5, further comprising: an active layer, the active layer being located on the substrate; a gate insulating layer, the gate insulating layer being located on the active layer; a gate electrode, the gate electrode overlapping the active layer on the gate insulating layer; a first interlayer insulating layer, wherein the first interlayer insulating layer is located on the gate electrode; a second interlayer insulating layer, the second interlayer insulating layer being located on the first interlayer insulating layer; a source electrode and a drain electrode, the source electrode and the drain electrode being disposed on the second interlayer insulating layer and electrically connected to the active layer; a first planarization layer, the first planarization layer being located on the source electrode and the drain electrode; a connecting electrode disposed on the first planarization layer and electrically connected to one of the source electrode and the drain electrode; a second planarization layer, wherein the second planarization layer is located on the connecting electrode; as well as a light emitting diode, wherein the light emitting diode is disposed on the second planarization layer, The plurality of gate lines and the gate electrode are disposed on the same layer, and the first compensation pattern and the source electrode and the drain electrode are disposed on the same layer.

11. The display device according to claim 5, further comprising: a first active layer, wherein the first active layer is located on the substrate; a first gate insulating layer, wherein the first gate insulating layer is located on the first active layer; a first gate electrode, the first gate electrode overlapping the first active layer on the first gate insulating layer; a first interlayer insulating layer, wherein the first interlayer insulating layer is located on the first gate electrode; a second active layer, wherein the second active layer is located on the first interlayer insulating layer; a second gate insulating layer, wherein the second gate insulating layer is located on the second active layer; a second gate electrode, the second gate electrode overlapping the second active layer on the second gate insulating layer; a second interlayer insulating layer, the second interlayer insulating layer being located on the second gate electrode; a first source electrode and a first drain electrode, the first source electrode and the first drain electrode being disposed on the second interlayer insulating layer and electrically connected to the first active layer; a second source electrode and a second drain electrode, the second source electrode and the second drain electrode being disposed on the second interlayer insulating layer and electrically connected to the second active layer; a first planarization layer, the first planarization layer being located on the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode; a connecting electrode disposed on the first planarization layer and electrically connected to one of the first source electrode and the first drain electrode; a second planarization layer, wherein the second planarization layer is located on the connecting electrode; as well as a light emitting diode, wherein the light emitting diode is disposed on the second planarization layer, The plurality of gate lines and the second gate electrode are disposed on the same layer, and the first compensation pattern and the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on the same layer.

12. The display device according to claim 1, wherein the active area comprises: a third region having a first width in a column direction; and a fourth region having a second width in the column direction that is smaller than the first width, and The display device further includes a second compensation pattern disposed in the fourth area.

13. The display device according to claim 12, further comprising: a clock line connected to the plurality of gate blocks and intersecting the plurality of gate lines, The second compensation pattern overlaps with the clock line.

14. The display device according to claim 13, further comprising: A third compensation pattern is overlapped with the clock line. 15 . The display device of claim 13 , wherein a width of the second compensation pattern is constant, and a length of the clock line differs according to a position. The display device according to claim 15 , wherein the clock line has a zigzag pattern.

17. The display device according to claim 14, further comprising: an active layer, the active layer being located on the substrate; a gate insulating layer, the gate insulating layer being located on the active layer; a gate electrode, the gate electrode overlapping the active layer on the gate insulating layer; a first interlayer insulating layer, wherein the first interlayer insulating layer is located on the gate electrode; a second interlayer insulating layer, the second interlayer insulating layer being located on the first interlayer insulating layer; a source electrode and a drain electrode, the source electrode and the drain electrode being disposed on the second interlayer insulating layer and electrically connected to the active layer; a first planarization layer, the first planarization layer being located on the source electrode and the drain electrode; a connecting electrode disposed on the first planarization layer and electrically connected to one of the source electrode and the drain electrode; a second planarization layer, wherein the second planarization layer is located on the connecting electrode; as well as a light emitting diode, wherein the light emitting diode is disposed on the second planarization layer, The second compensation pattern is disposed between the first interlayer insulating layer and the second interlayer insulating layer, and the third compensation pattern and the connecting electrode are disposed on the same layer.

18. The display device according to claim 14, further comprising: a first active layer, wherein the first active layer is located on the substrate; a first gate insulating layer, wherein the first gate insulating layer is located on the first active layer; a first gate electrode, the first gate electrode overlapping the first active layer on the first gate insulating layer; a first interlayer insulating layer, wherein the first interlayer insulating layer is located on the first gate electrode; a second active layer, wherein the second active layer is located on the first interlayer insulating layer; a second gate insulating layer, wherein the second gate insulating layer is located on the second active layer; a second gate electrode, the second gate electrode overlapping the second active layer on the second gate insulating layer; a second interlayer insulating layer, the second interlayer insulating layer being located on the second gate electrode; a first source electrode and a first drain electrode, the first source electrode and the first drain electrode being disposed on the second interlayer insulating layer and electrically connected to the first active layer; a second source electrode and a second drain electrode, the second source electrode and the second drain electrode being disposed on the second interlayer insulating layer and electrically connected to the second active layer; a first planarization layer, the first planarization layer being located on the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode; a connecting electrode disposed on the first planarization layer and electrically connected to one of the first source electrode and the first drain electrode; a second planarization layer, wherein the second planarization layer is located on the connecting electrode; as well as a light emitting diode, wherein the light emitting diode is disposed on the second planarization layer, The second compensation pattern is disposed between the first interlayer insulating layer and the second interlayer insulating layer, and the third compensation pattern and the connecting electrode are disposed on the same layer.

19. The display device according to claim 18, further comprising: A fourth compensation pattern overlaps the second compensation pattern and is disposed between the first interlayer insulating layer and the second compensation pattern.

20. The display device of claim 1, wherein a capacitor is formed between the first compensation pattern and the plurality of gate lines.

21. The display device of claim 5, wherein an area in which the power lines and the first compensation pattern overlap with the gate lines in the at least one second region is larger than an area in which the power lines overlap with the gate lines in the first regions.

22. The display apparatus of claim 12, wherein the second compensation pattern is electrically connected to one of a plurality of power lines.

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