Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a conventional display area and a functional area. The lengths of the third display area, the first display area and the second display area in the conventional display area are sequentially reduced in the first direction; wherein one of the first display area and the third display area is a specific display area, the specific display area comprises first semiconductor pattern layers, and any first semiconductor pattern layer is connected with at least one first semiconductor pattern layer which is arranged along the third direction and is adjacent to the first semiconductor pattern layer; the second display area comprises second semiconductor pattern layers, and any second semiconductor pattern layer is connected with at least one second semiconductor pattern layer which is arranged along the fourth direction and is adjacent to the second semiconductor pattern layer; wherein the second semiconductor pattern layers arranged and connected along the fourth direction are connected with the first semiconductor pattern layers arranged and connected along the third direction. According to the display panel, the reliability and uniformity of the performance of the semiconductor pattern layer are improved.

Description

[0001] This application is a divisional application of the parent case CN112164714A. The application date of the original parent case is October 23, 2020, the application number is: 202011149420.8, and the name of the invention is: A display panel and display device.

Technical field

[0002] The present application relates to the field of display technology, and in particular to a display panel and a display device. [Background Technology]

[0003] With increasing consumer demand, full-screen displays are becoming a mainstream display technology. Existing full-screen displays typically incorporate a light-transmitting area within the display area. This area is used to house optical components. Since the light-transmitting area is not located within the non-display area, the display's bezel is narrowed, enabling full-screen displays. However, the presence of this light-transmitting area within the display area can degrade the display quality of the display panel.

[0004] Application Contents

[0005] In view of this, embodiments of the present application provide a display panel and a display device to solve the above problems.

[0006] In a first aspect, an embodiment of the present application provides a display panel comprising a conventional display area and a functional area; the conventional display area comprises a first display area, a second display area and a third display area, and along a first direction, the length of the second display area is respectively smaller than the length of the first display area and the third display area, and the length of the first display area is smaller than the length of the third display area; the sub-pixel density of the functional area is smaller than the sub-pixel density of the conventional display area, and the second display area, the functional area and the first display area are adjacent to each other in sequence along the first direction, and at least one of the first display area and the second display area and the functional display area are adjacent to the third display area along the second direction; the first direction intersects with the second direction; wherein: one of the first display area and the third display area is a specific display area, and the specific display area comprises multiple A first pixel circuit is provided, wherein the first pixel circuit includes a first semiconductor pattern layer, any one of the first semiconductor pattern layers is connected to at least one first semiconductor pattern layer arranged and adjacent to it along a third direction, and the angle between the third direction and the first direction is a first angle α, 90°>α≥0°; the second display area includes a plurality of second pixel circuits, the second pixel circuit includes a second semiconductor pattern layer, any one of the second semiconductor pattern layers is connected to at least one second semiconductor pattern layer arranged and adjacent to it along a fourth direction; the angle between the fourth direction and the first direction is a second angle β, 90°>β≥0°; wherein the second semiconductor pattern layer arranged and connected along the fourth direction is connected to the first semiconductor pattern layer arranged and connected along the third direction.

[0007] In a second aspect, based on the same concept, an embodiment of the present application provides a display device, comprising a display panel as provided in the first aspect, and an optical device; the optical device is arranged at a position corresponding to a functional area of ​​the display device.

[0008] In the display panel and display device provided by the embodiments of the present application, the second semiconductor pattern layer is connected to the first semiconductor pattern layer in the functional area, ensuring continuity of the semiconductor pattern layer in the functional area and reducing the risk of static electricity flowing from the functional area into the semiconductor pattern layer. Furthermore, the connection of the second semiconductor pattern layer in a string with the first semiconductor pattern layer in a string disperses the high-density static electricity on the second semiconductor pattern layer 121. This can improve the reliability and uniformity of the performance of the semiconductor pattern layer during subsequent high-temperature processes, achieving display uniformity in the display panel and display device, and enhancing the display quality.

Brief Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0010] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application;

[0011] Figure 2 A schematic diagram of another display panel provided in an embodiment of the present application;

[0012] Figure 3 for Figure 1 A local magnified view of the middle AA area;

[0013] Figure 4 for Figure 1 Another partial magnification of the middle AA area;

[0014] Figure 5 An equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0015] Figure 6 A cross-sectional view corresponding to a sub-pixel region in this application;

[0016] Figure 7 A schematic diagram of a semiconductor pattern layer corresponding to a pixel circuit provided in an embodiment of the present application;

[0017] Figure 8 for Figure 3 A schematic diagram of the film layer where the corresponding semiconductor pattern layer is located;

[0018] Figure 9 for Figure 3 Another schematic diagram of the film layer where the corresponding semiconductor pattern layer is located;

[0019] Figure 10 for Figure 4 A schematic diagram of the film layer where the corresponding semiconductor pattern layer is located;

[0020] Figure 11 A connection diagram of the second semiconductor pattern layer provided in an embodiment of the present application;

[0021] Figure 12 A schematic diagram of the functional area of ​​the display panel provided in this application;

[0022] Figure 13 for Figure 12 A cross-section along the MN direction;

[0023] Figure 14 Another schematic diagram of the functional area of ​​the display panel provided by this application;

[0024] Figure 15 for Figure 14 A cross-section along the MN direction;

[0025] Figure 16 This is another schematic diagram of the functional area of ​​the display panel provided by this application;

[0026] Figure 17 for Figure 16 A cross-section along the MN direction;

[0027] Figure 18 for Figure 12 Another cross-section along the MN direction;

[0028] Figure 19 This is another schematic diagram of the functional area of ​​the display panel provided in this application;

[0029] Figure 20 for Figure 19 A cross-section along the MN direction;

[0030] Figure 21 A schematic diagram of a display device provided in an embodiment of the present application. [Specific implementation method]

[0031] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0032] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0033] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0034] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0035] In the description of this specification, it is necessary to understand that the words "substantially", "approximately", "approximately", "about", "roughly", "generally" and the like described in the claims and embodiments of this application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0036] It should be understood that although the terms "first," "second," "third," etc. may be used to describe display areas in the embodiments of the present application, these display areas should not be limited to these terms. These terms are merely used to distinguish one display area from another. For example, without departing from the scope of the embodiments of the present application, the first display area may also be referred to as the second display area, and similarly, the second display area may also be referred to as the first display area.

[0037] The applicant in this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0038] Embodiments of the present application provide a display panel and a display device.

[0039] The applicant found in the study that, for the display panel, since the light-transmitting area is set in the display area, in order to ensure the light transmittance of the light-transmitting area, no or few light-shielding structures are set in the light-transmitting area, such as no or few metal traces and semiconductor layers, which means that the metal traces and the semiconductor layer will be disconnected in the light-transmitting area. Among them, since the lengths of the semiconductor layers at the upper and lower positions of the light-transmitting area are inconsistent, the static electricity distribution during the preparation of the semiconductor layer is uneven, such as the static electricity density on the shorter semiconductor layer is large, while the static electricity density on the longer semiconductor layer is small. The process of the semiconductor layer includes high-temperature processes, such as annealing and activation processes, and the static electricity during the high-temperature process will have an irreversible effect on the performance of the semiconductor layer, thereby affecting the performance of the corresponding transistor, such as the threshold voltage. Since the semiconductor layer is disconnected at the position where the light-transmitting area is located, the static electricity on the semiconductor layer is unevenly distributed. The unevenly distributed static electricity has different irreversible effects on the performance of the semiconductor layer in the high-temperature process, so the performance of the transistors in the display screen is inconsistent, which leads to poor display uniformity of the display screen. Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application is shown. Figure 2 A schematic diagram of another display panel provided in an embodiment of the present application, Figure 3 for Figure 1 A local magnified view of the AA area in the middle. Figure 4 for Figure 1 Another partial enlarged view of the AA area. It should be noted that Figure 3 and Figure 4 The specific structure of the AA area is shown in the figure. Figure 2 The specific structures near the central functional area are basically the same.

[0040] like Figure 1 and Figure 2 As shown, the display panel provided in the embodiment of the present application includes a conventional display area 01 and a functional area 02, and the conventional display area 01 at least partially surrounds the functional area 02. Figure 1 As shown, the functional area 02 can be completely surrounded by the conventional display area 01; Figure 2 As shown, the function area 02 may also be partially surrounded by the conventional display area 01. Figure 3 and Figure 4 As shown, the conventional display area 01 includes multiple luminous sub-pixels PX for primary luminous display. The sub-pixel density in the functional area 02 is lower than that in the conventional display area 01, enabling at least one of other functions besides luminous display, such as photography, biometric recognition, and lighting. Furthermore, in an optional embodiment, the functional area 02 can perform these other functions as well as luminous display.

[0041] Please continue to refer to Figure 1 and Figure 2The conventional display area 01 includes a first display area 11, a second display area 12, and a third display area 13. The first display area 11, the second display area 12, and the third display area 13 are different areas of the conventional display area 01 and can have the same sub-pixel PX design pattern. Along the first direction Y, the second display area 12, the functional area 02, and the first display area 11 are adjacent to each other in sequence; that is, along the first direction Y, the functional area 02 is arranged between the first display area 11 and the second display area 12. Along the second direction X, at least one of the first display area 11 and the second display area 12 and the functional area 02 are adjacent to the third display area 13; that is, the first display area 11, the second display area 12, and the functional area 02 are aligned in the first direction Y and, as a whole, are adjacent to the third display area 13 in the second direction X. The first direction Y intersects the second direction X. In one implementation, the first direction Y can be perpendicular to the second direction X.

[0042] Along the first direction Y, the length of the second display area 12 is shorter than the length of the first display area 11 and the length of the third display area 13, and the length of the first display area 11 is shorter than the length of the third display area 13. The functional area 02 is at least partially surrounded by the conventional display area 01, which is equivalent to setting the functional area 02 within the conventional display area 01. This avoids increasing the bezel width of the display panel by setting the functional area 02 in the non-display area outside the conventional display area 01.

[0043] However, the function area 02 is usually set near the edge of the display panel to avoid affecting the display effect of the conventional display area 01. Figure 1 and Figure 2 As shown, the functional area 02 can be set close to the edge of one side of the conventional display area 01 along the first direction Y, so that the length of the first display area 11 and the length of the second display area 12 on both sides of the conventional display area 01 along the first direction Y are different. Figure 1 As shown, when the functional area 02 is set close to the edge of the conventional display area 01 along the first direction Y, Figure 1 As shown, the functional area 02 can be set in the middle of the conventional display area 01 along the second direction X; or as shown in FIG. Figure 2 As shown, the functional area 02 can be set along the second direction X at an edge position close to the conventional display area 01.

[0044] Among them, along the first direction Y, the length of the first display area 11, the length of the second display area 12 and the length of the third display area 13 respectively refer to the length of the area where the first display area 11 is located along the first direction Y, the length of the area where the second display area 12 is located along the first direction Y and the length of the third display area 13 along the first direction Y.

[0045] It should be noted that the functional area 02 can have a rectangular structure or other structures. When the functional area 02 has a non-rectangular structure, the corresponding first display area 11, second display area 12, and / or third display area 13 are also non-rectangular structures. Therefore, the length of the first display area 11, the length of the second display area 12, and the length of the third display area 13 referred to in this application can refer to the average length of the first display area 11, the average length of the second display area 12, and the average length of the third display area 13, respectively.

[0046] Since the length of the second display area 12 is smaller than the length of the first display area 11 and the length of the third display area 13, and the length of the first display area 11 is smaller than the length of the third display area 13, correspondingly, the number of sub-pixels PX arranged along the first direction Y in the second display area 12 is smaller than the number of sub-pixels PX arranged along the first direction Y in the first display area 11 and the number of sub-pixels PX arranged along the first direction Y in the third display area 13, and the number of sub-pixels PX arranged along the first direction Y in the first display area 11 is smaller than the number of sub-pixels PX arranged along the first direction Y in the third display area 13. In addition, the number of sub-pixels PX arranged along the first direction Y in the first display area 11 may be the average value of the sub-pixels PX arranged along the first direction Y in multiple columns in the first display area 11, the number of sub-pixels PX arranged along the first direction Y in the second display area 12 may be the average value of the sub-pixels PX arranged along the first direction Y in multiple columns in the second display area 12, and the number of sub-pixels PX arranged along the first direction Y in the third display area 13 may be the average value of the sub-pixels PX arranged along the first direction Y in multiple columns in the third display area 13.

[0047] The sub-pixel PX in the display panel provided in the embodiment of the present application may be a self-luminous device, such as an organic light emitting diode or a micro diode. Figure 3 As shown, the display panel further includes pixel circuits DI corresponding to the sub-pixels PX one by one, and the pixel circuits DI are used to provide the corresponding sub-pixels with the voltage required for emitting light.

[0048] Figure 5 This is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application. Figure 5 As shown, the pixel circuit DI and the sub-pixel PX are electrically connected.

[0049] Please continue to refer to Figure 5The pixel circuit DI may include a light-emitting driving transistor Td, a reset transistor T1, a data voltage writing transistor T2, a threshold grabbing transistor T3, a power supply voltage writing transistor T4, a light-emitting control transistor T5, and a first capacitor C0. Herein, the light-emitting driving transistor Td, the reset transistor T1, the data voltage writing transistor T2, the threshold grabbing transistor T3, the power supply voltage writing transistor T4, and the light-emitting control transistor T5 are all P-type transistors for illustration. In other optional embodiments, the light-emitting driving transistor Td, the reset transistor T1, the data voltage writing transistor T2, the threshold grabbing transistor T3, the power supply voltage writing transistor T4, and the light-emitting control transistor T5 may all be N-type transistors, or some may be P-type transistors and some may be N-type transistors.

[0050] The source of the reset transistor T1 is electrically connected to the reset signal line REF, and the drain of the reset transistor T1 is electrically connected to the gate of the light-emitting driving transistor Td. The source of the data voltage write transistor T2 is electrically connected to the data signal line DATA, and the drain of the data voltage write transistor T2 is electrically connected to the source of the light-emitting driving transistor Td. The source of the threshold grabbing transistor T3 is electrically connected to the drain of the light-emitting driving transistor Td, and the drain of the threshold grabbing transistor T3 is electrically connected to the gate of the light-emitting driving transistor Td. The source of the power supply voltage write transistor T4 is electrically connected to the power supply voltage line PVDD, and the drain of the power supply voltage write transistor T4 is electrically connected to the source of the light-emitting driving transistor Td. The source of the light-emitting control transistor T5 is electrically connected to the drain of the light-emitting driving transistor Td, and the drain of the light-emitting control transistor T5 is electrically connected to the light-emitting device EL. The first plate of the first capacitor C0 is electrically connected to the gate of the light-emitting driving transistor Td, and the second plate of the first capacitor C0 is electrically connected to the power supply voltage line PVDD.

[0051] The following Figure 5 The working process of the pixel circuit shown in FIG. 3 is described below. The working process of the pixel circuit may include a reset phase, a data voltage writing phase and a light emitting phase.

[0052] In the reset phase, the reset transistor T1 is turned on, and the reset signal line REF transmits a reset signal, and the reset signal is written into the gate of the light-emitting driving transistor Td. The gate of the light-emitting driving transistor Td is reset and the first capacitor C0 stores the reset signal.

[0053] In the data voltage writing stage, the power supply voltage writing transistor T4 and the light emitting control transistor T5 are turned off, the data voltage writing transistor T2 and the threshold grabbing transistor T3 are turned on, and the data voltage is transmitted on the data signal line DATA. Since the potential of the data voltage is higher than the potential of the reset signal, the light emitting driving transistor Td is turned on and the data voltage is written to the gate of the light emitting driving transistor Td.

[0054] In the light-emitting stage, the threshold capture transistor T3 is turned off, the power supply voltage writing transistor T4 and the light-emitting control transistor T5 are turned on, and the power supply voltage line PVDD transmits the power supply voltage, which is then transmitted to the source of the light-emitting driving transistor Td. If the potential of the power supply voltage is greater than the potential of the data voltage, the light-emitting driving transistor Td generates a light-emitting driving current and transmits it to the sub-pixel PX.

[0055] It should be noted that Figure 5 Only an equivalent circuit diagram of a pixel circuit is shown. The specific structure of the pixel circuit in this application may also be in other forms.

[0056] Figure 6 This is a cross-sectional view corresponding to a sub-pixel area in this application. Figure 5 and Figure 6 The pixel circuit DI that provides a light-emitting signal for a sub-pixel PX includes multiple transistor structures, and one of the transistor structures, such as the light-emitting control transistor T5, is electrically connected to the sub-pixel PX. To achieve a high density of sub-pixels PX in the light-emitting display panel, the multiple transistor structures included in a pixel circuit DI are arranged as closely as possible.

[0057] Figure 7 A schematic diagram of a semiconductor pattern layer corresponding to a pixel circuit provided in an embodiment of the present application. In the multiple transistor structures included in a pixel circuit DI, each transistor structure includes an active layer PL, and due to the limitation of process precision, the active layers PL of the multiple transistor structures in a pixel circuit DI are connected together to form a structure as shown in FIG. Figure 7 The semiconductor pattern layer shown. It should be noted that Figure 7 What is shown is only one semiconductor pattern layer corresponding to the pixel circuit DI. The semiconductor pattern layer corresponding to the pixel circuit DI may also have other shapes.

[0058] Figure 8 for Figure 3 A schematic diagram of the film layer where the corresponding semiconductor pattern layer is located, Figure 9 for Figure 3 Another schematic diagram of the film layer where the corresponding semiconductor pattern layer is located, Figure 10 for Figure 4 A schematic diagram of the film layer where the corresponding semiconductor pattern layer is located.

[0059] Please combine Figure 3 and Figure 8-Figure 9 、 Figure 4 and Figure 10One of the first display area 11 and the third display area 13 is a specific display area. The multiple pixel circuits DI in the specific display area are first pixel circuits 110. The first pixel circuit 110 includes a first semiconductor pattern layer 111. Any first semiconductor pattern layer 111 is connected to at least one first semiconductor pattern layer 111 arranged along the third direction and adjacent to it. The angle between the third direction and the first direction Y is a first angle α, 90°>α≥0°.

[0060] The plurality of pixel circuits DI in the second display area 12 are second pixel circuits 120. The second pixel circuits 120 include second semiconductor pattern layers 121. Any second semiconductor pattern layer 121 is connected to at least one second semiconductor pattern layer 121 adjacent to the second semiconductor pattern layer 121 arranged along the fourth direction. The angle between the fourth direction and the first direction Y is a second angle β, where 90°>β≥0°.

[0061] The second semiconductor pattern layers 121 arranged and connected along the fourth direction Y2 are connected to the first semiconductor pattern layers 111 arranged and connected along the third direction Y1.

[0062] In this application, by connecting the second semiconductor pattern layer 121 to the first semiconductor pattern layer 111, the continuity of the semiconductor pattern layer within the functional area 02 is achieved, reducing the risk of static electricity flowing into the semiconductor pattern layer within the functional area 02. Furthermore, by connecting the string of second semiconductor pattern layers 121 to the string of first semiconductor pattern layers 111, the high-density static electricity on the second semiconductor pattern layer 121 is dispersed across the first semiconductor pattern layer 111 and the second semiconductor pattern layer 121, ensuring a uniform distribution of static electricity within the semiconductor pattern layer. This, in turn, improves the reliability and uniformity of the performance of the semiconductor pattern layer during subsequent high-temperature processes, ensuring essentially consistent driving capabilities for the pixel circuits, achieving uniform display across the display panel, and enhancing the display quality.

[0063] In the present application, the ratio of the length of the second display area 12 along the first direction Y to the length of the specific display area along the first direction Y is in the range of [12, 50]. If the length of different display areas is characterized by the number of pixel circuits, the number of first pixel circuits 111 arranged along the first direction Y in the specific display area is N, and the number of second pixel circuits 121 arranged along the first direction Y in the second display area 12 is M, where M and N are both positive integers greater than or equal to 2, and 50 ≥ N / M ≥ 12. When the length of the second display area 12 satisfies the above relationship, the position of the functional area 02 has little effect on the display effect of the display panel. However, if the second semiconductor pattern 121 in the second display area 12 is not connected to the first semiconductor pattern layer to dissipate static electricity during the process, the display effect of the second display area 12 is significantly different from that of other display areas. Therefore, when the technical solution of connecting the second semiconductor pattern 121 and the first semiconductor pattern layer in the embodiment of the present application is applied to the situation where the ratio of the length of the second display area 12 along the first direction Y to the length of the specific display area along the first direction Y is in the range of [12, 50], it can effectively solve the problem that the display effect of the second display area 12 is significantly different from that of other display areas.

[0064] In the present application, the semiconductor pattern layer is one of polycrystalline silicon and metal oxide semiconductor. Pixel circuits using polycrystalline silicon as the semiconductor pattern layer have a faster response speed, while pixel circuits using metal oxide semiconductors as the semiconductor pattern layer can generate a stable luminous current. Therefore, when the semiconductor pattern layer in the display panel is one of polycrystalline silicon and metal oxide semiconductor, the display panel has excellent luminous performance. Furthermore, when the semiconductor pattern layer in the display panel is one of polycrystalline silicon and metal oxide semiconductor, the connection between the first semiconductor pattern layer 111 and the second semiconductor pattern layer 121 can effectively solve the problem of excessive static electricity accumulation in the semiconductor pattern layer in a specific display area.

[0065] In one implementation of the present application, the third direction Y1 is parallel to the fourth direction Y2. That is, adjacent first semiconductor pattern layers 111 are connected, and adjacent second semiconductor pattern layers 121 are connected in the same direction; and the interconnected first semiconductor pattern layers 111 and second semiconductor pattern layers 121 are also substantially arranged along the same direction.

[0066] In one embodiment of the present application, the third direction Y1 and the fourth direction Y2 are both parallel to the first direction Y, that is, α=0°, β=0°. Figure 7-Figure 9 As shown, the first semiconductor pattern layers 111 in the same column are connected in sequence, and the second semiconductor pattern layers 121 in the same column are connected in sequence.

[0067] Figure 11A connection diagram of the second semiconductor pattern layer provided in an embodiment of the present application is shown as follows: Figure 11 As shown, the second semiconductor pattern layers 121 arranged along the fourth direction Y2 are connected in sequence, and the fourth direction Y2 forms a non-0° angle with the first direction Y, that is, 90°>α>0°. Correspondingly, the effect of the first semiconductor pattern layers 111 arranged along the third direction Y1 being connected in sequence is the same as Figure 11 The connection effect of the second semiconductor pattern layer 121 shown is substantially the same, and thus 90°>β>0°.

[0068] It should be noted that in a conventional display area of ​​a display panel, the connection method of the semiconductor pattern layers in each area should be consistent. This can reduce the difficulty of design and ensure the uniformity of the coupling capacitance of each semiconductor pattern layer.

[0069] Furthermore, the first semiconductor pattern layers 111 to which a first semiconductor pattern layer 111 is directly connected may include not only the first semiconductor pattern layers 111 located on both sides thereof along the third direction Y1, but may also include the first semiconductor pattern layer 111 located on at least one side thereof along a direction intersecting the third direction Y1. Similarly, the second semiconductor pattern layer 121 to which a second semiconductor pattern layer 121 is directly connected may not only include the second semiconductor pattern layers 121 located on both sides thereof along the fourth direction Y2, but may also include the second semiconductor pattern layer 121 located on at least one side thereof along a direction intersecting the fourth direction Y2.

[0070] However, it should be noted that when the first semiconductor pattern layers 111 arranged along the third direction Y1 are connected sequentially, the number of first semiconductor pattern layers 111 connected along a direction intersecting the third direction Y1 is one to three, for example, two. This can reduce the coupling capacitance of the first semiconductor pattern layers 111. Based on the same principle, the number of second semiconductor pattern layers 121 connected along a direction intersecting the fourth direction Y2 is also one to three, for example, two.

[0071] In one embodiment of the present application, Figure 8 and Figure 9 As shown, the first display area 11 is a specific display area, and the multiple pixel circuits DI in the first display area 11 are first pixel circuits 110, and the semiconductor pattern layer included in the first pixel circuit 110 in the first display area 11 is a first semiconductor pattern layer 111. In addition, the functional area O2 includes at least one connecting semiconductor CL, and the second semiconductor pattern layer 121 arranged and connected along the fourth direction Y2 is electrically connected to the first semiconductor pattern layer 111 arranged and connected along the third direction Y1 through the connecting semiconductor CL.

[0072] In one implementation of this embodiment, Figure 8As shown, a connecting semiconductor CL is connected to multiple second semiconductor pattern layers 121 in the second display area 12 near the functional area 02, and is also connected to multiple first semiconductor pattern layers 111 in the first display area 11 near the functional area 02. Thus, a smaller number of connecting semiconductors CL can disperse static electricity in the second semiconductor pattern layers 121 to the first semiconductor pattern layers 111.

[0073] In one approach, Figure 8 As shown, the connecting semiconductor CL is connected to all the second semiconductor pattern layers 121 in the second display area 12 near the functional area 02, and is connected to all the first semiconductor pattern layers 111 in the first display area 11 near the functional area 02. That is, all the second semiconductor pattern layers 121 in the second display area 12 are directly or indirectly connected to the same connecting semiconductor CL, all the first semiconductor pattern layers 111 in the first display area 11 are directly or indirectly connected to the same connecting semiconductor CL, and one connecting semiconductor CL is directly or indirectly connected to all the second semiconductor pattern layers 121 and all the first semiconductor pattern layers 111.

[0074] That is, the multiple columns of first semiconductor pattern layers 111 arranged perpendicular to the third direction Y1 are all electrically connected to the same connecting semiconductor line CL, and the multiple columns of second semiconductor pattern layers 121 arranged perpendicular to the fourth direction Y2 are also electrically connected to the same connecting semiconductor line CL. This allows the static electricity in all second semiconductor pattern layers 121 to be balanced across the first display area 111 and second display area 121 on both sides of the functional area 02. In particular, when the irregular shape of the functional area 02 results in different numbers of second semiconductor pattern layers 121 in different columns, this design can achieve better static electricity balance across the functional area 02.

[0075] In addition, since a connecting semiconductor CL is directly or indirectly connected to all the second semiconductor pattern layers 121 and all the first semiconductor pattern layers 111, the number of connecting semiconductors CL in the functional area 02 can be one, which simplifies the process and reduces the impact of the connecting semiconductor CL on the film layer preparation process in the functional area 02.

[0076] In order to increase the flow paths of static electricity, the number of connection semiconductors CL can also be multiple. When the number of connection semiconductors CL is multiple, the multiple connection semiconductors CL can be connected to each other.

[0077] Figure 12 A schematic diagram of the functional area of ​​the display panel provided in this application, Figure 13 for Figure 12 A cross-section along the MN direction, Figure 14 This is another schematic diagram of the display panel functional area provided in this application. Figure 15 for Figure 14 A cross-section along the MN direction, Figure 16 This is another schematic diagram of the functional area of ​​the display panel provided in this application. Figure 17 for Figure 16 A cross-section along the MN direction.

[0078] like Figure 12 、 Figure 14 and Figure 16 As shown, the functional area 02 includes a light-transmitting area 21 and a transition area 22 surrounding the light-transmitting area 21. Within the light-transmitting area 21, light can penetrate the display panel along its thickness. The transition area 22 is positioned between the light-transmitting area 21 and the conventional display area 01. Metal windings can be placed within the transition area 22 to avoid the need for metal windings within the light-transmitting area 21, thereby increasing the light transmittance of the light-transmitting area 21. When the light-transmitting area 21 is present, the outer portion of the conventional display area 01 near the light-transmitting area 21 may also require encapsulation. In this case, the transition area 22 can be provided with an encapsulation structure.

[0079] like Figure 13 、 Figure 15 and Figure 17 As shown, to improve the light transmittance of the light-transmitting region 21, some film layers in the conventional display region 01 extend to the transition region 22 and terminate thereafter. For example, the organic layers of the planarization layer, pixel definition layer, and encapsulation layer, all made of organic materials, terminate at the transition region 22. To prevent moisture, oxygen, and the like from invading the conventional display region 01 through the light-transmitting region 21, a barrier structure, such as a first barrier structure SC1 and a second barrier structure SC2, can be provided within the transition region 22. The first barrier structure SC1 can be formed by stacking structures that are co-layered with and separate from the planarization layer and pixel definition layer, and an inorganic material layer from the encapsulation layer can be provided on its surface. The film layers on the outer side of the first barrier structure SC1, which is closer to the light-transmitting region 21, do not include a film layer made of organic materials. Therefore, the height of the first barrier structure SC1 is higher than that of the film layers on the outer side of the first barrier structure SC1, which increases the transmission path for moisture and oxygen, thereby effectively blocking moisture and oxygen. The second blocking structure SC2 may be formed by a metal stack in the same layer as the signal lines in the conventional display area 01 , and may effectively block water vapor and oxygen.

[0080] Please continue to combine Figure 12 and Figure 13 、 Figure 14 and Figure 15 、 Figure 16 and Figure 17Since the light-transmitting area 21 needs to allow light to pass through, the light-transmitting area 21 should have good light transmittance. Therefore, metal traces should be avoided as much as possible. If the signal lines on both sides of the functional area 02 in the conventional display area 01 need to be electrically connected, they can be electrically connected through the metal traces ML in the transition area 22. Therefore, the transition area 22 also includes a metal trace group, wherein the metal trace group includes multiple metal traces ML, such as Figure 12-17 As shown, the transition area 22 on one side of the functional area 02 includes three metal traces ML. Figure 12-17 As shown, the metal trace ML and the connecting semiconductor CL can be provided in different layers.

[0081] Please combine Figure 12 and Figure 13 、 Figure 14 and Figure 15 、 Figure 16 and Figure 17 At least one connecting semiconductor CL is disposed in the transition region 22. Although the connecting semiconductor CL is connected to the semiconductor pattern layer within the conventional display region 01, disposing the connecting semiconductor CL in the transition region 22 prevents the connecting semiconductor CL from affecting the arrangement of the pixel circuits DI within the conventional display region 01. Furthermore, disposing the connecting semiconductor CL in the transition region 22 also prevents the light transmittance of the light-transmitting region 02 from being affected.

[0082] In one implementation, combine Figure 12 and Figure 13 In a plane perpendicular to the thickness of the display panel, the connecting semiconductor CL is disposed on the side of the metal trace group away from the light-transmitting area 21. Specifically, the connecting semiconductor CL is disposed on the side of the transition region 22 close to the conventional display area 01, making it easier for the connecting semiconductor CL to connect to the semiconductor pattern layer. Furthermore, disposing the connecting semiconductor CL away from the metal trace group ensures that the film layer beneath the metal trace group is flat, thereby reducing the design difficulty of the metal trace ML and the risk of metal trace disconnection. Furthermore, there is essentially no parasitic capacitance or signal crosstalk between the metal trace ML and the connecting semiconductor CL.

[0083] In another implementation, combine Figure 14 and Figure 15In a plane perpendicular to the thickness of the display panel, the connecting semiconductor CL is disposed on the side of the metal trace group near the light-transmitting region 21. Furthermore, along the thickness of the display panel, the connecting semiconductor CL can be disposed below the first barrier structure SC1 and / or the second barrier structure SC2, further increasing the barrier path for water vapor and oxygen provided by the first barrier structure SC1 and / or the second barrier structure SC2. Furthermore, locating the connecting semiconductor CL away from the metal trace group ensures a flat film layer beneath the metal trace group, thereby reducing the design difficulty of the metal trace ML and the risk of metal trace breakage. Furthermore, parasitic capacitance and signal crosstalk are essentially eliminated between the metal trace ML and the connecting semiconductor CL.

[0084] In another implementation, please combine Figure 16 and Figure 17 , along the thickness direction of the display panel, the metal wiring group at least partially covers the connection semiconductor CL. Figure 17 As shown, along the thickness direction of the display panel, the connecting semiconductor CL is disposed below the metal routing group, and the metal routing group completely covers the connecting semiconductor CL. Because the lengths of the first display area 11 and the second display area 12 are both shorter than the length of the third display area 13, along the first direction Y, the intersections between the interconnected semiconductor pattern layers and the signal lines in the first display area 11 and the second display area 12 are fewer than the intersections between the interconnected semiconductor pattern layers and the signal lines in the third display area 13. By disposing the connecting semiconductor CL below the metal routing group, the intersections between the interconnected semiconductor pattern layers and the signal lines in the first display area 11 and the second display area 12 can be increased, balancing the coupling capacitance between the semiconductor pattern layers and the signal lines in various regions of the conventional display area 01.

[0085] like Figure 12-17 As shown, the sub-pixel density in the light-transmitting area 21 is 0, that is, no sub-pixel PX is provided in the area where the light-transmitting area 21 is located and is not used for light-emitting display.

[0086] In one implementation, Figure 13 、 Figure 15 and Figure 17 As shown, the light-transmitting area 21 is a non-hollowed area of ​​the display panel. That is, the display panel includes a first substrate BC and a second substrate TC that are oppositely arranged, and the first substrate BC and the second substrate TC are continuous structures in the light-transmitting area 21 and the conventional display area O1.

[0087] In another implementation, the light-transmitting area 21 is a hollow area of ​​the display panel. Figure 18 for Figure 12 Another cross-sectional view along the MN direction. Figure 18As shown, the display panel includes a first substrate BC and a second substrate TC that are arranged opposite to each other, and both the first substrate BC and the second substrate TC are hollowed out in the area where the light-transmitting area 21 is located. Figure 18 Only the case where the connecting semiconductor CL is located on the side of the transition region 22 away from the light-transmitting region 21 is illustrated. However, in this implementation, the structure of the transition region 22 may be the same as that of any of the above embodiments.

[0088] Figure 19 This is another schematic diagram of the functional area of ​​the display panel provided in this application. Figure 20 for Figure 19 A cross-section along the MN direction. Figure 19 and Figure 20 As shown, the sub-pixel density in the light-transmitting area 21 is greater than 0, that is, the light-transmitting area 21 can also perform luminous display, thereby increasing the display area of ​​the display panel. In one implementation, sub-pixels PX are also provided in the transition area 22, so that the conventional display area 01 and the functional area 02 of the display panel can display continuous images. Among them, pixel circuits DI and metal windings are provided in the transition area 22 to avoid providing pixel circuits DI and metal windings in the light-transmitting area 21, thereby increasing the light transmittance of the light-transmitting area 21. It should be noted that the pixel circuit DI that provides signals to the sub-pixels PX in the light-transmitting area 21 can be provided in the transition area 21.

[0089] When the sub-pixel PX is provided in the light-transmitting region 21 , the arrangement of the semiconductor CL and the metal wire group in the transition region 22 may be the same as any of the above embodiments, which will not be described in detail herein.

[0090] It should be noted that, in this embodiment, Figure 12 、 Figure 14 、 Figure 16 、 Figure 19 As shown, the connecting semiconductor CL can be a ring-shaped structure that surrounds the light-transmitting region 21. This allows for the use of a minimum number of connecting semiconductors CL to connect all of the first semiconductor pattern layers 111 and the second semiconductor pattern layers 112 near the light-transmitting region 21. This prevents the connecting semiconductors CL from affecting the arrangement of signal lines in the transition region 22 or the barrier structure. The minimum number of connecting semiconductors CL can be one.

[0091] Furthermore, it should be noted that in this embodiment, the connecting semiconductor CL is a ring-shaped structure, which means that the connecting semiconductor CL is a continuous structure and its overall outline is ring-shaped. The connecting semiconductor CL may also include a protruding structure connected to the first semiconductor pattern layer 111 and the second semiconductor pattern layer 121, but its overall outline remains ring-shaped.

[0092] In another implementation of this embodiment, Figure 9As shown, one end of a connecting semiconductor CL is connected to a second semiconductor pattern layer 121 in the second display area 12 near the functional area 02, and the other end is connected to a first semiconductor pattern layer 111 in the first display area near the functional area 02. The interconnected second semiconductor pattern layers 121 in the second display area 12 are then connected to the interconnected first semiconductor pattern layers 111 in the first display area 11 via the connecting semiconductor CL. The first semiconductor pattern layers 111 and the second semiconductor pattern layers 121 in the same column are then connected, and the semiconductor pattern layers in the same column in the third display area 13 are connected sequentially. This means that the connection method for the semiconductor pattern layers in the display areas on both sides of the functional area 02 is essentially the same as the connection method for the semiconductor pattern layers in other display areas. This ensures that the electrostatic and capacitive coupling in the semiconductor pattern layers in the conventional display area 01 are essentially consistent, ensuring display uniformity.

[0093] It should be noted that in this implementation, only the shape of the connected semiconductor CL and the connection method with the first semiconductor pattern layer 111 and the second semiconductor pattern layer 121 are different from the above embodiments. Other structural designs are the same as any of the above embodiments and will not be repeated here.

[0094] In one embodiment of the present application, Figure 10 As shown, the third display area 13 is a specific display area, and the multiple pixel circuits DI in the third display area 13 are first pixel circuits 110 , and the semiconductor pattern layer included in the first pixel circuit 110 in the third display area 13 is the first semiconductor pattern layer 111 .

[0095] In this embodiment, the display panel further includes a semiconductor connection region disposed on a side of the second display area 12 away from the functional area O2 along the first direction Y. The connection semiconductor region includes at least one connection semiconductor CL. Along the first direction Y, each of the multiple second semiconductor pattern layers 121 near the semiconductor connection region in the second display area 12 is connected to a connection semiconductor CL, and each of the multiple first semiconductor pattern layers 111 near the semiconductor connection region in the third display area 13 is connected to a connection semiconductor CL. Furthermore, the number of first semiconductor pattern layers 111 connected to the same connection semiconductor CL is greater than the number of second semiconductor pattern layers 121 connected to the same connection semiconductor CL.

[0096] Static electricity generated by the second semiconductor pattern layer 121 during the manufacturing process can be dispersed to the multiple first semiconductor pattern layers 111 via the connecting semiconductor CL, thus preventing display abnormalities in the second display area 11. Furthermore, in the third display area 13, the number of first semiconductor pattern layers 111 sequentially connected along the third direction Y1 is much greater than the number of second semiconductor pattern layers 121 sequentially connected along the fourth direction Y2. Furthermore, the number of columns of first semiconductor pattern layers 111 arranged perpendicular to the third direction Y1 is also much greater than the number of columns of second semiconductor pattern layers 121 arranged perpendicular to the first direction Y1. Therefore, static electricity in the second semiconductor pattern layer 121 can be fully dispersed.

[0097] In one implementation of this embodiment, Figure 10 As shown, along the first direction Y, all second semiconductor pattern layers 121 close to the semiconductor connection area in the second display area 12 are connected to a connection semiconductor CL, and all first semiconductor pattern layers 11 close to the semiconductor connection area in the third display area 13 are connected to a connection semiconductor CL.

[0098] The semiconductor connection region can be set in the edge region of the conventional display region 01 or in the non-display region outside the conventional display region 01 to prevent the connection semiconductor CL from affecting the arrangement of the semiconductor pattern layer in the conventional display region 01 .

[0099] In an optional embodiment, the semiconductor pattern layers of pixel circuits in different columns in the first display area 11 are not connected to each other in the second direction.

[0100] In the present application, the connecting semiconductor CL can be provided in the same layer as the semiconductor pattern layer, so that the two can be prepared at the same time, thereby reducing the complexity of the process.

[0101] It should be noted that the position of the connection semiconductor CL and the position of the first semiconductor pattern layer 111 in this implementation are different from those in the above embodiments. Other structural designs can be the same as any of the above embodiments and will not be repeated here.

[0102] Furthermore, along the thickness direction of the display panel, the connecting semiconductor CL can also be disposed below the semiconductor pattern layer, and a planar layer can be included between the connecting semiconductor and the semiconductor pattern layer, with vias provided in the planar layer. Specifically, the connecting semiconductor is prepared before the semiconductor pattern layer, and during the preparation of the semiconductor pattern layer, the semiconductor pattern layer and the connecting semiconductor are connected via vias. Furthermore, the connecting semiconductor can have a higher conductivity than the semiconductor pattern layer, facilitating the dissipation of static electricity.

[0103] Figure 21 A schematic diagram of a display device provided in an embodiment of the present application, such as Figure 21As shown, the display device includes the display panel 001 provided by any of the above embodiments. The display device provided by the embodiment of the present application can be a mobile phone. In addition, the display device provided by the embodiment of the present application can also be a display device such as a computer or a television.

[0104] like Figure 21 As shown, the display device provided in the embodiment of the present application further includes an optical device 002, and the optical device 002 is disposed at a position of the display device corresponding to the functional area 02 of the display panel 001. That is, along the thickness direction of the display panel 001, the optical device 002 is disposed below the functional area 02 of the display panel 001. The optical device 002 can then emit light through the functional area 02 toward the light-emitting surface of the display panel 001, or receive light from the light-emitting surface of the display panel 001 through the functional area 02. The optical device is at least one of an optical fingerprint sensor, an iris recognition sensor, a camera, and a flashlight.

[0105] In this application, by connecting the second semiconductor pattern layer 121 to the first semiconductor pattern layer 111, the continuity of the semiconductor pattern layer within the functional area 02 is achieved, reducing the risk of static electricity flowing into the semiconductor pattern layer within the functional area 02. Furthermore, by connecting the string of second semiconductor pattern layers 121 to the string of first semiconductor pattern layers 111, the high-density static electricity on the second semiconductor pattern layer 121 is dispersed across the first semiconductor pattern layer 111 and the second semiconductor pattern layer 121, ensuring a uniform distribution of static electricity within the semiconductor pattern layer. This, in turn, improves the reliability and uniformity of the performance of the semiconductor pattern layer during subsequent high-temperature processes, ensuring substantially consistent driving capabilities across the pixel circuits and achieving uniform display across the display panel.

[0106] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: a regular display area, the regular display area comprising a first display area, a second display area, and a third display area; wherein, along a first direction, a length of the second display area is smaller than a length of the first display area and a length of the third display area, respectively, and a length of the first display area is smaller than a length of the third display area; a functional area, wherein the sub-pixel density of the functional area is less than the sub-pixel density of the conventional display area; along the first direction, the second display area, the functional area, and the first display area are adjacent in sequence; along the second direction, at least one of the first display area, the second display area, and the functional display area are adjacent to the third display area; the first direction intersects the second direction; wherein: One of the first display area and the third display area is a specific display area, the specific display area includes a plurality of first pixel circuits, the first pixel circuit includes a first semiconductor pattern layer, the first semiconductor pattern layer is connected to at least one of the first semiconductor pattern layers arranged along a third direction and adjacent thereto; an angle α between the third direction and the first direction is 90°>α≥0°; The second display area includes a plurality of second pixel circuits, each of the second pixel circuits includes a second semiconductor pattern layer, the second semiconductor pattern layer is connected to at least one second semiconductor pattern layer arranged along a fourth direction and adjacent thereto; an angle between the fourth direction and the first direction is a second angle β, 90°>β≥0°; In which, the second semiconductor pattern layers arranged and connected along the fourth direction and the first semiconductor pattern layers arranged and connected along the third direction are connected by a connecting structure, and one of the connecting structures is connected to multiple second semiconductor pattern layers near the functional area in the second display area, and is connected to multiple first semiconductor pattern layers near the functional area in the first display area.

2. The display panel according to claim 1, wherein: The connection structure is a ring structure.

3. The display panel according to claim 1, wherein: The connection structure is arranged on the same layer as the first semiconductor pattern layer.

4. The display panel according to claim 1, wherein: The functional area includes a light-transmitting area and a transition area surrounding the light-transmitting area, and the connecting structure is located in the transition area.

5. The display panel according to claim 4, wherein: The transition region includes a metal wiring group, the metal wiring group includes a plurality of metal wirings, and the connection structure is arranged on a side of the metal wiring group away from the light-transmitting region.

6. The display panel according to claim 1, wherein: The sub-pixel density of the light-transmitting area is 0.

7. The display panel according to claim 6, wherein: The light-transmitting area is a hollow area of ​​the display panel.

8. The display panel according to claim 7, wherein: The light-transmitting area is a non-hollowed area of ​​the display panel.

9. The display panel according to claim 1, wherein: The sub-pixel density of the light-transmitting area is greater than 0.

10. The display panel according to claim 1, wherein The third display area is the specific display area; the display panel also includes a semiconductor connection area; the semiconductor connection area includes at least one connection structure; one connection structure is connected to multiple second semiconductor pattern layers near the semiconductor connection area in the second display area, and one connection structure is connected to multiple first semiconductor pattern layers near the semiconductor connection area in the third display area.

11. The display panel according to claim 10, wherein: Along the first direction, all the second semiconductor pattern layers close to the semiconductor connection area in the second display area are connected to one connection structure, and all the first semiconductor pattern layers close to the semiconductor connection area in the third display area are connected to the same connection structure.

12. The display panel according to claim 1, wherein The third direction is parallel to the fourth direction, and 90°>α>0°, and 90°>β>0°.

13. The display panel according to claim 1, wherein The third direction is parallel to the fourth direction, and α=0° and β=0°.

14. The display panel according to claim 1, wherein The first semiconductor pattern layer and the second semiconductor pattern layer are both made of one of polysilicon and metal oxide semiconductor.

15. A display device, characterized in that: It comprises the display panel and optical device according to any one of claims 1 to 14, wherein the optical device is arranged at a position of the display device corresponding to the functional area.

16. The display device according to claim 15, wherein: The optical device is at least one of an optical fingerprint sensor, an iris recognition sensor, a camera, and a flashlight.

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