Display device

Abstract

A display device includes: a substrate having a display area including a plurality of sub-pixels; a first bank layer on the substrate to define a plurality of sub-pixels; a light emitting diode in each of the plurality of sub-pixels, the light emitting diode including a first electrode, a light emitting layer on the first electrode, and a second electrode on the light emitting layer; and field generation units on both sides of the light-emitting layer, the field generation units applying an electric field parallel to the substrate to the light-emitting layer.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device with improved light emitting efficiency. Background Art

[0002] Recently, with the development of multimedia, the importance of display devices has increased. As a result, flat panel displays such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light-emitting diode (OLED) displays have been commercialized. Among various flat panel displays, OLED display devices are widely used due to their high response speed, high brightness, and wide viewing angle.

[0003] However, the OLED display device has a disadvantage of low light extraction efficiency. In addition, when the OLED display device displays an image using red light emitting diodes, green light emitting diodes, and blue light emitting diodes, the OLED display device has a light emission efficiency of 10% or less.

[0004] The description provided in this Background section should not be assumed to qualify as prior art merely because it is mentioned in or related to the Background section.The Background section may include information that describes one or more aspects of the subject technology. Summary of the Invention

[0005] Accordingly, the present disclosure is directed to a display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0006] An aspect of the present disclosure is to provide a display device having improved light emitting efficiency.

[0007] Other features and aspects of the present disclosure will be set forth in the following description, and in part will be apparent from the description, or may be learned by practicing the present disclosure. These and other aspects of the present disclosure will be realized and obtained through the structures particularly pointed out in the written description and the appended claims as well as the drawings.

[0008] To achieve these and other aspects and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a display device includes: a substrate having a display area, the display area having a plurality of sub-pixels; a first embankment layer on the substrate to define the plurality of sub-pixels; a light-emitting diode in each of the plurality of sub-pixels, the light-emitting diode including a first electrode, a light-emitting layer on the first electrode, and a second electrode on the light-emitting layer; and a field generating unit at both sides of the light-emitting layer, the field generating unit applying an electric field parallel to the substrate to the light-emitting layer.

[0009] In another aspect, a display device includes: a substrate having a display area, the display area having a plurality of sub-pixels; a first embankment layer on the substrate to define the plurality of sub-pixels; and a light-emitting diode in each of the plurality of sub-pixels, the light-emitting diode including a first electrode, a light-emitting layer on the first electrode, and a second electrode on the light-emitting layer, wherein the light-emitting molecules of the light-emitting layer are horizontally arranged to be parallel to the substrate.

[0010] According to one or more aspects of the present disclosure, the electric field generated by the ferroelectric pattern is applied to the light-emitting layer, which causes the light-emitting molecules in the light-emitting layer to be arranged horizontally, parallel to the surface of the substrate. Since holes and electrons move vertically, the internal quantum efficiency of the light-emitting layer and the luminous efficiency of the display device are improved.

[0011] According to one or more aspects of the present disclosure, as the ferroelectric pattern is subjected to heat treatment, the polarity state of the ferroelectric pattern is removed, thereby preventing or reducing current leakage between adjacent pixels due to polarity.

[0012] It is to be understood that both the foregoing general description and the following detailed description are explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure, and together with the description serve to explain the various principles of the present disclosure. In the drawings:

[0014] Figure 1A and Figure 1B are diagrams respectively showing random arrangement and vertical arrangement of light-emitting molecules of a light-emitting layer of a display device according to a comparative example;

[0015] Figure 2 is a diagram illustrating a horizontal arrangement of light-emitting molecules of a light-emitting layer of a display device according to an example embodiment of the present disclosure;

[0016] Figure 3 is a diagram illustrating a display device according to a first exemplary embodiment of the present disclosure;

[0017] Figure 4 is a diagram illustrating a sub-pixel of a display device according to an example embodiment of the present disclosure;

[0018] Figure 5 is a circuit diagram illustrating a sub-pixel of a display device according to a first exemplary embodiment of the present disclosure;

[0019] Figure 6 is a cross-sectional view showing a display device according to a first exemplary embodiment of the present disclosure;

[0020] Figure 7 is a cross-sectional view showing a light emitting layer and a ferroelectric layer of a display device according to a first exemplary embodiment of the present disclosure;

[0021] Figures 8A to 8E is a cross-sectional view illustrating a method of manufacturing a display device according to a first exemplary embodiment of the present disclosure;

[0022] Figure 9 is a cross-sectional view showing a display device according to a second exemplary embodiment of the present disclosure; and

[0023] Figure 10 is a cross-sectional view illustrating a display device according to a third exemplary embodiment of the present disclosure.

[0024] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The size, length, and thickness of layers, regions, and elements, and their illustrations may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0025] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be shown in the accompanying drawings. In the following description, detailed descriptions of known functions or configurations associated with this document will be omitted when they are determined to be unnecessary to obscure the essence of the inventive concept. The described progression of processing steps and / or operations are examples; however, the order of steps and / or operations is not limited to the order described herein and may be changed as known in the art, except for steps and / or operations that are required to occur in a specific order. Similar reference numerals refer to similar elements throughout. The names of the corresponding elements used in the following description may be selected solely for ease of writing the specification and may therefore be different from the names used in the actual product.

[0026] The advantages and features of the present disclosure and their implementation methods will be illustrated by the example embodiments described below with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the example embodiments described herein. On the contrary, these example embodiments are provided to make the present disclosure sufficiently thorough and complete to help those skilled in the art fully understand the scope of the present disclosure. In addition, the present disclosure is limited only by the scope of the claims.

[0027] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings for describing various exemplary embodiments of the present disclosure are given by way of example only. Therefore, the present disclosure is not limited to the illustrations in the drawings. Unless otherwise specified, like reference numerals refer to like elements throughout the specification.

[0028] In the following description, when a detailed description of related known functions or configurations may unnecessarily obscure features or aspects of the present disclosure, a detailed description of such known functions or configurations may be omitted or a brief description may be provided.

[0029] When the terms "comprising," "having," "including," "formed by," etc. are used, one or more other elements may be added unless a term such as "only" is used. Elements described in the singular are intended to include plural elements, and vice versa, unless the context clearly indicates otherwise. Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0030] When interpreting an element, even if an explicit description of the error or tolerance range is not provided, the element is interpreted as including the error or tolerance range.

[0031] When describing temporal relationships, discontinuities may be included when the temporal order is described as, for example, "after," "following," "next," and "before," unless more restrictive terms such as "only," "immediately," or "directly" are used.

[0032] When describing a positional relationship, for example, when using "on," "above," "below," "above," "below," "near," "adjacent," or "adjacent," "next to," or "next to" to describe the positional relationship between two components, one or more other components may be located between the two components, unless more restrictive terms such as "immediately," "directly," or "closely" are used. For example, when a structure is described as being located "on," "above," "below," "above," "below," "near," "adjacent," or "adjacent," "next to," or "next to" another structure, this description should be interpreted as including the case where these structures are in contact with each other and the case where a third structure is disposed or interposed therebetween. In addition, the terms "left," "right," "top," "bottom," "downward," "upward," "upper," "lower," or the like refer to an arbitrary reference system.

[0033] Although the terms "first," "second," "A," "B," "(a), (b)," etc., may be used herein to refer to various elements, these elements should not be construed as limited by these terms, as they are not used to define a particular order or precedence. These terms are only used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element without departing from the scope of this disclosure.

[0034] The term “at least one” should be understood to include all combinations of one or more of the relevant elements. For example, “at least one of the first element, the second element, and the third element” may include all combinations of two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0035] The term "display device" may include a narrow sense display device including a display panel and a driving unit for driving the display panel, such as a liquid crystal module (LCM), an organic light emitting diode (OLED) module, and a quantum dot (QD) module. In addition, the term "display device" may include a finished product (or final product) including an LCM, an OLED module, and a QD module, such as a notebook computer, a television, a computer monitor, an equipment display device including an in-vehicle display device or a shape other than a vehicle, and a complete set of electronic devices or a complete set (or complete set) of mobile electronic devices such as a smart phone or an electronic tablet.

[0036] Therefore, the display device of the present disclosure may include narrowly defined display devices such as LCM, OLED module, QD module, and application products or complete sets of devices of end users including LCM, OLED module, QD module.

[0037] Depending on the situation, an LCM, an OLED module, and a QD module having a display panel and a driving unit may be referred to as a "display device," and an electronic device comprising a complete product of an LCM, an OLED module, and a QD module may be referred to as a "set." For example, a display device in a narrow sense may include a display panel of liquid crystal, organic light-emitting diodes, and quantum dots, and a source printed circuit board (PCB) of a control unit for driving the display panel, and the set may further include a set PCB electrically connected to the source PCB for controlling a set control unit of the entire set.

[0038] The display panel of the present disclosure may include any type of display panel, such as a liquid crystal display panel, an organic light-emitting diode display panel, an inorganic light-emitting diode display panel, a quantum dot display panel, and an electroluminescent display panel. The display panel of the present disclosure is not limited to an organic light-emitting diode display panel having a flexible substrate and a specific display panel having a curved frame of a lower backplane support, and the shape or size of the display panel of the display device of the present disclosure is not limited thereto.

[0039] For example, when the display panel is an organic light emitting diode display panel, the display panel may include a plurality of gate lines, a plurality of data lines, and sub-pixels located in the intersection area of ​​the plurality of gate lines and the plurality of data lines. The display panel may include an array of thin film transistors having an element for selectively applying a voltage to each sub-pixel, a light emitting element layer on the array, and an encapsulation substrate or encapsulation component covering the light emitting element layer. The encapsulation component can protect the thin film transistors and the light emitting element layer from external impacts and can prevent or at least reduce the penetration of moisture or oxygen into the light emitting element layer. In addition, the layer on the array may include an inorganic light emitting layer, for example, a nano-sized material layer or quantum dots.

[0040] The thin film transistor of the present disclosure may include one of an oxide thin film transistor, an amorphous silicon thin film transistor, and a low-temperature polysilicon thin film transistor, but the present disclosure is not limited thereto.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, for example, and should not be interpreted as having an overly idealized or overly formal meaning, unless expressly defined as such herein. For example, the term "component" or "unit" may apply, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as would be understood by one of ordinary skill in the art.

[0042] The features of the various embodiments of the present disclosure may be partially or completely interconnected or combined. They may be technically linked and operated in various ways that are fully understood by those skilled in the art. These embodiments may be performed independently or in association with each other in various combinations.

[0043] Hereinafter, a display device according to various example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, in which luminous efficiency is improved and / or the influence on the oxide semiconductor layer of the thin film transistor of the driving element part is reduced by shielding light emitted and transmitted from the sub-pixel and / or light input from the outside.

[0044] The luminous efficiency of an organic light-emitting diode (OLED) display is determined by its internal quantum efficiency (IQE) and external quantum efficiency (EQE). Since the internal quantum efficiency is determined by the luminescent material and the internal structure of the display, it is improved through the development of luminescent materials and changes in the internal structure.

[0045] Due to differences in refractive index between the inside and outside of a display device, light may be trapped and unable to escape, or it may be lost due to surface plasmon polaritons. Consequently, external quantum efficiency is determined by this light loss. To improve external quantum efficiency, research is underway to minimize or reduce the effects of refractive index differences and surface plasmon polaritons.

[0046] In the present disclosure, the luminous efficiency of a display device is improved by changing the arrangement of luminescent molecules (e.g., phosphorescent molecules or fluorescent molecules), and the luminous efficiency of a display device is improved by changing the arrangement of luminescent molecules in a luminescent layer (rather than external conditions such as the structure or refractive index of the display device).

[0047] Figure 1A and Figure 1B are diagrams respectively showing random arrangement and vertical arrangement of light-emitting molecules of a light-emitting layer of a display device according to a comparative example, and Figure 2 is a diagram illustrating a horizontal arrangement of light-emitting molecules of a light-emitting layer of a display device according to an embodiment of the present disclosure.

[0048] exist Figure 1A In the embodiment, when the light emitting layer LEL is formed by depositing a light emitting material on the display device according to the comparative example without external force, the light emitting molecules LEM are randomly arranged in the light emitting layer LEL. The random arrangement of the light emitting molecules LEM may reduce light emitting efficiency.

[0049] In an organic light-emitting diode display device, when holes h and electrons e are injected into the light-emitting layer (LEL) from the anode (AND) having a relatively high work function and the cathode (CAT) having a relatively low work function, excitons are generated in the light-emitting layer (LEL). As the excitons decay, light corresponding to the energy difference between the lowest unoccupied molecular orbital (LUMO) and the highest occupied molecular orbital (HOMO) of the light-emitting layer (LEL) is generated to display an image.

[0050] As a result, the luminous efficiency of the light emitting layer LEL changes according to the probability of holes h and electrons e meeting. To increase the probability of holes h and electrons e meeting, holes h and electrons e should move toward the cathode CAT and anode AND along the vertical direction in which the cathode CAT and anode AND are arranged.

[0051] The movement of holes h and electrons e in organic materials is performed by hopping between organic molecules. Holes h and electrons e move by hopping between the backbones of light-emitting molecules (LEMs) of organic molecules.

[0052] When the light-emitting molecules LEM are randomly arranged in the light-emitting layer LEL, the holes h and electrons e do not move vertically toward the cathode CAT and anode AND, but move randomly. As a result, the probability of the holes h and electrons e meeting each other is reduced, and the light-emitting efficiency is reduced.

[0053] exist Figure 1B In the embodiment, the light emitting molecules LEM are arranged along the vertical direction in which the cathode CAT and the anode AND are arranged. The light emitting layer LEL is provided between the cathode CAT and the anode AND, and holes h and electrons e from the anode AND and the cathode CAT are transferred along the vertical direction.

[0054] The light-emitting molecules LEM can be arranged in a vertical direction due to an increase in temperature during the deposition step or subsequent steps of the light-emitting layer LEL. The light-emitting molecules LEM of organic molecules are arranged due to interaction with the substrate at a temperature equal to or lower than the glass transition temperature Tg. As the temperature increases to approach the glass transition temperature Tg, the light-emitting molecules LEM form aggregates for thermodynamic stabilization rather than interacting with the substrate. As the temperature increases, the light-emitting molecules LEM are arranged in a vertical direction to reduce the contact area between the main chain and the substrate. In addition, because the light-emitting layer LEL continuously absorbs heat generated during the process, the light-emitting molecules LEM are arranged in a vertical direction perpendicular to the substrate.

[0055] When the light-emitting molecules LEM are arranged in the vertical direction so that the main chains are parallel to the vertical direction, the holes h and the electrons e move by jumping between the main chains of the light-emitting molecules LEM. Since the holes h and the electrons e move in the horizontal direction rather than the vertical direction, the probability of the holes h and the electrons e meeting is further reduced compared to the light-emitting layer LEL in which the main chains of the light-emitting molecules LEM are randomly arranged, and the luminescence efficiency is further reduced.

[0056] Figure 2 is a diagram illustrating the arrangement of light-emitting molecules of a display device according to a first embodiment of the present disclosure.

[0057] exist Figure 2 In the display device according to the embodiment of the present disclosure, the field generating unit (field generating pattern) EGM is used to generate an electric field E in the light emitting layer LEL along a horizontal direction perpendicular to the vertical direction in which the anode AND and the cathode CAT are arranged. Since the light emitting molecules LEM in the light emitting layer LEL are organic molecules having polarity, the light emitting molecules LEM are arranged along the electric field E. Since the electric field E is generated in a horizontal direction perpendicular to the vertical direction, the light emitting molecules LEM are arranged in the horizontal direction parallel to the anode AND and the cathode CAT.

[0058] Since the holes h released from the anode AND and the electrons e released from the cathode CAT move between the main chains of the light-emitting molecules LEM by hopping, the holes h and the electrons e move in the vertical direction toward the cathode CAT and the anode AND. As a result, the probability of the holes h and the electrons e in the light-emitting layer LEL meeting each other increases, and the light-emitting efficiency is improved. It should be noted that although Figure 2 The embodiment shown is described as the light-emitting molecules LEM being arranged horizontally, but the art is not limited thereto. For example, when the light-emitting molecules LEM are arranged to intersect the direction from the anode AND to the cathode CAT, the luminous efficiency will also be increased compared to the vertical arrangement or random arrangement of the light-emitting molecules LEM.

[0059] Figure 3 is a diagram showing a display device according to a first embodiment of the present disclosure, and Figure 4 is a diagram illustrating sub-pixels of a display device according to a first embodiment of the present disclosure.

[0060] exist Figure 3 In the embodiment of the present disclosure, the display device 100 includes an image processing unit 102 , a timing control unit 104 , a gate driving unit 106 , a data driving unit 107 , a power supply unit 108 , and a display panel 109 .

[0061] The image processing unit 102 outputs a plurality of timing signals for each unit and an image signal provided from the outside. For example, the plurality of timing signals may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0062] The timing control unit 104 receives an image signal and a plurality of timing signals from the image processing unit 102. The timing control unit 104 generates image data DATA, a gate control signal GDC, and a data control signal DDC using the image signal and the plurality of timing signals. The timing control unit 104 transmits the gate control signal GDC to the gate driving unit 106 and transmits the image data and the data control signal DDC to the data driving unit 107.

[0063] The gate driving unit 106 generates a gate signal (gate voltage, scan signal) using the gate control signal GDC transmitted from the timing control unit 104 and applies the gate signal to the plurality of gate lines GL1 to GLm of the display panel 109. Although the gate driving unit 106 may be formed as an integrated circuit (IC), it is not limited thereto.

[0064] The gate driving unit 106 may have a gate in panel (GIP) type in which the gate driving unit 106 is provided on a substrate of the display panel 109 .

[0065] The data driving unit 107 generates a data signal (data voltage) using the data control signal DDC and the image data DATA sent from the timing control unit 104, and applies the data signal to the plurality of data lines DL1 to DLn of the display panel 109. The data driving unit 107 samples and latches the digital image data DATA to output an analog data signal based on the gamma reference voltage. Although the data driving unit 107 can be formed as an integrated circuit (IC), it is not limited thereto.

[0066] The power supply unit 108 outputs a high-level voltage Vdd and a low-level voltage Vss. The power supply unit 108 provides the high-level voltage Vdd to the display panel 109 through a first power line EVDD, and provides the low-level voltage Vss to the display panel 109 through a second power line EVSS. In addition, the high-level voltage Vdd and the low-level voltage Vss of the power supply unit 108 can be provided to the gate driving unit 106 or the data driving unit 107 for driving.

[0067] The display panel 109 displays an image using the gate signal of the gate driving unit 106 , the data signal of the data driving unit 107 , and the high-level voltage Vdd and the low-level voltage Vss of the power supply unit 108 .

[0068] The display panel 109 includes a plurality of sub-pixels SP, a plurality of gate lines GL1 to GLm, and a plurality of data lines DL1 to DLn. The plurality of sub-pixels SP may include red, green, and blue sub-pixels SP or white, red, green, and blue sub-pixels SP. The white, red, green, and blue sub-pixels SP may have the same area as each other or may have different areas from each other.

[0069] exist Figure 4 In the embodiment, a single sub-pixel SP can be connected to a gate line GL1, a data line DL1, a first power line EVDD, and a second power line EVSS. The driving method of the sub-pixel SP and the number of transistors and capacitors can be determined according to the structure of the sub-pixel circuit. For example, the sub-pixel SP can have a 2T1C structure including two transistors and one capacitor. In another embodiment, the sub-pixel SP can have a structure selected from 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2C, and 8T2C. However, the present disclosure is not limited thereto, and more or fewer transistors and capacitors can be included in the sub-pixel SP.

[0070] Figure 5 is a circuit diagram illustrating a sub-pixel of a display device according to a first embodiment of the present disclosure.

[0071] exist Figure 5, the display device 100 includes a gate line GL, a data line DL, and a power line PL crossing each other to define a sub-pixel SP. A switching transistor Ts, a driving transistor Td, a storage capacitor Cst, and a light emitting diode D are provided in the sub-pixel SP.

[0072] The switching transistor Ts is connected to the gate line GL and the data line DL. The driving transistor Td and the storage capacitor Cst are connected between the switching transistor Ts and the power line PL. The light emitting diode D is connected to the driving transistor Td.

[0073] When the switching transistor Ts is turned on according to the gate signal of the gate line GL, the data signal of the data line DL is applied to the gate electrode of the driving transistor Td and one capacitor electrode of the storage capacitor Cst through the switching transistor Ts.

[0074] Since the driving transistor Td is turned on according to the data signal, current proportional to the data signal flows from the power line PL through the driving transistor Td to the light emitting diode D, and the light emitting diode D emits light with brightness proportional to the current flowing through the driving transistor Td.

[0075] The storage capacitor Cst is charged with a voltage proportional to the data signal to keep the voltage of the gate electrode of the driving transistor Td constant within one frame.

[0076] Despite Figure 5 The subpixel SP includes two transistors Ts and Td and one capacitor Cst in one embodiment, but may include three or more transistors and two or more capacitors in another embodiment.

[0077] Figure 6 1 is a cross-sectional view showing a display device according to a first embodiment of the present disclosure. Although the display device 100 includes a plurality of sub-pixels, for ease of description, Figure 6 In addition, although a plurality of thin film transistors and a plurality of wires are provided in the sub-pixel, for the sake of convenience, Figure 6 Only one thin film transistor in the display area AA is shown in FIG.

[0078] exist Figure 6 In the embodiment, the buffer layer 142 is provided on the substrate 140. The substrate 140 may include a hard material such as glass or a soft material such as plastic.

[0079] When the substrate 140 includes a plastic material, the substrate 140 may include at least one of polyimide (PI), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyethersulfone (PES), and polycarbonate (PC), and is not limited thereto.

[0080] When the substrate 140 includes polyimide, the substrate 140 may include a plurality of polyimide layers. In addition, an inorganic layer may be provided between the polyimide layers, and is not limited thereto.

[0081] The buffer layer 142 may be provided on the entire substrate 140 to increase adhesive strength between each layer and the substrate 140 and to block alkali components released from the substrate 140. In addition, the buffer layer 142 may delay diffusion of moisture or oxygen penetrating the substrate 140.

[0082] The buffer layer 142 may include a single layer or multiple layers of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx). When the buffer layer 142 includes multiple layers, the silicon nitride (SiNx) layers and the silicon oxide (SiOx) layers may alternate with each other. The buffer layer 142 may be omitted depending on the type and material of the substrate 140 and the structure and type of the thin film transistor.

[0083] The thin film transistor T is provided on the buffer layer 142. Figure 6 FIG shows a driving thin film transistor among a plurality of thin film transistors in the display area AA, but the sub-pixel may include other thin film transistors such as a switching thin film transistor. Figure 6 The thin film transistor T in FIG. 4 has a top gate structure, but the thin film transistor T may have other structures such as a bottom gate structure or a double gate structure.

[0084] The thin film transistor T includes a semiconductor layer 112 on a buffer layer 142 , a gate insulating layer 144 on the semiconductor layer 112 , a gate electrode 114 on the gate insulating layer 144 , an interlayer insulating layer 146 on the gate electrode 114 , and a source electrode 115 and a drain electrode 116 on the interlayer insulating layer 146 .

[0085] The semiconductor layer 112 may include a polycrystalline semiconductor material. For example, the polycrystalline semiconductor material may include polysilicon, but is not limited thereto.

[0086] The semiconductor layer 112 may include an oxide semiconductor material. For example, the oxide semiconductor material may include one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), and is not limited thereto. In another example, the oxide semiconductor material may include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. Specifically, the oxide semiconductor material may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto. The semiconductor layer 112 has a channel region 112 a of an intrinsic material located at a central portion thereof, and a source region 112 b and a drain region 112 c of a dopant material located on both sides of the channel region 112 a .

[0087] The gate insulating layer 144 may have a single layer or multiple layers of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx), and is not limited thereto. The gate insulating layer 144 is an insulating layer for insulating the semiconductor layer 112 and the gate electrode 114 from each other.

[0088] The gate electrode 114 includes a metal material. For example, the gate electrode 114 may include a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof, but is not limited thereto.

[0089] The interlayer insulating layer 146 may have a single layer or multiple layers of an organic insulating material such as photo-acrylic or an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx). In addition, the interlayer insulating layer 146 may have multiple layers of organic layers and inorganic layers, and is not limited thereto.

[0090] The source electrode 115 and the drain electrode 116 may include a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof, and are not limited thereto. The source electrode 115 and the drain electrode 116 may be connected to the source region 112 b and the drain region 112 c of the semiconductor layer 112, respectively, through contact holes in the gate insulating layer 144 and the interlayer insulating layer 146.

[0091] Although not shown, the bottom shield metal layer may include a material capable of blocking or reflecting light and may be provided on the substrate 140 below the semiconductor layer 112. The bottom shield metal layer may minimize or reduce a back channel phenomenon generated by charges trapped in the substrate 140 to prevent or reduce afterimages or degradation of transistors. The bottom shield metal layer may include a single layer or multiple layers of one of titanium (Ti), molybdenum (Mo), and alloys thereof, and is not limited thereto.

[0092] The planarization layer 148 is provided on the thin film transistor T over the entire substrate 140. The planarization layer 148 may be configured to protect the thin film transistor and flatten steps caused by the thin film transistor. The planarization layer 148 may include an organic insulating material such as photo-acrylic, but is not limited thereto. The planarization layer 148 may include multiple layers of inorganic and organic layers.

[0093] The light emitting diode D is disposed on the planarization layer 148 in the display area AA. The light emitting diode D includes a first electrode 132, a light emitting layer 134, and a second electrode 136.

[0094] The first electrode 132 may be an anode. The first electrode 132 is disposed on the planarization layer 148 and is electrically connected to the drain electrode 116 of the thin film transistor T through a contact hole in the planarization layer 148. The first electrode 132 may include at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), and alloys thereof. Alternatively, the first electrode 132 may include a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0095] When the display device 100 has a top emission type, the first electrode 132 may further include an opaque conductive material for using the first electrode 132 as a reflective layer. When the display device 100 has a bottom emission type, the first electrode 132 may include a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0096] The bank layer BNK is provided in the boundary region of each sub-pixel. The bank layer BNK may be a kind of wall defining the sub-pixel. The bank layer BNK may prevent or reduce mixing of light of various colors emitted from adjacent sub-pixels.

[0097] The bank layer BNK may include at least one of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx), an organic insulating material such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin, and a photosensitive material including a black pigment, and is not limited thereto.

[0098] The ferroelectric pattern 150 is provided between the first electrode 132 and the bank layer BNK in the sub-pixel. The ferroelectric pattern 150 is a field generating unit EGM for arranging light emitting molecules of the light emitting layer 134 by applying an electric field to the light emitting layer 134.

[0099] The ferroelectric pattern 150 may extend from the planarization layer 148 toward the top edge surface of the first electrode 132 to wrap around the first electrode 132 in the boundary region. Since the bank layer BNK covers the ferroelectric pattern 150, a portion of each ferroelectric pattern 150 on the top edge surface of the first electrode 132 extends from the bank layer BNK, and the other portion of each ferroelectric pattern 150 is covered by the bank layer BNK.

[0100] The light-emitting layer 134 includes an organic light-emitting material. The light-emitting layer 134 is provided on the top surface of the first electrode 132 exposed by the ferroelectric pattern 150 so as to extend toward the non-display area NA. The thickness of the light-emitting layer 134 may be equal to or less than the thickness of each ferroelectric pattern 150, so that the side surface of each ferroelectric pattern 150 contacts the side surface of the light-emitting layer 134.

[0101] The ferroelectric pattern 150 may be formed by a deposition method. As a result, the ferroelectric pattern 150 may include a ferroelectric material having a Curie temperature higher than a deposition temperature of about 90° C. to about 100° C. For example, the ferroelectric pattern 150 may include a perovskite (ABO3) material such as barium titanate (BaTiO3), lead titanate (PbTiO3), potassium niobate (KNbO3), and potassium tantalate (KTaO3), and is not limited thereto.

[0102] The light emitting layer 134 may include a red light emitting layer emitting red light in the red sub-pixel, a green light emitting layer emitting green light in the green sub-pixel, and a blue light emitting layer emitting blue light in the blue sub-pixel.

[0103] The light emitting layer 134 may include a light emitting material layer, an electron injection layer that injects electrons, a hole injection layer that injects holes, an electron transport layer that transports electrons, a hole blocking layer that blocks holes, an electron blocking layer that blocks electrons, and a hole transport layer that transports holes, and is not limited thereto.

[0104] The second electrode 136 is provided on the light emitting layer 134. The second electrode 136 may have a single layer or multiple layers of a metal material or a metal material alloy. Alternatively, the second electrode 136 may include a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), but is not limited thereto.

[0105] When the display device 100 has a top emission type, the second electrode 136 may include a semi-transmissive conductive material that transmits light. For example, the second electrode 136 may include at least one of LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, and a LiF / Ca:Ag alloy.

[0106] When the display device 100 has a bottom emission type, the second electrode 136 may include an opaque conductive material to use the second electrode 136 as a reflective layer. For example, the second electrode 136 may include at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), and alloys thereof.

[0107] The light-emitting diode D may have a tandem structure. The tandem structure may include a plurality of light-emitting layers and a charge generation layer between the plurality of light-emitting layers. The charge generation layer for adjusting the charge balance of the plurality of light-emitting layers may have a multilayer including a first charge generation layer and a second charge generation layer. The charge generation layer may include a negative (N) type charge generation layer and a positive (P) type charge generation layer. For example, the charge generation layer may include a light-emitting layer doped with an alkali metal such as lithium (Li), sodium (Na), potassium (K), and cesium (Cs), or an alkaline earth metal such as magnesium (Mg), strontium (Sr), barium (Ba), and radium (Ra), and is not limited thereto.

[0108] Encapsulation layer 180 is provided on light-emitting diode D to encapsulate the light-emitting diode D. When light-emitting diode D is exposed to moisture or oxygen, pixel shrinkage may occur, where the light-emitting area is reduced or dark spots in the light-emitting area deteriorate. Furthermore, moisture or oxygen may oxidize metal electrodes. Encapsulation layer 180 blocks or reduces the penetration of moisture or oxygen from the outside, thereby preventing or reducing degradation of light-emitting diode D and electrodes.

[0109] Although the encapsulation layer 180 has three layers of the first encapsulation layer 182 , the second encapsulation layer 184 , and the third encapsulation layer 186 in the first embodiment, the encapsulation layer 180 may have two or four layers in another embodiment.

[0110] The first encapsulation layer 182 and the third encapsulation layer 186 may include a single layer or multiple layers of inorganic materials such as silicon oxide (SiOx), silicon oxynitride (SiON), and silicon nitride (SiNx). The first encapsulation layer 182 and the third encapsulation layer 186 may also include an organic material between the inorganic materials, but are not limited thereto. The second encapsulation layer 184 may include epoxy resin.

[0111] Although not shown, the display device 100 may include a touch unit. The touch unit may be provided in the display area to sense touch input. For example, the touch unit may sense external touch information using a user's finger or a touch pen.

[0112] In the display device 100 according to the first embodiment of the present disclosure, since the ferroelectric patterns 150 are respectively provided on opposite sides of the light emitting layer 134 , an electric field is generated between the ferroelectric patterns 150 , and the light emitting molecules are horizontally arranged along the electric field.

[0113] Figure 7 is a cross-sectional view illustrating a light emitting layer and a ferroelectric layer of a display device according to a first embodiment of the present disclosure.

[0114] exist Figure 7 In the embodiment, the ferroelectric layer or the ferroelectric pattern 150 is provided on opposite sides of the light emitting layer 134. Since the ferroelectric layer or the ferroelectric pattern 150 of the ferroelectric material is polarized in the horizontal direction at a temperature lower than the Curie temperature, an electric field E to be applied to the light emitting layer 134 is generated between portions of the ferroelectric layer or the ferroelectric pattern 150 located on both sides of the light emitting layer 134.

[0115] Since the light emitting molecules 134a of the light emitting layer 134 are polar molecules, the light emitting molecules 134a are arranged along the electric field E applied to the light emitting layer 134. As a result, the light emitting molecules 134a are horizontally arranged to be parallel to the surface of the substrate 140.

[0116] When the luminescent molecule 134a is Figure 2 When arranged horizontally as shown, holes h emitted from the first electrode 132 move in a vertical direction toward the second electrode 136, and electrons e emitted from the second electrode 136 move in a vertical direction toward the first electrode 132. As a result, the probability of the holes h and the electrons e meeting each other increases, and the internal quantum efficiency of the light-emitting layer 134 and the light-emitting efficiency of the display device 100 are improved.

[0117] Hereinafter, a method of manufacturing the display device 100 will be exemplified.

[0118] Figures 8A to 8E is a cross-sectional view illustrating a method of manufacturing the display device according to the first embodiment of the present disclosure.

[0119] exist Figure 8AIn the embodiment of the present invention, a buffer layer 142 is formed on the entire substrate 140. The substrate 140 may include a hard material such as glass or a plastic material such as polyimide (PI), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyethersulfone (PES), and polycarbonate (PC). The buffer layer 142 may have a single layer or multiple layers of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx).

[0120] Next, after forming a semiconductor material layer of a polycrystalline semiconductor material such as polysilicon or an oxide semiconductor material such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO) on the buffer layer 142, the semiconductor layer 112 is formed on the buffer layer 142 in each sub-pixel SP by patterning the semiconductor material layer. Next, a channel region 112 a, a source region 112 b, and a drain region 112 c are formed in the semiconductor layer 112 by doping the side portions of the semiconductor layer 112 with impurities.

[0121] Next, a gate insulating layer 144 made of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx) is formed on the semiconductor layer 112 over the entire substrate 140. Next, a metal material layer made of a metal material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) is formed on the gate insulating layer 144. The gate electrode 114 is then formed on the gate insulating layer 144 in each sub-pixel SP by patterning the metal material layer. Next, an interlayer insulating layer 146 made of an organic insulating material such as photo-acrylic or an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx) is formed on the gate electrode 114 over the entire substrate 140. Contact holes are then formed in the interlayer insulating layer 146 and the gate insulating layer 144 by patterning to expose the source region 112b and the drain region 112c.

[0122] Next, a metal material layer, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), is formed on the interlayer insulating layer 146. Then, the metal material layer is patterned, and a source electrode 115 and a drain electrode 116 are formed on the interlayer insulating layer 146 in each sub-pixel SP, respectively contacting the source region 112 b and the drain region 112 c of the semiconductor layer 112. The semiconductor layer 112, the gate insulating layer 144, the gate electrode 114, the source electrode 115, and the drain electrode 116 constitute a thin film transistor T.

[0123] exist Figure 8B In the embodiment, after forming a planarization layer 148 of an organic insulating material such as photo-acrylic on the thin film transistor T over the entire substrate 140 , a contact hole exposing the drain electrode 116 is formed in the planarization layer 148 by patterning.

[0124] Next, after forming a metal material layer of a metal material such as silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr) or a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) on the planarization layer 148, the first electrode 132 in contact with the drain electrode 116 of the thin film transistor T is formed on the planarization layer 148 by patterning the metal material layer.

[0125] exist Figure 8C In the process, after a ferroelectric material layer of a perovskite-type (ABO3) ferroelectric material such as barium titanate (BaTiO3), lead titanate (PbTiO3), potassium niobate (KNbO3) and potassium tantalate (KTaO3) is formed on the first electrode 132 above the entire substrate 140, a ferroelectric pattern 150 is formed on both edge portions of the first electrode 132 by patterning the ferroelectric material layer.

[0126] Next, after forming an insulating material layer of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx), an organic insulating material such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin, or a photosensitive material including a black pigment on the ferroelectric pattern 150 above the entire substrate 140, a dam layer BNK is formed on the ferroelectric pattern 150 and the planarization layer 148 by patterning the insulating material layer.

[0127] A bank layer BNK is disposed between adjacent sub-pixels SP, and a portion of each of the ferroelectric patterns 150 and a portion of the first electrode 132 are exposed through the bank layer BNK.

[0128] Next, the light emitting layer 134 is formed on the first electrode 132 by depositing and patterning a light emitting material.

[0129] The light emitting layer 134 is disposed between the ferroelectric patterns 150 such that side surfaces of the light emitting layer 134 contact side surfaces of the ferroelectric pattern 150. The ferroelectric pattern 150 and the light emitting layer 134 may have the same thickness as each other to have a flat top surface, or may have different thicknesses from each other to have a relatively small step difference on the top surface.

[0130] Since the light emitting layer 134 is disposed between the ferroelectric patterns 150, an electric field generated between the opposing ferroelectric patterns 150 is applied to the light emitting layer 134. Since the light emitting molecules randomly or vertically arranged in the light emitting layer 134 move along the electric field direction, the light emitting molecules are horizontally arranged parallel to the surface of the first electrode 132.

[0131] Although the light emitting layer 134 is formed after the bank layer BNK is formed in the first embodiment, in another embodiment, the bank layer BNK is formed after the light emitting layer 134 is formed.

[0132] exist Figure 8D In the embodiment, the substrate 140 having the ferroelectric pattern 150 is subjected to heat treatment (aging) at a temperature higher than the Curie temperature of the ferroelectric pattern 150. For example, when the ferroelectric pattern 150 includes a perovskite-type (ABO3) ferroelectric material such as barium titanate (BaTiO3), lead titanate (PbTiO3), potassium niobate (KNbO3), and potassium tantalate (KTaO3), the heat treatment may be performed at a temperature higher than about 90°C to about 100°C.

[0133] Since the ferroelectric pattern 150 is treated with heat having a temperature higher than the Curie temperature, the polarity state of the ferroelectric material of the ferroelectric pattern 150 is removed. As a result, current leakage or electron trapping between adjacent sub-pixels due to polarity is prevented or reduced.

[0134] exist Figure 8E In the embodiment, after forming a metal material layer of a metal material or a transparent conductive material on the light emitting layer 134 over the entire substrate 140, the metal material layer is patterned to form the second electrode 136 on the top and side surfaces of the light emitting layer 134, the ferroelectric pattern 150, and the bank layer BNK. The first electrode 132, the light emitting layer 134, and the second electrode 136 constitute a light emitting diode D.

[0135] Next, an encapsulation layer 180 including a first encapsulation layer 182 , a second encapsulation layer 184 , and a third encapsulation layer 186 is formed on the light emitting diode D over the entire substrate 140 by sequentially depositing an inorganic material, an organic material, and an inorganic material.

[0136] In the display device 100 according to the first embodiment of the present disclosure, since the ferroelectric patterns 150 having polarity states are provided on both sides of the light-emitting layer 134, the light-emitting molecules are arranged horizontally during the step of forming the light-emitting layer 134. As a result, the internal quantum efficiency of the light-emitting layer 134 is improved. Since the ferroelectric pattern 150 is treated with heat at a temperature higher than the Curie temperature after the step of forming the light-emitting layer 134, the polarity state of the ferroelectric molecules in the ferroelectric pattern 150 is removed. As a result, current leakage or electron trapping between adjacent sub-pixels due to polarity is prevented or reduced.

[0137] Figure 9 2 is a cross-sectional view showing a display device according to a second embodiment of the present disclosure. Illustrations of the same parts as those of the first embodiment may be omitted or may be briefly provided.

[0138] exist Figure 9 In the embodiment, the thin film transistor T and the light emitting diode D are disposed on a substrate 240 .

[0139] The thin film transistor T includes a semiconductor layer 212 on a buffer layer 242 , a gate insulating layer 244 on the semiconductor layer 212 , a gate electrode 214 on the gate insulating layer 244 , an interlayer insulating layer 246 on the gate electrode 214 , and a source electrode 215 and a drain electrode 216 on the interlayer insulating layer 246 .

[0140] A planarization layer 248 is disposed on the thin film transistor T, and a bank layer BNK is disposed in a boundary region of each sub-pixel. The light emitting diode D includes a first electrode 232, a light emitting layer 234, and a second electrode 236.

[0141] The bank layer BNK includes a first bank pattern BNK1 on the planarization layer 248 and a second bank layer BNK2 on the first bank pattern BNK1. The first bank pattern BNK1 includes a perovskite-type (ABO3) ferroelectric material such as barium titanate (BaTiO3), lead titanate (PbTiO3), potassium niobate (KNbO3), and potassium tantalate (KTaO3), or a polymer having polarity to apply an electric field to the light emitting layer 234. The first bank pattern may also be referred to as a first bank layer.

[0142] The first bank pattern BNK1 may have the same thickness as the light emitting layer 234, such that a side surface of the first bank pattern BNK1 contacts a side surface of the light emitting layer 234 to apply an electric field to the entire light emitting layer 234. Alternatively, the first bank pattern BNK1 may have a greater thickness than the light emitting layer 234. The light emitting molecules having polarity are horizontally arranged along the electric field to be parallel to the surface of the substrate 240.

[0143] The second bank layer BNK2 may include at least one of an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiOx), an organic insulating material such as benzocyclobutene (BCB), acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin, and a photosensitive material including a black pigment, and is not limited thereto.

[0144] The encapsulation layer 280 is disposed on the light emitting diode D, and includes a first encapsulation layer 282 of an inorganic material, a second encapsulation layer 284 of an organic material, and a third encapsulation layer 286 of an inorganic material.

[0145] In the display device 200 according to the second embodiment of the present disclosure, since a portion of the bank layer BNK is formed of a ferroelectric material and an electric field is generated between the bank layers BNK, the luminescent molecules are horizontally arranged to be parallel to the surface of the substrate 240, thereby improving the luminous efficiency of the display device 200.

[0146] In another embodiment, the entire bank layer BNK may be formed of a ferroelectric material to generate an electric field, and the light emitting molecules of the light emitting layer 234 may be horizontally arranged to be parallel to the surface of the substrate 240 .

[0147] After the light emitting molecules are arranged, the ferroelectric material of the bank layer BNK is treated with heat having a high temperature higher than the Curie temperature, and the polarity state of the ferroelectric material is removed.

[0148] Figure 10 3 is a cross-sectional view showing a display device according to a third embodiment of the present disclosure. Illustrations of the same parts as those of the first and second embodiments may be omitted or may be briefly provided.

[0149] exist Figure 10 In the embodiment, a ferroelectric pattern 350 for applying an electric field to the light emitting layer 334 is provided on a side surface of the bank layer BNK in contact with the light emitting layer 334 .

[0150] In the display device 300 according to the third embodiment of the present disclosure, since an electric field is generated between the ferroelectric patterns 350 of the ferroelectric material, the light-emitting molecules of the light-emitting layer 334 are horizontally arranged to be parallel to the surface of the substrate 340, thereby improving the light-emitting efficiency of the display device 300.

[0151] Although the ferroelectric pattern 350 is provided on the side surface of the bank layer BNK in the third embodiment, in another embodiment, the ferroelectric pattern 350 may be provided on both the side surface and the top surface of the bank layer BNK. Figures 6 to 10 For example, as long as the light-emitting molecules of the light-emitting layer are uniformly arranged to cross at least the vertical direction, Figures 6 to 10 The structure of the pixels in the display device shown can be changed in various ways.

[0152] Therefore, in the display device of the present disclosure, since the electric field generated by the ferroelectric pattern is applied to the light-emitting layer, the light-emitting molecules of the light-emitting layer are arranged horizontally to be parallel to the surface of the substrate. Since holes and electrons move vertically, the internal quantum efficiency of the light-emitting layer is improved, and the luminous efficiency of the display device is improved.

[0153] Furthermore, since the light emission efficiency is improved, low power consumption is achieved.

[0154] It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

[0155] CROSS-REFERENCE TO RELATED APPLICATIONS

[0156] This application claims the benefit of and priority to Korean Patent Application No. 10-2024-0027923, filed in Korea on February 27, 2024, which is hereby incorporated by reference in its entirety for all purposes.

Claims

1. A display device, comprising: a substrate, the substrate having a display area, the display area having a plurality of sub-pixels; a first bank layer on the substrate to define the plurality of sub-pixels; a light emitting diode in each of the plurality of sub-pixels, the light emitting diode comprising a first electrode, a light emitting layer on the first electrode, and a second electrode on the light emitting layer; as well as A field generating unit is provided on both sides of the light emitting layer, and applies an electric field parallel to the substrate to the light emitting layer.

2. The display device according to claim 1, wherein The field generating unit includes a ferroelectric material.

3. The display device according to claim 2, wherein: The ferroelectric material has a perovskite type (ABO3).

4. The display device according to claim 3, wherein The ferroelectric material includes one of barium titanate BaTiO3, lead titanate PbTiO3, potassium niobate KNbO3 and potassium tantalate KTaO3.

5. The display device according to claim 2, further comprising: a transistor in each sub-pixel of the plurality of sub-pixels; as well as a planarization layer covering the transistor, Wherein, the light-emitting layer is arranged on the planarization layer. The display device according to claim 5 , wherein: The field generating unit includes a ferroelectric pattern on the planarization layer, wherein the ferroelectric pattern extends to the first electrode, and The light emitting layer is disposed between the ferroelectric patterns on the first electrode.

7. The display device according to claim 6, wherein: The ferroelectric pattern extends from the planarization layer toward a top edge surface of the first electrode to surround the first electrode in a boundary region.

8. The display device according to claim 6, wherein: The thickness of the ferroelectric pattern is the same as that of the light emitting layer.

9. The display device according to claim 2, wherein: The field generating unit includes a second bank layer below the first bank layer.

10. The display device according to claim 2, wherein: The field generating unit includes a ferroelectric pattern on at least one side surface of the first bank layer.

11. The display device according to claim 2, wherein The field generating unit is treated with heat having a temperature higher than the Curie temperature.

12. The display device according to claim 2, wherein: The field generating unit is subjected to a heat treatment such that the polarity state of the ferroelectric material is removed.

13. The display device according to claim 1, wherein A side surface of the field generating unit contacts a side surface of the light emitting layer.

14. The display device according to claim 1, wherein The second electrode is in contact with the field generating unit.

15. A display device, comprising: a substrate, the substrate having a display area, the display area having a plurality of sub-pixels; a first bank layer on the substrate to define the plurality of sub-pixels; as well as A light emitting diode in each of the plurality of sub-pixels, the light emitting diode comprising a first electrode, a light emitting layer on the first electrode, and a second electrode on the light emitting layer, The light-emitting molecules of the light-emitting layer are arranged horizontally to be parallel to the substrate.

16. The display device according to claim 15, wherein The light-emitting molecules are arranged by an electric field applied to the light-emitting layer.

17. The display device according to claim 16, further comprising field generating units on both sides of the light emitting layer, in, The field generating unit includes a polymer having polarity and applying an electric field to the light emitting layer.

18. The display device according to claim 17, wherein: The polymer is treated with heat at a temperature above the Curie temperature.

19. The display device according to claim 17, wherein: The polymer is subjected to a heat treatment such that the polar state of the polymer is removed.

20. A display device, comprising: a substrate, the substrate having a display area, the display area having a plurality of sub-pixels; a first bank layer on the substrate to define the plurality of sub-pixels; as well as A light emitting diode in each of the plurality of sub-pixels, the light emitting diode comprising a first electrode, a light emitting layer on the first electrode, and a second electrode on the light emitting layer, The light-emitting molecules of the light-emitting layer are arranged to intersect with a direction from the first electrode to the second electrode.

21. The display device according to claim 20, wherein The light-emitting molecules of the light-emitting layer are arranged perpendicular to the direction from the first electrode to the second electrode.

Images