Display device

Abstract

According to an aspect of the present disclosure, a display device includes: a flexible substrate including a display area, a non-display area, and a bending area extending from the non-display area; a plurality of (1-1) th link lines disposed on the flexible substrate in the non-display area; one or more insulating layers disposed on the plurality of (1-1) th link lines; a plurality of (1-2) th link lines respectively connected to the plurality of (1-1) th link lines through a plurality of first contact holes provided in the one or more insulating layers; a first planarization layer disposed on the plurality of first to second link lines; a plurality of (1-3) th link lines respectively connected to the plurality of (1-2) th link lines through a plurality of second contact holes provided in the first planarization layer; and a plurality of first pads connected to the plurality of 1st-3rd link lines, in which the plurality of second contact holes are disposed closer to the display area than the plurality of first contact holes. Accordingly, corrosion resistance can be improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0028746 filed on February 28, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device including a bending area having improved corrosion resistance. Background Art

[0004] In recent years, display devices have been manufactured by forming light-emitting elements, wires, and the like on a substrate made of a flexible material such as plastic. This allows the display device to display images even when bent like paper. Consequently, these display devices have attracted attention as next-generation display devices, and research and development are actively underway.

[0005] However, due to recent developments in display technology, as data volumes increase, display devices are becoming lighter and thinner, and the resolution of products is improving. As a result, the number of wires connected to driver integrated circuits (ICs) and the number of pads corresponding to each wire are increasing. Inevitably, the bezel area becomes wider. Therefore, a technology has been developed to reduce the size of the bezel area by bending a portion of the bezel area. Summary of the Invention

[0006] One object to be achieved by the present disclosure is to provide a display device that achieves improvement in corrosion resistance of a plurality of link lines in a non-display area.

[0007] Another object to be achieved by the present disclosure is to provide a display device in which reliability defects caused by a voltage difference between a plurality of link lines can be minimized.

[0008] The objects of the exemplary embodiments of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0009] According to one aspect of the present disclosure, a display device includes: a flexible substrate, the flexible substrate including a display area, a non-display area, and a bending area extending from the non-display area; a plurality of 1-1 link lines, the plurality of 1-1 link lines being arranged on the flexible substrate in the non-display area; one or more insulating layers, the one or more insulating layers being arranged on the plurality of 1-1 link lines; a plurality of 1-2 link lines, the plurality of 1-2 link lines being respectively connected to the plurality of 1-1 link lines through a plurality of first contact holes arranged in the one or more insulating layers; a first planarization layer, the first planarization layer being arranged on the plurality of 1-2 link lines; a plurality of 1-3 link lines, the plurality of 1-3 link lines being respectively connected to the plurality of 1-2 link lines through a plurality of second contact holes arranged in the first planarization layer; and a plurality of first pads, the plurality of first pads being connected to the plurality of 1-3 link lines, wherein the plurality of second contact holes are arranged to be closer to the display area than the plurality of first contact holes.

[0010] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0011] According to the present disclosure, the organic layer contact hole is disposed in the non-display area so as to be closer to the display area than the inorganic layer contact hole without increasing the size of the frame area, thereby increasing the moisture permeation path.

[0012] According to the present disclosure, corrosion resistance in a non-display area can be improved.

[0013] According to the present disclosure, it is possible to suppress an increase in resistance and abnormal operation, thereby improving the reliability of the display device.

[0014] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure;

[0017] Figure 2 is a cross-sectional view illustrating a bent state of a display device according to an exemplary embodiment of the present disclosure;

[0018] Figure 3 is a cross-sectional view of a pixel in a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 4 yes Figure 1 An enlarged plan view of area A;

[0020] Figure 5 It is along Figure 4 A cross-sectional view taken along line V-V';

[0021] Figure 6 yes Figure 1 an enlarged plan view of area B;

[0022] Figure 7 It is along Figure 6 A cross-sectional view taken along line VII-VII';

[0023] Figure 8 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure; and

[0024] Figure 9 It is along Figure 8 A cross-sectional view taken along line IX-IX'. DETAILED DESCRIPTION

[0025] The advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear by reference to the exemplary embodiments described in detail below and the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only as examples so that those skilled in the art can fully understand the content disclosed by the present disclosure and the scope of the present disclosure.

[0026] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed explanations of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Unless expressly stated otherwise, any reference to the singular may include the plural.

[0027] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0028] When terms such as "on," "over," "below," and "next to" are used to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the terms "immediately next to" or "directly."

[0029] When an element or layer is referred to as being “on” another element or layer, the other layer or element can be directly interposed on the other element or interposed between the two elements.

[0030] Although the terms "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below can be the second component in the technical concept of the present disclosure.

[0031] Throughout the specification, like reference numerals generally refer to like elements.

[0032] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated components.

[0033] The features of the various embodiments of the present disclosure may be partially or completely coupled or combined with each other and may be technically interlocked and operated in various ways, and the embodiments may be performed independently of or in association with each other.

[0034] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 : is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 1 Only the flexible substrate 110 , the plurality of pads PAD, the plurality of link lines LNK, the plurality of scan lines SL, and the gate driver GD are shown among various components of the display device 100 .

[0036] refer to Figure 1 , the flexible substrate 110 includes a display area AA, a non-display area NA, and a bending area BA extending from the non-display area NA.

[0037] The flexible substrate 110 is a base member for supporting various components of the display device 100 and can be made of an insulating material. For example, the flexible substrate 110 can be made of a flexible material. The flexible substrate 110 can be made of a plastic material such as polyimide (PI).

[0038] The flexible substrate 110 may have a shaped corner area. The display area AA may correspond in shape to the shaped corner area of ​​the flexible substrate 110. The corners of the flexible substrate 110 and the corners of the display area AA may both have rounded shapes. However, the present disclosure is not limited thereto. The flexible substrate 110 and the display area AA may have various shapes suitable for the design of the electronic device in which the display device 100 is used.

[0039] The display area AA is an area where an image is displayed. A plurality of pixels are arranged in the display area AA. A driving unit for driving a plurality of light-emitting elements configured to display an image may be arranged in the display area AA. For example, if the display device 100 is an organic light-emitting display device, the plurality of light-emitting elements may be organic light-emitting elements each including an anode, an organic layer, and a cathode. The driving unit may include various components for driving the organic light-emitting elements, such as power lines, gate lines, data lines, thin film transistors, and storage capacitors. Hereinafter, for ease of description, the display device 100 will be described under the assumption that it is an organic light-emitting display device. However, the display device 100 is not limited to an organic light-emitting display device.

[0040] The non-display area NA is an area where no image is displayed. Various lines and circuits for driving the light-emitting elements in the display area AA are disposed in the non-display area NA. For example, a gate driver GD, a data driver, link lines LNK, a plurality of pads PAD, etc. may be disposed in the non-display area NA. The non-display area NA where no image is displayed may be a frame area, but exemplary embodiments of the present disclosure are not limited thereto.

[0041] The non-display area NA may be an area extending from the display area AA. However, the present disclosure is not limited thereto. The non-display area NA may be an area surrounding the display area AA.

[0042] The non-display area NA includes a first non-display area NA1, a bending area BA, and a second non-display area NA2. The second non-display area NA2 is an area extending from the display area AA. The bending area BA is an area extending from the second non-display area NA2. The bending area BA can be Figure 1 The first non-display area NA1 is an area extending from the bending area BA.

[0043] A gate driver GD, a plurality of pads PAD, etc. may be provided in the first non-display area NA1. The plurality of pads PAD include various link lines and pads connected to a flexible film or a printed circuit board.

[0044] The plurality of pads PAD include a plurality of first pads PAD1 and a plurality of second pads PAD2. The plurality of first pads PAD1 are located on both sides of the flexible substrate 110 in the first non-display area NA1. The plurality of second pads PAD2 are located in the center of the flexible substrate 110 in the first non-display area NA1. For example, the plurality of second pads PAD2 may be located between the plurality of first pads PAD1.

[0045] The plurality of first pads PAD1 are electrically connected to a plurality of first link lines LNK1 among the plurality of link lines LNK. The plurality of first link lines LNK1 may be connected to the gate driver GD.

[0046] The plurality of second pads PAD2 are electrically connected to a plurality of second link lines LNK2 among the plurality of link lines LNK. The plurality of second link lines LNK2 may be connected to data lines, power lines, etc. provided in the display area AA.

[0047] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL in response to a plurality of gate control signals supplied from the timing controller. Figure 1 It is shown that one gate driver GD is provided on one side of the display panel and is spaced apart from the display panel. However, the number and arrangement of the gate drivers GD are not limited thereto.

[0048] The second non-display area NA2 is an area surrounding the bending area BA and the display area AA. A plurality of link lines LNK (such as gate link lines, power link lines, data link lines, etc.) may be provided in the second non-display area NA2. That is, the second non-display area NA2 is used to transmit signals from the plurality of pads PAD to the display area AA. If the flexible substrate 110 has a special-shaped corner area, the second non-display area NA2 may correspond in shape to the flexible substrate 110 and the display area AA. Figures 4 to 7 The plurality of link lines LNK are described in detail.

[0049] Figure 2 : is a cross-sectional view showing a curved state of a display device according to an exemplary embodiment of the present disclosure. For ease of explanation, Figure 2 Various components provided on the flexible substrate 110 are not shown, and only the flexible substrate 110 is shown.

[0050] refer to Figure 2 The display device 100 according to an exemplary embodiment of the present disclosure may include a first adhesive layer AD1, a second adhesive layer AD2, a polarizing plate 150, a black matrix BM, a cover window 130, and a micro coating layer 140 provided on a flexible substrate 110. In addition, the display device 100 may include a third adhesive layer AD3, a fourth adhesive layer AD4, a fifth adhesive layer AD5, a sixth adhesive layer AD6, a backplane 160, and a metal plate 170 provided below the flexible substrate 110.

[0051] refer to Figure 2 The cover window 130 is provided on the front surface of the flexible substrate 110. The cover window 130 may be exposed from the outside of the display device 100 and may protect the display device 100 from external impacts and scratches. Furthermore, the cover window 130 may protect the display device 100 from external moisture and the like. The cover window 130 may be made of, but is not limited to, glass or a flexible plastic material.

[0052] A black matrix BM is disposed below the cover window 130. The black matrix BM can be disposed outside the cover window 130 along its perimeter. In this case, the black matrix BM can be disposed corresponding to the second non-display area NA2. The black matrix BM can be made of a material with low light transmittance. Thus, the black matrix BM can prevent various components disposed below the second non-display area NA2 from being visible from the outside. Furthermore, the black matrix BM can be made of a conductive material and can be used to dissipate static electricity from the cover window 130.

[0053] The black matrix BM may be made of chromium (Cr), graphite, or a resin containing conductive particles. In this context, the resin may be made of, but is not limited to, one or more of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, and benzocyclobutene. Furthermore, the conductive particles may be made of, but are not limited to, one of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and an alloy of silver (Ag) and magnesium (Mg).

[0054] Polarizing plate 150 is disposed between flexible substrate 110 and cover window 130. Polarizing plate 150 is disposed on the front surface of flexible substrate 110. Polarizing plate 150 selectively transmits light to reduce reflection of external light incident on flexible substrate 110. Specifically, various metal materials used in semiconductor devices, wires, light-emitting elements, etc. may be disposed on flexible substrate 110. Therefore, external light incident on flexible substrate 110 may be reflected from the metal material, potentially reducing the visibility of display device 100 due to the reflection of external light. At the same time, when polarizing plate 150 is disposed, it can suppress reflection of external light, thereby improving the outdoor visibility of display device 100. However, depending on the embodiment of display device 100, polarizing plate 150 may be omitted in some embodiments, but the present disclosure is not limited thereto.

[0055] A first adhesive layer AD1 is provided between the polarizing plate 150 and the cover window 130, and a second adhesive layer AD2 is provided between the polarizing plate 150 and the flexible substrate 110. The first adhesive layer AD1 can be used to bond the cover window 130 to the polarizing plate 150, and the second adhesive layer AD2 can be used to bond the polarizing plate 150 to the flexible substrate 110. As a result, the first adhesive layer AD1 and the second adhesive layer AD2 can be used to bond the flexible substrate 110 to the cover window 130. Each of the first adhesive layer AD1 and the second adhesive layer AD2 can be configured as a transparent adhesive layer that allows an image to be visible. For example, the first adhesive layer AD1 and the second adhesive layer AD2 can be made of an optically clear adhesive (OCA), but are not limited thereto.

[0056] The backplate 160 is disposed below the flexible substrate 110. The backplate 160 may be provided to support the flexible substrate 110. For example, if the flexible substrate 110 is made of a plastic material such as polyimide, additional components may be required to protect the substrate due to its flexibility. Therefore, a supporting substrate made of glass is disposed below the flexible substrate 110 to facilitate the manufacturing process of the display device 100. After the manufacturing process is completed, the supporting substrate can be separated and released. However, even after the supporting substrate is released, components are still required to support the flexible substrate 110. Therefore, the backplate 160 may be disposed below the flexible substrate 110 to support the flexible substrate 110.

[0057] The back plate 160 may include a plastic material. For example, the back plate 160 may be configured as a plastic film made of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or a combination of these polymers.

[0058] The third adhesive layer AD3 is disposed between the flexible substrate 110 and the back panel 160. The third adhesive layer AD3 may be used to bond the flexible substrate 110 to the back panel 160. The third adhesive layer AD3 may be made of a pressure sensitive adhesive (PSA), but is not limited thereto.

[0059] The metal plate 170 is provided below the back plate 160. The metal plate 170 can protect the components of the display device 100 from external impact. In addition, the metal plate 170 can be used as a ground to suppress static electricity from penetrating into the display device 100 or to easily discharge residual charges accumulated in the display device 100 to the outside. In addition, the metal plate 170 can easily dissipate the heat generated in the display device 100 to the outside. The metal plate 170 can be made of a metal material having excellent thermal conductivity, electrical conductivity and mechanical strength. For example, the metal plate 170 can be made of copper (Cu) or stainless steel (SUS), but is not limited thereto.

[0060] The fourth adhesive layer AD4 is disposed between the back plate 160 and the metal plate 170. The fourth adhesive layer AD4 may be used to bond the back plate 160 to the metal plate 170. The fourth adhesive layer AD4 may be made of a pressure sensitive adhesive (PSA), but is not limited thereto.

[0061] The additional back plate 160A and the additional metal plate 170A are disposed under the metal plate 170 in the first non-display area NA1 .

[0062] The additional backplate 160A and the additional metal plate 170A can be used to reinforce the strength of the first non-display area NA1 of the flexible substrate 110. At the same time, the additional backplate 160A and the additional metal plate 170A can be positioned so as not to overlap with the bending area BA. Therefore, the thickness of components positioned in the bending area BA can be minimized, and the neutral plane of the bending area BA can be easily controlled. Consequently, the flexibility of the bending area BA can be ensured.

[0063] A fifth adhesive layer AD5 is provided between the metal plate 170 and the additional metal plate 170A. Furthermore, a sixth adhesive layer AD6 is provided between the additional metal plate 170A and the additional backplate 160A. The fifth adhesive layer AD5 can be used to bond the metal plate 170 to the additional metal plate 170A. Furthermore, the sixth adhesive layer AD6 can be used to bond the additional metal plate 170A and the additional backplate 160A. For example, the fifth adhesive layer AD5 and the sixth adhesive layer AD6 can be made of a pressure-sensitive adhesive (PSA), but are not limited thereto.

[0064] The first non-display area NA1 of the flexible substrate 110 is disposed below the additional backplate 160A. Furthermore, a seventh adhesive layer AD7 is disposed between the additional backplate 160A and the first non-display area NA1 of the flexible substrate 110. The seventh adhesive layer AD7 may be used to bond the additional backplate 160A to the first non-display area NA1 of the flexible substrate 110. For example, the seventh adhesive layer AD7 may be made of a pressure-sensitive adhesive (PSA), but is not limited thereto.

[0065] The microcoating layer 140 is disposed on the first non-display area NA1, the second non-display area NA2, and the bending area BA of the flexible substrate 110. During bending, the link lines LNK disposed on the flexible substrate 110 may be subjected to tension and thus may develop microcracks. Therefore, the microcoating layer 140 is formed by coating a thin layer of resin at the bending location and serves to protect the link lines.

[0066] The micro coating layer 140 may be made of a resin, such as an acrylic-based material or urethane acrylate, but is not limited thereto.

[0067] Figure 3 is a cross-sectional view of a pixel in a display device according to an exemplary embodiment of the present disclosure.

[0068] refer to Figure 3According to an exemplary embodiment of the present disclosure, the display device 100 may include a flexible substrate 110, a first buffer layer 111, a first thin film transistor TR1, and a second thin film transistor TR2. Furthermore, the display device 100 may include a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, and a second interlayer insulating layer 113b. Furthermore, the display device 100 may include a connection electrode CE, a first planarization layer 115a, a second planarization layer 115b, an auxiliary electrode 145, a bank 116a, and a spacer 116b. Furthermore, the display device 100 may include an anode 121, an emission layer 122, a cathode 123, an encapsulation layer 117, and a touch sensing layer.

[0069] The flexible substrate 110 is used to support and protect the components of the display device 100 disposed thereon. The flexible substrate 110 is configured to support various components included in the display device 100 and may be made of an insulating material. For example, the flexible substrate 110 may be a polyimide (PI) substrate, but is not limited thereto.

[0070] The light shielding layer 125 may be disposed on the flexible substrate 110 .

[0071] The first buffer layer 111 may cover the light shielding layer 125 and may be disposed on the flexible substrate 110. Specifically, a multi-buffer layer 111a may be disposed on the flexible substrate 110 to cover the light shielding layer 125, and an active buffer layer 111b may be disposed on the multi-buffer layer 111a.

[0072] The multi-buffer layer 111 a may prevent moisture or oxygen from penetrating into the flexible substrate 110 , and include at least one of silicon nitride (SiNx) and silicon oxide (SiOx).

[0073] The active buffer layer 111b may protect the first active layer A1 and block various defects introduced from the flexible substrate 110. For example, the active buffer layer 111b may include at least one of a-Si, silicon nitride (SiNx), and silicon oxide (SiOx).

[0074] The first thin film transistor TR1 may be disposed on the first buffer layer 111. The first thin film transistor TR1 may include a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. Herein, depending on the design of the pixel circuit, the first source electrode S1 may be a first drain electrode, and the first drain electrode D1 may be a first source electrode.

[0075] The first active layer A1 may be disposed on the first buffer layer 111 so as to overlap with the light shielding layer 125. The first active layer A1 may include amorphous silicon or polycrystalline silicon. For example, the first active layer A1 may include low temperature polycrystalline silicon (LTPS). For example, polycrystalline silicon material has a high mobility (greater than or equal to 100 cm 2 / Vs), low energy consumption and excellent reliability. Therefore, it can be applied to a gate driver and / or a multiplexer (MUX), wherein the gate driver and / or multiplexer (MUX) is used in a driving element of a thin film transistor used to drive a light-emitting element. In addition, it can be applied to the active layer A1 of the driving thin film transistor of the display device 100 according to an exemplary embodiment of the present disclosure. However, the present disclosure is not limited thereto. For example, polycrystalline silicon material can be applied to the active layer A1 of the switching thin film transistor according to the characteristics of the display device 100. Amorphous silicon (a-Si) material is deposited on the first buffer layer 111, and polycrystalline silicon is formed by a dehydrogenation process and a crystallization process. Then, the first active layer A1 is prepared by patterning the polycrystalline silicon. In this article, the first active layer A1 may include a first channel region in which a channel is formed during driving the first thin film transistor TR1, and a first source region and a first drain region on both sides of the first channel region. The first source region refers to the portion of the first active layer A1 connected to the first source electrode S1. The first drain region refers to the portion of the first active layer A1 connected to the first drain electrode D1. For example, the first source region and the first drain region can be formed by ion doping (impurity doping) the first active layer A1. The first source region and the first drain region can be formed by ion doping polysilicon material. The first channel region can refer to the portion that is not ion doped but remains as polysilicon material.

[0076] A first gate insulating layer 112a may be disposed on the first active layer A1. The first gate insulating layer 112a may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof. The first gate insulating layer 112a may include contact holes. The contact holes are used to connect the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 to the first source region and the first drain region in the first active layer A1 of the first thin film transistor TR1, respectively.

[0077] The first gate electrode G1 of the first thin film transistor TR1 and the first capacitor electrode C1 of the storage capacitor Cst may be disposed on the first gate insulating layer 112 a .

[0078] Herein, each of the first gate electrode G1 and the first capacitor electrode C1 may be composed of a single layer or a multilayer made of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first gate electrode G1 may be disposed on the first gate insulating layer 112a so as to overlap with the first channel region in the first active layer A1 of the first thin film transistor TR1.

[0079] The first capacitor electrode C1 may be omitted based on the driving characteristics of the display device 100 and the structure and type of the thin film transistor. The first gate electrode G1 and the first capacitor electrode C1 may be manufactured by the same process. In addition, the first gate electrode G1 and the first capacitor electrode C1 may be made of the same material and disposed on the same layer.

[0080] A first interlayer insulating layer 113a may be disposed on the first gate insulating layer 112a, the first gate electrode G1, and the first capacitor electrode C1. The first interlayer insulating layer 113a may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof. Furthermore, the first interlayer insulating layer 113a may include a contact hole. The contact hole is used to expose the first source region and the first drain region in the first active layer A1 of the first thin film transistor TR1.

[0081] The second capacitor electrode C2 of the storage capacitor Cst can be disposed on the first interlayer insulating layer 113a. The second capacitor electrode C2 can be composed of a single layer or multiple layers made of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The second capacitor electrode C2 can be disposed on the first interlayer insulating layer 113a so as to overlap with the first capacitor electrode C1. In addition, the second capacitor electrode C2 can be made of the same material as the first capacitor electrode C1. The second capacitor electrode C2 can be omitted based on the driving characteristics of the display device 100 and the structure and type of the thin film transistor.

[0082] The second buffer layer 114 may be disposed on the first interlayer insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof. The second buffer layer 114 may include a contact hole. The contact hole is used to expose the first source region and the first drain region in the first active layer A1 of the first thin film transistor TR1. The second buffer layer 114 may also include a contact hole. The contact hole is used to expose the second capacitor electrode C2 of the storage capacitor Cst.

[0083] The second buffer layer 114 may also be composed of multiple layers, but is not limited thereto.

[0084] The second active layer A2 of the second thin film transistor TR2 may be disposed on the second buffer layer 114. Herein, the second thin film transistor TR2 may include the second active layer A2, the second gate insulating layer 112b, the second gate electrode G2, the second source electrode S2, and the second drain electrode D2. Herein, depending on the design of the pixel circuit, the second source electrode S2 may be a drain electrode, and the second drain electrode D2 may be a source electrode.

[0085] In addition, the second active layer A2 may include a second channel region in which a channel is formed during driving of the second thin film transistor TR2, as well as a second source region and a second drain region on both sides of the second channel region. The second source region refers to the portion of the second active layer A2 connected to the second source electrode S2. The second drain region refers to the portion of the second active layer A2 connected to the second drain electrode D2.

[0086] The second active layer A2 can be made of an oxide semiconductor. Because oxide semiconductor materials have a larger band gap than silicon materials, electrons cannot cross the band gap in the off state, resulting in a low off current. Therefore, a thin film transistor including an active layer made of an oxide semiconductor is suitable for a switching thin film transistor with a short on-time and a long off-time, but is not limited to this. Depending on the characteristics of the display device 100, the thin film transistor can be used as a driving thin film transistor. In addition, because the auxiliary capacitance is low due to the low off-current, the second active layer A2 is suitable for a high-resolution light-emitting element. For example, the second active layer A2 can be made of a metal oxide. The second active layer A2 can be made of various metal oxides, such as indium-gallium-zinc-oxide (IGZO). In this article, the second active layer A2 of the second thin film transistor TR2 is described under the assumption that it is made of IGZO among various metal oxides. However, the present disclosure is not limited to this. Instead of IGZO, the second active layer A2 can be made of other metal oxides, such as indium zinc oxide (IZO), indium gallium tin oxide (IGTO), or indium gallium oxide (IGO).

[0087] A metal oxide is deposited on the second buffer layer 114 and a heat treatment process is performed for stabilization. Then, the second active layer A2 is prepared by patterning the metal oxide.

[0088] The second gate insulating layer 112b may be disposed on the entire flexible substrate 110 including the second active layer A2. For example, the second gate insulating layer 112b may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0089] The second gate electrode G2 may be disposed on the second gate insulating layer 112 b .

[0090] The second gate electrode G2 may be composed of a single layer or a multilayer made of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or an alloy thereof.

[0091] For example, a metal material is provided on the second gate insulating layer 112b, and a photoresist pattern is formed on the metal material. Then, the second gate electrode G2 is prepared by wet etching the metal material using the photoresist pattern as a mask. The wet etchant used to etch the metal material may contain a material that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or alloys thereof but does not etch the insulating material.

[0092] The second interlayer insulating layer 113b may be disposed on the second gate insulating layer 112b and the second gate electrode G2. The second interlayer insulating layer 113b may include contact holes. The contact holes are used to expose the first active layer A1 of the first thin-film transistor TR1 and the second active layer A2 of the second thin-film transistor TR2. For example, the second interlayer insulating layer 113b may include contact holes. The contact holes are used to expose the first source region and the first drain region in the first active layer A1 of the first thin-film transistor TR1. The second interlayer insulating layer 113b may include contact holes. The contact holes are used to expose the second source region and the second drain region in the second active layer A2 of the second thin-film transistor TR2.

[0093] The second interlayer insulating layer 113b may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0094] The connection electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 , and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 may be disposed on the second interlayer insulating layer 113 b .

[0095] The connection electrode CE may be electrically connected to the second drain electrode D2 of the second thin film transistor TR2. Furthermore, the connection electrode CE may be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through a contact hole formed in the second buffer layer 114 and the second interlayer insulating layer 113 b. That is, the connection electrode CE may be used to electrically connect the second capacitor electrode C2 of the storage capacitor Cst to the second drain electrode D2 of the second thin film transistor TR2.

[0096] Herein, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 may be connected to the first active layer A1 of the first thin film transistor TR1 through contact holes formed in the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114, and the second interlayer insulating layer 113b.

[0097] The second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 may be connected to the second active layer A2 through a contact hole formed in the second interlayer insulating layer 113 b .

[0098] The connection electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 , and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 may be made of the same material through the same process.

[0099] For example, each of the connection electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 may be composed of a single layer or a multilayer structure made of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, each of the connection electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1, and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 may have a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), but is not limited thereto.

[0100] The connection electrode CE may be connected to and integrated with the second drain electrode D2 of the second thin film transistor TR2 , but is not limited thereto.

[0101] A first planarization layer 115 a may be disposed on the connection electrode CE, the first source electrode S1 and the first drain electrode D1 of the first thin film transistor TR1 , the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2 , and the second interlayer insulating layer 113 b .

[0102] The first planarization layer 115a may be an organic layer to planarize and protect the upper portions of the first and second thin film transistors TR1 and TR2. For example, the first planarization layer 115a may be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0103] The auxiliary electrode 145 may be disposed on the first planarization layer 115a. The auxiliary electrode 145 may be connected to the second drain electrode D2 of the second thin film transistor TR2 through a contact hole formed in the first planarization layer 115a. The auxiliary electrode 145 may be used to electrically connect the second thin film transistor TR2 to the anode 121. In addition, the auxiliary electrode 145 may be composed of a single layer or a multilayer made of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The auxiliary electrode 145 may be made of the same material as the second source electrode S2 and the second drain electrode D2 of the second thin film transistor TR2.

[0104] The second planarization layer 115b may be disposed on the auxiliary electrode 145 and the first planarization layer 115a. For example, the second planarization layer 115b may be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0105] The light emitting element 120 may be disposed on the second planarization layer 115 b .

[0106] The anode 121 may be disposed on the second planarization layer 115b. In this case, the anode 121 may be electrically connected to the auxiliary electrode 145 through a contact hole formed in the second planarization layer 115b. The anode 121 may be made of a metal material.

[0107] The display device 100 may be a top emission type, in which light emitted from the light-emitting element 120 is emitted above the flexible substrate 110 on which the light-emitting element 120 is disposed. In this case, the anode 121 may further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer may be made of a transparent conductive oxide such as ITO or IZO. The reflective layer may be made of, for example, silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

[0108] The bank 116a may be provided to cover the anode 121. The bank 116a may have an opening portion corresponding to the emission region of the sub-pixel. A portion of the anode 121 may be exposed through the opening portion of the bank 116a (hereinafter referred to as an "opening region"). In this document, the bank 116a may be made of an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiOx), or of an organic insulating material, such as a benzocyclobutene-based resin, an acryl-based resin, or an imide-based resin. However, the present disclosure is not limited thereto. A spacer 116b may be further provided on the bank 116a.

[0109] Emission layer 122 may be provided in and around the opening region of bank 116a. Thus, emission layer 122 may be provided on anode 121 exposed through the opening region of bank 116a.

[0110] The cathode 123 may be provided on the emission layer 122 .

[0111] The light emitting element 120 may be composed of an anode 121, an emission layer 122, and a cathode 123. The emission layer 122 may include a plurality of organic layers.

[0112] The encapsulation layer 117 may be located on the light emitting element 120 .

[0113] The encapsulation layer 117 may have a single-layer structure or a multi-layer structure. For example, the encapsulation layer 117 may include a first encapsulation layer 117a, a second encapsulation layer 117b, and a third encapsulation layer 117c.

[0114] Herein, each of the first encapsulation layer 117a and the third encapsulation layer 117c may be composed of an inorganic layer, and the second encapsulation layer 117b may be composed of an organic layer. Among the first encapsulation layer 117a, the second encapsulation layer 117b and the third encapsulation layer 117c, the second encapsulation layer 117b may have the largest thickness and serve as a planarization layer.

[0115] The first encapsulation layer 117a can be disposed on the cathode 123 so as to be closest to the light-emitting element 120. The first encapsulation layer 117a can be made of an inorganic insulating material suitable for low-temperature deposition. For example, the first encapsulation layer 117a can be made of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first encapsulation layer 117a is deposited in a low-temperature atmosphere, damage to the emission layer 122 containing organic materials that are susceptible to damage in a high-temperature atmosphere can be suppressed during the deposition process.

[0116] The second encapsulation layer 117b may have a smaller area than the first encapsulation layer 117a. In this case, the second encapsulation layer 117b may be provided to expose both ends of the first encapsulation layer 117a. The second encapsulation layer 117b may be used to buffer stress generated between layers during bending of the flexible display device and enhance flattening performance.

[0117] For example, the second encapsulation layer 117b may be made of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbide (SiOC). For example, the second encapsulation layer 117b may be prepared by an inkjet method, but is not limited thereto.

[0118] The third encapsulation layer 117c may be disposed on the flexible substrate 110 on which the second encapsulation layer 117b is disposed, so as to cover the upper and side surfaces of the second encapsulation layer 117b and the first encapsulation layer 117a. Herein, the third encapsulation layer 117c may minimize or prevent external moisture or oxygen from penetrating into the first and second encapsulation layers 117a and 117b. For example, the third encapsulation layer 117c may be made of an inorganic insulating material, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0119] The touch sensing layer may be provided on the encapsulation layer 117. The touch sensing layer may include a touch electrode TE including a touch sensor metal TS and a bridge metal BM. In addition, the touch sensing layer may include a touch insulation layer including a touch buffer layer 118a, a touch interlayer insulation layer 118b, and a touch planarization layer 118c.

[0120] For example, the touch buffer layer 118 a may be disposed on the third encapsulation layer 117 c , and the touch electrode TE may be disposed on the touch buffer layer 118 a .

[0121] The touch electrode TE may include a touch sensor metal TS and a bridge metal BM located on different layers from each other, and a touch interlayer insulating layer 118 b may be provided between the touch sensor metal TS and the bridge metal BM.

[0122] The touch buffer layer 118a and the touch interlayer insulating layer 118b may be provided to eliminate steps at the location where the touch electrode TE is provided and to promote electrical insulation. Therefore, the touch buffer layer 118a and the touch interlayer insulating layer 118b may be made of an inorganic material. For example, each of the touch buffer layer 118a and the touch interlayer insulating layer 118b may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0123] The touch planarization layer 118c is disposed on the touch interlayer insulating layer 118b and the touch sensor metal TS. The touch planarization layer 118c may be an organic layer for planarizing and protecting the upper portion of the touch interlayer insulating layer 118b. It may be flat. For example, the touch planarization layer 118c may be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The touch electrodes TE may have a mesh shape.

[0124] Figure 4 yes Figure 1 An enlarged plan view of area A. Figure 5 It is along Figure 4 A cross-sectional view taken along line V-V'. Figure 6 yes Figure 1An enlarged plan view of area B. Figure 7 It is along Figure 6 For ease of explanation, Figure 5 and Figure 7 Only the flexible substrate 110 and the plurality of link lines LNK are shown. Figure 5 and Figure 7 The region A in which a plurality of first link lines LNK1 are provided will be described, and reference will be made to Figure 6 and Figure 7 A region B in which a plurality of second link lines LNK2 are provided is described.

[0125] refer to Figure 1 and Figure 4 , the flexible substrate 110 of the display device 100 may include a display area AA and a non-display area NA. In addition, the non-display area NA may include a first non-display area NA1, a second non-display area NA2, and a bending area BA.

[0126] The plurality of link lines LNK may be provided in the first non-display area NA1, the second non-display area NA2, and the bending area BA. When the flexible substrate 110 and the display area AA correspond in shape to the irregular corner area, the plurality of link lines LNK may correspond in shape to the display area AA and the flexible substrate 110 in the irregular corner area.

[0127] The plurality of link lines LNK may include a plurality of first link lines LNK1 and a plurality of second link lines LNK2 .

[0128] The plurality of first link lines LNK1 may connect the plurality of pads PAD to the gate driver GD. Specifically, the plurality of first link lines LNK1 may transmit signals for driving the gate driver GD from the plurality of first pads PAD1 to the gate driver GD. For example, the plurality of first link lines LNK1 may transmit clock signals, power signals, etc. to the gate driver GD. Thus, the first link lines LNK1 may function as gate link lines, but are not limited thereto.

[0129] refer to Figure 3 and Figure 4 The plurality of first link lines LNK1 may include a plurality of 1-1st link lines LNK1-1, a plurality of 1-2nd link lines LNK1-2, and a plurality of 1-3rd link lines LNK1-3. The plurality of 1-1st link lines LNK1-1 and the plurality of 1-2nd link lines LNK1-2 may be disposed in the non-display area NA. Furthermore, the plurality of 1-3rd link lines LNK1-3 may be disposed in the non-display area NA and the bending area BA.

[0130] A multi-buffer layer 111a, an active buffer layer 111b, and a first gate insulating layer 112a are disposed on the flexible substrate 110. Furthermore, a plurality of 1-1th link lines LNK1-1 are disposed on the multi-buffer layer 111a, the active buffer layer 111b, and the first gate insulating layer 112a. The plurality of 1-1th link lines LNK1-1 may be connected to a gate driver GD.

[0131] Each of the plurality of 1-1th link lines LNK1-1 may have a different polarity than another adjacent 1-1th link line. Therefore, each of the plurality of first link lines LNK1 may also have a different polarity than another adjacent first link line LNK1. For example, when one of the plurality of 1-1th link lines LNK1-1 has a positive (+) polarity, another adjacent 1-1th link line LNK1-1 may have a negative (-) polarity. Therefore, a voltage difference may occur between the plurality of adjacent 1-1th link lines LNK1-1. At the same time, the plurality of 1-1th link lines LNK1-1 may have the same polarity. In this case, a relatively high voltage difference may exist between the adjacent 1-1th link lines LNK1-1.

[0132] The plurality of 1-1th link lines LNK1-1 may include a plurality of sub-link lines LNK1-1a, LNK1-1b, and LNK1-1c. Specifically, each of the plurality of 1-1th link lines LNK1-1 may include a plurality of sub-link lines LNK1-1a, LNK1-1b, and LNK1-1c with an insulating layer interposed therebetween. The plurality of sub-link lines LNK1-1a, LNK1-1b, and LNK1-1c may include a first sub-link line LNK1-1a, a second sub-link line LNK1-1b, and a third sub-link line LNK1-1c.

[0133] The first sub link line LNK1-1a of the plurality of 1-1th link lines LNK1-1 is disposed on the multi-buffer layer 111a, the active buffer layer 111b, and the first gate insulating layer 112a. In addition, the first sub link line LNK1-1a may be made of the same material and disposed on the same layer as the first gate electrode G1, but is not limited thereto.

[0134] A first interlayer insulating layer 113a is provided on the first sub-link line LNK1-1a among the plurality of 1-1th link lines LNK1-1. Furthermore, a second sub-link line LNK1-1b among the plurality of 1-1th link lines LNK1-1 is provided on the first interlayer insulating layer 113a. The second sub-link line LNK1-1b among the plurality of 1-1th link lines LNK1-1 may be made of the same material and provided on the same layer as the second capacitor electrode C2, but is not limited thereto.

[0135] A second gate insulating layer 112b and a second buffer layer 114 are provided on the second sub-link line LNK1-1b among the plurality of 1-1th link lines LNK1-1. In addition, a third sub-link line LNK1-1c among the plurality of 1-1th link lines LNK1-1 is provided on the second gate insulating layer 112b and the second buffer layer 114. The third sub-link line LNK1-1c among the plurality of 1-1th link lines LNK1-1 may be made of the same material and provided on the same layer as the second gate electrode G2, but is not limited thereto.

[0136] A second interlayer insulating layer 113b is disposed on the plurality of 1-1 link lines LNK1-1, and a plurality of 1-2 link lines LNK1-2 are disposed on the second interlayer insulating layer 113b. The plurality of 1-2 link lines LNK1-2 may be disposed to overlap the plurality of 1-1 link lines LNK1-1.

[0137] The plurality of first-second link lines LNK1-2 can be connected to the plurality of first-first link lines LNK1-1 through a plurality of first contact holes CNT1 disposed in the first interlayer insulating layer 113a, the second gate insulating layer 112b, the second buffer layer 114, and the second interlayer insulating layer 113b. Specifically, the plurality of first-second link lines LNK1-2 can be connected to the first sub-link line LNK1-1a through the first contact holes CNT1a disposed in the first interlayer insulating layer 113a, the second gate insulating layer 112b, the second buffer layer 114, and the second interlayer insulating layer 113b. Furthermore, the plurality of first-second link lines LNK1-2 can be connected to the second sub-link line LNK1-1b through the first contact holes CNT1b disposed in the second gate insulating layer 112b, the second buffer layer 114, and the second interlayer insulating layer 113b, and to the third sub-link line LNK1-1c through the first contact holes CNT1c disposed in the second interlayer insulating layer 113b.

[0138] The plurality of 1-2 link lines LNK1-2 may be made of the same material and disposed on the same layer as the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2, but are not limited thereto. For example, each of the plurality of 1-2 link lines LNK1-2 may have a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), but is not limited thereto.

[0139] A first planarization layer 115a is disposed on the plurality of first-second link lines LNK1-2, and a plurality of first-third link lines LNK1-3 are disposed on the first planarization layer 115a. The plurality of first-third link lines LNK1-3 may be respectively connected to the plurality of first-second link lines LNK1-2 through a plurality of second contact holes CNT2 disposed in the first planarization layer 115a. The plurality of first-third link lines LNK1-3 may be connected to a plurality of first pads PAD1.

[0140] The plurality of 1st to 3rd link lines LNK1-3 may be made of the same material and disposed on the same layer as the auxiliary electrode 145, but is not limited thereto. For example, each of the plurality of 1st to 3rd link lines LNK1-3 may have a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), but is not limited thereto.

[0141] The plurality of second contact holes CNT2 may be disposed closer to the display area AA than the plurality of first contact holes CNT1. That is, the plurality of first contact holes CNT1 electrically connecting the plurality of 1-1 link lines LNK1-1 to the plurality of 1-2 link lines LNK1-2 may be disposed farther from the display area AA than the plurality of second contact holes CNT2 electrically connecting the plurality of 1-2 link lines LNK1-2 to the plurality of 1-3 link lines LNK1-3.

[0142] The longitudinal width w1 of the plurality of first contact holes CNT1 may be smaller than the longitudinal width w2 of the plurality of second contact holes CNT2. In this document, the longitudinal width of a contact hole may refer to the distance from the upper surface to the lower surface of one or more insulating layers in which the contact holes are provided. The plurality of first contact holes CNT1 may be provided in the first interlayer insulating layer 113a, the second gate insulating layer 112b, the second buffer layer 114, and the second interlayer insulating layer 113b, all of which are made of inorganic materials. However, the plurality of second contact holes CNT2 may be provided in the first planarization layer 115a made of organic material. A layer made of inorganic material has a much smaller thickness than a layer made of organic material. Therefore, the longitudinal width w1 of the plurality of first contact holes CNT1 may be smaller than the longitudinal width w2 of the plurality of second contact holes CNT2.

[0143] The second planarization layer 115 b , the bank 116 a , the touch buffer layer 118 a , the touch interlayer insulating layer 118 b , and the touch planarization layer 118 c may be disposed on the plurality of 1st to 3rd link lines LNK1 - 3 .

[0144] Meanwhile, the multi-buffer layer 111a, active buffer layer 111b, first gate insulating layer 112a, first interlayer insulating layer 113a, second gate insulating layer 112b, second buffer layer 114, and second interlayer insulating layer 113b are only provided in the second non-display area NA2 and not in the bending area BA. This is to reduce stress in the bending area BA and suppress the occurrence of cracks in the insulating layer made of inorganic materials. Specifically, the touch insulating layer, including the touch buffer layer 118a, touch interlayer insulating layer 118b, and touch planarizing layer 118c, completely overlaps with the plurality of 1-1 link lines LNK1-1 and the plurality of 1-2 link lines LNK1-2. However, they are not provided in the bending area BA. Therefore, they may only overlap with a portion of the plurality of 1-3 link lines LNK1-3.

[0145] The plurality of second link lines LNK2 can connect the plurality of pads PAD to various lines disposed in the display area AA. Specifically, the plurality of second link lines LNK2 can transmit signals for driving pixels disposed in the display area AA from the plurality of second pads PAD2 to the various lines. For example, the plurality of second link lines LNK2 can be used to transmit data voltages, power supply voltages, etc. to the display area AA. Therefore, the plurality of second link lines LNK2 can function as data link lines or power link lines, but are not limited thereto.

[0146] refer to Figure 6 and Figure 7 The plurality of second link lines LNK2 may include a plurality of 2-1st link lines LNK2-1, a plurality of 2-2nd link lines LNK2-2, and a plurality of 2-3rd link lines LNK2-3. The plurality of 2-1st link lines LNK2-1 and the plurality of 2-2nd link lines LNK2-2 may be disposed in the non-display area NA. In addition, the plurality of 2-3rd link lines LNK2-3 may be disposed in the non-display area NA and the bending area BA.

[0147] A multi-buffer layer 111a, an active buffer layer 111b, and a first gate insulating layer 112a may be provided on the flexible substrate 110. Furthermore, a plurality of 2-1st link lines LNK2-1 are provided on the multi-buffer layer 111a, the active buffer layer 111b, and the first gate insulating layer 112a. The plurality of 2-1st link lines LNK2-1 may be connected to various lines provided in the display area AA.

[0148] There may be a very small voltage difference between each of the plurality of 2-1 link lines LNK2-1 and another adjacent 2-1 link line LNK2-1. For example, the voltage difference between signals transmitted by adjacent 2-1 link lines LNK2-1 among the plurality of 2-1 link lines LNK2-1 may be lower than the voltage difference between signals transmitted by adjacent 1-1 link lines LNK1-1 among the plurality of 1-1 link lines LNK1-1.

[0149] The plurality of 2-1st link lines LNK2-1 may include a plurality of sub-link lines LNK2-1a, LNK2-1b, and LNK2-1c. Specifically, each of the plurality of 2-1st link lines LNK2-1 may include a plurality of sub-link lines LNK2-1a, LNK2-1b, and LNK2-1c with an insulating layer interposed therebetween. The plurality of sub-link lines LNK2-1a, LNK2-1b, and LNK2-1c may include a first sub-link line LNK2-1a, a second sub-link line LNK2-1b, and a third sub-link line LNK2-1c.

[0150] The first sub link line LNK2-1a of the plurality of 2-1st link lines LNK2-1 is disposed on the multi-buffer layer 111a, the active buffer layer 111b, and the first gate insulating layer 112a. In addition, the first sub link line LNK2-1a may be made of the same material and disposed on the same layer as the first gate electrode G1, but is not limited thereto.

[0151] A first interlayer insulating layer 113a is provided on the first sub-link line LNK2-1a of the plurality of 2-1st link lines LNK2-1. Furthermore, a second sub-link line LNK2-1b of the plurality of 2-1st link lines LNK2-1 is provided on the first interlayer insulating layer 113a. The second sub-link line LNK2-1b of the plurality of 2-1st link lines LNK2-1 may be made of the same material and provided on the same layer as the second capacitor electrode C2, but is not limited thereto.

[0152] A second gate insulating layer 112b and a second buffer layer 114 are provided on the second sub-link line LNK2-1b among the plurality of 2-1st link lines LNK2-1. In addition, a third sub-link line LNK2-1c among the plurality of 2-1st link lines LNK2-1 is provided on the second gate insulating layer 112b and the second buffer layer 114. The third sub-link line LNK2-1c among the plurality of 2-1st link lines LNK2-1 may be made of the same material and provided on the same layer as the second gate electrode G2, but is not limited thereto.

[0153] The second interlayer insulating layer 113b is disposed on the plurality of 2-1st link lines LNK2-1, and the plurality of 2-2nd link lines LNK2-2 are disposed on the second interlayer insulating layer 113b. The plurality of 2-2nd link lines LNK2-2 may be disposed to overlap the plurality of 2-1st link lines LNK2-1.

[0154] The plurality of 2-2nd link lines LNK2-2 can be connected to the plurality of 2-1st link lines LNK2-1 through the plurality of third contact holes CNT3 disposed in the first interlayer insulating layer 113a, the second gate insulating layer 112b, the second buffer layer 114, and the second interlayer insulating layer 113b. That is, the plurality of 2-2nd link lines LNK2-2 can be connected to the first sub-link line LNK2-1a through the third contact holes CNT3a disposed in the first interlayer insulating layer 113a, the second gate insulating layer 112b, the second buffer layer 114, and the second interlayer insulating layer 113b. Furthermore, the plurality of 2-2nd link lines LNK2-2 can be connected to the second sub-link line LNK2-1b through the third contact holes CNT3b disposed in the second gate insulating layer 112b, the second buffer layer 114, and the second interlayer insulating layer 113b, and connected to the third sub-link line LNK2-1c through the third contact holes CNT3c disposed in the second interlayer insulating layer 113b.

[0155] The plurality of 2-2nd link lines LNK2-2 may be made of the same material and disposed on the same layer as the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2, but is not limited thereto. For example, each of the plurality of 2-2nd link lines LNK2-2 may have a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), but is not limited thereto.

[0156] A first planarization layer 115a is disposed on the plurality of 2nd-2nd link lines LNK2-2, and a plurality of 2nd-3rd link lines LNK2-3 are disposed on the first planarization layer 115a. The plurality of 2nd-3rd link lines LNK2-3 may be respectively connected to the plurality of 2nd-2nd link lines LNK2-2 through a plurality of fourth contact holes CNT4 disposed in the first planarization layer 115a. The plurality of 2nd-3rd link lines LNK2-3 may be connected to the plurality of second pads PAD2.

[0157] The plurality of 2nd-3rd link lines LNK2-3 may be made of the same material and disposed on the same layer as the auxiliary electrode 145, but is not limited thereto. For example, each of the plurality of 2nd-3rd link lines LNK2-3 may have a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), but is not limited thereto.

[0158] The plurality of fourth contact holes CNT4 may be disposed farther from the display area AA than the plurality of third contact holes CNT3. That is, the plurality of third contact holes CNT3 electrically connecting the plurality of 2-1st link lines LNK2-1 to the plurality of 2-2nd link lines LNK2-2 may be disposed closer to the display area AA than the plurality of fourth contact holes CNT4 electrically connecting the plurality of 2-2nd link lines LNK2-2 to the plurality of 2-3rd link lines LNK2-3.

[0159] The plurality of second contact holes CNT2 are disposed closer to the display area AA than the plurality of first contact holes CNT1. Furthermore, the plurality of fourth contact holes CNT4 are disposed farther from the display area AA than the plurality of third contact holes CNT3. Therefore, the plurality of 1-1th link wires LNK1-1 can be disposed further outside the flexible substrate 110 than the plurality of 2-1th link wires LNK2-1.

[0160] Meanwhile, the multi-buffer layer 111a, active buffer layer 111b, first gate insulating layer 112a, first interlayer insulating layer 113a, second gate insulating layer 112b, second buffer layer 114, and second interlayer insulating layer 113b are only provided in the second non-display area NA2 and not in the bending area BA. This is to reduce stress in the bending area BA and suppress the occurrence of cracks in the insulating layer made of inorganic materials. Specifically, the touch insulating layer, including the touch buffer layer 118a, touch interlayer insulating layer 118b, and touch planarizing layer 118c, completely overlaps the plurality of 2-1st link lines LNK2-1 and the plurality of 2-2nd link lines LNK2-2. However, they are not provided in the bending area BA. Therefore, they may overlap only a portion of the plurality of 2-3rd link lines LNK2-3.

[0161] In general display devices, various inorganic layers are used to block the penetration of moisture. However, such inorganic layers have lower flexibility than organic layers and therefore show brittleness, which has a tendency to break. Therefore, in a display device including a frame area to be bent, the inorganic layer is not provided in the bent area to suppress moisture from penetrating into the display device through cracks or gaps in the inorganic layer caused by the stress in the bent area from the bent area. Therefore, the inorganic layer can be designed to suppress the occurrence of cracks or gaps in the bent area. However, in the bent area, only organic layers that are relatively susceptible to damage from moisture penetration are provided. Therefore, moisture easily penetrates into the display device from the bent area. In addition, the penetration of moisture can be accelerated in a high temperature and / or high humidity environment.

[0162] In particular, each link line disposed in the bending area and the non-display area may have a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti). In this case, aluminum (Al) is a metal material with low resistance but susceptible to moisture damage. In other words, aluminum (Al) is easily oxidized and corroded, and is therefore fragile, and it may be highly susceptible to damage from moisture penetration. However, using aluminum material to maintain low resistance is important for the design of the link line.

[0163] At the same time, the commonly used inorganic layer has a very small thickness, while the organic layer has a much larger thickness than the inorganic layer. Therefore, if the wires or electrodes are connected through contact holes provided in the inorganic layer, the possibility of cracks or gaps appearing in the contact holes is very low. However, if the wires or electrodes are connected through contact holes provided in the organic layer, since the contact holes are deep, there may be a steep step change between the wires or electrodes provided in the contact holes. Therefore, cracks or gaps may appear in the wires or electrodes provided in the contact holes. If the wires or electrodes contain materials such as aluminum (Al), the aluminum is easily oxidized or corroded, which may result in poor electrical connection between the wires or electrodes. Therefore, the resistance in the wires or electrodes may increase, which may cause defects in the reliability of the display device, such as abnormal operation or abnormal display.

[0164] Furthermore, organic layers can contain relatively more moisture than inorganic layers. Therefore, wires or electrodes placed in contact holes in the organic layer may be exposed to more moisture than wires or electrodes placed in contact holes in the inorganic layer. Furthermore, when an electric field is applied to a wire or electrode placed in a contact hole, ions from the organic layer reach the wire or electrode, making it more likely to oxidize or corrode. Specifically, as the voltage difference between adjacent wires or electrodes increases, the intensity of the applied electric field increases. Consequently, oxidation or corrosion can be accelerated.

[0165] In particular, in currently used contact hole structures, contact holes in the organic layer are closer to the border area than contact holes in the inorganic layer. This oxidation or corrosion is more likely to occur in contact holes in the organic layer. Therefore, increasing the distance between the contact holes in the organic layer and the border area can be considered. However, this approach may result in an increase in the border area.

[0166] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the plurality of second contact holes CNT2 are arranged closer to the display area AA than the plurality of first contact holes CNT1. Therefore, oxidation or corrosion of the 1-3 link lines LNK1-3 arranged in the plurality of second contact holes CNT2 can be suppressed. The plurality of first contact holes CNT1 connecting the plurality of 1-1 link lines LNK1-1 to the 1-2 link lines LNK1-2 are arranged in the inorganic layer. Furthermore, the plurality of second contact holes CNT2 connecting the plurality of 1-2 link lines LNK1-2 to the plurality of 1-3 link lines LNK1-3 are arranged in the organic layer. Therefore, the longitudinal width w1 of the plurality of first contact holes CNT1 can be smaller than the longitudinal width w2 of the plurality of second contact holes CNT2. Therefore, the 1-3 link lines LNK1-3 arranged in the plurality of second contact holes CNT2 may be oxidized or corroded in the plurality of second contact holes CNT2. Specifically, the plurality of 1-1 link lines LNK1-1 can serve as gate link lines connected to the gate driver GD. Each 1-1 link line LNK1-1 may have a different polarity than another adjacent 1-1 link line, or a relatively high voltage difference may exist between the 1-1 link lines LNK1-1. Therefore, the multiple 1-1 link lines LNK1-1 may be easily oxidized or corroded. Therefore, in the display device according to the exemplary embodiment of the present disclosure, the multiple second contact holes CNT2 provided in the organic layer are arranged farther away from the bending area BA than the multiple first contact holes CNT1 provided in the inorganic layer. Therefore, oxidation or corrosion of the multiple 1-3 link lines LNK1-3 in the multiple second contact holes CNT2 provided in the organic layer can be suppressed. Therefore, the increase in resistance of the multiple 1-3 link lines LNK1-3 can be minimized, and reliability defects of the display device 100, such as abnormal operation or abnormal display, can also be suppressed. Therefore, the reliability of the display device 100 can be improved.

[0167] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, oxidation or corrosion of the first to third link lines LNK1-3 can be suppressed without increasing the size of the border area. In the central area of ​​the display device 100, without changing the design, the plurality of fourth contact holes CNT4 are arranged farther away from the display area AA than the plurality of third contact holes CNT3. However, the plurality of second contact holes CNT2 can be arranged closer to the display area AA than the plurality of first contact holes CNT1 only on both sides of the display device 100 (i.e., only in the area where the first link line LNK1 is arranged). That is, the distance between the plurality of second contact holes CNT2 arranged in the organic layer and the bending area BA can be increased by changing the position of the contact holes. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the distance between the plurality of second contact holes CNT2 and the bending area BA can be increased without increasing the size of the border area. Therefore, the reliability of the display device 100 can be improved.

[0168] Figure 8 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Figure 9 It is along Figure 8 In addition to the connection between the second link lines LNK2 in the region B, Figure 8 and Figure 9 The display device shown in Figures 1 to 7 The display devices shown in FIG. 1 are substantially the same as those shown in FIG. 1 , and therefore, repeated descriptions are omitted.

[0169] The plurality of second link lines LNK2 may connect the plurality of pads PAD to various lines disposed in the display area AA. Specifically, the plurality of second link lines LNK2 may transmit signals for driving pixels disposed in the display area AA from the plurality of second pads PAD2 to the various lines. For example, the plurality of second link lines LNK2 may be used to transmit data voltages, power supply voltages, and the like to the display area AA. Therefore, the second link lines LNK2 may function as data link lines or power link lines, but are not limited thereto.

[0170] refer to Figure 8 and Figure 9 The plurality of second link lines LNK2 may include a plurality of 2-1st link lines LNK2-1, a plurality of 2-2nd link lines LNK2-2, and a plurality of 2-3rd link lines LNK2-3. The plurality of 2-1st link lines LNK2-1 and the plurality of 2-2nd link lines LNK2-2 may be disposed in the non-display area NA. In addition, the plurality of 2-3rd link lines LNK2-3 may be disposed in the non-display area NA and the bending area BA.

[0171] A multi-buffer layer 111a, an active buffer layer 111b, and a first gate insulating layer 112a are disposed on the flexible substrate 110. Furthermore, a plurality of 2-1st link lines LNK2-1 are disposed on the multi-buffer layer 111a, the active buffer layer 111b, and the first gate insulating layer 112a. The plurality of 2-1st link lines LNK2-1 can be connected to various lines disposed in the display area AA.

[0172] There may be a relatively low voltage difference between signals transmitted by adjacent 2-1 link lines LNK2-1 among the plurality of 2-1 link lines LNK2-1. For example, the voltage difference between signals transmitted by adjacent 2-1 link lines LNK2-1 among the plurality of 2-1 link lines LNK2-1 may be lower than the voltage difference between signals transmitted by adjacent 1-1 link lines LNK1-1 among the plurality of 1-1 link lines LNK1-1.

[0173] The plurality of 2-1st link lines LNK2-1 may include a plurality of sub-link lines LNK2-1a, LNK2-1b, and LNK2-1c. Specifically, each of the plurality of 2-1st link lines LNK2-1 may include a plurality of sub-link lines LNK2-1a, LNK2-1b, and LNK2-1c with an insulating layer interposed therebetween. The plurality of sub-link lines LNK2-1a, LNK2-1b, and LNK2-1c may include a first sub-link line LNK2-1a, a second sub-link line LNK2-1b, and a third sub-link line LNK2-1c.

[0174] The first sub link line LNK2-1a of the plurality of 2-1st link lines LNK2-1 is disposed on the multi-buffer layer 111a, the active buffer layer 111b, and the first gate insulating layer 112a. In addition, the first sub link line LNK2-1a may be made of the same material and disposed on the same layer as the first gate electrode G1, but is not limited thereto.

[0175] A first interlayer insulating layer 113a is provided on the first sub-link line LNK2-1a of the plurality of 2-1st link lines LNK2-1. Furthermore, a second sub-link line LNK2-1b of the plurality of 2-1st link lines LNK2-1 is provided on the first interlayer insulating layer 113a. The second sub-link line LNK2-1b of the plurality of 2-1st link lines LNK2-1 may be made of the same material and provided on the same layer as the second capacitor electrode C2, but is not limited thereto.

[0176] A second gate insulating layer 112b and a second buffer layer 114 are provided on the second sub-link line LNK2-1b among the plurality of 2-1st link lines LNK2-1. In addition, a third sub-link line LNK2-1c among the plurality of 2-1st link lines LNK2-1 is provided on the second gate insulating layer 112b and the second buffer layer 114. The third sub-link line LNK2-1c among the plurality of 2-1st link lines LNK2-1 may be made of the same material and provided on the same layer as the second gate electrode G2, but is not limited thereto.

[0177] The second interlayer insulating layer 113b is disposed on the plurality of 2-1st link lines LNK2-1, and the plurality of 2-2nd link lines LNK2-2 are disposed on the second interlayer insulating layer 113b. The plurality of 2-2nd link lines LNK2-2 may be disposed to overlap the plurality of 2-1st link lines LNK2-1.

[0178] The plurality of 2-2nd link lines LNK2-2 can be connected to the plurality of 2-1st link lines LNK2-1 through a plurality of third contact holes CNT3 disposed in the first interlayer insulating layer 113a, the second gate insulating layer 112b, the second buffer layer 114, and the second interlayer insulating layer 113b. That is, the plurality of 2-2nd link lines LNK2-2 can be connected to the first sub-link line LNK2-1a through the third contact holes CNT3a disposed in the first interlayer insulating layer 113a, the second gate insulating layer 112b, the second buffer layer 114, and the second interlayer insulating layer 113b. Furthermore, the plurality of 2-2nd link lines LNK2-2 can be connected to the second sub-link line LNK2-1b through the third contact holes CNT3b disposed in the second gate insulating layer 112b, the second buffer layer 114, and the second interlayer insulating layer 113b, and to the third sub-link line LNK2-1c through the third contact holes CNT3c disposed in the second interlayer insulating layer 113b.

[0179] The plurality of 2-2nd link lines LNK2-2 may be made of the same material and disposed on the same layer as the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2, but are not limited thereto. For example, each of the plurality of 2-2nd link lines LNK2-2 may have a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), but is not limited thereto.

[0180] A first planarization layer 115a is disposed on the plurality of 2nd-2nd link lines LNK2-2, and a plurality of 2nd-3rd link lines LNK2-3 are disposed on the first planarization layer 115a. The plurality of 2nd-3rd link lines LNK2-3 may be respectively connected to the plurality of 2nd-2nd link lines LNK2-2 through a plurality of fourth contact holes CNT4 disposed in the first planarization layer 115a. The plurality of 2nd-3rd link lines LNK2-3 may be connected to the plurality of second pads PAD2.

[0181] The plurality of 2nd-3rd link lines LNK2-3 may be made of the same material and disposed on the same layer as the auxiliary electrode 145, but is not limited thereto. For example, each of the plurality of 2nd-3rd link lines LNK2-3 may have a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), but is not limited thereto.

[0182] The plurality of fourth contact holes CNT4 may be disposed farther from the display area AA than the plurality of third contact holes CNT3. That is, the plurality of third contact holes CNT3 electrically connecting the plurality of 2-1st link lines LNK2-1 to the plurality of 2-2nd link lines LNK2-2 may be disposed closer to the display area AA than the plurality of fourth contact holes CNT4 electrically connecting the plurality of 2-2nd link lines LNK2-2 to the plurality of 2-3rd link lines LNK2-3.

[0183] The plurality of fourth contact holes CNT4 are disposed closer to the display area AA than the plurality of third contact holes CNT3. Furthermore, the plurality of third contact holes CNT3 are disposed farther from the display area AA than the plurality of fourth contact holes CNT4. Therefore, the plurality of 1-1th link lines LNK1-1 can be disposed at positions corresponding to the plurality of 2-1st link lines LNK2-1 on a plane.

[0184] In a display device 200 according to another exemplary embodiment of the present disclosure, the plurality of fourth contact holes CNT4 are disposed closer to the display area AA than the plurality of third contact holes CNT3. Thus, oxidation or corrosion of the 2nd-3rd link lines LNK2-3 disposed in the plurality of fourth contact holes CNT4 can be suppressed. That is, in a display device according to another exemplary embodiment of the present disclosure, the plurality of fourth contact holes CNT4 disposed in the organic layer are disposed farther from the bending area BA than the plurality of third contact holes CNT3 disposed in the inorganic layer. Thus, oxidation or corrosion of the plurality of 2nd-3rd link lines LNK2-3 disposed in the plurality of fourth contact holes CNT4 disposed in the organic layer can be suppressed. Consequently, an increase in resistance of the plurality of 2nd-3rd link lines LNK2-3 can be minimized, and reliability defects of the display device 200, such as abnormal operation or display, can also be suppressed. Consequently, the reliability of the display device 200 can be improved.

[0185] Furthermore, in a display device 200 according to another exemplary embodiment of the present disclosure, the plurality of fourth contact holes CNT4 are disposed closer to the display area AA than the plurality of third contact holes CNT3. Thus, oxidation or corrosion of the 2nd-3rd link lines LNK2-3 disposed in the plurality of fourth contact holes CNT4 can be suppressed. Each of the plurality of second link lines LNK2 functions as a data link line or a power link line. The voltage difference between adjacent second link lines LNK2 can be lower than the voltage difference between the plurality of first link lines LNK1. Therefore, the second link lines LNK2 can have higher oxidation resistance or corrosion resistance than the plurality of first link lines LNK1. However, the plurality of 2nd-3rd link lines LNK2-3 among the plurality of second link lines LNK2 are disposed in the fourth contact holes CNT4 disposed in the organic layer. Therefore, oxidation or corrosion may occur in the plurality of 2nd-3rd link lines LNK2-3. Therefore, in a display device 200 according to another exemplary embodiment of the present disclosure, the plurality of fourth contact holes CNT4 disposed in the organic layer are positioned farther from the bending area BA than the plurality of third contact holes CNT3 disposed in the inorganic layer. Consequently, oxidation or corrosion of the plurality of second-third link lines LNK2-3 within the plurality of fourth contact holes CNT4 disposed in the organic layer can be suppressed. Consequently, an increase in resistance of the plurality of second-third link lines LNK2-3 can be minimized, and reliability defects in the display device 200, such as abnormal operation or display, can be suppressed. Consequently, the reliability of the display device 200 can be improved.

[0186] Furthermore, in a display device 200 according to another exemplary embodiment of the present disclosure, oxidation or corrosion of the 2nd-3rd link line LNK2-3 can be suppressed without increasing the size of the border area. Specifically, the distances between the plurality of fourth contact holes CNT4 provided in the organic layer and the distances between the plurality of fourth contact holes CNT4 and the bending area BA can be increased simply by changing the positions of the contact holes. Therefore, in a display device 200 according to another exemplary embodiment of the present disclosure, the distances between the plurality of fourth contact holes CNT4 and the distances between the plurality of fourth contact holes CNT4 and the bending area BA can be increased without increasing the size of the border area. Consequently, the reliability of the display device 200 can be improved.

[0187] Exemplary embodiments of the present disclosure may also be described as follows:

[0188] According to one aspect of the present disclosure, a display device includes: a flexible substrate, the flexible substrate including a display area, a non-display area, and a bending area extending from the non-display area; a plurality of 1-1 link lines, the plurality of 1-1 link lines being arranged on the flexible substrate in the non-display area; one or more insulating layers, the one or more insulating layers being arranged on the plurality of 1-1 link lines; a plurality of 1-2 link lines, the plurality of 1-2 link lines being respectively connected to the plurality of 1-1 link lines through a plurality of first contact holes arranged in the one or more insulating layers; a first planarization layer, the first planarization layer being arranged on the plurality of 1-2 link lines; a plurality of 1-3 link lines, the plurality of 1-3 link lines being respectively connected to the plurality of 1-2 link lines through a plurality of second contact holes arranged in the first planarization layer; and a plurality of first pads, the plurality of first pads being connected to the plurality of 1-3 link lines, wherein the plurality of second contact holes are arranged to be closer to the display area than the plurality of first contact holes.

[0189] The one or more insulating layers may be made of an inorganic material, and the first planarization layer may be made of an organic material.

[0190] A longitudinal width of the plurality of first contact holes may be smaller than a longitudinal width of the plurality of second contact holes.

[0191] The display device may further include a gate driver disposed in the non-display area, wherein the plurality of 1-1th link lines may be connected to the gate driver.

[0192] A signal applied to each of the plurality of 1-1th link lines may have a different polarity from a signal applied to another 1-1th link line adjacent thereto.

[0193] At least one of the plurality of 1-1 link lines may include a plurality of sub link lines that are disposed on different layers from each other and connected to the same 1-2 link line of the plurality of 1-2 link lines.

[0194] The display device may further include: a plurality of 2-1 link lines, the plurality of 2-1 link lines being arranged below the one or more insulating layers in the non-display area; a plurality of 2-2 link lines, the plurality of 2-2 link lines being arranged between the one or more insulating layers and the first planarization layer, and being respectively connected to the plurality of 2-1 link lines through a plurality of third contact holes arranged in the one or more insulating layers; a plurality of 2-3 link lines, the plurality of 2-3 link lines being respectively connected to the plurality of 2-2 link lines through a plurality of fourth contact holes arranged in the first planarization layer; and a plurality of second pads, the plurality of second pads being connected to the plurality of 2-3 link lines, wherein the plurality of third contact holes may be arranged to be closer to the display area than the plurality of fourth contact holes.

[0195] Each of the plurality of 2-1th link lines, the plurality of 2-2th link lines, and the plurality of 2-3th link lines may be used as a data link line or a power link line.

[0196] The plurality of 1-1th link lines may be disposed at an outer side of the flexible substrate than the plurality of 2-1th link lines.

[0197] The display device may also include: a plurality of 2-1 link lines, which are arranged under the one or more insulating layers in the non-display area; a plurality of 2-2 link lines, which are arranged between the one or more insulating layers and the first planarization layer, and are respectively connected to the plurality of 2-1 link lines through a plurality of third contact holes arranged in the one or more insulating layers; a plurality of 2-3 link lines, which are respectively connected to the plurality of 2-2 link lines through a plurality of fourth contact holes arranged in the first planarization layer; and a plurality of second pads, which are connected to the plurality of 2-3 link lines, and the plurality of fourth contact holes can be arranged to be closer to the display area than the plurality of third contact holes.

[0198] The plurality of 1-1th link lines and the plurality of 1-2th link lines may be disposed in the non-display area, and the plurality of 1-3th link lines may be disposed in the non-display area and the bending area.

[0199] The display device may further include: a plurality of light-emitting elements, which are arranged on the flexible substrate in the display area; an encapsulation layer, which is arranged on the plurality of light-emitting elements; and a touch insulation layer, which is arranged on the encapsulation layer, wherein the plurality of 1-1 link lines and the plurality of 1-2 link lines can completely overlap with the touch insulation layer.

[0200] The touch insulation layer may be disposed in the non-display area among the non-display area and the bending area, and may overlap only a portion of the plurality of 1st to 3rd link lines.

Claims

1. A display device comprising: a flexible substrate comprising a display area, a non-display area, and a bending area extending from the non-display area; a plurality of 1-1 link lines, wherein the plurality of 1-1 link lines are arranged on the flexible substrate in the non-display area; One or more insulating layers, the one or more insulating layers being disposed on the plurality of 1-1 link lines; a plurality of 1-2 link lines, wherein the plurality of 1-2 link lines are respectively connected to the plurality of 1-1 link lines through a plurality of first contact holes provided in the one or more insulating layers; a first planarization layer, the first planarization layer being disposed on the plurality of 1-2 link lines; a plurality of 1st to 3rd link lines, wherein the plurality of 1st to 3rd link lines are respectively connected to the plurality of 1st to 2nd link lines through a plurality of second contact holes provided in the first planarization layer; as well as a plurality of first pads connected to the plurality of 1st to 3rd link lines; The plurality of second contact holes are arranged to be closer to the display area than the plurality of first contact holes.

2. The display device according to claim 1, wherein The one or more insulating layers are made of an inorganic material, and The first planarization layer is made of an organic material.

3. The display device according to claim 2, wherein: A longitudinal width of the plurality of first contact holes is smaller than a longitudinal width of the plurality of second contact holes.

4. The display device according to claim 1, further comprising: a gate driver, the gate driver being disposed in the non-display area, The plurality of 1-1 link lines are connected to the gate driver.

5. The display device according to claim 4, wherein A signal applied to each of the plurality of 1-1 link lines has a different polarity from a signal applied to another 1-1 link line adjacent thereto. The display device according to claim 4 , wherein: At least one of the plurality of 1-1 link lines includes a plurality of sub link lines that are disposed on different layers from each other and connected to the same 1-2 link line of the plurality of 1-2 link lines.

7. The display device according to claim 1, further comprising: a plurality of 2-1 link lines, wherein the plurality of 2-1 link lines are disposed below the one or more insulating layers in the non-display area; a plurality of 2-2 link lines, the plurality of 2-2 link lines being disposed between the one or more insulating layers and the first planarization layer and respectively connected to the plurality of 2-1 link lines through a plurality of third contact holes disposed in the one or more insulating layers; a plurality of 2-3 link lines, wherein the plurality of 2-3 link lines are respectively connected to the plurality of 2-2 link lines through a plurality of fourth contact holes provided in the first planarization layer; as well as a plurality of second pads connected to the plurality of 2nd-3rd link lines, The plurality of third contact holes are arranged to be closer to the display area than the plurality of fourth contact holes.

8. The display device according to claim 7, wherein: Each of the plurality of 2-1th link lines, the plurality of 2-2th link lines, and the plurality of 2-3th link lines functions as a data link line or a power link line.

9. The display device according to claim 7, wherein: The plurality of 1-1th link lines are disposed on an outer side of the flexible substrate than the plurality of 2-1th link lines.

10. The display device according to claim 4, further comprising: a plurality of 2-1 link lines, wherein the plurality of 2-1 link lines are disposed below the one or more insulating layers in the non-display area; a plurality of 2-2 link lines, the plurality of 2-2 link lines being disposed between the one or more insulating layers and the first planarization layer and respectively connected to the plurality of 2-1 link lines through a plurality of third contact holes disposed in the one or more insulating layers; a plurality of 2-3 link lines, wherein the plurality of 2-3 link lines are respectively connected to the plurality of 2-2 link lines through a plurality of fourth contact holes provided in the first planarization layer; as well as a plurality of second pads connected to the plurality of 2nd-3rd link lines, The plurality of fourth contact holes are arranged to be closer to the display area than the plurality of third contact holes.

11. The display device according to claim 1, wherein The plurality of 1-1 link lines and the plurality of 1-2 link lines are arranged in the non-display area, and The plurality of first to third link lines are disposed in the non-display area and the bending area.

12. The display device according to claim 1, further comprising: a plurality of light-emitting elements, the plurality of light-emitting elements being disposed on the flexible substrate in the display area; an encapsulation layer, the encapsulation layer being disposed on the plurality of light-emitting elements; as well as a touch insulating layer, the touch insulating layer being arranged on the encapsulation layer, The plurality of 1-1 link lines and the plurality of 1-2 link lines completely overlap with the touch insulation layer.

13. The display device according to claim 12, wherein: The touch insulation layer is disposed in the non-display area among the non-display area and the bending area, and overlaps only a portion of the plurality of 1st to 3rd link lines.

14. The display device according to claim 7 or 10, wherein: The plurality of 2-1 link lines and the plurality of 2-2 link lines are arranged in the non-display area, and The plurality of 2nd-3rd link lines are disposed in the non-display area and the bending area.

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