Display device, method for manufacturing display device, and head-mounted display device

Abstract

The invention provides a display device, a method for manufacturing the display device, and a head-mounted display device. The display device includes: a first single crystal semiconductor substrate at which a first transistor is positioned; a second single crystal semiconductor substrate on the first single crystal semiconductor substrate, and a second transistor positioned at the second single crystal semiconductor substrate; and a connection line layer between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate. The second single crystal semiconductor substrate includes a display area in which sub-pixels are positioned, each of the plurality of sub-pixels including a light emitting element, a plurality of first through-holes in a non-display area around the display area, and a plurality of second through-holes in a non-display area around the display area. And a first conductive via connected to a data line extending in the first direction is positioned in the plurality of first vias, a plurality of second vias is in the non-display area, and a second conductive via is positioned in the plurality of second vias.

Description

Technical Field

[0001] One or more embodiments of the present disclosure relate to a display device, a method for manufacturing a display device, and a head-mounted display device. Background Art

[0002] A head-mounted display (HMD) is a device worn on a user's head in the form of glasses or a helmet, with an image display focused at a close distance in front of the user's eyes. This device can enable virtual reality (VR) and / or augmented reality (AR).

[0003] Head-mounted display devices use multiple lenses to magnify an image displayed on a small display device and then display the magnified image. Therefore, the display device used in head-mounted display devices needs to provide high-resolution images, for example, images with a resolution of 3,000 pixels per inch (PPI) or higher. To this end, organic light-emitting diodes on silicon (OLEDoS), which are small, high-resolution organic light-emitting display devices, are used as display devices for head-mounted display devices. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are provided on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided. Summary of the Invention

[0004] Aspects and features of embodiments of the present disclosure provide a display device including a plurality of different single-crystal semiconductor substrates and a head-mounted display device including the display device.

[0005] Aspects and features of embodiments of the present disclosure also provide a display device implemented by effectively designing and arranging a through hole connecting two different semiconductor substrates and a method for manufacturing the display device.

[0006] However, the present disclosure is not limited to the contents set forth herein. The above and other embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to one or more embodiments of the present disclosure, a display device is provided, comprising: a first single-crystalline semiconductor substrate, wherein a plurality of first transistors are positioned; a second single-crystalline semiconductor substrate, located on the first single-crystalline semiconductor substrate, wherein a plurality of second transistors are positioned; and a connection line layer, located between the first and second single-crystalline semiconductor substrates. The second single-crystalline semiconductor substrate includes a display area in which a plurality of sub-pixels are positioned, a plurality of first through-holes, and a plurality of second through-holes, each of the plurality of sub-pixels including a light-emitting element. The plurality of first through-holes are located in a non-display area surrounding the display area, and first conductive vias connected to a plurality of data lines extending in a first direction are positioned in the plurality of first through-holes. The plurality of second through-holes are located in the non-display area, and second conductive vias connected to a plurality of first scan lines extending in a second direction are positioned in the plurality of second through-holes. The connection line layer includes first connection lines connecting the first conductive vias to a data driver on the first single-crystalline semiconductor substrate, and second connection lines connecting the second conductive vias to a scan driver on the first single-crystalline semiconductor substrate.

[0008] The first through holes may be spaced apart from each other, and the second through holes may be spaced apart from each other.

[0009] The plurality of first through-holes may be spaced apart from other adjacent first through-holes in an oblique direction, and the plurality of second through-holes may be spaced apart from other adjacent second through-holes in an oblique direction.

[0010] In the display area, a plurality of pixels may be arranged, each pixel including three sub-pixels. The three first through holes may be in an area occupied by one pixel and extending in one direction toward the non-display area.

[0011] The pixel may include three sub-pixel portions corresponding to the three sub-pixels, respectively. A distance between the first through holes may be 61.0328% or less of a distance between corresponding sub-pixel portions in adjacent pixels among the plurality of pixels.

[0012] The plurality of first through-holes and the plurality of second through-holes may not overlap with the first single crystal semiconductor substrate. Each of the first connection wire and the second connection wire may have at least a portion overlapping with the first single crystal semiconductor substrate.

[0013] The second single crystal semiconductor substrate may further include a plurality of third through holes in the non-display area, third conductive vias connected to a plurality of second scan lines extending in the second direction are positioned in the plurality of third through holes, and the connection line layer may further include third connection lines connecting the third conductive vias to the emission driver on the first single crystal semiconductor substrate.

[0014] The number of the first through holes may be equal to the number of the data lines and the number of the pixel columns of the plurality of sub-pixels.

[0015] The number of the second through holes may be equal to the number of the first scan lines, and may be greater than the number of pixel rows of the plurality of sub-pixels.

[0016] The display device may further include a plurality of signal terminals on the first single-crystalline semiconductor substrate. The second single-crystalline semiconductor substrate may further include a plurality of fourth through holes formed in the non-display region. The connection line layer may further include fourth connection lines connecting the signal terminals to fourth conductive vias in the fourth through holes.

[0017] An area of ​​the first single crystal semiconductor substrate in a plan view may be smaller than an area of ​​the second single crystal semiconductor substrate in a plan view.

[0018] A length of a minimum line width of the first transistor may be smaller than a length of a minimum line width of the second transistor.

[0019] The minimum line width of the first transistor may be less than 100 nm. The minimum line width of the second transistor may be greater than or equal to 100 nm.

[0020] The display device further includes a passivation layer surrounding the first single crystal semiconductor substrate and overlapping the second single crystal semiconductor substrate.

[0021] According to one or more embodiments of the present disclosure, a method for manufacturing a display device is provided, the method comprising the following steps: preparing a first wafer substrate and a second wafer substrate that are different from each other; forming a plurality of first transistors on the first wafer substrate; forming a pixel circuit on one surface of the second wafer substrate, and forming a plurality of through holes penetrating at least a portion of the second wafer substrate and a plurality of conductive vias respectively in the plurality of through holes; forming a connection line layer including a plurality of connection lines on the other surface of the second wafer substrate opposite to the one surface; dividing the first wafer substrate into a plurality of first single crystal semiconductor substrates, and attaching the first single crystal semiconductor substrate to the other surface of the second wafer substrate; forming a planarization layer covering the other surface of the second wafer substrate and the first single crystal semiconductor substrate attached to the other surface; forming a display element layer including a plurality of light-emitting elements on one surface of the second wafer substrate; and dividing the second wafer substrate into a plurality of second single crystal semiconductor substrates, in which the display element layer is formed on one surface and the first single crystal semiconductor substrate is on the other surface. The plurality of through holes include a plurality of first through holes in a non-display area surrounding the display area and having first conductive vias therein, and a plurality of second through holes in the non-display area and having second conductive vias therein. The connection line layer includes first connection lines connecting the first conductive vias to a data driver on the first single crystal semiconductor substrate, and second connection lines connecting the second conductive vias to a scan driver on the first single crystal semiconductor substrate.

[0022] The method may further include: performing etching to reduce a thickness of the second wafer substrate after forming the plurality of through holes and the plurality of conductive vias. The first single crystal semiconductor substrate may be attached to the connection line layer.

[0023] Each of the plurality of first through-holes and the plurality of second through-holes may not overlap with the first single crystal semiconductor substrate.

[0024] An area of ​​the first single crystal semiconductor substrate in a plan view may be smaller than an area of ​​the second single crystal semiconductor substrate in a plan view.

[0025] In the step of forming the pixel circuit on the second wafer substrate, a plurality of second transistors may be formed on the second wafer substrate. The minimum line width of the first transistor may be smaller than the minimum line width of the second transistor.

[0026] According to one or more embodiments of the present disclosure, a head-mounted display device is provided, comprising: a frame configured to be mounted on a user's body and corresponding to left and right eyes; a plurality of display devices within the frame; and a lens within each of the plurality of display devices. The display device includes: a first single-crystalline semiconductor substrate, a plurality of first transistors positioned on the first single-crystalline semiconductor substrate; a second single-crystalline semiconductor substrate positioned on the first single-crystalline semiconductor substrate, a plurality of second transistors positioned on the second single-crystalline semiconductor substrate; and a connection line layer between the first and second single-crystalline semiconductor substrates. The second single-crystalline semiconductor substrate includes a display area in which a plurality of sub-pixels are positioned, a plurality of first through-holes, and a plurality of second through-holes, each of the plurality of sub-pixels including a light-emitting element. The plurality of first through-holes are formed in a non-display area surrounding the display area, and first conductive vias connected to a plurality of data lines extending in a first direction are positioned within the plurality of first through-holes. A plurality of second through-holes are formed in the non-display area, and second conductive vias connected to a plurality of first scan lines extending in a second direction are positioned within the plurality of second through-holes. The connection line layer includes a first connection line connecting the first conductive via to a data driver on the first single crystal semiconductor substrate and a second connection line connecting the second conductive via to a scan driver on the first single crystal semiconductor substrate.

[0027] A display device according to one or more embodiments may include two different single-crystal semiconductor substrates and a through-hole through which a routing line connecting the two different single-crystal semiconductor substrates is provided. In a manufacturing process of the single-crystal semiconductor substrate provided on the lower side, a large number of semiconductor substrates can be manufactured per unit wafer substrate, thereby improving manufacturing yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other embodiments and features of the present disclosure will become more apparent by describing embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is an exploded perspective view of a display device according to one or more embodiments; Figure 2 It shows Figure 1 A plan view of an example of a drive portion shown in FIG; Figure 3 It shows Figure 1 A plan view of an example of a display portion shown in FIG; Figure 4 is shown in the settings Figure 3 A plan view of the arrangement of a plurality of wirings in a display portion; Figure 5 is a block diagram illustrating a display device according to one or more embodiments; Figure 6 is an equivalent circuit diagram of a pixel according to one or more embodiments; Figure 7 is a schematic cross-sectional view of a display device according to one or more embodiments; Figure 8 is a schematic diagram illustrating a rear surface of a display device according to one or more embodiments; Figure 9 is a schematic cross-sectional view of a driving portion according to one or more embodiments; Figure 10 is a plan view showing a pixel defining film provided in a display region of a display portion and first electrodes and emission regions of a plurality of sub-pixels according to one or more embodiments; Figure 11 is a plan view showing a pixel defining film provided in a display region of a display portion and first electrodes and emission regions of a plurality of sub-pixels according to one or more embodiments; Figures 12 to 14 is a cross-sectional view showing a portion of a display area and a portion of a non-display area in a display portion according to one or more embodiments; Figure 15 is a diagram illustrating relative arrangement of pixels and through-holes provided in a display portion of a display device according to one or more embodiments; Figure 16 is a flowchart illustrating a method for manufacturing a display device according to one or more embodiments; Figures 17 to 22 are diagrams sequentially illustrating a manufacturing process of a display device according to one or more embodiments; Figures 23 to 34 are cross-sectional views sequentially illustrating a manufacturing process of a display device according to one or more embodiments; Figure 35is a plan view showing the arrangement of a plurality of wirings provided in a display portion of a display device according to one or more embodiments; Figure 36 It shows Figure 35 A schematic diagram of the rear surface of the display device; Figure 37 is shown in the settings Figure 35 A diagram showing relative arrangement of through holes and pixels in a display portion of a display device; Figure 38 is a perspective view showing a head-mounted display device according to one or more embodiments; Figure 39 It shows Figure 38 an exploded perspective view of an example of a head-mounted display device; and Figure 40 is a perspective view illustrating a head-mounted display device according to one or more embodiments. DETAILED DESCRIPTION

[0029] By referring to the detailed description of the embodiments and the accompanying drawings, it is possible to more easily understand the aspects and features of the embodiments of the present disclosure and the methods for realizing the same. Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be implemented in various different forms and should not be interpreted as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described.

[0030] Unless otherwise specified, the same reference numerals, symbols or combinations thereof denote the same elements throughout the drawings and written description, and therefore, description thereof will not be repeated. In addition, parts not related to the description of one or more embodiments may not be shown to make the description clear.

[0031] In the accompanying drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. Additionally, the use of cross-hatching and / or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. Thus, unless otherwise indicated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the illustrated elements, and / or any other characteristics, attributes, properties, etc., of the elements.

[0032] Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Furthermore, for purposes of describing embodiments according to the present disclosure, specific structural or functional descriptions disclosed herein are illustrative only. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes of regions shown, but are intended to include deviations in shape due to, for example, manufacturing techniques.

[0033] For example, an implanted region illustrated as a rectangle may have rounded (rounded) or curved features and / or a gradient of implant concentration at its edges, rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation may cause some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions illustrated in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to be limiting. Additionally, as will be appreciated by those skilled in the art, the described embodiments may be modified in a variety of different ways, all without departing from the scope of this disclosure.

[0034] In the detailed description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0035] For ease of explanation, spatially relative terms such as "under," "beneath," "below," "beneath," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as "under," "beneath," or "below" another element or feature would then be oriented "above" the other element or feature. Thus, the example terms "under" and "beneath" can encompass both above and below orientations. The device can be oriented differently (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being disposed "on" a second part, this indicates that the first part is disposed at the upper or lower side of the second part, and is not limited to the upper side of the second part based on the direction of gravity.

[0036] Furthermore, in this specification, the phrase “on a plane” or “in a plan view” means viewing an object portion from the top, and the phrase “in section” means viewing a section formed by vertically cutting the object portion from the side.

[0037] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "bonded to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly bonded to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly bonded to the other element, layer, region, or component, such that one or more intervening elements, layers, regions, or components may be present. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically bonded" to another layer, region, or component, it may be directly electrically connected or directly bonded to the other layer, region, and / or component, or there may be intervening layers, regions, or components. However, "directly connected / directly bonded" means that one component is directly connected to or directly bonded to another component without intervening components. Meanwhile, other expressions describing the relationship between components, such as “between,” “immediately between,” or “adjacent to,” and “directly adjacent to,” should be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0038] For the purposes of this disclosure, expressions such as “at least one of,” “any of,” and “selected from,” when preceding or following a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XY, XZ, and YZ), or any variation thereof. Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B. In addition, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.”

[0039] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the first element, component, region, layer, or part described below may be named as the second element, component, region, layer, or part without departing from the scope of this disclosure.

[0040] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0041] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "an" are also intended to include the plural forms. It will also be understood that when the terms "comprises," "having," "including," and variations thereof are used in this specification, they indicate the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0042] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for inherent deviations in measured or calculated values ​​that one of ordinary skill in the art would recognize. As used herein, “about” or “approximately” is inclusive of the stated value and means within an acceptable range of deviation for the particular value determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Additionally, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.”

[0043] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in a reverse order to the described order.

[0044] In addition, any numerical range disclosed and / or recited herein is intended to include all subranges of the same numerical precision contained within the recited range. For example, a range of "1.0 to 10.0" is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, e.g., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit recited herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit recited in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to explicitly recite any subranges contained within the ranges explicitly recited herein. All such ranges are intended to be inherently described in this specification, such that amendment to explicitly recite any such subranges would be satisfactory.

[0045] The electronic or electrical devices described herein according to one or more embodiments of the present disclosure and / or any other related devices or components may be implemented using any suitable hardware, firmware (e.g., an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on a single integrated circuit (IC) chip or on separate IC chips. Furthermore, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0046] In addition, the various components of these devices can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. Computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (such as random access memory (RAM) as an example). Computer program instructions can also be stored in other non-transitory computer-readable media (such as CD-ROMs, flash drives, etc. as examples). In addition, it should be recognized by those skilled in the art that, without departing from the scope of the embodiments of the present disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed to one or more other computing devices.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0048] It will be appreciated by those skilled in the art that, in view of the overall content of the present disclosure, each suitable feature of the various embodiments of the present disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in various suitable manners, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable manner.

[0049] Figure 1 is an exploded perspective view of a display device according to one or more embodiments.

[0050] Reference Figure 1 The display device 10 according to one or more embodiments is a device for displaying moving images and / or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices (such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notepads, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile personal computers (UMPCs), etc.). For example, the display device 10 can be applied as a display portion of a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IoT) device. Alternatively, the display device 10 can be applied to a smartwatch, a watch phone, and / or a head-mounted display device (HMD) for implementing virtual reality and augmented reality.

[0051] The display device 10 according to one or more embodiments may include a driving portion 100, a display portion 200, and a circuit board 300. The display device 10 may further include a passivation layer 900 disposed around the driving portion 100.

[0052] The driving unit 100 may have a planar shape similar to a quadrilateral. For example, the driving unit 100 may have a planar shape similar to a rectangular shape having one side in a first direction DR1 and the other side in a second direction DR2 intersecting the first direction DR1. The one side of the driving unit 100 in the first direction DR1 and the other side of the driving unit 100 in the second direction DR2 may have different lengths. In the driving unit 100, the corner where the one side in the first direction DR1 and the other side in the second direction DR2 meet may be a right angle or rounded with a suitable curvature (e.g., a predetermined curvature). The planar shape of the driving unit 100 is not limited to a rectangular shape and may be a shape similar to another polygonal shape, a circular shape, and / or an elliptical shape.

[0053] The display unit 200 may be provided on the drive unit 100. In the display device 10, the drive unit 100 and the display unit 200 may be joined to each other. Unlike the drive unit 100, the display unit 200 may have a shape similar to a square. For example, the display unit 200 may have a planar shape similar to a square in which one side in a first direction DR1 and the other side in a second direction DR2 intersecting the first direction DR1 have the same length. The planar shape of the display unit 200 is not limited to a square shape and may be a shape similar to another polygonal shape, a circular shape, and / or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the display unit 200, but is not limited thereto.

[0054] According to one or more embodiments, in the display device 10, the area of ​​the display portion 200 in a plan view may be larger than the area of ​​the drive portion 100 in a plan view. The display device 10 may include a drive portion 100 and a display portion 200 having different substrates, and they may have different areas. The elements formed in the drive portion 100 and the elements formed in the display portion 200 may be different, and these elements may be formed separately on different substrates. The display device 10 can be manufactured by forming a plurality of elements having different sizes, line widths, and manufacturing processes on different substrates and then joining them. Product performance and manufacturing yield can be improved by manufacturing the display device 10.

[0055] The circuit board 300 can be electrically connected to a plurality of pads (also called "pads") in the pad area of ​​the display portion 200 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board (FPCB) and / or a flexible film having a flexible material. Although the circuit board 300 is Figure 1Although shown as being unfolded in FIG, the circuit board 300 can be bent. In this case, one end of the circuit board 300 can be placed on the bottom surface of the driving unit 100. The other end of the circuit board 300 can be connected to the plurality of pads in the pad area of ​​the display unit 200 using a conductive adhesive member. In one or more embodiments, the circuit board 300 can be attached to the bottom surface of the driving unit 100.

[0056] The passivation layer 900 may be provided on the bottom surface of the display unit 200 and around (eg, surrounding) the driving unit 100. The passivation layer 900 may reduce the level difference caused by the area difference between the driving unit 100 and the display unit 200 and may also protect the driving unit 100 and the display unit 200.

[0057] Figure 2 It shows Figure 1 2 is a plan view of an example of a drive portion shown in FIG. Figure 3 It shows Figure 1 A plan view of an example of a display portion shown in FIG. Figure 4 is shown in the settings Figure 3 A plan view showing the arrangement of multiple wirings in a display portion.

[0058] Reference Figures 2 to 4 The driving portion 100 of the display device 10 may include driving circuit elements of the display device 10. The driving portion 100 may include a first single crystal semiconductor substrate 110, and a driving circuit 400, a gate driver 600, and a data driver 700 formed on the first single crystal semiconductor substrate 110. The gate driver 600 may include a scan driver 610 and an emission driver 620.

[0059] The first single crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. A plurality of first transistors may be formed on the first single crystal semiconductor substrate 110. The plurality of first transistors may be electrically connected to each other and may constitute the driving circuit 400, the gate drivers 600: 610 and 620, the data driver 700, and the pixel circuit 220 (see FIG. Figure 6 )(For example, Figure 6 The first transistors may be formed by a semiconductor process. For example, the plurality of first transistors may be formed as complementary metal oxide semiconductor (CMOS) transistors.

[0060] exist Figure 2For example, the drive circuit 400 is shown disposed at the center of the drive unit 100, the data driver 700 and the signal terminal area TDA are disposed at the upper and lower sides of the drive circuit 400 in the second direction DR2, and the gate drivers 600 (610 and 620) are disposed on both sides of the drive circuit 400 in the first direction DR1. The scan driver 610 may be disposed on the left side of the drive circuit 400, and the emission driver 620 may be disposed on the right side of the drive circuit 400. However, the present disclosure is not limited thereto. The positions of the drive circuit 400, the gate drivers 600 (610 and 620), and the data driver 700 may vary depending on the design structure of the plurality of circuit elements formed on the first single crystal semiconductor substrate 110.

[0061] In the signal terminal area TDA, a plurality of signal terminals STD arranged along the first direction DR1 may be provided. The plurality of signal terminals STD may be electrically connected to the display portion 200, and may be electrically connected to the circuit board 300 via the display portion 200. The signal terminals STD may transmit electrical signals applied from the circuit board 300 to the driving circuit 400, the gate driver 600, the data driver 700, and the pixel circuit 220 (e.g., Figure 6 PXC).

[0062] The display portion 200 may include a second single crystal semiconductor substrate 210 and a plurality of pixels PX and a pixel circuit 220 (eg, Figure 6 The display portion 200 may include a display area DAA in which a plurality of pixels PX are provided, and a non-display area NA around (e.g., surrounding) the display area DAA along an edge or periphery of the display area DAA. Through hole areas TSA1, TSA2, TSA3, and TSA4 and a pad area PDA may be provided in the non-display area NA.

[0063] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, and / or a silicon germanium substrate. A plurality of second transistors may be formed on the second single crystal semiconductor substrate 210, and the plurality of second transistors may be electrically connected to each other to form a pixel circuit 220 (e.g., Figure 6 The second transistors may be formed by a semiconductor process. For example, the plurality of second transistors may be formed as complementary metal oxide semiconductor (CMOS) transistors.

[0064] A plurality of pixels PX including light-emitting elements may be provided in the display area DAA. Each of the plurality of pixels PX may include three sub-pixels, for example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The three sub-pixels SP1, SP2, and SP3 may constitute one pixel PX to display a color. However, the present disclosure is not limited thereto, and one pixel PX may include four or more sub-pixels SP. The plurality of sub-pixels SP may be arranged in a matrix form along the first direction DR1 and the second direction DR2. For example, the plurality of sub-pixels SP may be arranged along rows and columns of the matrix along the first direction DR1 and the second direction DR2. Each of the plurality of sub-pixels SP1, SP2, and SP3 may be electrically connected to a pixel circuit PXC (see Figure 6 Each of the sub-pixels SP1, SP2, and SP3 may include a light emitting element, and the light emitting element may emit light according to an electrical signal applied from a pixel circuit PXC provided in the display area DAA.

[0065] Some of the sub-pixels SP1, SP2, and SP3 disposed in the display area DAA of the display portion 200 may overlap the driving portion 100 in the thickness direction (e.g., the third direction DR3) of the display device 10, while other sub-pixels may not overlap the driving portion 100. The driving portion 100 has an area smaller than that of the display portion 200 and may be disposed adjacent to one side of the display portion 200. Therefore, only some of the sub-pixels SP1, SP2, and SP3 may overlap the driving portion 100 in the thickness direction (e.g., the third direction DR3).

[0066] Pixel circuit 220 (eg, Figure 6 The PXC includes a plurality of pixel transistors formed on a second single crystal semiconductor substrate 210. The plurality of pixel transistors may be formed by a semiconductor process. For example, the plurality of pixel transistors may be formed as CMOS transistors.

[0067] The pixel circuit 220 may include a pixel circuit PXC (eg, see FIG. 1 ) composed of a plurality of pixel transistors and electrically connected to each of the sub-pixels SP1, SP2, and SP3. Figure 6 ) and a plurality of scan lines GL1 and GL2 and data lines DL. A plurality of pixel circuits PXC may be arranged along a first direction DR1 and a second direction DR2 in the pixel circuit 220. The arrangement of the pixel circuits PXC may be similar to the arrangement of the sub-pixels SP1, SP2, and SP3.

[0068] The plurality of scan lines GL1 and GL2 may extend in the first direction DR1 and may be spaced apart from each other (e.g., spaced apart) in the second direction DR2, and the plurality of data lines DL may extend in the second direction DR2 and may be spaced apart from each other (e.g., spaced apart) in the first direction DR1. The plurality of data lines DL may extend from a first through hole area TSA1 disposed to the upper side of the display area DAA, and the plurality of scan lines GL1 and GL2 may extend from a second through hole area TSA2 and a third through hole area TSA3 disposed to the left and right sides of the display area DAA, respectively. The plurality of scan lines GL1 and GL2 may include different types of scan lines, for example, first to third scan lines GWL, GCL, and GBL (see Figure 5 ) and emission control lines EL1 and EL2 (see Figure 5 For example, the first scan line GL1 extending from the second through hole area TSA2 may include first to third scan lines GWL, GCL, and GBL (see Figure 5 ), and the second scan line GL2 extending from the third through hole area TSA3 may include a plurality of emission control lines EL1 and EL2 (see Figure 5 ). A plurality of scan lines GL1 and GL2 and a data line DL can be connected to a plurality of sub-pixels SP1, SP2, and SP3 of the display area DAA. The plurality of scan lines GL1 and GL2 can be electrically connected to the gate driver 600 of the driving unit 100, and the plurality of data lines DL can be electrically connected to the data driver 700 of the driving unit 100. The data lines DL can be electrically connected to the data driver 700 of the driving unit 100 through a first through-hole TSV1, the first scan line GL1 can be electrically connected to the scan driver 610 through a second through-hole TSV2, and the second scan line GL2 can be electrically connected to the emission driver 620 through a third through-hole TSV3.

[0069] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be electrically connected to scan lines GL1 and GL2 and a data line DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive a data voltage of the data line DL in response to a scan signal of the scan lines GL1 and GL2 and emit light from the light emitting element according to the data voltage.

[0070] The non-display area NA may be disposed around (e.g., surrounding) the display area DAA. The non-display area NA may be an area where no pixels PX are disposed and thus no light is emitted. The pad area PDA and the plurality of through holes TSV1, TSV2, TSV3, and TSV4 may be disposed in the non-display area NA.

[0071] The display device 10 may include a plurality of through-holes (TSV1, TSV2, TSV3, and TSV4) forming paths through which elements provided in the driving unit 100 and the display unit 200 are electrically connected to each other. The plurality of through-holes (TSV1, TSV2, TSV3, and TSV4) may be formed to penetrate the second single crystal semiconductor substrate 210 of the display unit 200. The driving circuit 400, the gate drivers 600 (610 and 620), and the data driver 700 provided in the driving unit 100 may be electrically connected to the display unit 200 and the circuit board 300 via connection lines provided in the through-holes (TSV1, TSV2, TSV3, and TSV4).

[0072] The plurality of through holes TSV1 , TSV2 , TSV3 , and TSV4 may include a first through hole TSV1 , a second through hole TSV2 , a third through hole TSV3 , and a fourth through hole TSV4 disposed in the non-display area NA.

[0073] The first through hole TSV1 may be provided in the non-display area NA on one side of the display area DAA in the second direction DR2. For example, the first through hole TSV1 may be provided in the first through hole area TSA1 positioned to the upper side of the display area DAA. The first through hole TSV1 may be provided to correspond to the plurality of data lines DL provided in the display area DAA, respectively. The number of the first through holes TSV1 may be equal to the number of data lines DL and the number of pixel columns of the plurality of sub-pixels SP1, SP2, and SP3 provided in the display area DAA. Each of the plurality of data lines DL may correspond to the first through hole TSV1 and may be electrically connected to a connection line provided in the first through hole TSV1. Each of the sub-pixels SP1, SP2, and SP3 may receive a data signal from the data line DL of the data driver 700 connected to the driving unit 100 through the first through hole TSV1.

[0074] The second through hole TSV2 and the third through hole TSV3 may be respectively arranged in the non-display area NA on both sides of the display area DAA in the first direction DR1. For example, the second through hole TSV2 may be arranged in the second through hole area TSA2 positioned to the left side of the display area DAA, and the third through hole TSV3 may be arranged in the third through hole area TSA3 positioned to the right side of the display area DAA. The second through hole TSV2 may be arranged to correspond to the plurality of first scan lines GL1 respectively arranged in the display area DAA, and the third through hole TSV3 may be arranged to correspond to the plurality of second scan lines GL2 respectively arranged in the display area DAA. The number of the second through holes TSV2 may be the same as the number of the first scan lines GL1, and the number of the third through holes TSV3 may be the same as the number of the second scan lines GL2. In Figure 4, it is shown that one first scan line GL1 and one second scan line GL2 are connected to each of the sub-pixels SP1, SP2, and SP3. However, as will be referred to later Figure 5 As described, the sub-pixels SP1, SP2, and SP3 may each be connected to three first scan lines (eg, Figure 5 The first to third scan lines GWL, GCL and GBL) and two second scan lines (eg, Figure 5 Therefore, the number of the second through holes TSV2 may be equal to three times the number of pixel rows of the plurality of sub-pixels SP1, SP2, and SP3 provided in the display area DAA, and the number of the third through holes TSV3 may be equal to twice the number of pixel rows of the plurality of sub-pixels SP1, SP2, and SP3 provided in the display area DAA.

[0075] Each of the plurality of first scan lines GL1 may correspond to the second through-hole TSV2 and may be electrically connected to the connection line provided in the second through-hole TSV2. Each of the sub-pixels SP1, SP2, and SP3 may receive a scan signal from the first scan line GL1 connected to the scan driver 610 of the driving unit 100 through the second through-hole TSV2. Each of the plurality of second scan lines GL2 may correspond to the third through-hole TSV3 and may be electrically connected to the connection line provided in the third through-hole TSV3. Each of the sub-pixels SP1, SP2, and SP3 may receive an emission control signal from the second scan line GL2 connected to the emission driver 620 of the driving unit 100 through the third through-hole TSV3.

[0076] The fourth through hole TSV4 may be provided in the fourth through hole area TSA4 of the non-display area NA. The fourth through hole area TSA4 may be provided between the pad area PDA and the display area DAA. The fourth through hole TSV4 may be a connection path for electrically connecting the signal terminal STD of the driving unit 100 to the signal connection line of the circuit board 300. A plurality of fourth through holes TSV4 may be formed to correspond to the signal terminals STD of the driving unit 100, respectively. In one or more embodiments, the number of the fourth through holes TSV4 may be equal to the number of the signal terminals STD, and the fourth through holes TSV4 may be formed to overlap with the signal terminals STD, respectively. However, the present disclosure is not limited thereto. The circuit board 300 may be electrically connected to the signal terminal STD of the driving unit 100 via a plurality of pads PD and the signal connection line provided in the fourth through hole TSV4.

[0077] The pad area PDA may be provided on the lower side of the display area DAA, which is the side in the second direction DR2. A plurality of pads PD arranged along the first direction DR1 may be provided in the pad area PDA. The circuit board 300 may be attached to the plurality of pads PD. The pads PD may be electrically connected to the circuit board 300 and may be used to transmit electrical signals applied from the circuit board 300 to the driving unit 100.

[0078] Figure 5 is a block diagram illustrating a display device according to one or more embodiments.

[0079] Reference Figure 5 The driving circuit 400 may include a timing control circuit or a timing controller 410. In addition, the driving circuit 400 may also include various circuits related to driving the display device 10, such as a gamma circuit and a logic circuit. The driving circuit 400 may include driving circuit transistors formed on the first single crystal semiconductor substrate 110.

[0080] The driving circuit 400, including the timing controller 410, can receive digital video data DATA and timing signals from the outside. The timing control circuit 410 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display unit 200 based on the timing signals. The timing control circuit 410 can output the scan timing control signal SCS to the scan driver 610 of the gate driver 600, and can output the emission timing control signal ECS to the emission driver 620 of the gate driver 600. The timing control circuit 410 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0081] The power supply unit (eg, power supply or power supply circuit) 800 may generate a plurality of panel driving voltages from an external power supply voltage. For example, the power supply unit 800 may generate a first driving voltage VSS, a second driving voltage VDD, a reference voltage VREF, and an initialization voltage VINT, and supply them to a plurality of pixels PX.

[0082] The scanning timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the driving circuit 400 can be supplied to the plurality of pixels PX. The first driving voltage VSS, the second driving voltage VDD, the reference voltage VREF, and the initialization voltage VINT of the power supply unit 800 can also be supplied to the plurality of pixels PX.

[0083] The gate drivers 600, 610, and 620 may include a scan driver 610 and an emission driver 620. The scan driver 610 may include a plurality of scan transistors formed on a first single crystal semiconductor substrate 110, and the emission driver 620 may include a plurality of emission transistors formed on the first single crystal semiconductor substrate 110. The plurality of scan transistors and the plurality of emission transistors may be formed using a semiconductor process. For example, the plurality of scan transistors and the plurality of emission transistors may be formed as CMOS transistors.

[0084] The scan driver 610 may include a first scan signal output unit 611, a second scan signal output unit 612, and a third scan signal output unit 613. Each of the first scan signal output unit 611, the second scan signal output unit 612, and the third scan signal output unit 613 may receive a scan timing control signal SCS from the driver circuit 400. The first scan signal output unit 611 may generate write scan signals in response to the scan timing control signal SCS from the driver circuit 400 and sequentially output them to the first scan lines GWL. The second scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and sequentially output them to the second scan lines GCL. The third scan signal output unit 613 may generate bias scan signals in response to the scan timing control signal SCS and sequentially output them to the third scan lines GBL.

[0085] The emission driver 620 may include a first emission signal output unit 621 and a second emission signal output unit 622. Each of the first emission signal output unit 621 and the second emission signal output unit 622 may receive an emission timing control signal ECS from the driving circuit 400. The emission driver 620 may generate emission control signals based on the emission timing control signal ECS and sequentially output them to the first emission control line EL1 and the second emission control line EL2.

[0086] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the driving circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0087] Figure 6 is an equivalent circuit diagram of a pixel according to one or more embodiments.

[0088] Reference Figure 6Pixel circuits PXC (e.g., 220) of subpixels SP1, SP2, and SP3 can be connected to first scan line GWL, second scan line GCL, third scan line GBL, first emission control line EL1, second emission control line EL2, and data line DL. Furthermore, pixel circuit PXC can be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage VINT is applied. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In this case, the first drive voltage VSS can be lower than the third drive voltage VINT. The second drive voltage VDD can be higher than the third drive voltage VINT.

[0089] The pixel circuit PXC of the sub-pixels SP1 , SP2 , and SP3 includes a plurality of transistors T1 to T6 , a light emitting element LE, a first capacitor C1 , and a second capacitor C2 .

[0090] The light-emitting element LE emits light in response to a drive current Ids flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE may be proportional to the drive current Ids. The light-emitting element LE may be disposed between the fourth transistor T4 and the first drive voltage line VSL. A first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and a second electrode of the light-emitting element LE may be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be, but is not limited to, an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0091] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (also referred to herein as a "driving current Ids") flowing between its source and drain electrodes according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0092] The second transistor T2 can be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the first scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Therefore, a data voltage from the data line DL can be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the first scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0093] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a write control signal from the second scan line GCL to connect the first node N1 to the second node N2. For this reason, because the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode (e.g., the first transistor T1 may be diode-connected). The third transistor T3 includes a gate electrode connected to the second scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0094] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Thus, the driving current Ids of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0095] The fifth transistor T5 can be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the third scan line GBL to connect the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the third scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0096] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0097] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0098] The second capacitor C2 is formed between the gate electrode of the first transistor T1 (eg, the first node N1) and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 (eg, the first node N1) and the other electrode connected to the second driving voltage line VDL.

[0099] The first node N1 is a junction point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a junction point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0100] Each of the first to sixth transistors T1 to T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but is not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs, and the remaining transistors may each be an N-type MOSFET.

[0101] Although Figure 6 The pixel circuit PXC of the sub-pixels SP1, SP2, and SP3 is shown to include six transistors T1 to T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the sub-pixel SP is not limited to Figure 6 For example, the number of transistors and the number of capacitors of the pixel circuit PXC are not limited to Figure 6The example shown in .

[0102] Figure 7 is a schematic cross-sectional view of a display device according to one or more embodiments. Figure 8 is a schematic diagram illustrating a rear surface of a display device according to one or more embodiments. Figure 7 Schematic connection relationships of routing lines RM1 , RM2 , RM3 , and RM4 that electrically connect the display portion 200 to the driving portion 100 are shown. Figure 8 The arrangement of through-vias TSV1 , TSV2 , TSV3 , and TSV4 and routing lines RDL, GCL1 , GCL2 , and SCL viewed from the rear of the display device 10 is shown.

[0103] Combine Figure 4 Reference Figure 7 and Figure 8 The display device 10 according to one or more embodiments may include a driving portion 100 including a first single crystal semiconductor substrate 110 and a driving circuit layer 120 disposed on the first single crystal semiconductor substrate 110; and a display portion 200 including a second single crystal semiconductor substrate 210 and a pixel circuit 220 and a display layer 230 disposed on the second single crystal semiconductor substrate 210. The display device 10 may include two different single crystal semiconductor substrates 110 and 210 stacked on each other in a third direction DR3, which is a thickness direction of the display device 10.

[0104] The driving portion 100 may include circuit elements necessary for light emission of the light-emitting element included in the display layer 230 of the display portion 200. As described above, the driving circuit layer 120 of the driving portion 100 may include a driving circuit 400, a gate driver 600, and a data driver 700, and circuit elements constituting them (such as transistors and capacitors) may be formed of CMOS on the first single crystal semiconductor substrate 110.

[0105] The display section 200 may include a plurality of light emitting elements that emit light to display an image of the display device 10. The light emitting elements may be electrically connected to circuit elements formed in the driving section 100 to emit light. In addition, the display section 200 may include a pixel circuit 220 in which circuit elements constituting a pixel circuit PXC electrically connected to each of the sub-pixels SP1, SP2, and SP3 are provided. The pixel circuit 220 may include circuit elements constituting the pixel circuit PXC (e.g., Figure 6 The pixel circuit 220 may further include a plurality of terminals DTD, GTD1, GTD2, and PTD connected to through holes TSV1, TSV2, TSV3, and TSV4 provided in the non-display area NA of the display portion 200 (see FIG. Figures 12 to 14 ).

[0106] According to one or more embodiments, in the display device 10, in a plan view, the area of ​​the driving portion 100 or the first single crystal semiconductor substrate 110 can be smaller than the area of ​​the display portion 200 or the second single crystal semiconductor substrate 210. The plurality of transistors formed in the driving portion 100 can be formed by a semiconductor microprocess and thus can have very small sizes or line widths. In the driving portion 100, since a large number of circuit elements can be provided at a high integration density, power consumption can be reduced due to the miniaturization of the elements.

[0107] In addition, because the driving unit 100 only includes circuit elements formed by CMOS on the first single crystal semiconductor substrate 110 and does not include light-emitting elements, the driving unit 100 only needs to ensure space therein for accommodating elements formed by microprocessing. Even if the first single crystal semiconductor substrate 110 has a smaller area than the second single crystal semiconductor substrate 210, it still functions, and a large number of driving units 100 can be manufactured on a single wafer substrate on which the process of forming the driving circuit layer 120 is performed, so that manufacturing yield can be improved. Specifically, because a high-cost semiconductor process is performed to manufacture the driving unit 100, this improvement in manufacturing yield of the driving unit 100 can lead to cost reduction. In addition, in the display unit 200, because a large number of light-emitting elements can be formed on the second single crystal semiconductor substrate 210 having a relatively large area, a high-resolution display device 10 can be realized.

[0108] The display device 10 may include a connection line layer 500 disposed between the second single crystal semiconductor substrate 210 of the display portion 200 and the driving circuit layer 120 of the driving portion 100. The connection line layer 500 may be disposed on the bottom surface of the second single crystal semiconductor substrate 210. Portions of a plurality of routing lines RM1, RM2, RM3, and RM4 may be disposed in the connection line layer 500, and the routing lines RM1, RM2, RM3, and RM4 may connect the pixel circuits 220 and the circuit board 300 of the display portion 200 to the driving portion 100. The driving circuit layer 120 of the driving portion 100 may be electrically connected to the display portion 200 and the circuit board 300 through the routing lines RM1, RM2, RM3, and RM4 of the connection line layer 500 to transmit electrical signals for light emission.

[0109] The first routing line RM1 may be connected to the data line DL provided in the display unit 200 and the data driver 700 provided in the driving unit 100. The first routing line RM1 may be provided in the first through-hole TSV1 formed in the second single crystal semiconductor substrate 210 and may include a data routing line RDL of the connection line layer 500. A plurality of first through-holes TSV1 may be provided in the first through-hole area TSA1 of the non-display area NA of the display unit 200 and may not overlap with the driving unit 100 in the thickness direction (e.g., the third direction DR3). The first routing line RM1 may be partially provided in the first through-hole TSV1, and the data routing line RDL may be provided in the connection line layer 500 and may connect the first through-hole TSV1, which does not overlap with the driving unit 100, to the data driver 700.

[0110] The second routing line RM2 may be connected to the first scan line GL1 or the first to third scan lines GWL, GCL, and GBL provided in the display unit 200, and the scan driver 610 provided in the driver unit 100. The second routing line RM2 may be provided in a second through-hole TSV2 formed in the second single-crystalline semiconductor substrate 210 and may include the first scan routing line GCL1 of the connection line layer 500. A plurality of second through-holes TSV2 may be provided in the second through-hole area TSA2 of the non-display area NA of the display unit 200 and may not overlap with the driver unit 100 in the thickness direction (e.g., the third direction DR3). The second routing line RM2 may be partially provided in the second through-hole TSV2, and the first scan routing line GCL1 may be provided in the connection line layer 500. The second through-hole TSV2, which does not overlap with the driver unit 100, may be connected to the scan driver 610.

[0111] The third routing line RM3 may be connected to the second scan line GL2 or the first and second emission control lines EL1 and EL2 provided in the display unit 200, and the emission driver 620 provided in the driving unit 100. The third routing line RM3 may be provided in a third through-hole TSV3 formed in the second single-crystal semiconductor substrate 210 and may include a second scan routing line GCL2 of the connection line layer 500. A plurality of third through-holes TSV3 may be provided in a third through-hole area TSA3 of the non-display area NA of the display unit 200 and may not overlap with the driving unit 100 in the thickness direction (e.g., the third direction DR3). The third routing line RM3 may be partially provided in the third through-hole TSV3, and the second scan routing line GCL2 may be provided in the connection line layer 500 and may connect the third through-hole TSV3, which does not overlap with the driving unit 100, to the emission driver 620.

[0112] According to one or more embodiments, the number of first through holes TSV1 may be equal to the number of pixel columns of the plurality of sub-pixels SP1, SP2, and SP3 arranged in the display area DAA. For example, the plurality of sub-pixels SP1, SP2, and SP3 may be arranged along the first direction DR1 and the second direction DR2 in the display area DAA, and when the number of pixel columns arranged along the first direction DR1 is 4000, the number of first through holes TSV1 may also be equal to 4000. The first through holes TSV1 may correspond one-to-one to the pixel columns of the sub-pixels SP1, SP2, and SP3 arranged along the first direction DR1, and may also correspond one-to-one to the plurality of data lines DL and first routing lines RM1 arranged along the first direction DR1. A data line DL arranged parallel to a pixel column may be connected to the data driver 700 via the first routing line RM1 arranged in one first through hole TSV1. The first routing lines RM1 and the first through holes TSV1 may both be provided in the same number as the plurality of pixel columns and the number of data lines DL.

[0113] On the other hand, the number of second through holes TSV2 and third through holes TSV3 can be greater than the number of pixel rows of the plurality of sub-pixels SP1, SP2, and SP3 provided in the display area DAA. As described above, because two or more scan lines GL1 and GL2 are provided in one sub-pixel SP1, SP2, and SP3, three second through holes TSV2 and two third through holes TSV3 can be provided to correspond to one pixel row. However, the plurality of second through holes TSV2 can correspond to the second path line RM2 and the plurality of first scan lines GL1 arranged along the second direction DR2 in a one-to-one manner, and the plurality of third through holes TSV3 can correspond to the third path line RM3 and the plurality of second scan lines GL2 arranged along the second direction DR2 in a one-to-one manner.

[0114] Multiple data lines DL can extend in the second direction DR2 and can be connected to the first through-hole TSV1 in parallel without bending, even in the non-display area NA. Multiple scan lines GL1 and GL2 can also extend in the first direction DR1 and can be connected to the second through-hole TSV2 and the third through-hole TSV3 in parallel without bending, even in the non-display area NA. The display device 10 can maintain a constant gap between the signal lines in the display area DAA and the non-display area NA of the display unit 200, and can omit the fan-out structure in which the signal lines bend and narrow in the non-display area NA. Similar to the gap between the signal lines, the gap between the first through-hole TSV1, the second through-hole TSV2, and the third through-hole TSV3 can also be constant. However, the routing lines (e.g., the data routing lines RDL and the scan routing lines GCL1 and GCL2) arranged on the rear surface of the display unit 200 can connect the display unit 200 to the small-area driving unit 100 starting from the edge of the display unit 200, so that the gap between them can decrease as they approach the driving unit 100.

[0115] The fourth routing line RM4 may be connected to the circuit board 300 via a pad PD provided in the display unit 200 and may be connected to the signal terminal STD of the driver unit 100. The fourth routing line RM4 may be provided in a fourth through-hole TSV4 formed in the second single crystal semiconductor substrate 210 and may include a signal routing line SCL of the connection line layer 500. A plurality of fourth through-holes TSV4 may be provided in the fourth through-hole area TSA4 of the non-display area NA of the display unit 200 and may not overlap with the driver unit 100 in the thickness direction (e.g., the third direction DR3). The fourth routing line RM4 may be partially provided in the fourth through-hole TSV4, and the signal routing line SCL may be provided in the connection line layer 500 and may connect the fourth through-hole TSV4 that does not overlap with the driver unit 100 to the signal terminal STD. The fourth routing line RM4 may be a wiring that transmits a signal applied from the circuit board 300 to the driver unit 100.

[0116] The routing lines RM1, RM2, RM3, and RM4 may include connection lines RML1, RML2, RML3, and RML4 provided in the connection line layer 500 (see FIG. Figure 12 、 Figure 13 and Figure 14 ) and conductive vias RVA1, RVA2, RVA3 and RVA4 provided in the through holes TSV1, TSV2, TSV3 and TSV4 of the second single crystal semiconductor substrate 210 (see Figures 12 to 14). The routing lines RM1, RM2, RM3, and RM4 are wirings that electrically connect layers disposed above and below the second single crystal semiconductor substrate 210, and the arrangement and design of the through holes formed in the second single crystal semiconductor substrate 210 may vary depending on the arrangement of the layers electrically connected to the routing lines RM1, RM2, RM3, and RM4.

[0117] Hereinafter, structures of the driving circuit layer 120 of the driving part 100 and the pixel circuit 220 and the display layer 230 of the display part 200 will be described in detail with reference to other drawings.

[0118] Figure 9 is a schematic cross-sectional view of a driving portion according to one or more embodiments.

[0119] Reference Figure 9 The driving part 100 may include a first single crystal semiconductor substrate 110 and a driving circuit layer 120 disposed on the first single crystal semiconductor substrate 110 . Figure 9 The cross-sectional structure of the data driver 700 among the circuit units provided in the driving part 100 is schematically shown.

[0120] The first single crystal semiconductor substrate 110 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The first single crystal semiconductor substrate 110 may be a substrate doped with first-type impurities. A plurality of well regions WA may be provided on the top surface of the first single crystal semiconductor substrate 110. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the aforementioned first-type impurities. For example, when the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. Alternatively, when the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0121] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the first transistor PTR1 , a drain region DA corresponding to a drain electrode of the first transistor PTR1 , and a channel region CH disposed between the source region SA and the drain region DA.

[0122] The lower insulating film BINS may be provided between the gate electrode GE of the first transistor PTR1 and the well area WA. The side insulating film SINS may be provided on the side surface of the gate electrode GE. The side insulating film SINS may be provided on the lower insulating film BINS.

[0123] Each of the source region SA and the drain region DA may be a region doped with first-type impurities. The gate electrode GE of the first transistor PTR1 may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be provided on one side of the gate electrode GE, and the drain region DA may be provided on the other side of the gate electrode GE.

[0124] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2 may increase the distance between the source region SA and the drain region DA. Therefore, the length of the channel region CH of each of the first transistors PTR1 may be increased, thereby preventing punch-through and hot carrier phenomena that may be caused by a short channel.

[0125] The first single crystal semiconductor substrate 110 may include a plurality of first transistors PTR1 constituting a plurality of circuit elements of the driving portion 100. The first transistors PTR1 formed on the first single crystal semiconductor substrate 110 may constitute the driving circuit 400 or the data driver 700.

[0126] When the driving circuit layer 120 is formed on the silicon wafer substrate, a process may be performed to reduce the thickness of the first single crystal semiconductor substrate 110. The first single crystal semiconductor substrate 110 may have a thickness smaller than that of the wafer substrate on which the semiconductor process for forming the driving circuit layer 120 is performed. In one or more embodiments, the thickness of the first single crystal semiconductor substrate 110 may be 100 μm or less, for example, in the range of 80 μm to 100 μm.

[0127] The driving circuit layer 120 may include a first semiconductor insulating layer SINS1, a second semiconductor insulating layer SINS2, a plurality of contact electrodes CTE, a first interlayer insulating layer INS1, a second interlayer insulating layer INS2, a plurality of conductive layers ML1 to ML8, and a plurality of vias VA1 to VA8. The driving circuit layer 120 may include wiring electrically connected to the plurality of first transistors PTR1 included in the first single crystal semiconductor substrate 110.

[0128] The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be provided on the first single crystal semiconductor substrate 110. The first semiconductor insulating layer SINS1 may be an insulating layer provided on the first single crystal semiconductor substrate 110 and the gate electrode GE of the first transistor PTR1, and the second semiconductor insulating layer SINS2 may be an insulating layer provided on the gate electrode GE of the first transistor PTR1 and the first semiconductor insulating layer SINS1. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be made of silicon carbon nitride (SiCN) and / or silicon oxide (SiOx ) type inorganic film, but is not limited thereto. In the drawings, the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 are each shown as an example of a single layer having a suitable thickness (e.g., a predetermined thickness), but are not limited thereto. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may have a structure in which one or more layers are stacked on top of each other.

[0129] A plurality of contact electrodes (CTEs) may be disposed on the first single crystalline semiconductor substrate 110. The plurality of contact electrodes (CTEs) may be connected to one of the gate electrode GE, source region SA, and drain region DA of each first transistor (PTR1) formed on the first single crystalline semiconductor substrate 110 via holes penetrating the semiconductor insulating layers (SINS1 and SINS2). The plurality of contact electrodes (CTEs) may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more of these. Top surfaces of the plurality of contact electrodes (CTEs) may be exposed and not covered by the semiconductor insulating layers (SINS1 and SINS2).

[0130] The first interlayer insulating layer INS1 may be provided on the plurality of contact electrodes CTE and the semiconductor insulating layers SINS1 and SINS2. The second interlayer insulating layer INS2 may be provided on the first interlayer insulating layer INS1. Each of the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may be made of silicon carbon nitride (SiCN) and / or silicon oxide (SiO x ) type inorganic film, but is not limited thereto. Although the drawings illustrate that each of the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 is formed as a single layer, the present disclosure is not limited thereto. Each of the first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may have a structure in which one or more layers are stacked on top of each other, and may be provided between a plurality of first to eighth conductive layers ML1 to ML8, which will be described later.

[0131] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be electrically connected to the plurality of contact electrodes CTE to form the driving circuit 400 or the data driver 700 of the driving part 100. The plurality of first transistors PTR1 formed on the first single crystal semiconductor substrate 110 may be electrically connected to each other through the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8, and may form the driving circuit 400 and the data driver 700 of the driving part 100.

[0132] The first conductive layer ML1 may be connected to the contact electrode CTE through a first via VA1. The first conductive layer ML1 may be disposed on the contact electrode CTE, and the first via VA1 may be disposed between the first conductive layer ML1 and the contact electrode CTE to contact both. The second conductive layer ML2 may be connected to the first conductive layer ML1 through a second via VA2. The second conductive layer ML2 may be disposed on the first conductive layer ML1, and the second via VA2 may be disposed between the first conductive layer ML1 and the second conductive layer ML2 to contact both.

[0133] The third conductive layer ML3 can be connected to the second conductive layer ML2 through a third via VA3. The fourth conductive layer ML4 can be connected to the third conductive layer ML3 through a fourth via VA4, the fifth conductive layer ML5 can be connected to the fourth conductive layer ML4 through a fifth via VA5, and the sixth conductive layer ML6 can be connected to the fifth conductive layer ML5 through a sixth via VA6. The third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be sequentially disposed on the second conductive layer ML2, and the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be disposed therebetween. The third to sixth vias VA3 to VA6 can contact different metal layers disposed above and below them, respectively. A seventh via VA7 can be disposed on the sixth conductive layer ML6. The seventh via VA7 can contact the seventh conductive layer ML7 disposed thereon and the sixth conductive layer ML6 disposed therebelow.

[0134] The first to sixth conductive layers ML1 to ML6 and the first to seventh via holes VA1 to VA7 may be provided in the first interlayer insulating layer INS1. The first to sixth conductive layers ML1 to ML6 and the first to seventh via holes VA1 to VA7 may constitute a first driving circuit layer provided in the first interlayer insulating layer INS1 of the driving circuit layer 120.

[0135] The seventh conductive layer ML7 may be connected to the sixth conductive layer ML6 through a seventh via VA7. The seventh conductive layer ML7 may be disposed on the first interlayer insulating layer INS1 and the sixth conductive layer ML6, and the seventh via VA7 may be disposed between the sixth conductive layer ML6 and the seventh conductive layer ML7 to contact both of them. The eighth conductive layer ML8 may be connected to the seventh conductive layer ML7 through an eighth via VA8. The eighth conductive layer ML8 is disposed on the seventh conductive layer ML7, and the eighth via VA8 may be disposed between the seventh conductive layer ML7 and the eighth conductive layer ML8 to contact both of them. The top surface of the eighth conductive layer ML8 may be exposed without being covered by the second interlayer insulating layer INS2 and may be electrically connected to a routing line RM disposed in the display portion 200.

[0136] The seventh conductive layer ML7, the eighth via hole VA8, and the eighth conductive layer ML8 may be disposed in the second interlayer insulating layer INS2. The seventh conductive layer ML7, the eighth via hole VA8, and the eighth conductive layer ML8 may constitute a second driving circuit layer disposed in the second interlayer insulating layer INS2 of the driving circuit layer 120.

[0137] In the drawings, although the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are shown as being sequentially stacked on top of each other, their layout and connection can be modified in various ways according to the circuits of the driving circuit 400 and the data driver 700 of the driving unit 100. The connection structure shown in the drawings is merely an example, and the connection of the driving circuit layer 120 provided in the driving unit 100 of the display device 10 is not limited thereto. In addition, the driving circuit layer 120 may not necessarily include the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8, and some of these layers may be omitted or more layers may be provided.

[0138] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of substantially the same material. For example, the first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof.

[0139] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be respectively greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately 1360Å; the thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be approximately 1440Å; and the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 may be approximately 1150Å.

[0140] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately 9000 Å. The thickness of each of the seventh via VA7 and the eighth via VA8 may be approximately 6000 Å.

[0141] Figure 10 is a plan view illustrating a pixel defining film disposed in a display region of a display portion, and first electrodes and emission regions of a plurality of sub-pixels according to one or more embodiments.

[0142] Reference Figure 10 Each of the plurality of pixels PX may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. The first to third subpixels SP1, SP2, and SP3 may include emission areas EA1, EA2, and EA3, respectively. For example, the first subpixel SP1 may include a first emission area EA1, the second subpixel SP2 may include a second emission area EA2, and the third subpixel SP3 may include a third emission area EA3.

[0143] In a plan view, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a quadrilateral shape such as a rectangle, a square, and / or a diamond. For example, in a plan view, the third emission area EA3 may have a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2. In addition, in a plan view, each of the second emission area EA2 and the first emission area EA1 may have a rectangular shape having long sides in the first direction DR1 and short sides in the second direction DR2.

[0144] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be a region defined by the pixel defining film PDL. For example, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be a region defined by the first pixel defining film PDL1.

[0145] The length of the third emission area EA3 in the first direction DR1 may be smaller than the length of the first emission area EA1 in the first direction DR1 and may be smaller than the length of the second emission area EA2 in the first direction DR1. The length of the first emission area EA1 in the first direction DR1 and the length of the second emission area EA2 in the first direction DR1 may be substantially the same.

[0146] In each of the plurality of pixels PX, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the second direction DR2. Furthermore, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. Furthermore, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first direction DR1. The areas of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be different.

[0147] Although the drawings illustrate that each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 has a rectangular shape in a plan view, the present disclosure is not limited thereto. For example, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than a quadrilateral shape, a circular shape, and / or an elliptical shape in a plan view.

[0148] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the first color light may be light in a red wavelength band, the second color light may be light in a green wavelength band, and the third color light may be light in a blue wavelength band. For example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 370 nm to approximately 460 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 480 nm to approximately 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 600 nm to approximately 750 nm.

[0149] The first electrode AND of the light emitting element (for example, see Figure 12) may have a rectangular shape in a plan view. The planar shapes of the first electrodes AND of the light-emitting elements may differ in the first, second, and third subpixels SP1, SP2, and SP3. For example, the first electrode AND of the first subpixel SP1 and the first electrode AND of the second subpixel SP2 may have a rectangular planar shape having a long side in the first direction DR1 and a short side in the second direction DR2. In a plan view, the first electrode AND of the third subpixel SP3 may have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2. The length of the first electrode AND of the third subpixel SP3 in the first direction DR1 may be shorter than the length of the first electrode AND of each of the first and second subpixels SP1 and SP2 in the first direction DR1. The length of the first electrode AND of the first subpixel SP1 in the second direction DR2 may be greater than the length of the first electrode AND of the second subpixel SP2 in the second direction DR2.

[0150] The first electrode AND of the light emitting element can be connected to the electrode via hole VAP (for example, see Figure 12 ) is connected to the reflective electrode layer RL (see, for example, Figure 12 The electrode via VAP may overlap the first pixel defining film PDL1 , the second pixel defining film PDL2 , and the third pixel defining film PDL3 in the third direction DR3 .

[0151] At least one trench TRC may be used to cut off the light emitting stack IL between the adjacent emission areas EA1, EA2, and EA3 (eg, see FIG. 1 ). Figure 12 ) structure of at least one charge generation layer. At least one trench TRC may be provided between the first emission area EA1 and the second emission area EA2, between the first emission area EA1 and the third emission area EA3, and between the second emission area EA2 and the third emission area EA3. More specifically, at least one trench TRC may be provided between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the second sub-pixel SP2, between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the third sub-pixel SP3, and between the first electrode AND of the second sub-pixel SP2 and the first electrode AND of the third sub-pixel SP3.

[0152] Figure 11 is a plan view illustrating a pixel defining film disposed in a display region of a display portion, and first electrodes and emission regions of a plurality of sub-pixels according to one or more embodiments.

[0153] Reference Figure 11 , except that the plane shapes of the first emission area EA1, the second emission area EA2 and the third emission area EA3 are the same as Figure 10In addition to the different planar shapes of the embodiments, Figure 11 Examples and Figure 10 The embodiments are basically the same, and the Figure 10 The description of the embodiment is repeated.

[0154] The first, second, and third emission areas EA1, EA2, and EA3 may be arranged in a hexagonal structure having a hexagonal shape in a plan view. In this case, the first and second emission areas EA1, EA2 may be adjacent to each other in the first direction DR1, but the second and third emission areas EA2, EA3 may be adjacent to each other in the first oblique direction DD1, and the first and third emission areas EA1, EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first and second directions DR1 and DR2 and may be a direction inclined 45 degrees relative to the first and second directions DR1 and DR2, and the second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0155] Although Figure 10 and Figure 11 , each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four emission areas.

[0156] In addition, the layout of the emission regions of the plurality of pixels PX is not limited to the layout shown in the drawings. For example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure, a PENTILE ® Structure and / or hexagonal structure, in the stripe structure, the emission area is arranged along the first direction DR1, in the PENTILE ® In the PENTILE structure, the emission areas are arranged in a diamond shape, and in the hexagonal structure, the emission areas having a hexagonal shape in plan view are arranged side by side. ® The pixel arrangement structure may be referred to as an RGBG matrix structure (eg, PENTILE ® Matrix structure or RGBG structure (for example, PENTILE ® structure)). PENTILE ® is a registered trademark of Samsung Display Co., Ltd. of South Korea.

[0157] Figures 12 to 14 is a cross-sectional view illustrating a portion of a display area and a portion of a non-display area in a display portion according to one or more embodiments. Figures 12 to 14 Disclosed are schematic cross-sectional structures of the display area DAA, the non-display area NA, and the pad area PDA.

[0158] Reference Figures 12 to 14 The display portion 200 may include a semiconductor backplane SBP, a pixel circuit backplane EBP, a display element layer EML, an encapsulation layer TFE, an adhesive layer ADL, a color filter layer CFL, a lens LNS, and a cover layer DCL. The semiconductor backplane SBP and the pixel circuit backplane EBP of the display portion 200 may constitute the pixel circuit 220. The display element layer EML, the encapsulation layer TFE, the adhesive layer ADL, the optical layer OPL including the color filter layer CFL, the lens LNS, and the filler layer FIL of the display portion 200, and the cover layer DCL may constitute the display layer 230. In one or more embodiments, the display portion 200 may further include a polarizing plate disposed on the cover layer DCL. The connecting line layer 500 may be disposed between the first single crystal semiconductor substrate 110 and the second single crystal semiconductor substrate 210 of the semiconductor backplane SBP. Alternatively, the connecting line layer 500 may be disposed between the display element layer EML and the first single crystal semiconductor substrate 110.

[0159] The semiconductor backplane SBP includes a second single crystal semiconductor substrate 210 including a plurality of second transistors PTR2, a plurality of semiconductor insulating films disposed on the plurality of second transistors PTR2, and a plurality of contact electrodes CTE electrically connected to the plurality of second transistors PTR2. The plurality of second transistors PTR2 may be a plurality of Figure 6 The first to sixth transistors T1 to T6 of the pixel circuit 220 may be scanning transistors of the gate driver 600 .

[0160] The second single crystal semiconductor substrate 210 may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The second single crystal semiconductor substrate 210 may be a substrate doped with impurities. A plurality of well regions WA may be provided on the top surface of the second single crystal semiconductor substrate 210. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the first-type impurities described above. For example, when the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. Alternatively, when the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0161] The second single crystalline semiconductor substrate 210 may include a plurality of second transistors PTR2 similar to the first single crystalline semiconductor substrate 110. The structure of the second transistors PTR2 may be the same as that of the first transistors PTR1, and thus, a detailed description thereof will be omitted.

[0162] In the display device 10, a wafer substrate on which the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 of the driving unit 100 is formed and a wafer substrate on which the second transistor PTR2 formed on the second single crystal semiconductor substrate 210 of the display unit 200 is formed may be different. According to one or more embodiments, in the display device 10, the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 and the second transistor PTR2 formed on the second single crystal semiconductor substrate 210 may have different sizes and / or line widths, etc.

[0163] For example, in the display device 10, the minimum line width of the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 can be smaller than the minimum line width of the second transistor PTR2 formed on the second single crystal semiconductor substrate 210. The semiconductor process performed on the first wafer substrate for forming the first transistor PTR1 is a process with higher resolution than the semiconductor process performed on the second wafer substrate for forming the second transistor PTR2, and thus the size of the element such as the manufactured transistor can be smaller. In other words, the semiconductor process performed on the first wafer substrate can be a finer process than the semiconductor process performed on the second wafer substrate.

[0164] As described above, the first single crystal semiconductor substrate 110 of the driver unit 100 can have a smaller area in plan view than the second single crystal semiconductor substrate 210 of the display unit 200, and small-sized elements can be arranged with a high integration density to reduce power consumption and improve manufacturing yield. On the other hand, the second single crystal semiconductor substrate 210 of the display unit 200 can have a larger area in plan view than the first single crystal semiconductor substrate 110, and processes with relatively large line widths can be performed. The second transistor PTR2 disposed in the second single crystal semiconductor substrate 210 can be formed in a larger area than when formed in the first single crystal semiconductor substrate 110, and the second transistor PTR2 constituting the pixel circuit can be formed without a high integration density. Therefore, the semiconductor process performed on the first wafer substrate can be performed as a high-cost process with a small line width, and the semiconductor process performed on the second wafer substrate can be performed as a low-cost process with a relatively large line width.

[0165] In one or more embodiments, the lengths of the channel regions CH of the plurality of transistors PTR1 and PTR2 may be different from each other, and the minimum line width or length of the channel region CH of the first transistor PTR1 may be smaller than the minimum line width or length of the channel region CH of the second transistor PTR2. The minimum line width or length of the channel region CH of the first transistor PTR1 may be equal to or less than 100 nm, or may be within a range of 2 nm to 80 nm. The minimum line width or length of the channel region CH of the second transistor PTR2 may be greater than or equal to 100 nm, or may be within a range of 100 nm to 5 μm.

[0166] The second single crystal semiconductor substrate 210 may include a plurality of through-holes TSV1, TSV2, TSV3, and TSV4 spaced apart from one another (e.g., separated). The through-holes TSV1, TSV2, TSV3, and TSV4 may penetrate from the top surface to the bottom surface of the second single crystal semiconductor substrate 210 and may also penetrate the plurality of semiconductor insulation layers SINS3 and SINS4 and interlayer insulation layers INS3, INS4, and INS5 disposed on the second single crystal semiconductor substrate 210. Conductive vias RVA1, RVA2, RVA3, and RVA4 of the routing lines RM1, RM2, RM3, and RM4 may be disposed in the through-holes TSV1, TSV2, TSV3, and TSV4. The through-holes TSV1, TSV2, TSV3, and TSV4 may form connection paths for the routing lines RM1, RM2, RM3, and RM4 that electrically connect the driving unit 100 to the terminals DTD, GTD1, GTD2, and PTD of the display unit 200. In one or more embodiments, the through-holes TSV1, TSV2, TSV3, and TSV4 of the second single-crystalline semiconductor substrate 210 may be formed by a through-silicon via (TSV) process in which a hole is formed through a wafer substrate. Through the through-holes TSV1, TSV2, TSV3, and TSV4 formed in the second single-crystalline semiconductor substrate 210, the display layer 230 and the driving unit 100 may be electrically connected to each other through the routing lines RM1, RM2, RM3, and RM4 without requiring additional wiring.

[0167] The process of reducing the thickness of the second single crystal semiconductor substrate 210 may be performed after the driver 100 is bonded to the silicon wafer substrate. The second single crystal semiconductor substrate 210 may have a thickness smaller than that of the wafer substrate on which the process for forming the conductive layer is performed. In one or more embodiments, the thickness of the second single crystal semiconductor substrate 210 may be 100 μm or less, for example, within a range of 80 μm to 100 μm.

[0168] The pixel circuit 220 may be provided on the second single crystalline semiconductor substrate 210. The pixel circuit 220 may include a pixel circuit back plate EBP and a semiconductor back plate SBP.

[0169] The third semiconductor insulating layer SINS3 may be provided on the second single crystal semiconductor substrate 210. The third semiconductor insulating layer SINS3 may be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO x ) type inorganic film formation, but not limited to this.

[0170] The fourth semiconductor insulating layer SINS4 may be provided on the third semiconductor insulating layer SINS3. The fourth semiconductor insulating layer SINS4 may be made of silicon oxide (SiO x ) type inorganic film formation, but not limited to this.

[0171] Each of the plurality of contact electrodes CTE may be connected to any one of the gate electrode GE, source area SA, and drain area DA of each of the second transistors PTR2 via a hole penetrating the third semiconductor insulating layer SINS3 and the fourth semiconductor insulating layer SINS4. The plurality of contact electrodes CTE may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof.

[0172] The pixel circuit backplane EBP may include third to seventh interlayer insulating layers INS3, INS4, INS5, INS6, and INS7, and a plurality of connection conductive layers RMT. The connection conductive layer RMT may include wiring electrically connected to a plurality of second transistors PTR2 formed on the second single crystal semiconductor substrate 210. The pixel circuit backplane EBP may include a plurality of scan lines GL1 and GL2, a data line DL, and a plurality of terminals DTD, GTD1, GTD2, and PTD provided in the display portion 200.

[0173] A third interlayer insulating layer INS3 may be provided on the plurality of contact electrodes CTE and the semiconductor insulating layers SINS3 and SINS4. A fourth interlayer insulating layer INS4 may be provided on the third interlayer insulating layer INS3. A fifth interlayer insulating layer INS5, a sixth interlayer insulating layer INS6, and a seventh interlayer insulating layer INS7 may be sequentially provided on the fourth interlayer insulating layer INS4. A plurality of connecting conductive layers RMT may be provided between the third interlayer insulating layer INS3 to the seventh interlayer insulating layer INS7. Each of the third interlayer insulating layer INS3 to the seventh interlayer insulating layer INS7 may be made of silicon carbon nitride (SiCN) and / or silicon oxide (SiO x) type inorganic film, but is not limited thereto. Although the drawings illustrate that each of the third to seventh interlayer insulating layers INS3 to INS7 is formed as a single layer, the present disclosure is not limited thereto. Each of the third to seventh interlayer insulating layers INS3 to INS7 may have a structure in which one or more layers are stacked on top of each other, and may be provided between the plurality of first to eighth conductive layers ML1 to ML8 as described above.

[0174] The connection conductive layer RMT may have a structure similar to the plurality of conductive layers ML1 to ML8 and the vias VA1 to VA8 of the driving circuit layer 120. The connection conductive layer RMT may include one or more conductive layers and vias provided therebetween to form terminals DTD, GTD1, GTD2, and PTD or wiring provided in the display portion 200. For example, the connection conductive layer RMT of the pixel circuit 220 provided in the display area DAA may be electrically connected to the second transistor PTR2. The connection conductive layer RMT shown in the drawings may be connected to the plurality of second transistors PTR2 to form Figure 6 The pixel circuit 220 of FIG. 220 may be configured as a pixel circuit 220. The connecting conductive layer RMT may be used as a connecting line connecting the second transistor PTR2 to other circuit elements. In addition, in one or more embodiments, some of the connecting conductive layers RMT provided in the display area DAA of the pixel circuit 220 may be scan lines GL1 and GL2 or data lines DL, or may be used as terminals DTD, GTD1, GTD2, and PTD.

[0175] The pixel circuit 220 may include a plurality of terminals DTD, GTD1, GTD2, and PTD disposed in the non-display area NA. The plurality of terminals DTD, GTD1, GTD2, and PTD may include a data terminal DTD electrically connected to the data line DL, gate terminals GTD1 and GTD2 connected to the scan lines GL1 and GL2, and a pad signal terminal PTD. The plurality of terminals DTD, GTD1, GTD2, and PTD may be connected to conductive vias RVA1, RVA2, RVA3, and RVA4 of the routing line RM in the through-hole areas TSA1, TSA2, TSA3, and TSA4 of the non-display area NA.

[0176] The connection line layer 500 may be disposed on the bottom surface of the second single crystal semiconductor substrate 210. The connection line layer 500 may include an interlayer insulating layer RINS and a plurality of connection lines RML1, RML2, RML3, and RML4.

[0177] An interlayer insulating layer RINS may be provided on the bottom surface of the second single crystal semiconductor substrate 210. The interlayer insulating layer RINS may be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO x) type inorganic film is formed, but is not limited thereto. In the drawings, the interlayer insulating layer RINS is shown as a single layer, but is not limited thereto and may have a structure in which one or more layers are stacked on top of each other, and they may be provided between the connection lines RML1, RML2, RML3, and RML4.

[0178] The connecting lines RML1, RML2, RML3, and RML4 may form routing lines RM1, RM2, RM3, and RM4 together with a plurality of conductive vias RVA1, RVA2, RVA3, and RVA4. The connecting lines RML1, RML2, RML3, and RML4 may include one or more conductive layers and one or more vias connecting them to each other. The connection and structure of the connecting lines RML1, RML2, RML3, and RML4 may be the same as described above for the conductive layers ML1 to ML8 and the vias VA1 to VA8. The connection lines RML1, RML2, RML3 and RML4 can be electrically connected to the terminals DTD, GTD1, GTD2 and PTD and the lines GL1, GL2 and DL set in the display part 200 through the conductive vias RVA1, RVA2, RVA3 and RVA4 set in the through holes TSV1, TSV2, TSV3 and TSV4 of the second single crystal semiconductor substrate 210, and can be electrically connected to the driving circuit layer 120 of the driving part 100.

[0179] According to one or more embodiments, the display portion 200 of the display device 10 may include a first through-hole TSV1, a second through-hole TSV2, a third through-hole TSV3, and a fourth through-hole TSV4 penetrating the second single crystal semiconductor substrate 210. The first through-holes TSV1, TSV2, TSV3, and TSV4 may all be disposed in the non-display area NA. As described above, the first through-hole TSV1 may be disposed in the first through-hole area TSA1 positioned to the upper side of the display area DAA, and the second through-hole TSV2 and the third through-hole TSV3 may be disposed in the second through-hole area TSA2 and the third through-hole area TSA3 positioned to the left and right sides of the display area DAA, respectively. The fourth through-hole TSV4 may be disposed in the fourth through-hole area TSA4 positioned between the display area DAA and the pad area PDA.

[0180] The first conductive via RVA1 of the first routing line RM1 may be provided in the first through hole TSV1. The first through hole TSV1 may penetrate the second single crystal semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3, INS4, and INS5 to extend from the bottom surface of the data terminal DTD to the bottom surface of the second single crystal semiconductor substrate 210. The first conductive via RVA1 may also be provided from the bottom surface of the data terminal DTD to the bottom surface of the second single crystal semiconductor substrate 210 to connect to each of the data terminal DTD and the first connection line RML1. The first connection line RML1 may be the one described above with reference to FIG. Figure 7 and Figure 8 The first routing line RM1 may connect the data terminal DTD connected to the data line DL to the driving circuit layer 120 of the driving part 100 or the data driver 700 .

[0181] The second conductive via RVA2 of the second routing line RM2 may be provided in the second through-hole TSV2. The second through-hole TSV2 may penetrate the second single crystal semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3, INS4, and INS5 to extend from the bottom surface of the first gate terminal GTD1 to the bottom surface of the second single crystal semiconductor substrate 210. The second conductive via RVA2 may also be provided from the bottom surface of the first gate terminal GTD1 to the bottom surface of the second single crystal semiconductor substrate 210 to be connected to each of the first gate terminal GTD1 and the second connection line RML2. The second connection line RML2 may be the one described above with reference to FIG. Figure 8 The second routing line RM2 may connect the first gate terminal GTD1 connected to the first scan line GL1 to the driving circuit layer 120 of the driving part 100 or the scan driver 610 .

[0182] The third conductive via RVA3 of the third routing line RM3 may be provided in the third through hole TSV3. The third through hole TSV3 may penetrate the second single crystal semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3, INS4, and INS5 to extend from the bottom surface of the second gate terminal GTD2 to the bottom surface of the second single crystal semiconductor substrate 210. The third conductive via RVA3 may also be provided from the bottom surface of the second gate terminal GTD2 to the bottom surface of the second single crystal semiconductor substrate 210 to connect to each of the second gate terminal GTD2 and the third connection line RML3. The third connection line RML3 may be the one described above with reference to FIG. Figure 8 The third routing line RM3 may connect the second gate terminal GTD2 connected to the second scan line GL2 to the driving circuit layer 120 of the driving part 100 or the emission driver 620 .

[0183] The fourth conductive via RVA4 of the fourth routing line RM4 may be provided in the fourth through hole TSV4. The fourth through hole TSV4 may penetrate the second single crystalline semiconductor substrate 210, the semiconductor insulating layers SINS3 and SINS4, and the interlayer insulating layers INS3, INS4, and INS5 to extend from the bottom surface of the pad signal terminal PTD to the bottom surface of the second single crystalline semiconductor substrate 210. The fourth conductive via RVA4 may also be provided from the bottom surface of the pad signal terminal PTD to the bottom surface of the second single crystalline semiconductor substrate 210 to connect to each of the pad signal terminal PTD and the fourth connection line RML4. The fourth connection line RML4 may be the above referenced Figure 8 The fourth routing wire RM4 may connect the pad signal terminal PTD electrically connected to the circuit board 300 to the signal terminal STD of the driving part 100 .

[0184] In the display device 10, the circuit elements provided in the driver unit 100 can be formed using a high-cost micro-semiconductor process and can therefore be formed with high integration density on the first single-crystal semiconductor substrate 110 having a small area. The manufacturing process of the driver unit 100 can achieve high yield per unit wafer substrate, and the circuit elements (e.g., the first transistor) can be small in size, thereby reducing power consumption. Furthermore, by providing wiring and pixel circuits for light emission from the light-emitting element in the display unit 200, the integration density of the first single-crystal semiconductor substrate 110 can be prevented from becoming excessively high. Furthermore, by optimizing the number of through-vias TSV1, TSV2, TSV3, and TSV4, which connect the routing lines RM1, RM2, RM3, and RM4, the space in which the through-vias TSV1, TSV2, TSV3, and TSV4 having (e.g., required) suitable diameters (e.g., predetermined diameters) and spacings are provided can be reduced or minimized.

[0185] The display layer 230 may be disposed on the second single crystal semiconductor substrate 210 and the pixel circuit 220. The display layer 230 may include a display element layer EML, an encapsulation layer TFE, an adhesive layer ADL, an optical layer OPL, and a cover layer DCL. The display layer 230 may include a light emitting element electrically connected to the driving unit 100 and emitting light.

[0186] The display element layer EML may be provided on the pixel circuit backplane EBP of the pixel circuit 220. The display element layer EML may include a light emitting element having a first electrode AND, a light emitting stack IL, and a second electrode CAT, a reflective electrode layer RL, an eighth interlayer insulating layer INS8 and a ninth interlayer insulating layer INS9, an electrode via VAP, a pixel defining film PDL, and a plurality of trenches TRC.

[0187] The reflective electrode layer RL may be disposed on the seventh interlayer insulating layer INS7. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. Figure 12 As shown in , the reflective electrode layer RL may include first to fourth reflective electrodes RL1 , RL2 , RL3 , and RL4 .

[0188] Each of the first reflective electrodes RL1 may be disposed on the seventh interlayer insulating layer INS7 and may be connected to a via hole penetrating the seventh interlayer insulating layer INS7. The first reflective electrodes RL1 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0189] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrodes RL2 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. For example, the second reflective electrodes RL2 may include aluminum (Al).

[0190] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrodes RL3 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. For example, the third reflective electrodes RL3 may include titanium nitride (TiN).

[0191] The fourth reflective electrode RL4 may be disposed on each of the third reflective electrodes RL3. The fourth reflective electrode RL4 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more of these. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0192] Because the second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately 100 Å, and the thickness of the second reflective electrode RL2 can be 850 Å. However, in one or more other embodiments, the thickness of the second reflective electrode RL2 can be the same as the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0193] The eighth interlayer insulating layer INS8 may be disposed on the seventh interlayer insulating layer INS7. The eighth interlayer insulating layer INS8 may be disposed between adjacent reflective electrode layers RL. The eighth interlayer insulating layer INS8 may be disposed on the reflective electrode layer RL in the first sub-pixel SP1. The eighth interlayer insulating layer INS8 may be made of silicon oxide (SiO x ) type inorganic film formation, but not limited to this.

[0194] The ninth interlayer insulating layer INS9 may be disposed on the eighth interlayer insulating layer INS8 and the reflective electrode layer RL. The ninth interlayer insulating layer INS9 may be made of silicon oxide (SiO x ) type inorganic film formation, but not limited to this.

[0195] In at least one of the first to third subpixels SP1 to SP3 , the eighth and ninth interlayer insulating layers INS8 and INS9 may not be disposed under the first electrode AND considering a resonance distance of light emitted from the light emitting element.

[0196] For example, the first electrode AND of the third subpixel SP3 may be directly disposed on the fourth reflective electrode RL4, and the first electrode AND of the third subpixel SP3 may not overlap the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9. The first electrode AND of the second subpixel SP2 may be disposed on the ninth interlayer insulating layer INS9, and the ninth interlayer insulating layer INS9 may be directly disposed on the fourth reflective electrode RL4. In other words, the first electrode AND of the second subpixel SP2 may not overlap the eighth interlayer insulating layer INS8. The first electrode AND of the first subpixel SP1 may be disposed on the ninth interlayer insulating layer INS9 and may overlap the eighth interlayer insulating layer INS8.

[0197] In one or more embodiments, the distance between the first electrode AND and the reflective electrode layer RL may be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the main wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9 may be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, Figure 12 In the embodiment of the present invention, the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3. However, the present disclosure is not limited thereto. The distance between the first electrode AND and the reflective electrode layer RL in each of the subpixels SP1, SP2, and SP3 can be modified and designed differently.

[0198] In addition, although the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9 are shown in the drawings, a tenth interlayer insulating layer may be further provided under the first electrode AND of the sub-pixel SP. In this case, the ninth interlayer insulating layer INS9 and the tenth interlayer insulating layer may be provided under the first electrode AND of the second sub-pixel SP2, and the eighth interlayer insulating layer INS8, the ninth interlayer insulating layer INS9, and the tenth interlayer insulating layer may be provided under the first electrode AND of the first sub-pixel SP1.

[0199] Each of the electrode vias VAP can be connected to the fourth reflective electrode RL4 exposed through the eighth interlayer insulating layer INS8 and / or the ninth interlayer insulating layer INS9 in the first and second subpixels SP1 and SP2. The electrode vias VAP can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. The thickness of the electrode via VAP in the second subpixel SP2 can be smaller than that of the electrode via VAP in the first subpixel SP1.

[0200] The first electrode AND of each light-emitting element is disposed on the ninth interlayer insulating layer INS9 or the reflective electrode layer RL and can be connected to an electrode via VAP. The first electrode AND of each light-emitting element can be connected to the second transistor PTR2 via the electrode via VAP, the first to fourth reflective electrodes RL1 to RL4, the connecting conductive layer RMT, and the contact electrode CTE. The first electrode AND of each light-emitting element can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more of these. For example, the first electrode AND of each light-emitting element can be titanium nitride (TiN).

[0201] The pixel definition film PDL may be disposed on a portion of the first electrode AND of each light emitting element. The pixel definition film PDL may cover the edge of the first electrode AND of each light emitting element. The pixel definition film PDL may be used to divide the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0202] The first emission area EA1 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0203] The pixel definition film PDL may include first to third pixel definition films PDL1, PDL2, and PDL3. The first pixel definition film PDL1 may be provided on the edge of the first electrode AND of each of the light emitting elements, the second pixel definition film PDL2 may be provided on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be provided on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be made of silicon oxide (SiO x The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may each have a thickness of about 500 Å.

[0204] When the first, second, and third pixel-defining layers PDL1, PDL2, and PDL3 are formed into one pixel-defining layer, the height of the one pixel-defining layer increases, which may cause the first inorganic encapsulation layer TFE1 to be cut due to step coverage. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the more likely the film will be cut at the inclined portion.

[0205] To prevent the first inorganic encapsulation layer TFE1 from being cut due to step coverage, the first, second, and third pixel defining layers (PDL1, PDL2, and PDL3) may have a cross-sectional structure with a stepped portion. For example, the width of the first pixel defining layer (PDL1) may be greater than the widths of the second and third pixel defining layers (PDL2 and PDL3), and the width of the second pixel defining layer (PDL2) may be greater than the width of the third pixel defining layer (PDL3). The width of the first pixel defining layer (PDL1) refers to the horizontal length of the first pixel defining layer (PDL1) defined in the first and second directions (DR1, DR2).

[0206] Each of the plurality of trenches TRC may penetrate the first to third pixel defining films PDL1 to PDL2 , and PDL3 , and a portion of the eighth interlayer insulating layer INS8 may be dug and the ninth interlayer insulating layer INS9 may be penetrated in each of the plurality of trenches TRC.

[0207] At least one trench TRC may be provided between adjacent sub-pixels SP1 , SP2 , and SP3 . Figures 12 to 14 It is shown that two trenches TRC are disposed between adjacent sub-pixels SP1 , SP2 , and SP3 , but the present disclosure is not limited thereto.

[0208] The light-emitting stack IL may include a plurality of stacks. The drawings illustrate a light-emitting stack IL having a triple-series structure including a first light-emitting stack IL1, a second light-emitting stack IL2, and a third light-emitting stack IL3, but the present disclosure is not limited thereto. For example, the light-emitting stack IL may have a dual-series structure including two light-emitting stacks.

[0209] In the triple-series structure, the light-emitting stack IL may have a series structure including a plurality of light-emitting stacks IL1, IL2, and IL3 that emit different lights. For example, the light-emitting stack IL may include a first light-emitting stack IL1 that emits light of a first color, a second light-emitting stack IL2 that emits light of a second color, and a third light-emitting stack IL3 that emits light of a third color. The first light-emitting stack IL1, the second light-emitting stack IL2, and the third light-emitting stack IL3 may be stacked sequentially.

[0210] The first light-emitting stack IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second light-emitting stack IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a second color, and a second electron transport layer are sequentially stacked. The third light-emitting stack IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a third color, and a third electron transport layer are sequentially stacked.

[0211] A first charge generation layer for supplying holes to the second light-emitting stack IL2 and electrons to the first light-emitting stack IL1 may be provided between the first light-emitting stack IL1 and the second light-emitting stack IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first light-emitting stack IL1 and a P-type charge generation layer for supplying holes to the second light-emitting stack IL2. The N-type charge generation layer may include a dopant of a metal material.

[0212] A second charge generation layer for supplying holes to the third light-emitting stack IL3 and electrons to the second light-emitting stack IL2 may be provided between the second light-emitting stack IL2 and the third light-emitting stack IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second light-emitting stack IL2 and a P-type charge generation layer for supplying holes to the third light-emitting stack IL3.

[0213] The first light-emitting stack IL1 may be disposed on the first electrode AND and the pixel-defining film PDL and may be disposed on the bottom surface of each trench TRC. Due to the trench TRC, the first light-emitting stack IL1 may be cut off between adjacent sub-pixels SP1, SP2, and SP3. The second light-emitting stack IL2 may be disposed on the first light-emitting stack IL1. Due to the trench TRC, the second light-emitting stack IL2 may be cut off between adjacent sub-pixels SP1, SP2, and SP3. A gap or empty space ESS may be disposed between the first light-emitting stack IL1 and the second light-emitting stack IL2. The third light-emitting stack IL3 may be disposed on the second light-emitting stack IL2. The third light-emitting stack IL3 is not cut off by the trench TRC and may be disposed so as to cover the second light-emitting stack IL2 in each trench TRC. That is, in the three-series structure, each of the multiple trenches TRC may be a structure for cutting off the first and second light-emitting stacks IL1 and IL2, and the first and second charge generation layers, of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. In addition, in the dual series structure, each of the plurality of trenches TRC may be a structure for cutting off the charge generation layer disposed between the lower light emitting stack and the upper light emitting stack.

[0214] In order to stably cut off the first light-emitting stack IL1 and the second light-emitting stack IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel-defining film PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel-defining film PDL refers to the length of the pixel-defining film PDL in the third direction DR3. In order to cut off the first to third light-emitting stacks IL1, IL2, and IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, another structure may be provided in place of the grooves TRC. For example, instead of the grooves TRC, an inverted tapered partition wall may be provided on the pixel-defining film PDL.

[0215] The number of light-emitting stacks IL1, IL2, and IL3 that emit different light is not limited to the number shown in the drawings. For example, the light-emitting stack IL may include two light-emitting stacks. In this case, one of the two light-emitting stacks may be substantially identical to the first light-emitting stack IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one light-emitting stack and holes to the other light-emitting stack may be provided between the two light-emitting stacks.

[0216] in addition, Figures 12 to 14 It is shown that the first to third light-emitting stacks IL1, IL2, and IL3 are all arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the present disclosure is not limited to this. For example, the first light-emitting stack IL1 can be arranged in the first emission area EA1, and may not be arranged in the second emission area EA2 and the third emission area EA3. In addition, the second light-emitting stack IL2 can be arranged in the second emission area EA2, and may not be arranged in the first emission area EA1 and the third emission area EA3. In addition, the third light-emitting stack IL3 can be arranged in the third emission area EA3, and may not be arranged in the first emission area EA1 and the second emission area EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0217] The second electrode CAT may be disposed on the third light-emitting stack IL3. The second electrode CAT may be disposed on the third light-emitting stack IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a light-transmitting transparent conductive material (TCO) such as ITO or IZO, or a semi-transmitting conductive material such as magnesium (Mg), silver (Ag), and / or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmitting conductive material, light emission efficiency may be improved in each of the first to third subpixels SP1, SP2, and SP3 due to a microcavity effect.

[0218] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic encapsulation layer TFE1 and TFE3 to prevent oxygen and / or moisture from penetrating into the display element layer EML. In addition, the encapsulation layer TFE may include at least one organic film to protect the display element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0219] The first inorganic encapsulation layer TFE1 may be disposed on the second electrode CAT, the organic encapsulation layer TFE2 may be disposed on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be formed by alternately stacking silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ) and aluminum oxide (AlO x The organic encapsulation layer TFE2 may be a monomer. Alternatively, the organic encapsulation layer TFE2 may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0220] The adhesive layer ADL may be provided on the encapsulation layer TFE. The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE to the layer provided thereon. The adhesive layer ADL may be a double-sided adhesive member. Alternatively, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0221] The optical layer OPL may include a color filter layer CFL, a plurality of lenses LNS, and a filling layer FIL. The color filter layer CFL may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be disposed on the adhesive layer ADL.

[0222] The first color filter CF1 may overlap the first emission area EA1. The first color filter CF1 may transmit light of the first color, that is, light of a red wavelength band. The red wavelength band may be approximately 600nm to 750nm. The first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0223] The second color filter CF2 may overlap the second emission area EA2. The second color filter CF2 may transmit light of the second color, i.e., light in the green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm. The second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0224] The third color filter CF3 may overlap the third emission area EA3. The third color filter CF3 may transmit light of a third color, i.e., light in a blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm. The third color filter CF3 may transmit light of the third color among the light emitted from the third emission area EA3.

[0225] A plurality of lenses LNS may be provided on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light guided to the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction.

[0226] A filling layer FIL may be provided on the plurality of lenses LNS. The filling layer FIL may have a suitable refractive index (e.g., a predetermined refractive index) such that light travels in the third direction DR3 at the interface between the filling layer FIL and the plurality of lenses LNS. Furthermore, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0227] The cover layer DCL can be disposed on the filler layer FIL. The cover layer DCL can be a glass substrate and / or a polymer resin. When the cover layer DCL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer DCL. When the cover layer DCL is a glass substrate, it can serve as an encapsulation substrate. When the cover layer DCL is a polymer resin, it can be applied directly to the filler layer FIL.

[0228] In one or more embodiments, the display portion 200 may further include a polarizing plate disposed on the cover layer DCL. The polarizing plate may be disposed on one surface of the cover layer DCL. The polarizing plate may be a structure for preventing visibility degradation caused by reflection of external light. The polarizing plate may include a linear polarizing plate and a phase retarder film. For example, the phase retarder film may be a λ / 4 plate (quarter-wave plate), but is not limited thereto. However, if visibility degradation caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3, the polarizing plate may be omitted.

[0229] Figure 15 is a diagram illustrating relative arrangement of pixels and through-holes provided in a display portion of a display device according to one or more embodiments.

[0230] Reference Figure 15 , each pixel PX of the display unit 200 may include three sub-pixel sections PXS corresponding to the corresponding sub-pixels SP1, SP2 and SP3. The sub-pixel section PXS may be one of the three evenly divided areas from one pixel PX. The sub-pixel section PXS may be an area allocated to each of the sub-pixels SP1, SP2 and SP3 included in one pixel PX, but may not be the same as the sub-pixels SP1, SP2 and SP3. As described above, in the display unit 200, the shape and arrangement of the sub-pixels SP1, SP2 and SP3 or the emission areas EA1, EA2 and EA3 may vary according to the arrangement and shape of the first electrode AND of the light-emitting element or the trench TRC of the pixel defining film PDL in a plan view. The shape and arrangement of the sub-pixels SP1, SP2 and SP3 may be designed based on the three sub-pixel sections PXS included in one pixel PX, and the light-emitting element and the pixel circuit PXC provided based on the sub-pixel section PXS may be electrically connected.

[0231] For example, in Figure 10 In the embodiment of the present invention, the three sub-pixels SP1, SP2 and SP3 and the three emission areas EA1, EA2 and EA3 can be arranged adjacent to each other in the first direction DR1 and the second direction DR2. Although the arrangement of the three sub-pixel portions PXS is different from the arrangement of the three sub-pixels SP1, SP2 and SP3, at least a portion of each sub-pixel SP1, SP2 and SP3 can overlap with the area of ​​the sub-pixel portion PXS. When one sub-pixel SP1, SP2 and SP3 is designed relative to the sub-pixel portion PXS and there is an overlapping area thereof, the first electrode AND or the reflective electrodes RL1, RL2, RL3 and RL4 can be arranged to cover the overlapping area. Therefore, the pixel circuit PXC of the pixel circuit 220 designed relative to the sub-pixel portion PXS can be electrically connected to the light-emitting element.

[0232] In the display area DAA, the sub-pixels SP1, SP2, and SP3 may not necessarily have a uniform arrangement depending on the type of light emitted from each light-emitting element or the type of light displayed from the emission areas EA1, EA2, and EA3. On the other hand, the sub-pixel portion PXS is one of the areas uniformly divided from each pixel PX and may have a constant arrangement throughout the display area DAA. Therefore, when each of the sub-pixels SP1, SP2, and SP3 is connected to another element (e.g., the pixel circuit PXC of the pixel circuit 220), the arrangement of the connecting conductive layer RMT can be easily designed based on the arrangement of the sub-pixel portion PXS rather than the arrangement of the sub-pixels SP1, SP2, and SP3.

[0233] According to one or more embodiments, the display portion 200 may include a plurality of through-holes TSV1, TSV2, TSV3, and TSV4, and each of them may be arranged along one direction. For example, a plurality of first through-holes TSV1 may be arranged to be spaced apart from each other (e.g., spaced apart) in a first direction DR1 in a first through-hole area TSA1, and a plurality of second through-holes TSV2 may be arranged to be spaced apart from each other (e.g., spaced apart) in a second direction DR2 in a second through-hole area TSA2. In one or more embodiments, the third through-holes TSV3 may be arranged to be spaced apart from each other (e.g., spaced apart) in the second direction DR2 in the third through-hole area TSA3, and the fourth through-holes TSV4 may be arranged to be spaced apart from each other (e.g., spaced apart) in the first direction DR1 in the fourth through-hole area TSA4.

[0234] Three sub-pixel parts PXS may be uniformly disposed in one pixel PX, and three data lines DL, three first scan lines GL1, and two second scan lines GL2 may pass through one pixel PX.

[0235] The data lines DL may be provided to correspond to the sub-pixel portions PXS, respectively, and the first through holes TSV1 may also be provided to correspond to the sub-pixel portions PXS, respectively. When the area occupied by one pixel PX extends in the second direction DR2, three first through holes TSV1 may be arranged in the extension area of ​​the pixel PX in the first through hole area TSA1.

[0236] Three first scan lines GL1 may be provided to correspond to one pixel PX, and three second through holes TSV2 may also be provided to correspond to one pixel PX. When the area occupied by one pixel PX extends in the first direction DR1, the three second through holes TSV2 may be arranged in the extended area of ​​the pixel PX in the second through hole area TSA2. In one or more embodiments, two second scan lines GL2 may be provided to correspond to one pixel PX, and when the area occupied by one pixel PX extends in the first direction DR1, two third through holes TSV3 may be arranged in the extended area of ​​the pixel PX in the third through hole area TSA3.

[0237] Therefore, the diameters and spacings of the plurality of first through-holes TSV1, TSV2, and TSV3 can vary depending on the area of ​​the region occupied by the pixel PX or the distance PXP between adjacent pixels PX. For example, if the distance TVP between adjacent first through-holes TSV1, TSV2, and TSV3 is greater than the distance PXP between adjacent pixels PX, then three or two through-holes cannot be arranged correspondingly in the region corresponding to one pixel PX. In this case, the region in which the through-holes TSV1, TSV2, and TSV3 are arranged becomes larger, and the data lines DL and scan lines GL1 and GL2 have a shape that curves toward a wide region rather than extending in a single direction. In other words, by designing the arrangement of the through-holes TSV1, TSV2, and TSV3 and the distance TVP between them based on the distance PXP between pixels PX in the display portion 200, an appropriate number (e.g., a desired number) of through-holes TSV1, TSV2, and TSV3 can be arranged to fully correspond to the region occupied by each pixel PX. Therefore, the non-display area NA or dead space of the display part 200 may be reduced, and the micro display device 10 may be implemented.

[0238] In one or more embodiments, the distance TVP between the centers of the plurality of first through holes TSV1 may be 62% or less or 61.0328% or less of the distance PXP between adjacent pixels PX. For example, in one or more embodiments in which the distance PXP between the pixels PX is 8.47 μm, the distance TVP between the centers of adjacent first through holes TSV1 may be 5.16 μm or less. Similarly, the distance TVP between the centers of adjacent second through holes TSV2 may also be 5.16 μm or less. The distance PXP between two adjacent pixels PX in the first direction DR1 and the second direction DR2 may be the same, and the distance TVP between the first through holes TSV1 arranged along the first direction DR1 and the distance TVP between the second through holes TSV2 arranged along the second direction DR2 may both be 62% or less or 61.0328% or less of the distance PXP between adjacent pixels PX.

[0239] In the display device 10 according to one or more embodiments, the optimized manufacturing processes for the elements of the driving unit 100 and the light-emitting elements of the display unit 200 may be different from each other. In view of this, they can be formed on different wafers through separate processes that can increase manufacturing yields. Specifically, because the process of forming the driving circuit layer 120 included in the driving unit 100 of the display device 10 is performed as a micro semiconductor process, the first wafer substrate WF1 (for example, see Figure 17 In addition, in the process of forming the display portion 200 of the display device 10, the space occupied by unnecessary elements other than the light-emitting element can be reduced or minimized, and the display device 10 with high resolution per unit area can be realized.

[0240] In addition, the display device 10 may have a structure in which the driving unit 100 and the display unit 200, which include different single-crystal semiconductor substrates, are connected via routing lines RM1, RM2, RM3, and RM4. Through-holes TSV1, TSV2, TSV3, and TSV4, in which the conductive vias RVA1, RVA2, RVA3, and RVA4 of the routing lines RM1, RM2, RM3, and RM4 are provided, may be spaced apart (e.g., separated) from each other based on a distance PXP between pixels PX of the display unit 200. A plurality of through-holes TSV1, TSV2, TSV3, and TSV4 may be provided in pairs to correspond to an area occupied by each pixel PX, and an inactive space or a separate space for the through-holes TSV1, TSV2, TSV3, and TSV4 or signal lines may be reduced.

[0241] Hereinafter, a method for manufacturing the display device 10 will be described with reference to other drawings.

[0242] Figure 16is a flowchart illustrating a method for manufacturing a display device according to one or more embodiments.

[0243] Reference Figure 16 According to one or more embodiments, the method for manufacturing the display device 10 may include the following steps: preparing two different wafer substrates (step S10); forming a first transistor on the first wafer substrate and forming a through hole and a conductive via in the second wafer substrate (step S20); dividing the first wafer substrate into a first single crystal semiconductor substrate and attaching the first single crystal semiconductor substrate to the second wafer substrate (step S30); forming a planarization layer covering the first single crystal semiconductor substrate on one surface of the second wafer substrate, and forming a display element layer on the other surface thereof (step S40); and dividing the second wafer substrate into a second single crystal semiconductor substrate (step S50).

[0244] The method for manufacturing the display device 10 may include performing processes suitable for separately forming components of the display device 10 on two different wafer substrates and bonding them to each other. The driving unit 100 including the driving circuit layer 120 can be manufactured by forming fine-sized elements on a first wafer substrate and bonding it to a second wafer substrate. Then, the display layer 230 including the display element layer EML can be formed to manufacture the display unit 200. Therefore, on the first wafer substrate, fine elements can be formed with high integration density, thereby improving manufacturing yield and reducing manufacturing costs, and on the second wafer substrate, circuits other than the light-emitting elements are not provided, thereby reducing unnecessary area and enabling the realization of a high-resolution display device 10.

[0245] Figures 17 to 22 are views sequentially illustrating a manufacturing process of a display device according to one or more embodiments. Figures 17 to 22 A process in which two different wafer substrates WF1 and WF2 are bonded to each other and divided is schematically shown.

[0246] Reference Figure 17 , a first wafer substrate WF1 and a second wafer substrate WF2 are prepared (step S10). Each of the first wafer substrate WF1 and the second wafer substrate WF2 can be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The first wafer substrate WF1 and the second wafer substrate WF2 can be substrates doped with first-type impurities. A plurality of well regions WA can be provided on the top surfaces of the first wafer substrate WF1 and the second wafer substrate WF2. The first wafer substrate WF1 and the second wafer substrate WF2 can be parent substrates for the first single crystal semiconductor substrate 110 and the second single crystal semiconductor substrate 210 of the display device 10.

[0247] Reference Figure 18The driving unit 100 is manufactured by forming a plurality of first transistors PTR1 and a driving circuit layer 120 on one surface of a first wafer substrate WF1. A plurality of second transistors PTR2 and a pixel circuit 220 are formed on one surface of a second wafer substrate WF2, and a plurality of through-holes TSVs penetrating the second wafer substrate WF2 and conductive vias disposed therein are formed to form a temporary single crystal semiconductor substrate 210'.

[0248] The process of forming the plurality of first transistors PTR1 and the driver circuit layer 120 on the first wafer substrate WF1 may be a micro-semiconductor process. On the other hand, the process of forming the second transistors PTR2 and the process of forming the through-holes TSV on the second wafer substrate WF2 may be processes having a larger line width than the semiconductor process performed on the first wafer substrate WF1. Although the first wafer substrate WF1 and the second wafer substrate WF2 have the same area, the driver unit 100 and the temporary single crystal semiconductor substrate 210' formed in this process may have different areas. Therefore, the number of driver units 100 formed on the first wafer substrate WF1 may be greater than the number of temporary single crystal semiconductor substrates 210' formed on the second wafer substrate WF2. The process of manufacturing the driver unit 100 on the first wafer substrate WF1 is an expensive semiconductor process, but it can have a relatively high yield.

[0249] The method for manufacturing the display device 10 can manufacture the display device 10 in which the circuit units necessary for driving the light-emitting elements of the display unit 200 are provided in the driving circuit layer 120 of the driving unit 100. In the process of forming the driving circuit layer 120 on the first wafer substrate WF1, the driving circuit layer 120 may include a driving circuit 400, a gate driver 600, and a data driver 700. On the other hand, the pixel circuit 220 may be formed on the second wafer substrate WF2.

[0250] Next, refer to Figure 19, the first wafer substrate WF1 is divided into a plurality of first single crystal semiconductor substrates 110, and the first single crystal semiconductor substrates 110 are attached to the bottom surface of the second wafer substrate WF2. The first wafer substrate WF1 can be divided into a plurality of first single crystal semiconductor substrates 110, each having a driving circuit layer 120 formed thereon. In one or more embodiments, the driving circuit layer 120 disposed on the first single crystal semiconductor substrate 110 can be bonded to the bottom surface of a temporary single crystal semiconductor substrate 210'. The process of bonding the first single crystal semiconductor substrate 110 to the bottom surface of the second wafer substrate WF2 may not be bonding between two different wafer substrates, but rather a process of separating the first single crystal semiconductor substrate 110 from the first wafer substrate WF1 and then bonding it to the second wafer substrate WF2. The plurality of first single crystal semiconductor substrates 110 can be bonded to the plurality of temporary single crystal semiconductor substrates 210' formed on the second wafer substrate WF2 in a corresponding manner.

[0251] The process of bonding the first single crystal semiconductor substrate 110 to the second wafer substrate WF2 may be performed under a higher temperature condition than the process of forming the display element layer EML, which will be described later. According to one or more embodiments, the process of bonding the first single crystal semiconductor substrate 110 to the second wafer substrate WF2 may be performed before the process of forming the display element layer EML including the light-emitting element on the second wafer substrate WF2. The method for manufacturing the display device 10 may not be a method of separately manufacturing the driving unit 100 including the first single crystal semiconductor substrate 110 and the display unit 200 including the second single crystal semiconductor substrate 210 and bonding them to each other. The method for manufacturing the display device 10 may involve dividing the first wafer substrate WF1 into the driving units 100 and bonding them to the second wafer substrate WF2 on which the light-emitting element is not formed.

[0252] In one or more embodiments, when executing Figure 19 Before the bonding process, a connection line layer 500 (eg, see Figure 7 ). A connection line layer 500 may be formed on the bottom surface of the second wafer substrate WF2, and the first single crystal semiconductor substrate 110 may be attached to the bottom surface of the second wafer substrate WF2 on which the connection line layer 500 is formed. Therefore, the driving circuit layer 120 formed on the first single crystal semiconductor substrate 110 may be electrically connected to the connection line layer 500. However, the present disclosure is not limited thereto. The first single crystal semiconductor substrate 110 may be attached to the top surface of the second wafer substrate WF2 on which the connection line layer 500 is not formed. In this case, a planarization layer 910 (see FIG. 1 ) to be described later may be formed on the top surface of the second wafer substrate WF2. Figure 20), and a display element layer EML may be formed on a top surface of the connection line layer 500 or a bottom surface of the second wafer substrate WF2.

[0253] Next, refer to Figure 20 A planarization layer 910 is formed on the bottom surface of the second wafer substrate WF2. The planarization layer 910 can even out steps caused by the plurality of first single crystal semiconductor substrates 110 disposed on the bottom surface of the second wafer substrate WF2. Due to the provision of the planarization layer 910, subsequent processes can be smoothly performed on the top surface of the second wafer substrate WF2. When the second wafer substrate WF2 is divided, the planarization layer 910 can also be divided to form the passivation layer 900 of the display device 10.

[0254] Next, refer to Figure 21 A display element layer EML is formed on the top surface of the second wafer substrate WF2, opposite to the bottom surface to which the driving unit 100 is attached, to form the display unit 200. The process of forming the display element layer EML can be performed using a different semiconductor process from the process of forming the driving circuit layer 120 on the first wafer substrate WF1. For example, the process of forming the display element layer EML can be performed using a semiconductor process having a relatively large line width, and can be a process that results in (e.g., requires) a relatively low cost compared to the process of forming the driving circuit layer 120.

[0255] During the process of forming the display element layer EML, the multiple light-emitting elements of the display element layer EML can be electrically connected to the second transistor PTR2 formed on the second single crystal semiconductor substrate 210. The multiple terminals DTD, GTD1, GTD2, and PTD of the display element layer EML can be electrically connected to the conductive vias formed in the through-holes TSV and the connection lines of the connection line layer 500, and can be electrically connected to the driving circuit layer 120 of the driving unit 100 through the conductive vias and connection lines. In addition, during this process, the display layer 230 including the display element layer EML, the encapsulation layer TFE, the optical layer OPL, etc. can be formed. Since the display layer 230 is formed on the second wafer substrate WF2, the display unit 200 including the display layer 230 can be formed.

[0256] Next, refer to Figure 22 The second wafer substrate WF2 may be divided into second single crystal semiconductor substrates 210 on which the display element layer EML is formed. The display layer 230 including the display element layer EML may be formed on the top surface of the divided second single crystal semiconductor substrate 210, and the connection line layer 500, the first single crystal semiconductor substrate 110, and the passivation layer 900 may be attached to the bottom surface of the divided second single crystal semiconductor substrate 210. Next, in one or more embodiments, the display device 10 may be manufactured by attaching the circuit board 300 to one surface of the display portion 200.

[0257] In the method for manufacturing the display device 10 according to one or more embodiments, the process of forming the elements of the circuit unit and the process of forming the light-emitting elements can be performed on different wafer substrates WF1 and WF2, respectively. In the display device 10, the elements of the circuit unit and the light-emitting elements can have different optimized manufacturing processes. Taking this into account, they can be formed on different wafer substrates WF1 and WF2 by separate processes that can increase manufacturing yield. Specifically, because the process of forming the driving circuit layer 120 included in the driving unit 100 of the display device 10 is performed as a micro-semiconductor process, the yield per unit area of ​​the first wafer substrate WF1 can be improved. In addition, in the process of forming the display unit 200 of the display device 10, the space occupied by unnecessary elements other than the light-emitting elements can be reduced or minimized, and a display device 10 with high resolution per unit area can be achieved.

[0258] Figures 23 to 34 are cross-sectional views sequentially illustrating a manufacturing process of a display device according to one or more embodiments. Figures 23 to 34 The process of forming the through-vias TSV1 , TSV2 , TSV3 , and TSV4 and the routing lines RM1 , RM2 , RM3 , and RM4 of the display part 200 and connecting them to the driving part 100 is shown in more detail. Figures 23 to 34 The process of forming the driving part 100 on the first wafer substrate WF1 and dividing it is omitted.

[0259] Reference Figure 23 and Figure 24 , prepare a second wafer substrate WF2, and form a pixel circuit 220 and a pad PD on one surface of the second wafer substrate WF2. The pixel circuit 220 may include the above reference Figures 12 to 14 The semiconductor backplane SBP and pixel circuit backplane EBP are described. A plurality of second transistors PTR2 are formed on the second wafer substrate WF2, and the pixel circuit 220 may include a plurality of insulating layers, a connection conductive layer RMT connected to the second transistors PTR2, and a plurality of terminals DTD, GTD1, GTD2, and PTD.

[0260] Reference Figure 25, forming a plurality of through-holes TSV1, TSV2, TSV3, and TSV4 that penetrate a portion of the second wafer substrate WF2 on which the pixel circuit 220 is formed, and conductive vias RVA1, RVA2, RVA3, and RVA4 disposed in the through-holes TSV1, TSV2, TSV3, and TSV4. The plurality of through-holes TSV1, TSV2, TSV3, and TSV4 can be disposed spaced apart (e.g., separated) from each other in an area of ​​the second wafer substrate WF2 corresponding to the non-display area NA of the display portion 200. The first through-hole TSV1 can be disposed in a first through-hole area TSA1 positioned above the display area DAA, and the second and third through-holes TSV2 and TSV3 can be disposed in the second and third through-hole areas TSA2 and TSA3 positioned to the left and right of the display area DAA, respectively. The fourth through-hole TSV4 can be disposed in a fourth through-hole area TSA4 positioned between the display area DAA and the pad area PDA.

[0261] A plurality of first conductive vias RVA1 may be formed to fill the first through-holes TSV1, respectively, and a plurality of second conductive vias RVA2 may be formed to fill the second through-holes TSV2, respectively. A plurality of third conductive vias RVA3 may be formed to fill the third through-holes TSV3, respectively, and a plurality of fourth conductive vias RVA4 may be formed to fill the fourth through-holes TSV4, respectively. The first conductive via RVA1 may be connected to the data terminal DTD of the pixel circuit 220, the second conductive via RVA2 may be connected to the first gate terminal GTD1, and the third conductive via RVA3 may be connected to the second gate terminal GTD2. The fourth conductive via RVA4 may be connected to the pad signal terminal PTD.

[0262] The depth of the through-holes TSV1, TSV2, TSV3, and TSV4 may be less than the thickness of the second wafer substrate WF2. As will be described later, a process of reducing the thickness of the second wafer substrate WF2 may be performed (for example, a process of etching the second wafer substrate WF2 to reduce its thickness may be performed). In this process, the through-holes TSV1, TSV2, TSV3, and TSV4 may penetrate the second wafer substrate WF2, the thickness of which has been reduced.

[0263] Reference Figure 26 and Figure 27, the second wafer substrate WF2 is moved onto the first carrier substrate CSB1, and then the thickness of the second wafer substrate WF2 is reduced to form a second single crystal semiconductor substrate 210. The first carrier substrate CSB1 can be attached to one surface of the second wafer substrate WF2 on which the through-holes TSV1, TSV2, TSV3 and TSV4 are formed, for example, the top surface of the second wafer substrate WF2. The second wafer substrate WF2 can be flipped so that the other surface or bottom surface on which the through-holes TSV1, TSV2, TSV3 and TSV4 are not formed faces upward, and a process of reducing the thickness of the second wafer substrate WF2 can be performed. In one or more embodiments, the thickness of the second wafer substrate WF2 can be reduced to 100 μm or less, for example, in the range of 80 μm to 100 μm. After performing this process, the plurality of through-holes TSV1 , TSV2 , TSV3 , and TSV4 may completely penetrate the second single crystalline semiconductor substrate 210 , and the plurality of conductive vias RVA1 , RVA2 , RVA3 , and RVA4 may be exposed from the top and bottom surfaces of the second single crystalline semiconductor substrate 210 .

[0264] Reference Figure 28 A connection line layer 500 including connection lines is formed on a surface (e.g., the bottom surface) of the second single crystalline semiconductor substrate 210 that is not in contact with the first carrier substrate CSB1. The connection line layer 500 may include an interlayer insulating layer and a plurality of connection lines, each of which may correspond to a different conductive via RVA1, RVA2, RVA3, or RVA4. The first conductive via RVA1 and the connection line may form a first routing line RM1, the second conductive via RVA2 and the connection line may form a second routing line RM2, the third conductive via RVA3 and the connection line may form a third routing line RM3, and the fourth conductive via RVA4 and the connection line may form a fourth routing line RM4.

[0265] Reference Figure 29 , the driving part 100 including the first single crystal semiconductor substrate 110 and the driving circuit layer 120 is attached to the connection line layer 500. The driving part 100 may be formed on and separated from the first wafer substrate WF1, and may have an area smaller than that of the second single crystal semiconductor substrate 210. A plurality of routing lines RM1, RM2, RM3, and RM4 may be connected to the data driver 700, the gate driver 600, and the signal terminals STD of the driving part 100.

[0266] Reference Figure 30 , a passivation layer 900 or a planarization layer is formed to cover the driving part 100. The passivation layer 900 can compensate for a step caused by the driving part 100 and protect the driving part 100.

[0267] Reference Figure 31 and Figure 32 , the second carrier substrate CSB2 is attached to one surface of the passivation layer 900, turned over, and then the first carrier substrate CSB1 is removed. If the first carrier substrate CSB1 is removed, the top surface of the second single crystal semiconductor substrate 210 may be exposed.

[0268] Reference Figure 33 and Figure 34 A display layer 230 is formed on the pixel circuit 220 to form the display unit 200, and the second carrier substrate CSB2 is removed. During the process of forming the display layer 230, the light-emitting element of the display element layer EML can be electrically connected to the second transistor PTR2 of the second single crystal semiconductor substrate 210. The pad PD can be electrically connected to the signal terminal STD of the driving unit 100 via the fourth routing line RM4.

[0269] Next, in one or more embodiments, the circuit board 300 may be attached to the pad PD of the display part 200 , thereby manufacturing the display device 10 .

[0270] Hereinafter, various embodiments of the display device 10 will be described with reference to other drawings.

[0271] Figure 35 is a plan view illustrating the arrangement of a plurality of wirings provided in a display portion of a display device according to one or more embodiments. Figure 36 It shows Figure 35 Schematic diagram of the rear surface of a display device. Figure 37 is shown in the settings Figure 35 A diagram showing the relative arrangement of through holes and pixels in a display portion of a display device.

[0272] Reference Figures 35 to 37, the multiple through-holes TSV1 and TSV2 formed in the display portion 200 can be spaced apart (e.g., separated) from other adjacent through-holes TSV1 and TSV2 in the diagonal direction. As described above, the multiple through-holes TSV1, TSV2, TSV3, and TSV4 can be formed to correspond to one pixel PX. For example, three first through-holes TSV1 and three second through-holes TSV2 can be formed to correspond to one pixel PX. In one or more embodiments, two third through-holes TSV3 can also be formed to correspond to one pixel PX. If the distance TVP between adjacent through-holes TSV1, TSV2, and TSV3 is too small, interference may occur between the conductive vias RVA1, RVA2, and RVA3 provided in the through-holes TSV1, TSV2, and TSV3. If the distance TVP between the through-holes TSV1, TSV2, and TSV3 corresponding to one pixel PX is too large, it is impossible to provide a suitable number (e.g., a required number) of through-holes TSV1, TSV2, and TSV3 in the area corresponding to one pixel PX. In this case, separate routing lines can connect the through-holes TSV1, TSV2, and TSV3, or the conductive vias RVA1, RVA2, and RVA3 disposed within the through-holes TSV1, TSV2, and TSV3 (e.g., separate routing lines may be required to connect the through-holes TSV1, TSV2, and TSV3, or the conductive vias RVA1, RVA2, and RVA3 disposed within the through-holes TSV1, TSV2, and TSV3) to the signal lines DL, GL1, and GL2. That is, by designing the arrangement of the through-holes TSV1, TSV2, and TSV3 and the distance TVP therebetween based on the distance PXP between the pixels PX of the display portion 200, a plurality of through-holes TSV1, TSV2, and TSV3 can be disposed in an area corresponding to each pixel PX. Consequently, the non-display area NA, or dead space, of the display portion 200 can be reduced, and the microdisplay device 10 can be implemented.

[0273] Figure 38 is a perspective view illustrating a head-mounted display device according to one or more embodiments. Figure 39 It shows Figure 38 An exploded perspective view of an example of a head-mounted display device.

[0274] Reference Figure 38 and Figure 39 According to one or more embodiments, the head-mounted display device 1000 includes a first display device 11, a second display device 12, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and connectors.

[0275] The first display device 11 provides an image to the left eye of the user, and the second display device 12 provides an image to the right eye of the user. Figure 1 The display devices 10 described are substantially the same, so descriptions of the first display device 11 and the second display device 12 will be omitted.

[0276] The first optical member 1510 may be disposed between the first display device 11 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 12 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0277] The middle frame 1400 may be disposed between the first display device 11 and the control circuit board 1600 and between the second display device 12 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 11, the second display device 12, and the control circuit board 1600.

[0278] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 11 and the second display device 12 via a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA, and may transmit the digital video data DATA to the first display device 11 and the second display device 12 via the connector.

[0279] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 11, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 12. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 11 and the second display device 12.

[0280] The display device housing 1100 is used to accommodate the first display device 11, the second display device 12, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connectors. The housing cover 1200 is provided to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. The drawings illustrate that the first eyepiece 1210 and the second eyepiece 1220 are provided separately, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0281] The first eyepiece 1210 may be aligned with the first display device 11 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 12 and the second optical member 1520. Therefore, the user can view the image of the first display device 11 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 12 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0282] The headband 1300 is used to secure the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain positioned over the user's left eye and right eye, respectively. If the display device housing 1100 is lightweight and compact, the head-mounted display device 1000 may be provided with an eyeglass frame instead of the headband 1300.

[0283] In addition, the head-mounted display device 1000 may further include a battery for power supply, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, and / or a Bluetooth module.

[0284] Figure 40 is a perspective view illustrating a head-mounted display device according to one or more embodiments.

[0285] Reference Figure 40 The head-mounted display device 1000_1 according to one or more embodiments may be a glasses-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display device 1000_1 according to one or more embodiments may include a display device 13, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0286] The display device housing 1200_1 can accommodate the display device 13, the optical member 1060, and the optical path changing member 1070. The image displayed on the display device 13 can be magnified by the optical member 1060, and the optical path can be changed by the optical path changing member 1070 to provide the image to the user's right eye through the right-eye lens 1020. As a result, the user can view an augmented reality image in which a virtual image displayed on the display device 13 and a real image viewed through the right-eye lens 1020 are combined through the right eye.

[0287] The display device housing 1200_1 is shown as being located at the right end of the support frame 1030 in the drawings, but the present disclosure is not limited thereto. For example, the display device housing 1200_1 may be located at the left end of the support frame 1030, in which case the image of the display device 13 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be located at both the left and right ends of the support frame 1030, in which case the user can view the image displayed on the display device 13 with both the left and right eyes.

[0288] However, it should be understood that the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the claims and the equivalents of the claims to be included therein.

Claims

1. A display device, comprising: a first single crystal semiconductor substrate, a plurality of first transistors being positioned at the first single crystal semiconductor substrate; a second single crystal semiconductor substrate on the first single crystal semiconductor substrate, wherein a plurality of second transistors are positioned at the second single crystal semiconductor substrate; as well as a connecting line layer between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate, wherein the second single crystal semiconductor substrate includes a display area in which a plurality of sub-pixels are positioned, a plurality of first through holes, and a plurality of second through holes, each of the plurality of sub-pixels including a light-emitting element, the plurality of first through holes being located in a non-display area surrounding the display area, and first conductive vias connected to a plurality of data lines extending in a first direction being located in the plurality of first through holes, the plurality of second through holes being located in the non-display area, and second conductive vias connected to a plurality of first scan lines extending in a second direction being located in the plurality of second through holes, and The connection line layer includes a first connection line connecting the first conductive via to a data driver on the first single crystal semiconductor substrate and a second connection line connecting the second conductive via to a scan driver on the first single crystal semiconductor substrate.

2. The display device according to claim 1, wherein The first through holes are spaced apart from each other, and the second through holes are spaced apart from each other.

3. The display device according to claim 2, wherein: The plurality of first through-holes are spaced apart from other adjacent first through-holes in an oblique direction, and the plurality of second through-holes are spaced apart from other adjacent second through-holes in an oblique direction.

4. The display device according to claim 1, wherein A plurality of pixels are arranged in the display area, each pixel including three sub-pixels, and The three first through holes are located in an area occupied by one pixel and extending in a direction toward the non-display area.

5. The display device according to claim 4, wherein The pixel includes three sub-pixel portions corresponding to the three sub-pixels, respectively, and The distance between the first through holes is 61.0328% or less of a distance between corresponding sub-pixel portions in adjacent pixels among the plurality of pixels. The display device according to claim 1 , wherein: The plurality of first through-holes and the plurality of second through-holes do not overlap with the first single crystal semiconductor substrate, and Each of the first connection line and the second connection line has at least a portion overlapping the first single crystal semiconductor substrate.

7. The display device according to claim 1, wherein The second single crystal semiconductor substrate further includes a plurality of third through holes in the non-display area, third conductive vias connected to a plurality of second scan lines extending in the second direction are positioned in the plurality of third through holes, and The connection line layer further includes a third connection line connecting the third conductive via to the emission driver on the first single crystal semiconductor substrate.

8. The display device according to claim 1, wherein The number of the first through holes is equal to the number of the data lines and the number of pixel columns of the plurality of sub-pixels.

9. The display device according to claim 1, wherein The number of the second through holes is equal to the number of the first scan lines and is greater than the number of pixel rows of the plurality of sub-pixels.

10. The display device according to claim 1, further comprising a plurality of signal terminals on the first single crystal semiconductor substrate, in, The second single crystal semiconductor substrate further includes a plurality of fourth through holes formed in the non-display area, and The connection line layer further includes a fourth connection line connecting the signal terminal to a fourth conductive via in the fourth through hole.

11. The display device according to claim 1, wherein An area of ​​the first single crystal semiconductor substrate in a plan view is smaller than an area of ​​the second single crystal semiconductor substrate in the plan view.

12. The display device according to claim 1, wherein The length of the minimum line width of the first transistor is smaller than the length of the minimum line width of the second transistor.

13. The display device according to claim 12, wherein: The minimum line width of the first transistor is less than 100 nm, and Wherein, the minimum line width of the second transistor is greater than or equal to 100 nm. 14 . The display device according to claim 1 , further comprising a passivation layer surrounding the first single crystal semiconductor substrate and overlapping the second single crystal semiconductor substrate.

15. A method for manufacturing a display device, the method comprising the following steps: preparing a first wafer substrate and a second wafer substrate that are different from each other; forming a plurality of first transistors on the first wafer substrate, forming a pixel circuit on one surface of the second wafer substrate, and forming a plurality of through holes penetrating at least a portion of the second wafer substrate and a plurality of conductive vias respectively positioned in the plurality of through holes; forming a connection line layer including a plurality of connection lines on another surface of the second wafer substrate opposite to the one surface; dividing the first wafer substrate into a plurality of first single crystal semiconductor substrates, and attaching the first single crystal semiconductor substrates to the other surface of the second wafer substrate; forming a planarization layer covering the other surface of the second wafer substrate and the first single crystal semiconductor substrate attached to the other surface; forming a display element layer including a plurality of light emitting elements on the one surface of the second wafer substrate; as well as dividing the second wafer substrate into a plurality of second single crystal semiconductor substrates in which the display element layer is formed on one surface and the first single crystal semiconductor substrate is formed on the other surface, wherein the plurality of through holes include a plurality of first through holes in a non-display area surrounding the display area and having first conductive vias therein, and a plurality of second through holes in the non-display area and having second conductive vias therein, and The connection line layer includes a first connection line connecting the first conductive via and a data driver on the first single crystal semiconductor substrate, and a second connection line connecting the second conductive via and a scan driver on the first single crystal semiconductor substrate.

16. The method according to claim 15, further comprising: After the step of forming the plurality of through holes and the plurality of conductive vias, performing etching to reduce the thickness of the second wafer substrate, The first single crystal semiconductor substrate is attached to the connection line layer.

17. The method according to claim 15, wherein: Each of the plurality of first through-holes and the plurality of second through-holes does not overlap with the first single crystal semiconductor substrate.

18. The method according to claim 15, wherein An area of ​​the first single crystal semiconductor substrate in a plan view is smaller than an area of ​​the second single crystal semiconductor substrate in the plan view.

19. The method according to claim 15, wherein In the step of forming the pixel circuit on the second wafer substrate, a plurality of second transistors are formed on the second wafer substrate, and The length of the minimum line width of the first transistor is smaller than the length of the minimum line width of the second transistor.

20. A head-mounted display device, comprising: a frame configured to be mounted on a user's body and corresponding to the left and right eyes; a plurality of display devices in the frame; as well as a lens, on each of the plurality of display devices, The display device among the plurality of display devices includes: a first single crystal semiconductor substrate, a plurality of first transistors are positioned on the first single crystal semiconductor substrate; a second single crystal semiconductor substrate, on the first single crystal semiconductor substrate, a plurality of second transistors are positioned on the second single crystal semiconductor substrate; and a connecting line layer, between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate. wherein the second single crystal semiconductor substrate includes a display area in which a plurality of sub-pixels are positioned, a plurality of first through holes, and a plurality of second through holes, each of the plurality of sub-pixels including a light-emitting element, the plurality of first through holes being located in a non-display area surrounding the display area, and first conductive vias connected to a plurality of data lines extending in a first direction being located in the plurality of first through holes, the plurality of second through holes being located in the non-display area, and second conductive vias connected to a plurality of first scan lines extending in a second direction being located in the plurality of second through holes, and The connection line layer includes a first connection line connecting the first conductive via to a data driver on the first single crystal semiconductor substrate and a second connection line connecting the second conductive via to a scan driver on the first single crystal semiconductor substrate.

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