Display device

Abstract

Provided is a display device including: a substrate; a first electrode layer disposed on the substrate; a bank layer disposed on the first electrode layer and configured to define a plurality of sub-pixels; a light emitting layer disposed on the bank layer; and an encapsulation layer disposed on the light emitting layer, in which the encapsulation layer includes a recess.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2024-0029333, filed on February 29, 2024, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] An embodiment of the present disclosure relates to a display device. Background Art

[0004] The display panel of a display device may include a display area for displaying images and a non-display area for not displaying images. Since various structures, circuits, and lines need to be arranged in the non-display area (also called the frame area), it is not easy to reduce the frame of the display panel.

[0005] In particular, when a structure for preventing moisture penetration is formed in the bezel of the display panel, it is more difficult to reduce the size of the bezel. Summary of the Invention

[0006] Embodiments of the present disclosure may provide a display device capable of delaying moisture penetration into a frame area.

[0007] Embodiments of the present disclosure may provide a display device capable of implementing an extremely narrow bezel while delaying the penetration of moisture into the bezel area.

[0008] According to an embodiment of the present disclosure, a display device capable of delaying the penetration of moisture into a bezel area can be provided.

[0009] According to the embodiments of the present disclosure, a display device capable of optimizing a process by delaying the penetration of moisture into a frame area while implementing an extremely narrow frame can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a diagram showing a system configuration of a display device according to an embodiment of the present disclosure;

[0012] Figure 2 An equivalent circuit diagram of a sub-pixel in a display panel according to an embodiment of the present disclosure is shown;

[0013] Figure 3 is a plan view showing a display panel according to an embodiment of the present disclosure;

[0014] Figure 4A 、 Figure 4Band Figure 4C Along the Figure 3 Cross-sectional views taken along lines I-I', II-II', and III-III';

[0015] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D and Figure 7 yes Figure 4A An enlarged cross-sectional view of portion A of FIG. DETAILED DESCRIPTION

[0016] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings that illustrate specific examples or embodiments that may be implemented, and the same reference numerals and symbols may be used to refer to the same or similar components in the drawings even if they are shown in different drawings. In addition, in the following description of examples or embodiments of the present disclosure, when it is determined that a detailed description of well-known functions and components incorporated herein may make the subject matter in some embodiments of the present disclosure quite unclear, that description will be omitted. Terms such as "including," "having," "comprising," "consisting of," "composed of," and "formed" as used herein are generally intended to be able to add other components unless the term is used with the term "only." As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise.

[0017] Terms such as "first," "second," "A," "B," "(A)," and "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, or quantity of the elements, but is only used to distinguish the corresponding element from other elements.

[0018] When a first element is referred to as being “connected or coupled to” a second element, or “contacting or overlapping” the second element, etc., it should be interpreted that not only the first element may be “directly connected or coupled to” the second element, or “directly contacting or overlapping” the second element, etc., but also a third element may be “interposed” between the first and second elements, or the first and second elements may be “connected or coupled to,” “contacting or overlapping” each other via a fourth element, etc. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled to,” “contacting or overlapping,” etc., with each other.

[0019] When time-related terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or arrangement, or a process or step in an operation, process, or manufacturing method, these terms may be used to describe non-continuous or non-sequential processes or operations unless used with the terms “directly” or “immediately.”

[0020] Furthermore, when referring to any dimension, relative size, etc., even if there is no specific description thereof, it should be considered that the numerical value of the element or feature, or the corresponding information (e.g., level, range, etc.) includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully includes all meanings of the term "can."

[0021] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 is a diagram illustrating a system configuration of a display device 100 according to an embodiment of the present disclosure.

[0023] Reference Figure 1 , the display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a display driving circuit as components for displaying an image.

[0024] The display driving circuit is a circuit for driving the display panel 110 and may include a data driving circuit 120 , a gate driving circuit 130 , and a display controller 140 .

[0025] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111 .

[0026] The substrate 111 of the display panel 110 may include a display area DA capable of displaying an image and a non-display area NDA located outside the display area DA.

[0027] A plurality of sub-pixels SP for image display may be provided in the display area DA, and the non-display area NDA may include a pad area PA arranged in a first direction from the display area DA.

[0028] In the display panel 110 according to an embodiment of the present disclosure, the non-display area NDA may be very small.

[0029] In this disclosure, the non-display area NDA may also be referred to as a “bezel”.

[0030] For example, the non-display area NDA may include a first non-display area located outside the display area DA along a first direction, a second non-display area located outside the display area DA along a second direction intersecting the first direction, a third non-display area located outside the display area DA in a direction opposite to the first direction, and a fourth non-display area located outside the display area DA in a direction opposite to the second direction.

[0031] At least one or two of the first to fourth non-display areas may include a pad area connected or coupled to the data driving circuit 120 .

[0032] At least two or three non-display areas excluding the pad area among the first to fourth non-display areas may be small.

[0033] As another example, a boundary area between the display area DA and the non-display area NDA may be bent so that the non-display area NDA may be located below the display area.

[0034] In this case, when the user views the display area DA from the front, the non-display area NDA may be almost invisible to the user.

[0035] Various types of signal lines for driving the plurality of sub-pixels SP may be provided on the substrate 111 of the display panel 110 .

[0036] The display device 100 according to an embodiment of the present disclosure may be a liquid crystal display device or a self-luminous display device in which the display panel 110 emits light itself.

[0037] When the display device 100 according to an embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light emitting element.

[0038] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light emitting diode display in which the light emitting elements are implemented as organic light emitting diodes (OLEDs).

[0039] As another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light emitting display device in which light emitting elements are implemented as light emitting diodes based on inorganic materials.

[0040] As another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device in which light emitting elements are implemented as quantum dots (QDs) which are self-luminous semiconductor crystals.

[0041] The structure of each of the plurality of sub-pixels SP may vary according to the type of the display device 100 .

[0042] For example, when the display device 100 is a self-luminous display device in which the sub-pixels SP emit light by themselves, each sub-pixel SP may include a self-luminous light-emitting element, one or more transistors, and one or more capacitors.

[0043] For example, the various types of signal lines may include a plurality of data lines DL transmitting N data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL transmitting gate signals (also referred to as scan signals).

[0044] The plurality of data lines DL and the plurality of gate lines GL may cross each other.

[0045] Each of the plurality of data lines DL may be disposed to extend in a first direction, and each of the plurality of gate lines GL may be disposed to extend in a second direction.

[0046] Here, the first direction may be a column direction, and the second direction may be a row direction.

[0047] The first direction may be a row direction, and the second direction may be a column direction.

[0048] For convenience of description, described below is an example in which each of the plurality of data lines DL is disposed in a column direction and each of the plurality of gate lines GL is disposed in a row direction.

[0049] The data driving circuit 120 is a circuit for driving the plurality of data lines DL and may output data signals to the plurality of data lines DL.

[0050] The data driving circuit 120 may receive digital image data DATA from the display controller 140 and may convert the received image data DATA into analog data signals and output them to a plurality of data lines DL.

[0051] For example, the data driving circuit 120 can be connected to the display panel 110 through a tape automated bonding (TAB) method, or connected to the bonding pads of the display panel 110 through a chip on glass (COG) or chip on panel (COP) method, or can be implemented and connected to the display panel 110 through a chip on film (COF) method.

[0052] The data driving circuit 120 may be connected to one side (eg, an upper side or a lower side) of the display panel 110 .

[0053] In contrast, the data driving circuit 120 may be connected to both sides (eg, both upper and lower sides) of the display panel 110 , or two or more of the four sides of the display panel 110 , depending on a driving scheme or a panel design scheme.

[0054] The data driving circuit 120 may be connected outside the display area DA of the display panel 110 , but alternatively, the data driving circuit 120 may be provided in the display area DA of the display panel 110 .

[0055] The gate driving circuit 130 is a circuit for driving the plurality of gate lines GL, and may output gate signals to the plurality of gate lines GL.

[0056] The gate driving circuit 130 may receive a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage, and various gate driving control signals GCS, generate gate signals, and supply the generated gate signals to a plurality of gate lines GL.

[0057] In the display device 100 according to an embodiment of the present disclosure, the gate driving circuit 130 may be built in the display panel 110 in a gate-in-panel (GIP) type.

[0058] When the gate driving circuit 130 is a gate-in-panel type, the gate driving circuit 130 may be formed on the substrate 111 of the display panel 110 during a manufacturing process of the display panel 110 .

[0059] In the display device 100 according to an embodiment of the present disclosure, the gate driving circuit 130 may be provided in the display area DA of the display panel 110 .

[0060] For example, the gate driving circuit 130 may be disposed in a first partial region of the display area DA (eg, a left region or a right region of the display area DA).

[0061] As another example, the gate driving circuit 130 may be disposed in a first partial area (e.g., a left area or a right area in the display area DA) and a second partial area (e.g., a right area or a left area in the display area DA).

[0062] In the present disclosure, the gate driving circuit 130 built into the display panel 110 in a gate-in-panel type may also be referred to as an “in-panel gate circuit”.

[0063] As described above, the gate driving circuit 130 of the intra-panel gate type is not connected to or disposed in the non-display area NDA of the display panel 110 , but is disposed in the display area DA, thereby significantly reducing the bezel of the display panel 110 .

[0064] The display controller 140 is a device for controlling the data driving circuit 120 and the gate driving circuit 130 and may control driving timing for a plurality of data lines DL and driving timing for a plurality of gate lines GL.

[0065] The display controller 140 may supply a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120 and may supply a gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130 .

[0066] The display controller 140 may be implemented as a separate component from the data driving circuit 120 , or the display controller 140 and the data driving circuit 120 may be integrated in an integrated circuit (IC).

[0067] The display controller 140 may be a timing controller used in general display technology, a control device that can perform other control functions as well as the function of the timing controller, a control device other than the timing controller, or a circuit in the control device.

[0068] The display controller 140 may be implemented as various circuits or electronic devices, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0069] The display controller 140 may be mounted on a printed circuit board or a flexible printed circuit and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board or the flexible printed circuit.

[0070] The display controller 140 may transmit and receive signals to and from the data driving circuit 120 according to one or more predetermined interfaces.

[0071] The interface may include, for example, a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI), and a serial peripheral interface (SPI).

[0072] To provide a touch sensing function as well as an image display function, the display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch object (e.g., a finger or a pen) touches or the position of the touch.

[0073] The touch sensing circuit may include a touch driving circuit that drives and senses the touch sensor and generates and outputs touch sensing data, and a touch controller that may detect occurrence of a touch or a touched position using the touch sensing data.

[0074] The touch sensor may include a plurality of touch electrodes.

[0075] The touch sensor may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes and the touch driving circuit.

[0076] The touch sensor may exist outside the display panel 110 in the form of a touch panel or may exist inside the display panel 110 .

[0077] When a touch sensor in the form of a touch panel exists outside the display panel 110 , the touch panel is an external type.

[0078] When the touch sensor is an external type, the touch panel and the display panel 110 may be manufactured separately or may be combined during an assembly process.

[0079] The external type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0080] When the touch sensor exists inside the display panel 110 , the touch sensor may be formed on a substrate together with signal lines and electrodes related to display driving during a manufacturing process of the display panel 110 .

[0081] The touch driving circuit may supply a touch driving signal to at least one of the plurality of touch electrodes and may sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0082] The touch sensing circuit may perform touch sensing in a self-capacitance sensing scheme or a mutual-capacitance sensing scheme.

[0083] When the touch sensing circuit performs touch sensing in a self-capacitance sensing scheme, the touch sensing circuit may perform touch sensing based on capacitance between each touch electrode and a touch object (eg, a finger or a pen).

[0084] According to the self-capacitance sensing scheme, each of the plurality of touch electrodes may serve as both a driving touch electrode and a sensing touch electrode.

[0085] The touch driving circuit may drive all or a portion of the plurality of touch electrodes and sense all or a portion of the plurality of touch electrodes.

[0086] When the touch sensing circuit performs touch sensing in a mutual capacitance sensing scheme, the touch sensing circuit may perform touch sensing based on capacitance between touch electrodes.

[0087] According to the mutual capacitance sensing scheme, a plurality of touch electrodes may be divided into driving touch electrodes and sensing touch electrodes.

[0088] The touch driving circuit may drive the driving touch electrodes and sense the sensing touch electrodes.

[0089] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented as separate devices or as a single device.

[0090] The touch driving circuit and the data driving circuit may be implemented as separate devices or as a single device.

[0091] At the same time, a plurality of touch lines (a plurality of touch routing lines) for electrically connecting a plurality of touch electrodes constituting a touch sensor and a touch driving circuit can be arranged on the display area DA without bypassing the pad area ( Figure 3 The non-display area ( Figure 3 The second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4 are formed, and can extend to Figure 3 The pad area PA.

[0092] Therefore, the area excluding the pad ( Figure 3 The non-display area ( Figure 3 The size of the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4 is reduced, and thus the frame size can be greatly reduced.

[0093] The display device 100 may further include a power supply circuit for supplying various types of power to the display driver integrated circuit or the touch sensing circuit.

[0094] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal such as a smart phone or a tablet, or a monitor or television (TV) of various sizes, but is not limited thereto. The display device 100 may be a display of various types and sizes capable of displaying information or images.

[0095] The display device 100 according to an embodiment of the present disclosure may further include electronic devices such as a camera (image sensor), a detection sensor, and the like.

[0096] For example, the detection sensor may be a sensor that detects an object or a human body by receiving light such as infrared rays, ultrasonic waves, or ultraviolet rays.

[0097] Figure 2 is an equivalent circuit of a sub-pixel in the display panel 110 according to an embodiment of the present disclosure.

[0098] Reference Figure 2 , the display panel 110 may include a substrate 111 disposed in a plurality of sub-pixels SP and an encapsulation layer 200 on the substrate 111 .

[0099] Here, the encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation portion.

[0100] Reference Figure 2When the display device 100 according to an embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP provided on the substrate 111 may include a light emitting element ED and a sub-pixel circuit SPC for driving the light emitting element ED.

[0101] Reference Figure 2 , the sub-pixel circuit SPC may include a plurality of pixel driving transistors for driving the light emitting element ED and at least one capacitor.

[0102] In the present disclosure, the sub-pixel circuit SPC may drive the light emitting element ED by supplying a driving current to the light emitting element ED at a predetermined timing.

[0103] The light emitting element ED can be driven by a driving current to emit light.

[0104] The plurality of pixel driving transistors may include a driving transistor DT for driving the light emitting element ED and a scanning transistor ST that is turned on or off according to a scanning signal SC.

[0105] The driving transistor DT may supply a driving current to the light emitting element ED.

[0106] The scan transistor ST may control an electrical state of a corresponding node in the sub-pixel circuit SPC or control a state or operation of the drive transistor DT.

[0107] The at least one capacitor may include a storage capacitor Cst for maintaining a constant voltage during one frame.

[0108] To drive the sub-pixel SP, a data signal VDATA as an image signal and a scan signal SC as a gate signal may be applied to the sub-pixel SP.

[0109] In addition, to drive the sub-pixel SP, a common pixel driving voltage including a first common driving voltage VDD and a second common driving voltage VSS may be applied to the sub-pixel SP.

[0110] The light emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. However, the present disclosure is not limited thereto. In one embodiment, the light emitting element ED may include a first electrode layer, a light emitting layer, and a second electrode layer.

[0111] The intermediate layer EL may be located between the pixel electrode PE and the common electrode CE.

[0112] For example, the pixel electrode PE may be an anode AND, and the common electrode CE may be a cathode CAT.

[0113] On the contrary, the pixel electrode PE may be the cathode CAT, and the common electrode CE may be the anode AND.

[0114] Hereinafter, for convenience of description, an example in which the pixel electrode PE is the anode AND and the common electrode CE is the cathode CAT is described.

[0115] When the light emitting element ED is an organic light emitting element, the intermediate layer EL may include a light emitting layer EML, a first common intermediate layer COM1 between the anode AND and the light emitting layer EML, and a second common intermediate layer COM2 between the light emitting layer EML and the cathode CAT.

[0116] A light emitting layer EML may be provided for each sub-pixel SP.

[0117] In contrast, the first common intermediate layer COM1 and the second common intermediate layer COM2 may be disposed together over the plurality of sub-pixels SP.

[0118] The light emitting layer EML may be provided for each light emitting region, and the first common intermediate layer COM1 and the second common intermediate layer COM2 may be commonly provided over the plurality of light emitting regions and non-light emitting regions.

[0119] The first common intermediate layer COM1 and the second common intermediate layer COM2 may be collectively referred to as a common intermediate layer EL_COM.

[0120] For example, the first common intermediate layer COM1 may include a hole injection layer HIL and a hole transport layer HTL.

[0121] The second common intermediate layer COM2 may include an electron transport layer ETL and an electron injection layer EIL.

[0122] The hole injection layer can inject holes from the anode AND into the hole transport layer, and the hole transport layer can transport holes to the light-emitting layer EML. The electron injection layer can inject electrons from the cathode CAT into the electron transport layer, and the electron transport layer can transport electrons to the light-emitting layer EML.

[0123] For example, the cathode CAT may be electrically connected to the second common driving voltage line VSSL.

[0124] A second common driving voltage VSS, which is a common pixel driving voltage, may be applied to the cathode CAT through a second common driving voltage line VSSL.

[0125] The anode AND may be electrically connected to the first node N1 of the driving transistor DT of each sub-pixel SP.

[0126] In the present disclosure, the “second common driving voltage VSS” may also be referred to as a “basic voltage VSS”, and the “second common driving voltage line VSSL” may also be referred to as a “basic voltage line VSSL”.

[0127] For example, the pixel electrode PE may be an electrode provided in each sub-pixel SP, and the common electrode CE may be an electrode commonly provided in all sub-pixels SP.

[0128] Each light emitting element ED may include a portion where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap.

[0129] Each light emitting element ED can form a predetermined light emitting area.

[0130] For example, the light emitting region of each light emitting element ED may include a region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap.

[0131] For example, the light emitting element ED may be an organic light emitting diode (OLED), an inorganic light emitting diode (LED), or a quantum dot (QD) light emitting element.

[0132] For example, when the light emitting element ED is an organic light emitting diode (OLED), the intermediate layer EL of the light emitting element ED may include an intermediate layer EL including an organic material.

[0133] The driving transistor DT may be a driving transistor for supplying a driving current to the light emitting element ED.

[0134] The driving transistor DT may be connected between the first common driving voltage line VDDL and the light emitting element ED.

[0135] The driving transistor DT may include a first node N1 electrically connected to the light emitting element ED, a second node N2 to which the data signal VDATA may be applied, and a third node N3 to which the driving voltage VDD is applied from the driving voltage line DVL.

[0136] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node.

[0137] Hereinafter, for convenience of description, an example is described in which, in the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node, and the third node N3 may be a drain node.

[0138] Reference Figure 2 , the scan transistor ST included in the sub-pixel circuit SPC may be a switching transistor for transmitting the data signal VDATA (which is an image signal) to the second node N2 (which is the gate node of the driving transistor DT).

[0139] The scan transistor ST may be controlled to be turned on and off by a scan signal SC, which is a gate signal applied through a scan line SCL, which is a type of gate line GL, to control electrical connection between the second node N2 of the drive transistor DT and the data line DL.

[0140] A drain or source of the scan transistor ST may be electrically connected to the data line DL, a source or drain of the scan transistor ST may be electrically connected to the second node N2 of the drive transistor DT, and a gate of the scan transistor ST may be electrically connected to the scan line SCL.

[0141] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT.

[0142] The storage capacitor Cst may include a first capacitor electrode electrically connected to or corresponding to the first node N1 of the driving transistor DT and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the driving transistor DT.

[0143] The capacitor Cst may be an external capacitor intentionally designed to be outside the driving transistor DT, rather than a parasitic capacitor (eg, Cgs or Cgd) that is an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DT.

[0144] Each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor.

[0145] The display panel 110 may have a top emission structure or a bottom emission structure.

[0146] When the display panel 110 has a top emission structure, at least a portion of the sub-pixel circuit SPC may overlap with at least a portion of the light emitting element ED in a vertical direction.

[0147] In contrast, when the display panel 110 has a bottom emission structure, the sub-pixel circuit SPC may not overlap with the light emitting element ED in the vertical direction.

[0148] like Figure 2 As shown, the sub-pixel circuit SPC may have a 2T (transistor) 1C (capacitor) structure including two transistors DT and ST and one capacitor Cst. In some cases, the sub-pixel circuit SPC may further include one or more transistors or one or more capacitors.

[0149] For example, the sub-pixel circuit SPC may have an 8T1C structure including 8 transistors and 1 capacitor.

[0150] As another example, the sub-pixel circuit SPC may have a 6T2C structure including 6 transistors and 2 capacitors.

[0151] As another example, the sub-pixel circuit SPC may have a 7T1C structure including 7 transistors and 1 capacitor.

[0152] According to the structure of the sub-pixel circuit SPC, the type and number of gate lines or gate signals supplied to the sub-pixels SP may vary.

[0153] In addition, the type and amount of the common pixel driving voltage supplied to the sub-pixel SP may vary according to the structure of the sub-pixel circuit SPC.

[0154] Since the circuit elements in each subpixel SP (especially the light-emitting elements implemented as organic light-emitting diodes containing organic materials) are susceptible to external moisture or oxygen, an encapsulation layer 200 for preventing external moisture or oxygen from penetrating into the circuit elements (especially the light-emitting elements) can be provided on the display panel 110.

[0155] The encapsulation layer 200 may be configured in various forms so that the light emitting element ED does not come into contact with moisture or oxygen.

[0156] Reference Figure 2 The display device 100 according to an embodiment of the present disclosure may further include a touch sensor layer 210 having a plurality of sensor electrodes and a touch sensing circuit 220 configured to sense the plurality of sensor electrodes to determine the presence or absence of a touch or the coordinates of the touch.

[0157] The touch sensor layer 210 may be built into the display panel 110 .

[0158] For example, the touch sensor layer 210 may be provided on the encapsulation layer 200 in the display panel 110 .

[0159] The display panel 110 may include not only a touch sensor layer 210, but also a plurality of touch pads electrically connected to the touch sensing circuit 220, and a plurality of touch routing lines TL for electrically connecting the plurality of sensor electrodes included in the touch sensor layer 210 to the plurality of touch pads connected to the touch sensing circuit 220.

[0160] The display device 100 according to an embodiment of the present disclosure may have an extremely narrow bezel structure in which the non-display area NDA of the display panel 110 is very small or almost non-existent.

[0161] Hereinafter, an extremely narrow bezel structure of the display panel 110 of the display device 100 according to an embodiment of the present disclosure is described.

[0162] Figure 3is a plan view of a display panel 110 according to an embodiment of the present disclosure.

[0163] Reference Figure 3 , the substrate 111 of the display panel 110 according to an embodiment of the present disclosure may include a display area DA that may display an image and a non-display area NDA that does not display an image.

[0164] Reference Figure 3 The non-display area NDA may include a first non-display area NDA1 arranged along a first direction from the display area DA, a second non-display area NDA2 arranged along a second direction from the display area DA, a third non-display area NDA3 arranged along a direction opposite to the first direction from the display area DA, and a fourth non-display area NDA4 arranged along a direction opposite to the second direction from the display area DA.

[0165] For example, the first direction may be a column direction (Y-axis direction), and the second direction intersecting the first direction may be a row direction (X-axis direction).

[0166] The first non-display area NDA1 may include a pad area PA where a plurality of pads are provided.

[0167] In the pad area PA, a plurality of pads electrically connected to the driving circuit may be provided.

[0168] A plurality of driving circuits or printed circuit boards may be electrically connected.

[0169] For example, the plurality of pads may include a plurality of display pads and a plurality of touch pads.

[0170] A plurality of data lines, a first common driving voltage line VDDL, a second common driving voltage line VSSL, etc. may be electrically connected to the plurality of display pads.

[0171] The plurality of touch routing lines TL may be electrically connected to the plurality of touch pads.

[0172] The first non-display area NDA1 may further include a bending area BA.

[0173] In this case, the substrate 111 may be a flexible substrate.

[0174] In some cases, the first non-display area NDA1 may not include the bending area BA.

[0175] The display panel 110 may further include a ground line disposed in the non-display area NDA of the substrate 111 .

[0176] The ground line may be provided from one point of the pad area PA to another point of the pad area PA via the second non-display area NDA2 , the third non-display area NDA3 , and the fourth non-display area NDA4 .

[0177] Figure 4A 、 Figure 4B and Figure 4C Along the Figure 3 Cross-sectional views taken along lines I-I', II-II', and III-III'.

[0178] Figure 4A It is along Figure 3 A cross-sectional view taken along line II'. Figure 4B It is along Figure 3 A cross-sectional view taken along line II-II'. Figure 4C It is along Figure 3 A cross-sectional view taken along line III-III'.

[0179] Reference Figure 4A , the display panel 110 according to an embodiment of the present disclosure may include transistors TFT1 and TFT2 , a light emitting element ED, and encapsulation layers PAS1 , PCL, and PAS2 from a vertical structural perspective.

[0180] The substrate can be single-layer or multi-layer.

[0181] When the substrate includes multiple layers, the substrate may include a first substrate PI1, a substrate intermediate layer IPD, and a second substrate PI2.

[0182] The substrate intermediate layer IPD may be located between the first substrate PI1 and the second substrate PI2.

[0183] For example, each of the first substrate PI1 and the second substrate PI2 may be a polyimide layer.

[0184] The intermediate substrate layer IPD may be an inorganic insulating layer.

[0185] When the first substrate PI1 as a polyimide layer is charged with charges, the substrate intermediate layer IPD may prevent the charges from affecting transistors provided on the second substrate PI2 through the second substrate PI2 as a polyimide layer.

[0186] In addition, the substrate intermediate layer IPD may prevent moisture and the like from penetrating upward through the first substrate PI1.

[0187] For example, the substrate intermediate layer IPD can be made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or a single layer or a multilayer thereof, or may be formed of silicon dioxide (SiO2) and silicon nitride (SiN x ) is formed by a double layer, but is not limited thereto.

[0188] The transistor may include a first transistor TFT1 and a second transistor TFT2.

[0189] The first transistor TFT1 may include a first active layer ACT1 , a first electrode E1 a , a second electrode E1 b , and a third electrode E1 c .

[0190] The first active layer ACT1 may be a first semiconductor layer, but embodiments of the present disclosure are not limited thereto.

[0191] For example, the first active layer ACT1 may be formed of an oxide semiconductor, amorphous silicon, polycrystalline silicon, or low temperature polycrystalline silicon (LTPS), but is not limited thereto.

[0192] The first transistor TFT1 may be implemented as a p-channel transistor or an n-channel transistor, but is not limited thereto.

[0193] The first electrode E1 a may be a gate electrode, the second electrode E1 b may be a source electrode or a drain electrode, and the third electrode E1 c may be a drain electrode or a source electrode.

[0194] Hereinafter, for convenience of description, an example is described in which the first electrode E1a is the first gate E1a, the second electrode E1b is the first source E1b, and the third electrode E1c is the first drain E1c, but the present disclosure is not limited thereto.

[0195] The second transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c.

[0196] The second active layer ACT2 may be a second semiconductor layer, but the embodiments of the present disclosure are not limited thereto.

[0197] For example, the second active layer ACT2 may be formed of an oxide semiconductor, amorphous silicon, polycrystalline silicon, or low temperature polycrystalline silicon (LTPS), but is not limited thereto.

[0198] The second transistor TFT2 may be implemented as a p-channel transistor or an n-channel transistor, but is not limited thereto.

[0199] For example, one of the first transistor TFT1 and the second transistor TFT2 may use an oxide semiconductor as an active layer.

[0200] As another example, one of the first transistor TFT1 and the second transistor TFT2 may use low-temperature polysilicon as an active layer.

[0201] As another example, the first transistor TFT1 and the second transistor TFT2 may use an oxide semiconductor as an active layer.

[0202] As another example, the first transistor TFT1 and the second transistor TFT2 may use low-temperature polysilicon as an active layer.

[0203] As another example, in the first transistor TFT1 and the second transistor TFT2 , the driving transistor DT may use an oxide semiconductor as an active layer, and the scanning transistor ST may use low-temperature polysilicon as an active layer.

[0204] As another example, in the first transistor TFT1 and the second transistor TFT2 , the driving transistor DT may use low-temperature polysilicon as an active layer, and the scanning transistor ST may use an oxide semiconductor as an active layer.

[0205] As another example, a transistor included in a gate-in-panel (GIP) type gate driving circuit may include an oxide semiconductor or low-temperature polysilicon as an active layer.

[0206] As another example, all transistors arranged on a substrate and transistors included in a gate-in-panel (GIP) type gate driving circuit may use an oxide semiconductor as an active layer.

[0207] The fourth electrode E2a may be a gate electrode, the fifth electrode E2b may be a source electrode or a drain electrode, and the sixth electrode E2c may be a drain electrode or a source electrode.

[0208] Hereinafter, for convenience of description, an example is described in which the fourth electrode E2a is the second gate E2a, the fifth electrode E2b is the second source E2b, and the sixth electrode E2c is the second drain E2c, but the present disclosure is not limited thereto.

[0209] The second active layer ACT2 of the second transistor TFT2 may be disposed higher from the substrate than the first active layer ACT1 of the first transistor TFT1 .

[0210] The second buffer layer BUF2 may be disposed under the first active layer ACT1 of the first transistor TFT1 , and the second insulating layer ILD2 may be disposed under the second active layer ACT2 of the second transistor TFT2 .

[0211] For example, the first active layer ACT1 of the first transistor TFT1 may be located on the second buffer layer BUF2 , and the second active layer ACT2 of the second transistor TFT2 may be located on the second insulating layer ILD2 .

[0212] The second insulating layer ILD2 may be disposed higher than the second buffer layer BUF2 .

[0213] The storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0214] At least one planarization layer PLN1 and PLN2 may be disposed on the transistors TFT1 and TFT2 .

[0215] The light emitting element ED may be disposed on at least one planarization layer PLN1 and PLN2 .

[0216] The light emitting element ED may be a plurality of light emitting diodes.

[0217] Each of the plurality of light emitting diodes ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0218] The encapsulation layers PAS1 , PCL, and PAS2 may be located on the light emitting element ED.

[0219] The encapsulation layer can be a single layer or multiple layers.

[0220] Reference Figure 4A , buffer layers BUF1 and BUF2 may be disposed on the substrate.

[0221] The buffer layer can be a single layer or multiple layers.

[0222] When the buffer layer includes a plurality of layers, the buffer layer may include a first buffer layer BUF1 and a second buffer layer BUF2 .

[0223] The first active layer ACT1 of the first transistor TFT1 may be disposed on the second buffer layer BUF2 .

[0224] The first active layer ACT1 may include a channel region in which a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0225] A first gate insulating layer GI1 may be disposed on the first active layer ACT1 of the first transistor TFT1.

[0226] A first gate electrode E1 a of the first transistor TFT1 may be disposed on the first gate insulating layer GI1 .

[0227] A first insulating layer ILD1 may be disposed on the first gate electrode E1 a of the first transistor TFT1 .

[0228] The second insulating layer ILD2 may be disposed on the first insulating layer ILD1 .

[0229] The second active layer ACT2 of the second transistor TFT2 may be disposed on the second insulating layer ILD2 .

[0230] The second active layer ACT2 may include a channel region forming a channel, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0231] A third insulating layer ILD3 may be disposed on the second active layer ACT2 of the second transistor TFT2 .

[0232] A third insulating layer ILD3 may be disposed on the second gate electrode E2 a of the second transistor TFT2 .

[0233] The first source electrode E1 b and the first drain electrode E1 c of the first transistor TFT1 , and the second source electrode E2 b and the second drain electrode E2 c of the second transistor TFT2 may be disposed on the third insulating layer ILD3 .

[0234] The first source E1b and the first drain E1c of the first transistor TFT1 may be respectively connected to the source connection region and the drain connection region of the first active layer ACT1 through holes of the third insulating layer ILD3 , the second gate insulating layer GI2 , the second insulating layer ILD2 , the first insulating layer ILD1 , and the first gate insulating layer GI1 .

[0235] The second source electrode E2 b and the second drain electrode E2 c of the second transistor TFT2 may be respectively connected to the source connection region and the drain connection region of the second active layer ACT2 through the holes of the third insulating layer ILD3 and the second gate insulating layer GI2 .

[0236] The first source electrode E1 b and the first drain electrode E1 c of the first transistor TFT1 , and the second source electrode E2 b and the second drain electrode E2 c of the second transistor TFT2 may include a first metal and may be provided in a first metal layer.

[0237] Here, the first metal and the first metal layer may also be referred to as a first source-drain metal and a first source-drain metal layer.

[0238] Reference Figure 4A , for example, the storage capacitor Cst may be formed of a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0239] In some cases, the storage capacitor Cst may be formed of three or more capacitor electrodes, or may have a form in which two or more capacitors are connected in parallel.

[0240] Each of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 may be disposed on a respective metal layer provided in the display panel.

[0241] For example, the first capacitor electrode CAPE1 may include the same first gate metal as the first gate E1 a of the first transistor TFT1 on the first gate insulating layer GI1 and may be provided in a first gate metal layer.

[0242] For example, the second capacitor electrode CAPE2 may be disposed on the first insulating layer ILD1 .

[0243] For example, the first transistor TFT1 may be Figure 2The scanning transistor ST, the second transistor TFT2 can be Figure 2 The driving transistor DT.

[0244] Reference Figure 4A , the first light blocking layer BSM1 may overlap with the first active layer ACT1 of the first transistor TFT1 and may be disposed under the first active layer ACT1 of the first transistor TFT1.

[0245] For example, the first light blocking layer may be disposed between the first buffer layer BUF1 and the second buffer layer BUF2 .

[0246] Reference Figure 4A , the second light blocking layer BSM2 may overlap with the second active layer ACT2 of the second transistor TFT2 and may be disposed under the second active layer ACT2 of the second transistor TFT2.

[0247] For example, the second light blocking layer BSM2 may be disposed between the first insulating layer ILD1 and the second insulating layer ILD2 .

[0248] For example, the second light blocking layer BSM2 may be provided in the same metal layer as the second capacitor electrode CAPE2.

[0249] Meanwhile, at least one planarization layer PLN1 and PLN2 may be disposed on the first transistor TFT1 and the second transistor TFT2 .

[0250] exist Figure 4A , an example in which two planarization layers PLN1 and PLN2 are provided on the first transistor TFT1 and the second transistor TFT2 is described, but the present disclosure is not limited thereto, and three planarization layers may be provided.

[0251] Reference Figure 4A , a first planarization layer PLN1 may be disposed on the first transistor TFT1 and the second transistor TFT2 .

[0252] For example, the first planarization layer PLN1 may be provided to cover both the first transistor TFT1 and the second transistor TFT2 .

[0253] Reference Figure 4A , the relay electrode RE may be disposed on the first planarization layer PLN1 .

[0254] The relay electrode RE may be electrically connected to the second source electrode E2 b of the second transistor TFT2 through the hole of the first planarization layer PLN1 .

[0255] Here, the second source electrode E2 b of the second transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 of the storage capacitor Cst.

[0256] The relay electrode RE may be disposed in the second metal layer on the first planarization layer PLN1 and may include a second metal.

[0257] The second metal and the second metal layer may also be referred to as a second source-drain metal and a second source-drain metal layer.

[0258] The second planarization layer PLN2 may be disposed on the relay electrode RE.

[0259] Reference Figure 4A , the light emitting element ED can be set on the second planarization layer PLN2.

[0260] The light emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0261] A light emitting region of the light emitting element ED may be formed in a region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap and contact each other.

[0262] The pixel electrode PE may be disposed on the second planarization layer PLN2 , and the bank layer BNK may be disposed on the pixel electrode PE.

[0263] The opening area of ​​the bank layer BNK may be substantially the same as the light emitting area.

[0264] The intermediate layer EL of the light emitting element ED may be disposed on a portion of the pixel electrode PE and the bank layer BNK.

[0265] The common electrode CE may be disposed on the intermediate layer EL.

[0266] Reference Figure 4A , the encapsulation layers PAS1 , PCL and PAS2 may be disposed on the common electrode CE.

[0267] The encapsulation layer can prevent moisture or oxygen from penetrating into the light emitting element ED.

[0268] For example, the encapsulation layer can prevent moisture or oxygen from penetrating into the organic material included in the intermediate layer EL of the light emitting element ED.

[0269] Here, the encapsulation layer may be composed of a single layer or multiple layers, but is not limited thereto.

[0270] Reference Figure 4A , for example, the encapsulation layer may include a first inorganic encapsulation layer PAS1 , an organic encapsulation layer PCL, and a second inorganic encapsulation layer PAS2 .

[0271] Reference Figure 4A, at least one planarization layer PLN1 or PLN2 may include at least one concave portion CNC in a region adjacent to a boundary between the display area DA and the second non-display area NDA2 or in the second non-display area NDA2. Figure 4A As shown, the concave portion CNC is located in the display area DA at a position close to the boundary between the display area DA and the second non-display area NDA2.

[0272] exist Figure 4A , an example is described in which the concave portion CNC includes the flat portion FLT and the first and second side portions SLO1 and SLO2 surrounding the flat portion FLT.

[0273] exist Figure 4A , an example is described in which the first side portion SLO1 and the second side portion SLO2 are partial regions of the side surface of the second planarization layer PLN2 and the flat portion FLT is a partial region of the upper surface of the first planarization layer PLN1.

[0274] Reference Figure 4A , the first inorganic encapsulation layer PAS1 of the encapsulation layer may include at least one uneven portion UE. When the first inorganic encapsulation layer PAS1 covers the concave portion CNC, the at least one uneven portion UE is located in the concave portion CNC. The at least one uneven portion UE may also be referred to as an uneven pattern UE. Figure 4A As shown, in one embodiment, an uneven pattern UE may be formed at an interface between the first inorganic encapsulation layer PAS1 and the organic encapsulation layer PCL.

[0275] The uneven portion UE may be disposed lower than the bank layer BNK, but is not limited thereto. That is, the concave portion CNC is formed in the second planarization layer PLN2 (which is a lower layer of the bank layer BNK) and may be located lower than the bank layer BNK.

[0276] When the uneven portion UE is provided in the concave portion CNC, a movement path of moisture penetrating to the surfaces of the first inorganic encapsulating layer PAS1 and the organic encapsulating layer PCL may be increased to delay moisture penetration and enhance reliability of the display panel 110 .

[0277] Reference Figure 4B , the first transistor TFT1 and the storage capacitor Cst may not be arranged in reference Figure 4A of the components described.

[0278] In reference Figure 4A Among the components described, except for matters concerning the first transistor TFT1 and the storage capacitor Cst, Figure 4B The components can be used with Figure 4A Basically the same.

[0279] Reference Figure 4C, except for the pads PAD located in the pad area PA, Figure 4C The components can be compared with the reference Figure 4A The components described are essentially the same.

[0280] Reference Figure 4C , a plurality of pads PAD electrically connected to the driving circuit may be provided in the pad area PA.

[0281] The plurality of pads PAD of the pad area PA may be located in the first non-display area NDA1 .

[0282] A plurality of pads PAD of the pad area PA may be located on the substrates PI1 , IPD, and PI2 .

[0283] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D and Figure 7 yes Figure 4A An enlarged cross-sectional view of portion A of FIG.

[0284] Figure 5A and Figure 5B The first inorganic encapsulation layer PAS1 including at least one uneven portion UE1 and UE2 in the concave portion CNC while covering the concave portion CNC is illustrated.

[0285] The uneven parts UE1 and UE2 may be formed in a pillar shape through a dry etching process, but are not limited thereto.

[0286] Reference Figure 5A , the first uneven portion UE1 may have a structure in which an upper end of a protrusion is recessed inward.

[0287] Reference Figure 5B , the second uneven portion UE2 may have a shape of protruding edge portions and a hollow center portion.

[0288] Figure 5A An example including only the first uneven portion UE1 is shown, and Figure 5B An example including only the second uneven portion UE2 is shown. However, the first uneven portion UE1 and the second uneven portion UE2 may be randomly distributed, or uneven portions having shapes other than the first uneven portion UE1 or the second uneven portion UE2 may be formed, so that various combinations of uneven portions are possible by adjusting the dry etching process.

[0289] In addition, the manufacturing method of forming the uneven portion is not limited to the dry etching process, and various other manufacturing methods may be used, for example, by forming an uneven shape using impurities as a stopper.

[0290] Figure 5A and Figure 5B It is shown that the uneven portions UE1 and UE2 are located only in the flat portion FLT of the concave portion CNC, but this is exemplary and not limited thereto. Figure 5C As shown, it may also be located in the first side portion SLO1 or the second side portion SLO2.

[0291] Figures 5A to 5C A structure in which the organic encapsulation layer PCL covers the uneven portions UE1 and UE2 located in the concave portion CNC is shown, but is not limited thereto, and the uneven portions UE1 and UE2 that do not overlap with the organic encapsulation layer PCL may exist.

[0292] Reference Figure 5D The organic encapsulation layer PCL may cover the concave portion CNC located closest to the bank layer BNK among the concave portions, but may not cover the concave portion CNC located outside the concave portion CNC located closest to the bank layer BNK.

[0293] Reference Figure 5D , in a region where the organic encapsulating layer PCL does not cover the uneven portion UE1 of the first inorganic encapsulating layer PAS1 , the second inorganic encapsulating layer PAS2 may be positioned on the first inorganic encapsulating layer PAS1 .

[0294] Here, the second inorganic encapsulating layer PAS2 may also be formed in an uneven shape along the uneven shape of the first inorganic encapsulating layer PAS1.

[0295] Reference Figure 6A , the first inorganic encapsulation layer PAS1 may include at least one hole H on the bank layer BNK. That is, the at least one hole H may be formed in the first inorganic encapsulation layer PAS1 and expose the upper surface of the bank layer BNK.

[0296] At least one hole H may be located in the display area DA.

[0297] The pattern layer FPL containing fluorine may be included in the at least one hole H.

[0298] The organic encapsulation layer PCL may cover the at least one hole H and the pattern layer FPL in the hole H.

[0299] The pattern layer FPL may be located on the same layer as the first inorganic encapsulation layer PAS1 .

[0300] The pattern layer FPL may be a polymer, a single molecule, or a composite including at least one fluorine atom.

[0301] For example, the pattern layer FPL may be a polymer based on a carbon-carbon backbone including at least one fluorine atom.

[0302] As another example, the pattern layer FPL may be a single molecule or a composite including at least one fluorine atom based on a carbon-carbon skeleton.

[0303] When the pattern layer FPL located on the same layer as the first inorganic encapsulating layer PAS1 includes fluorine, moisture may be prevented from penetrating into the interface between the bank layer BNK and the first inorganic encapsulating layer PAS1.

[0304] Reference Figure 6B , the first inorganic encapsulation layer PAS1 may include a burr B surrounding the at least one hole H.

[0305] The burr B may be formed of substantially the same material as the first inorganic encapsulation layer PAS1 .

[0306] The pattern layer FPL may be surrounded by the burr B while being located in the hole H.

[0307] Here, the organic encapsulation layer PCL may cover the burr B and the pattern layer FPL.

[0308] When the burrs B are provided to surround the pattern layer FPL, moisture penetration may be delayed by increasing a movement path of moisture penetrating to the interface between the first inorganic encapsulating layer PAS1 and the organic encapsulating layer PCL by the burrs B.

[0309] Reference Figure 6C , the dummy passivation layer DPAS including the first groove GRV1 may be located on the bank layer BNK. The dummy passivation layer DPAS may be disposed in the hole H.

[0310] The intermediate layer EL may be disposed on the dummy passivation layer DPAS, and the common electrode CE may be provided on the intermediate layer EL.

[0311] Here, the intermediate layer EL and the common electrode CE located in the first groove GRV1 and the intermediate layer EL and the common electrode CE located in a region other than the first groove GRV1 may not be connected to each other.

[0312] The first inorganic encapsulation layer PAS1 may cover the intermediate layer EL and the common electrode CE located in the first groove GRV1 , and the intermediate layer EL and the common electrode CE located in a region other than the first groove GRV1 .

[0313] When the first inorganic encapsulation layer PAS1 covers the intermediate layer EL and the common electrode CE located in the first groove GRV1 and the intermediate layer EL and the common electrode CE located in an area other than the first groove GRV1, the first inorganic encapsulation layer PAS1 may have a second groove GRV2 formed along the shape of the first groove GRV1.

[0314] The organic encapsulation layer PCL may cover the second groove GRV2 .

[0315] Reference Figure 6D , a first inorganic encapsulation layer PAS1 including at least one hole H may be positioned on the bank layer BNK.

[0316] Reference Figure 6D , the metal protrusion M can be located in the hole H.

[0317] The metal protrusion M may be located on the bank layer BNK.

[0318] The height of the metal protrusion M may be greater than the depth of the hole H.

[0319] In other words, the length t2 of the metal protrusion M may be greater than the depth t1 of the hole H.

[0320] The metal protrusions M may be a transition metal or an alloy thereof.

[0321] Preferably, the metal protrusion M may include titanium, but is not limited thereto.

[0322] Figure 6D An example is shown in which the metal protrusion M has a vertical tapered shape, but is not limited thereto and may have an inverted tapered shape.

[0323] When the metal protrusions M are provided in the holes H, moisture or hydrogen may be prevented from penetrating into the interface between the first inorganic encapsulating layer PAS1 and the organic encapsulating layer PCL.

[0324] Reference Figure 7 , a height h2 of the second side portion SLO2 may be greater than a height h1 of the first side portion SLO1 of the concave portion CNC.

[0325] When the height h2 of the second side portion SLO2 is greater than the height h1 of the first side portion SLO1 of the recess CNC, the planarization layer including the second side portion SLO2 can be used as a dam to prevent overflow into the outer area of ​​the non-display area when coating the organic encapsulation layer PCL, and can delay moisture penetration by increasing the movement path of moisture into the interface between the organic encapsulation layer PLC and the first inorganic encapsulation layer PAS1.

[0326] The embodiments of the present disclosure described above are briefly described below.

[0327] The present disclosure provides a display device including: a substrate; a first electrode layer disposed on the substrate; a dam layer disposed on the first electrode layer and configured to define a plurality of pixels; a light-emitting layer disposed on the dam layer; and an encapsulation layer disposed on the light-emitting layer, wherein the encapsulation layer includes a recess.

[0328] In one embodiment, a display device has a display area and a non-display area surrounding the display area, and wherein at least a portion of the recess is located in the display area.

[0329] In one embodiment, the display device further includes a planarization layer, the planarization layer is located between the substrate and the first electrode layer, wherein the concave portion is located in the planarization layer.

[0330] In one embodiment, the encapsulation layer includes: a first encapsulation layer formed of an inorganic material; and a second encapsulation layer formed of an organic material; wherein an uneven pattern is formed at an interface between the first encapsulation layer and the second encapsulation layer.

[0331] In one embodiment, the recess includes a first side portion, a flat portion, and a second side portion, and wherein an uneven pattern is formed at each of the first side portion, the flat portion, and the second side portion.

[0332] In one embodiment, the display device further includes a hole formed in the first encapsulation layer, and the hole exposes an upper surface of the bank layer.

[0333] In one embodiment, a pattern layer is formed in the hole.

[0334] In one embodiment, the pattern layer is formed of a polymer, a single molecule, or a composite, and contains fluorine.

[0335] In one embodiment, the display device further includes a burr formed on the first encapsulation layer and surrounding the hole.

[0336] In one embodiment, the display device further includes a dummy passivation layer disposed in the bank layer and including a first groove, and wherein the first encapsulation layer forms a second groove along an inner surface of the first groove.

[0337] In one embodiment, the display device further includes a metal protrusion disposed in the hole.

[0338] In one embodiment, the height of the metal protrusion is greater than the depth of the hole.

[0339] In one embodiment, the first side portion is farther away from the non-display area than the second side portion, and a height of the first side portion is smaller than a height of the second side portion.

[0340] A display device according to one embodiment of the present disclosure may include: a substrate, the substrate including a display area and a non-display area surrounding the display area; an insulating layer located on the substrate and including at least one recess in an area near a boundary between the display area and the non-display area or in the non-display area; a dam layer located in the display area, located on the insulating layer, and including an opening area; and an inorganic encapsulation layer located on the dam layer, covering the recess and including at least one uneven portion in the recess.

[0341] In the display device according to one embodiment of the present disclosure, the uneven portion may be located lower than the bank layer.

[0342] The display device according to one embodiment of the present disclosure may further include an organic encapsulation layer on the inorganic encapsulation layer. The organic encapsulation layer may cover a concave portion closest to the bank layer among the at least one concave portion.

[0343] In the display device according to one embodiment of the present disclosure, the inorganic encapsulation layer may include at least one hole on the bank layer, and may include a pattern layer including fluorine in the hole.

[0344] In the display device according to one embodiment of the present disclosure, the inorganic encapsulation layer may further include burrs surrounding the inorganic encapsulation layer.

[0345] The display device according to one embodiment of the present disclosure may further include an organic encapsulation layer located on the inorganic encapsulation layer. The organic encapsulation layer may cover the burrs and the pattern layer.

[0346] In the display device according to one embodiment of the present disclosure, the pattern layer may be located on the same layer as the inorganic encapsulation layer.

[0347] In a display device according to one embodiment of the present disclosure, the bank layer may include at least one first groove located between the opening region and the recessed portion. The display device may further include a passivation layer located on the bank layer, covering the at least one first groove and including at least one second groove located on the at least one first groove; and a dummy intermediate layer located on an upper surface of the passivation layer.

[0348] In a display device according to an embodiment of the present disclosure, the concave portion may include a first inclined portion adjacent to the opening area and a second inclined portion facing the first inclined portion. The second inclined portion may have a height greater than that of the first inclined portion.

[0349] In the display device according to one embodiment of the present disclosure, the inorganic encapsulation layer may include at least one hole on the bank layer, and may include a pattern layer in the hole, the pattern layer including a metal protrusion longer than a depth of the hole.

[0350] In the display device according to one embodiment of the present disclosure, the dummy intermediate layer located in the at least one second groove and the dummy intermediate layer located in a region outside the second groove may be disconnected from each other.

[0351] A display device according to one embodiment of the present disclosure may include a substrate including a display area and a non-display area surrounding the display area; an insulating layer located on the substrate and including an area located near a boundary between the display area and the non-display area or at least one recess in the non-display area; a dam layer located in the display area, located on the insulating layer, and including an opening area; an inorganic encapsulation layer including at least one hole located on the dam layer; and a pattern layer containing fluorine included in the hole.

[0352] In the display device according to one embodiment of the present disclosure, the inorganic encapsulation layer may further include burrs surrounding the inorganic encapsulation layer.

[0353] The display device according to one embodiment of the present disclosure may further include an organic encapsulation layer located on the inorganic encapsulation layer. The organic encapsulation layer may cover the burrs and the pattern layer.

[0354] In the display device according to one embodiment of the present disclosure, the pattern layer may be located on the same layer as the inorganic encapsulation layer.

[0355] According to one embodiment of the present disclosure, a display device may include: a substrate, the substrate including a display area and a non-display area surrounding the display area; a embankment layer, located in the display area, located on the insulating layer, including an opening area, and including at least one first groove located between the opening area and the recess; a passivation layer located on the embankment layer, covering the at least one first groove, and including at least one second groove located on the at least one first groove; and a dummy intermediate layer located on the upper surface of the passivation layer.

[0356] In a display device according to an embodiment of the present disclosure, the concave portion may include a first inclined portion adjacent to the opening area and a second inclined portion facing the first inclined portion. The second inclined portion may have a height greater than that of the first inclined portion.

[0357] The display device according to one embodiment of the present disclosure may further include: an inorganic encapsulation layer located on the dummy intermediate layer and covering the second groove. The inorganic encapsulation layer may include at least one hole located on the bank layer; and a pattern layer further including a metal protrusion included in the hole.

[0358] In the display device according to one embodiment of the present disclosure, the dummy intermediate layer located in the at least one second groove and the dummy intermediate layer located in a region outside the second groove may be disconnected from each other.

[0359] The above description has been provided to enable those skilled in the art to make and use the technical concepts of the present disclosure, and has been provided in the context of specific applications and their requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical concepts of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the present disclosure.

Claims

1. A display device comprising: substrate; a first electrode layer, disposed on the substrate; a bank layer disposed on the first electrode layer and configured to define a plurality of sub-pixels; a light-emitting layer, disposed on the bank layer; as well as an encapsulation layer, disposed on the light-emitting layer, Wherein, the encapsulation layer includes a concave portion.

2. The display device according to claim 1, wherein The display device has a display area and a non-display area surrounding the display area, and Wherein, at least a portion of the recess is located in the display area.

3. The display device according to claim 1 , further comprising a planarization layer located between the substrate and the first electrode layer, and in, The recess is located in the planarization layer.

4. The display device according to claim 1, wherein The encapsulation layer includes: a first encapsulation layer formed of an inorganic material; a second encapsulation layer, disposed on the first encapsulation layer and formed of an organic material; An uneven pattern is formed at an interface between the first encapsulation layer and the second encapsulation layer.

5. The display device according to claim 4, wherein: The recess includes a first side portion, a flat portion, and a second side portion, and The uneven pattern is formed at each of the first side portion, the flat portion, and the second side portion. 6 . The display device of claim 2 , further comprising a hole formed in the first encapsulation layer in the display area, and the hole exposes an upper surface of the bank layer.

7. The display device according to claim 6, wherein: A pattern layer is formed in the hole.

8. The display device according to claim 7, wherein: The pattern layer is formed of a polymer, a single molecule or a composite, and contains fluorine. 9 . The display device of claim 6 , further comprising a burr protruding from an upper surface of the first encapsulation layer and surrounding the hole.

10. The display device of claim 6, further comprising a dummy passivation layer disposed in the bank layer and comprising a first groove in the hole, and in, The first encapsulation layer forms a second groove along an inner surface of the first groove.

11. The display device of claim 6, further comprising a metal protrusion disposed in the hole.

12. The display device according to claim 11, wherein The height of the metal protrusion is greater than the depth of the hole.

13. The display device according to claim 5, wherein The first side portion is farther away from the non-display area than the second side portion, and Wherein, the height of the first side portion is smaller than the height of the second side portion.

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