Display device

Abstract

A display device is provided. The display device includes a substrate on which a plurality of sub-pixels are disposed, and which includes a first display area including a first light emitting area, a second light emitting area, and a transmission area, and a second display area surrounding the first display area. Each of the sub-pixels disposed on the second display area includes: a first thin film transistor and a second thin film transistor; a first light emitting diode; a second light emitting diode; and a first lens and a second lens. Each of the sub-pixels disposed in the first light emitting region includes: a third thin film transistor; a third light emitting diode; and a third lens. Each of the sub-pixels disposed in the second light emitting region includes: a fourth thin film transistor; a fourth light emitting diode; and a fourth lens.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0030309 filed on February 29, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and particularly to improvement in the lifespan of a display device capable of selectively controlling a viewing angle. Background Art

[0004] The field of display devices that visually display electrical information signals has been rapidly developed, and various display devices have been studied to improve thinness, weight reduction, and performance such as low power consumption of the display devices.

[0005] Typical display devices may include a liquid crystal display (LCD) device, a field emission display (FED) device, an electrowetting display (EWD) device, an organic light emitting display (OLED) device, and the like.

[0006] Unlike liquid crystal displays (LCDs), field emission displays (FETs), which are typical organic light-emitting displays, do not require a separate light source. This allows for lightweight and thin displays. Furthermore, due to their low-voltage operation, FETs offer excellent color reproduction, response speed, viewing angle, contrast ratio (CR), and power consumption, and are expected to be used in various fields.

[0007] In recent years, the multimedia functionality of mobile terminals has been improved. For example, a display device has been developed that has an optical electronic device, such as a camera or sensor, substantially built on its front surface. However, the camera or sensor disposed on the front surface of the display device may limit the screen design. In order to reduce the space occupied by the camera or sensor on the front surface of the display device, a design including a notch or perforation may be applied, but the size of the screen is still limited, making it difficult to achieve a full-screen display.

[0008] In order to achieve full-screen display, an area where low-resolution pixels are arranged may be provided in the screen of the display device, and a camera and / or various types of sensors may be provided in the area where the low-resolution pixels are provided.

[0009] Furthermore, with the advancement of modern technology, display devices are used to provide information to users in various ways. Display devices include various electronic devices that require technology for checking user input and providing information in response to the checked input, and electronic display boards that simply transmit visual information in one direction.

[0010] As described above, the viewing angle of the display device is not limited, but for reasons such as privacy protection and information protection, it is necessary to selectively limit the viewing angle of the display device when necessary. Summary of the Invention

[0011] An object of the present disclosure is to provide a display device that can improve the resolution of a transmissive region provided with an optical electronic device such as an imaging device or a sensor.

[0012] Another object of the present disclosure is to provide a display device that can selectively limit the viewing angle.

[0013] Yet another object of the present disclosure is to provide a display device that can ensure improved lifespan.

[0014] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above may be clearly understood by those skilled in the art from the following description.

[0015] A display device according to one embodiment includes a substrate on which a plurality of sub-pixels are arranged. The substrate includes a first display area including a first light-emitting area, a second light-emitting area, and a transmissive area, and includes a second display area surrounding the first display area. Each sub-pixel arranged in the second display area includes: a first thin-film transistor (TFT); a second thin-film transistor (TFT); a first light-emitting diode (LED); a first anode electrode connected to the first thin-film transistor; a first light-emitting layer; and a cathode electrode; a second light-emitting diode (LED); a second anode electrode connected to the second thin-film transistor; a second light-emitting layer; and a cathode electrode, and emitting light of the same color as that of the first LED; and a lens layer including a first lens corresponding to the first LED and refracting light from the first LED, and a second lens corresponding to the second LED and refracting light from the second LED. Each of the sub-pixels arranged in the first light-emitting area includes: a third thin film transistor; a third light-emitting diode including a third anode electrode connected to the third thin film transistor, a third light-emitting layer, and a cathode electrode; and a third lens corresponding to the third light-emitting diode and refracting light from the third light-emitting diode, and each of the sub-pixels arranged in the second light-emitting area includes: a fourth thin film transistor; a fourth light-emitting diode including a fourth anode electrode connected to the fourth thin film transistor, a fourth light-emitting layer, and a cathode electrode; and a fourth lens corresponding to the fourth light-emitting diode and refracting light from the fourth light-emitting diode.

[0016] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0017] According to the present disclosure, the camera or the sensor may be provided at the lower end of the light emitting diode or the touch electrode in the display area, thereby preventing the display on the camera or the touch on the sensor from being cut off / disconnected.

[0018] According to the present disclosure, it is possible to improve the resolution of a transmission region where an optical electronic device such as an imaging device or a sensor is provided.

[0019] According to the present disclosure, the aperture ratio of a display device can be improved, and the current density supplied to a sub-pixel can be reduced, thereby ensuring improvement in the lifespan of a light emitting diode.

[0020] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0022] Figures 1A to 1D is a schematic plan view of a display device according to an embodiment;

[0023] Figure 2 is a system block diagram of a display device according to an embodiment;

[0024] Figure 3 is a diagram illustrating an example of arrangement of sub-pixels in a display area according to an embodiment;

[0025] Figure 4 is a plan view of a pixel in a normal area of ​​a display device according to an embodiment;

[0026] Figure 5 It is along Figure 4 A-A' and BB' cross-sectional views;

[0027] Figure 6 is a plan view of a pixel of a first optical region of a display device according to an embodiment;

[0028] Figure 7 It is along Figure 6 C-C' cross-sectional view;

[0029] Figure 8A is a circuit diagram of a sub-pixel in a normal area of ​​a display device according to an embodiment;

[0030] Figure 8B is a circuit diagram of a sub-pixel in a first light-emitting region in a first optical region of a display device according to an embodiment;

[0031] Figure 8Cis a circuit diagram of a sub-pixel in a second light-emitting region in a first optical region of a display device according to an embodiment;

[0032] Figure 9 is a diagram for describing an example of driving of a normal area and a first optical area of ​​a display device according to one embodiment; and

[0033] Figure 10 is a diagram showing an example of a display device according to an embodiment. DETAILED DESCRIPTION

[0034] The advantages and features of the present disclosure and methods for achieving these advantages and features will be apparent by reference to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure and scope of the present disclosure.

[0035] The shapes, sizes, ratios, angles, numbers, etc. used to describe the exemplary embodiments of the present disclosure shown in the accompanying drawings are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed descriptions of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Unless otherwise expressly stated, any reference to the singular may include the plural.

[0036] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0037] When terms such as "on," "above," "below," and "next to" are used to describe the positional relationship between two parts, one or more parts may be positioned between the two parts unless these terms are used together with the terms "immediately" or "directly."

[0038] When an element or layer is referred to as being “on” another element or layer, the other layer or element can be directly on or directly interposed between the other element.

[0039] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0040] Throughout the specification, like reference numerals generally refer to like elements.

[0041] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0042] The features of the various embodiments of the present disclosure may be partially or completely dependent on or combined with each other, and may be technically interlocked and operated in various ways, and these embodiments may be performed independently or in association with each other.

[0043] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0044] Figures 1A to 1D is a schematic plan view of a display device according to an embodiment.

[0045] Reference Figures 1A to 1D The display device 100 of one embodiment may include a display panel DP that displays an image and one or more optical electronic devices 190, 190a, 190b. The optical electronic devices 190, 190a, 190b may include a light receiving device that receives light, such as a camera or a sensor.

[0046] The display panel DP is a panel for displaying images to a user.

[0047] The display panel DP may include display elements for displaying images, driving elements for driving the display elements, and lines for transmitting various types of signals to the display elements and driving elements. The display elements may be defined in different ways depending on the type of display panel DP. For example, if the display panel DP is an organic light-emitting display panel, the display elements may be organic light-emitting diodes (OLEDs) including an anode, a light-emitting layer, and a cathode. Furthermore, the display device 100 of one embodiment may be a flexible display device.

[0048] Furthermore, the display panel DP may include a substrate, multiple insulating films on the substrate, a transistor layer, a light-emitting diode layer, and the like. The display panel DP may include multiple sub-pixels and various types of signal lines for driving the multiple sub-pixels to display an image. The signal lines may include multiple data lines, multiple gate lines, multiple power lines, and the like. In this case, each of the multiple sub-pixels may include a transistor disposed in the transistor layer and a light-emitting diode disposed in the light-emitting diode layer.

[0049] The display panel DP may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed.

[0050] In the display area DA, multiple sub-pixels constituting multiple pixels and circuits for driving the multiple sub-pixels may be provided. The multiple sub-pixels may be the smallest unit constituting the display area DA, and a display element may be provided in each of the multiple sub-pixels, and the multiple sub-pixels may constitute a pixel. For example, an organic light-emitting diode including an anode, a light-emitting layer, and a cathode may be provided in each of the multiple sub-pixels, but the present invention is not limited thereto. Furthermore, the circuits for driving the multiple sub-pixels may include driving elements, lines, and the like. For example, the circuits may include, but the present invention is not limited to, thin-film transistors, storage capacitors, gate lines, data lines, and the like.

[0051] The non-display area NDA is curved and is not seen from the front or is covered by a case (not shown), and is referred to as a bezel area.

[0052] In the non-display area NDA, circuits and various types of lines for driving the organic light-emitting diodes in the display area DA may be provided. For example, in the non-display area NDA, connection lines for transmitting signals to the plurality of sub-pixels and circuits in the display area DA, gate-in-panel (GIP) lines, or driver ICs such as gate driver ICs and data driver ICs may be provided, but the present invention is not limited thereto.

[0053] exist Figures 1A to 1D In the embodiment, the non-display area NDA surrounds the display area shaped like a rectangle, but the shapes and arrangements of the display area DA and the non-display area NDA are not limited to Figures 1A to 1D That is, the display area DA and the non-display area NDA may have a shape suitable for the design of an electronic device equipped with the display device 100. For example, the display area DA may be shaped like a pentagon, a hexagon, a circle, an ellipse, etc.

[0054] The display device 100 may also include various additional components for generating various types of signals or driving pixels in the display area DA. Additional components for driving pixels may include converter circuits, multiplexers, electrostatic discharge (ESD) circuits, etc. The display device 100 may also include additional components related to functions other than driving pixels. For example, the display device 100 may also include additional components that provide a touch sensing function, a user authentication function (e.g., a fingerprint recognition function), a multi-level pressure sensing function, a tactile feedback function, etc. The above-mentioned additional components may be placed in an external circuit connected to the non-display area NDA and / or the connection interface.

[0055] Reference Figures 1A to 1D , the one or more optical electronic devices 190, 190a, 190b are electronic components placed below the display panel DP (opposite to the viewing surface) in the display device 100 of the embodiment.

[0056] Light may enter the front surface (viewing surface) of the display panel DP, pass through the display panel DP, and be delivered to one or more optical electronic devices 190, 190a, 190b placed below the display panel DP (opposite the viewing surface).

[0057] The one or more optical electronic devices 190 , 190 a , 190 b may be devices that receive light passing through the display panel DP and perform predetermined functions based on the received light.

[0058] For example, the optical electronic devices 190 , 190 a , 190 b may include any one or more of a capture device such as a camera (image sensor), or a detection sensor such as a proximity sensor, an illumination sensor, and the like.

[0059] Reference Figures 1A to 1D In the display device 100 of the embodiment, the display area DA may include a normal area NA and one or more optical areas DA1 and DA2.

[0060] The one or more optical areas DA1 , DA2 may be areas overlapping with the one or more optical electronic devices 190 , 190 a , 190 b .

[0061] exist Figure 1A In an example, the display area DA may include a normal area NA and a first optical area DA1. Herein, at least a portion of the first optical area DA1 may overlap with the first optical electronic device 190.

[0062] exist Figure 1A In the embodiment, the first optical area DA1 has a circular structure, but the shape of the first optical area DA1 of the embodiment is not limited thereto. Figure 1B As shown, the first optical area DA1 may be shaped as an octagon, and may be shaped as various polygons other than the octagon.

[0063] exist Figure 1C In the example of , the display area DA may include a normal area NA, a first optical area DA1, and a second optical area DA2. Figure 1C In an example of , the normal area NA may be between the first optical area DA1 and the second optical area DA2. Herein, at least a portion of the first optical area DA1 may overlap with the first optical-electronic device 190a, and at least a portion of the second optical area DA2 may overlap with the second optical-electronic device 190b.

[0064] exist Figure 1D In the example of , the display area DA may include a normal area NA, a first optical area DA1, and a second optical area DA2. Figure 1D In the example of FIG. 1 , the normal area NA is not between the first optical area DA1 and the second optical area DA2. That is, the first optical area DA1 and the second optical area DA2 may be in contact with each other. Here, at least a portion of the first optical area DA1 may overlap with the first optical-electronic device 190a, and at least a portion of the second optical area DA2 may overlap with the second optical-electronic device 190b.

[0065] An image display structure and a light-transmitting structure need to be formed in one or more optical areas DA1 and DA2. That is, since one or more optical areas DA1 and DA2 are part of the display area DA, sub-pixels for displaying an image need to be disposed in one or more optical areas DA1 and DA2. A light-transmitting structure for transmitting light to one or more optical-electronic devices 190, 190a, and 190b needs to be formed in one or more optical areas DA1 and DA2.

[0066] The one or more optical electronic devices 190, 190a, 190b are devices required to receive light but are disposed behind (below, opposite to the viewing surface) the display panel DP, and receive light passing through the display panel DP.

[0067] One or more optical electronic devices 190, 190a, 190b are not exposed to the front surface (viewing surface) of the display panel DP. Therefore, when a user looks at the front surface of the display device 100, the user cannot see the optical electronic devices 190, 190a, 190b.

[0068] For example, the first optical electronic device 190 , 190 a may be a camera device, and the second optical electronic device 190 b may be a detection sensor such as a proximity sensor, an illumination sensor, etc. For example, the detection sensor may be an infrared sensor that senses infrared rays.

[0069] In contrast, the first optical-electronic device 190 , 190 a may be a detection sensor, and the second optical-electronic device 190 b may be a camera device.

[0070] Hereinafter, for convenience of description, for example, the first optical electronic device 190, 190a is a camera, and the second optical electronic device 190b may be a detection sensor. Herein, the camera may be a camera lens or an image sensor.

[0071] When the first optical electronic device 190, 190a is a camera, the camera may be provided behind (below) the display panel DP, but may also be a front-facing camera that captures images in the direction of the front surface of the display panel DP. Therefore, the user can capture images through the camera that is not visible from the viewing surface when the user is viewing the viewing surface of the display panel DP.

[0072] The normal area NA and one or more optical areas DA1 and DA2 included in the display area DA are areas where images can be displayed, but a light-transmitting structure does not need to be formed in the normal area NA, while a light-transmitting structure needs to be formed in one or more optical areas DA1 and DA2.

[0073] Therefore, one or more optical areas DA1 , DA2 need to have transmittance of a predetermined level or higher, while the normal area NA may have no transmittance or have low transmittance of a predetermined level or lower.

[0074] For example, one or more optical areas DA1, DA2 and normal area NA may have different resolutions, different sub-pixel arrangement structures, different numbers of sub-pixels per unit surface area, different electrode structures, different line structures, different electrode arrangement structures or different line arrangement structures, etc.

[0075] For example, the number of sub-pixels per unit surface area in one or more optical areas DA1 and DA2 may be smaller than the number of sub-pixels per unit surface area in the normal area NA. In other words, the resolution of one or more optical areas DA1 and DA2 may be smaller than the resolution of the normal area NA. In this case, the number of sub-pixels per unit surface area may be a unit used to measure resolution, or it may be pixels per inch (PPI), which represents the number of pixels per inch.

[0076] For example, the number of sub-pixels per unit surface area in the first optical area DA1 may be smaller than that in the normal area NA. In addition, the number of sub-pixels per unit surface area in the second optical area DA2 may be the same as or greater than that in the first optical area DA1.

[0077] The first optical area DA1 may have various shapes, such as a circle, an ellipse, a rectangle, a hexagon, or an octagon, etc. The second optical area DA2 may have various shapes, such as a circle, an ellipse, a rectangle, a hexagon, or an octagon, etc. The first optical area DA1 and the second optical area DA2 may have the same shape or different shapes.

[0078] Reference Figure 1DIn the case where the first optical area DA1 and the second optical area DA2 contact each other, the entire optical area including the first optical area DA1 and the second optical area DA2 may also have various shapes, such as circle, ellipse, rectangle, hexagon or octagon.

[0079] Hereinafter, for convenience of description, for example, each of the first optical area DA1 and the second optical area DA2 has a circular shape.

[0080] In the display device 100 of one embodiment, when the first optical electronic device 190, 190a that is not exposed to the outside and hidden under the display panel DP is a camera device, the display device 100 of this embodiment may be a display to which under-screen camera (UDC) technology is applied.

[0081] Therefore, in the case of the display device 100 of this embodiment, since there is no need to form a notch or a camera hole in the display panel DP for exposing the camera device, the surface area of ​​the display area DA is not reduced. As a result, since the display panel DP does not need to have a notch or a camera hole for exposing the camera device, the size of the frame area can be reduced and design restrictions are eliminated, thereby ensuring a high degree of design freedom.

[0082] Although the one or more optical electronic devices 190 , 190 a , 190 b are hidden behind the display panel DP in the display device 100 of one embodiment, the one or more optical electronic devices 190 , 190 a , 190 b need to normally receive light and normally perform predetermined functions.

[0083] In addition, although in the display device 100 of one embodiment, one or more optical electronic devices 190, 190a, 190b are hidden behind the display panel DP and are arranged to overlap with the display area DA, the image needs to be normally displayed in one or more optical areas DA1, DA2 overlapping with the one or more optical electronic devices 190, 190a, 190b in the display area DA.

[0084] Therefore, the display device 100 of one embodiment may have a structure in which transmittance of the first and second optical areas DA1 and DA2 overlapping the optical electronic devices 190 , 190 a , and 190 b is improved.

[0085] Figure 2 This is a system block diagram of a display device according to an embodiment.

[0086] Reference Figure 2The display device 100 may include a display panel DP and a display driving circuit as components for displaying images. The display driving circuit, as a circuit for driving the display panel DP, may include a data driving circuit DDC, a gate driving circuit GDC, and a display controller DCTR.

[0087] The display panel DP may include a display area DA that displays an image and a non-display area NDA that does not display an image. The non-display area NDA may be an area outside the display area DA or may be a frame area. All or part of the non-display area NDA may be an area visible from the front surface of the display device 100, or may be a curved area that is not visible from the front surface of the display device 100.

[0088] The display panel DP may include a substrate SUB and a plurality of sub-pixels SP disposed on the substrate SUB. In addition, the display panel DP may further include various types of signal lines to drive the plurality of sub-pixels SP.

[0089] The display device 100 of the embodiment may be a self-luminous OLED in which the display panel DP emits light by itself, and each of the plurality of sub-pixels SP may include a light emitting diode.

[0090] For example, the display device 100 of the embodiment may be an organic light-emitting display device in which the light-emitting diodes are implemented as organic light-emitting diodes (OLEDs). In another example, the display device 100 of the embodiment may be an inorganic light-emitting display device in which the light-emitting diodes are implemented as light-emitting diodes based on inorganic materials. In yet another example, the display device 100 of the embodiment may be a quantum dot display device in which the light-emitting diodes are implemented as quantum dots, which are semiconductor crystals that emit light themselves.

[0091] The structure of each of the plurality of sub-pixels SP may vary depending on the type of the display device 100. For example, in the case where the display device 100 is a self-luminous display device in which the sub-pixels SP emit light by themselves, each sub-pixel SP may include a light-emitting diode that emits light by itself, one or more transistors, and one or more capacitors.

[0092] The various types of signal lines may include a plurality of data lines DL transmitting data signals (also referred to as data voltages or image signals), a plurality of gate lines GL transmitting gate signals (also referred to as scan signals), and the like.

[0093] The plurality of data lines DL and the plurality of gate lines GL may intersect each other. Each of the plurality of data lines DL may be arranged to extend along a first direction. Each of the plurality of gate lines GL may be arranged to extend along a second direction. The first direction may be a column direction, and the second direction may be a row direction. Alternatively, the first direction may be a row direction, and the second direction may be a column direction.

[0094] The data driving circuit DDC is a circuit for driving the plurality of data lines DL and can output data signals to the plurality of data lines DL. The gate driving circuit GDC is a circuit for driving the plurality of gate lines GL and can output gate signals to the plurality of gate lines GL.

[0095] The display controller DCTR, as a device for controlling the data driving circuit DDC and the gate driving circuit GDC, can control the driving timing of the plurality of data lines DL and the driving timing of the plurality of gate lines GL.

[0096] The display controller DCTR may supply a data driving control signal DCS to the data driving circuit DDC to control the data driving circuit DDC, and supply a gate driving control signal GCS to the gate driving circuit GDC to control the gate driving circuit GDC.

[0097] The display controller DCTR may receive input image data from the host system HSYS and supply image data Data to the data driving circuit DDC based on the input image data.

[0098] The data driving circuit DDC can supply data signals to the multiple data lines DL under the driving timing control of the display controller DCTR. The data driving circuit DDC can receive digital image data from the display controller DCTR, convert the received image data into analog data signals, and output the data signals to the multiple data lines DL.

[0099] The gate drive circuit GDC can supply gate signals to the plurality of gate lines GL under the timing control of the display controller DCTR. The gate drive circuit GDC can be supplied with a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage, as well as various types of gate drive control signals GCS, to generate gate signals, and supply the generated gate signals to the plurality of gate lines GL.

[0100] The gate driving circuit GDC supplies gate signals to the gate lines GL according to the gate driving control signals GCS supplied from the display controller DCTR. The gate driving circuit GDC may be provided on one or both sides of the display panel DP based on a gate-in-panel (GIP) method.

[0101] The gate driving circuit GDC continuously outputs gate signals to the plurality of gate lines GL under the control of the display controller DCTR. The gate driving circuit GDC may shift the gate signals by using a shift register and continuously supply the signals to the gate lines GL.

[0102] In a display device, a gate signal may include a scan signal SC and an emission control signal EM. The scan signal SC includes a scan signal pulse that swings between a first gate voltage and a second gate voltage. The emission control signal EM includes an emission control signal pulse that swings between a third gate voltage and a fourth gate voltage.

[0103] The scan pulse is synchronized with the data voltage Vdata and selects the sub-pixel SP of a line to which data is to be written. The light emission control signal EM defines the light emission time of each sub-pixel SP.

[0104] The gate driving circuit GDC may include a light emitting control signal driver EDC outputting a light emitting control signal EM and at least one or more scan drivers SDC outputting a scan signal SC.

[0105] The light emitting control signal driver EDC outputs the light emitting control signal EM in response to a start pulse and a shift clock from the display controller DCTR, and continuously shifts the light emitting control signal pulse based on the shift clock.

[0106] At least one or more scan drivers SDC outputs a scan signal SC in response to a start pulse and a shift clock from the display controller DCTR, and shifts a scan signal pulse according to a shift clock timing.

[0107] In a gate driver circuit GDC arranged using the GIP method, the shift registers can be arranged symmetrically on both sides of the display area DA. Furthermore, in the gate driver circuit GDC, the shift register on one side of the display area DA can include at least one scan driver SDC and a light emission control signal driver, and the shift register on the other side of the display area DA can include at least one scan driver SDC, but the present invention is not limited thereto. Depending on the embodiment, the light emission control signal driver EDC and the at least one scan driver SDC can be arranged in various ways.

[0108] The data driving circuit DDC can be connected to the display panel DP based on tape automated bonding (TAB), or connected to the bonding pad of the display panel DP based on a chip on glass (COG) method or a chip on panel (COP) method, or implemented based on a chip on film (COF) method and connected to the display panel DP.

[0109] The gate drive circuit GDC can be connected to the display panel DP based on a tape automated bonding (TAB) method, or connected to a bonding pad of the display panel DP based on a chip on glass (COG) method or a chip on panel (COP) method, or connected to the display panel DP based on a chip on film (COF) method. Alternatively, the gate drive circuit GDC can be formed in the non-display area NDA of the display panel DP as a gate-in-panel (GIP) type gate drive circuit. The gate drive circuit GDC can be set on the substrate or connected to the substrate. That is, in the case where the gate drive circuit GDC is a GIP type gate drive circuit, the gate drive circuit GDC can be set in the non-display area NDA of the substrate. In the case where the gate drive circuit GDC is a chip on glass (COG) type gate drive circuit, a chip on film (COF) type gate drive circuit, etc., the gate drive circuit GDC can be connected to the substrate.

[0110] In addition, at least one of the data driving circuit DDC and the gate driving circuit GDC may be provided in the display area DA of the display panel DP. For example, at least one of the data driving circuit DDC and the gate driving circuit GDC may be provided so as not to overlap with the sub-pixel SP, or so as to partially or completely overlap with the sub-pixel SP.

[0111] The data driving circuit DDC may be connected to one side (e.g., the upper side or the lower side) of the display panel DP. Depending on a driving method, a panel design method, etc., the data driving circuit DDC may be connected to both sides (e.g., the upper side and the lower side) of the display panel DP, or to two or more of the four side surfaces of the display panel DP.

[0112] The gate drive circuit GDC may also be connected to one side (e.g., the left side or the right side) of the display panel DP. Depending on the driving method, panel design method, etc., the gate drive circuit GDC may be connected to both sides (e.g., the left side and the right side) of the display panel DP, or to two or more of the four side surfaces of the display panel DP.

[0113] The display controller DCTR may be implemented as a separate component from the data driving circuit DDC, or integrated with the data driving circuit DDC and implemented as an integrated circuit.

[0114] The display controller DCTR may be a timing controller for general display technology, or a control device that includes a timing controller and also performs other control functions, or a control device different from the timing controller, or a circuit in the control device. The display controller DCTR may be implemented as an integrated circuit IC, a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or various circuits or electronic components such as a processor.

[0115] The display controller DCTR may be mounted on a printed circuit board, a flexible printed circuit, or the like, and electrically connected to the data driving circuit DDC and the gate driving circuit GDC through the printed circuit board, the flexible printed circuit, or the like.

[0116] The display controller DCTR can transmit and receive signals with the data driving circuit DDC according to one or more predetermined interfaces. For example, the interface may include a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI), a serial peripheral interface (SPI), etc.

[0117] The display device 100 of the embodiment may include a touch sensor and a touch sensing circuit to further provide a touch sensing function as well as an image display function. The touch sensing circuit senses the touch sensor and detects whether a touch with a touch object such as a finger or a pen occurs or detects a touch position.

[0118] The touch sensing circuit may further include: a touch driving circuit that drives and senses the touch sensor and generates and outputs touch sensing data; a touch controller that senses occurrence of a touch or detects a touch position by using the touch sensing data; and the like.

[0119] The touch sensor may include a plurality of touch electrodes and a plurality of touch wires for electrically connecting the plurality of touch electrodes and a touch driving circuit.

[0120] The touch sensor may be located outside the display panel DP in the form of a touch panel, or may be provided within the display panel DP. When the touch sensor is located outside the display panel DP in the form of a touch panel, the touch sensor is referred to as an external touch sensor. In the case of an external touch sensor, the touch panel and the display panel DP may be manufactured separately and coupled during assembly. The external touch panel may include, for example, a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0121] In the case where the touch sensor is located in the display panel DP, the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to driving of the display during manufacturing of the display panel DP.

[0122] The touch driving circuit TDC may supply a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0123] The touch sensing circuit may perform touch sensing based on a self-capacitance sensing method or a mutual capacitance sensing method.

[0124] In the case where the touch sensing circuit performs touch sensing based on self-capacitance sensing, the touch sensing circuit may perform touch sensing based on capacitance between each touch electrode and a touch object (eg, a finger, a pen, etc.).

[0125] In self-capacitance sensing, each of the multiple touch electrodes can be used as a driving touch electrode and a sensing touch electrode. The touch driving circuit TDC can drive all or part of the multiple touch electrodes and sense all or part of the multiple touch electrodes.

[0126] In the case where the touch sensing circuit performs touch sensing based on mutual capacitance sensing, the touch sensing circuit may perform touch sensing based on capacitance between touch electrodes.

[0127] In mutual capacitance sensing, multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. A touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0128] The touch driving circuit and the touch controller included in the touch sensing circuit can be implemented as separate devices or as one device. In addition, the touch driving circuit and the data driving circuit DDC can be implemented as separate devices or as one device.

[0129] In addition, the display device 100 may further include a power supply circuit or the like that supplies various types of power to the display driving circuit and / or the touch sensing circuit.

[0130] The display device 100 of the embodiment may be a mobile terminal such as a smartphone, a tablet, or a monitor or TV of various sizes, but is not limited thereto and may be a display of various types and sizes that outputs information or images.

[0131] As described above, the display area DA in the display panel DP may include the normal area NA and one or more optical areas DA1 , DA2 .

[0132] The normal area NA and the one or more optical areas DA1 and DA2 are areas capable of displaying images. However, the normal area NA is an area where a light-transmitting structure does not need to be formed, while the one or more optical areas DA1 and DA2 are areas where a light-transmitting structure needs to be formed.

[0133] As described above, the display area DA in the display panel DP may include the normal area NA and one or more optical areas DA1 , DA2 .

[0134] Hereinafter, for convenience of description, it is assumed that the display area DA includes both the first optical area DA1 and the second optical area DA2 ( Figure 1C and Figure 1D ).

[0135] Figure 3 FIG. 1 is a diagram showing an example of arrangement of sub-pixels in a display area according to an embodiment.

[0136] Figure 3 The arrangement of sub-pixels SP in three areas NA, DA1, and DA2 included in the display area DA of the display panel of this embodiment is shown.

[0137] Reference Figure 3 , a plurality of sub-pixels SP may be provided in each of the normal area NA, the first optical area DA1, and the second optical area DA2 included in the display area.

[0138] In an example, the plurality of sub-pixels SP may include a red sub-pixel Red SP emitting red light, a green sub-pixel Green SP emitting green light, and a blue sub-pixel Blue SP emitting blue light.

[0139] Therefore, each of the normal area NA, the first optical area DA1, and the second optical area DA2 may include a light emitting area EA of the red sub-pixel Red SP, a light emitting area EA of the green sub-pixel Green SP, and a light emitting area EA of the blue sub-pixel Blue SP.

[0140] Reference Figure 3 , the normal area NA may include the light emitting area EA without including the light transmitting structure.

[0141] However, the first and second optical areas DA1 and DA2 need to include the light-transmitting structure as well as the light-emitting area EA.

[0142] Therefore, the first optical area DA1 may include the emission area EA and the transmission area TA.

[0143] The emission area EA and the transmission area TA can be distinguished according to whether they transmit light. That is, the emission area EA may be an area where light transmission is impossible, while the transmission area TA may be an area where light transmission is possible.

[0144] In addition, the light-emitting area EA and the transmissive area TA can be distinguished based on whether a specific metal layer is formed. For example, a cathode electrode can be formed in the light-emitting area EA but not in the transmissive area TA. In addition, a light-shielding layer can be formed in the light-emitting area EA but not in the transmissive area TA.

[0145] In the transmission area TA, a deposition prevention layer (not shown) made of an organic material may be provided on the same plane surface as the cathode electrode. During the formation of the cathode electrode, the cathode electrode material may not be deposited on the deposition prevention layer, and the cathode electrode may be selectively formed on the substrate SUB.

[0146] Since the first optical area DA1 includes the transmission area TA, the first optical area DA1 may transmit light.

[0147] although Figure 3 Although not shown in the figure, the second optical area DA2 may also include a light-emitting area EA and a transmissive area TA. Since the second optical area DA2 also includes the transmissive area TA, both the first optical area DA1 and the second optical area DA2 can transmit light. The structure and arrangement of the light-emitting area EA and the transmissive area TA of the first optical area DA1 may be the same as or different from the structure and arrangement of the light-emitting area EA and the transmissive area TA of the second optical area DA2.

[0148] Specifically, the transmittance (transmittance) of the first optical area DA1 and the transmittance (transmittance) of the second optical area DA2 may be the same. In this case, the shape or size of the transmission area TA of the first optical area DA1 may be the same as the shape or size of the transmission area TA of the second optical area DA2. Alternatively, although the shape or size of the transmission area TA of the first optical area DA1 is different from the shape or size of the transmission area TA of the second optical area DA2, the ratio of the transmission area TA in the first optical area DA1 may be the same as the ratio of the transmission area TA in the second optical area DA2.

[0149] In contrast, the transmittance (transmittance) of the first optical area DA1 may be different from the transmittance (transmittance) of the second optical area DA2 .

[0150] At this time, the shape or size of the transmission area TA of the first optical area DA1 may be different from the shape or size of the transmission area TA of the second optical area DA2. Alternatively, although the shape or size of the transmission area TA of the first optical area DA1 is the same as that of the transmission area TA of the second optical area DA2, the ratio of the transmission area TA in the first optical area DA1 may be different from the ratio of the transmission area TA in the second optical area DA2.

[0151] For example, when the first optical electronic device overlapping the first optical area DA1 is a camera and the second optical electronic device overlapping the second optical area DA2 is a detection sensor, the camera may require a larger amount of light than the detection sensor.

[0152] Therefore, the transmittance (transmittance) of the first optical area DA1 may be greater than the transmittance (transmittance) of the second optical area DA2. At this time, the transmission area TA of the first optical area DA1 may have a size larger than that of the transmission area TA of the second optical area DA2. Alternatively, although the size of the transmission area TA of the first optical area DA1 is the same as that of the transmission area TA of the second optical area DA2, the ratio of the transmission area TA in the first optical area DA1 may be greater than the ratio of the transmission area TA in the second optical area DA2.

[0153] Hereinafter, for convenience of description, for example, it is assumed that the transmittance (transmittance) of the first optical area DA1 is the same as the transmittance (transmittance) of the second optical area DA2 .

[0154] In this embodiment, Figure 3 The transmissive area TA shown may also be referred to as a transparent area, and the transmittance may also be referred to as transparency.

[0155] In one embodiment, it is assumed that the first optical area DA1 and the second optical area DA2 are placed at the upper end of the display area of ​​the display panel and are arranged side by side in the left-right direction. Figure 3 shown.

[0156] Reference Figure 3 , a display area where the first optical area DA1 and the second optical area DA2 are disposed in the horizontal direction is called a first horizontal display area HA1, and a display area where the first optical area DA1 and the second optical area DA2 are not disposed in the horizontal direction is called a second horizontal display area HA2.

[0157] The first horizontal display area HA1 may include a normal area NA, a first optical area DA1, and a second optical area DA2. In contrast, the second horizontal display area HA2 may include only the normal area NA.

[0158] Reference Figure 3 , the first optical area DA1 included in the first horizontal display area HA1 may include a light emitting area EA and a transmissive area TA. In the first optical area DA1, an outer area of ​​the transmissive area TA may include the light emitting area EA.

[0159] Reference Figure 3 , at the first optical area DA1 in the first horizontal display area HA1, the light emitting area EA may be disposed between the transmissive areas TA adjacent to each other in the left-right direction. At the first optical area DA1 in the first horizontal display area HA1, the light emitting area EA may be disposed between two transmissive areas TA adjacent to each other in the up-down direction.

[0160] In the following, reference is made to Figure 4and Figure 5 The structure of the normal area NA of the display device 100 according to one embodiment will be described in detail.

[0161] Figure 4 This is a plan view of a pixel in a normal area NA of a display device according to one embodiment.

[0162] exist Figure 4 , only the multiple first anode electrodes 142-1, 142-2, 142-3, the second anode electrodes 144-1, 144-2, 144-3, the first openings 145a-1, 145a-2, 145a-3, the second openings 145b-1, 145b-2, 145b-3, the first lenses 182-1, 182-2, 182-3 and the second lenses 184-1, 184-2, 184-3 in each of the first to third sub-pixels SP1, SP2, SP3 of the pixels of the light-emitting display device are shown.

[0163] like Figure 4 As shown, a pixel of a light-emitting display device of an embodiment includes first to third subpixels SP1, SP2, and SP3, and the first subpixel SP1 may be a red subpixel, the second subpixel SP2 may be a green subpixel, and the third subpixel SP3 may be a blue subpixel.

[0164] Herein, the second subpixel SP2 and the third subpixel SP3 may be disposed along the Y direction, and the first subpixel SP1 may be disposed along the X direction with respect to the second subpixel SP2 and the third subpixel SP3.

[0165] Each of the first to third sub-pixels SP1, SP2, and SP3 may have a polygonal shape. In this case, the first to third sub-pixels SP1, SP2, and SP3 may have different shapes. The shapes of the first to third sub-pixels SP1, SP2, and SP3 are not limited and may vary.

[0166] The first to third subpixels SP1, SP2, and SP3 may have different surface areas. The surface areas of the first to third subpixels SP1, SP2, and SP3 may be determined based on the lifespan and luminous efficiency of the light-emitting diodes provided in each subpixel. In this case, the red light-emitting diode has the longest lifespan. To ensure uniform lifespans, the surface area of ​​the first subpixel SP1 is smaller than the surface areas of each of the second and third subpixels SP2 and SP3, but the present invention is not limited thereto.

[0167] The ratio of the surface areas of the first to third sub-pixels SP1 , SP2 , SP3 may vary.

[0168] The first to third sub-pixels SP1, SP2, and SP3 include a first light emitting diode ED1 and a second light emitting diode ED2, respectively. The first light emitting diode ED1 and the second light emitting diode ED2 may have the same structure and realize the same color.

[0169] like Figures 4 and 5 As shown, the first subpixel SP1 includes a first anode electrode 142-1 disposed in the first light-emitting portion EP1 and a second anode electrode 144-1 disposed in the second light-emitting portion EP2. The first anode electrode 142-1 disposed in the first subpixel SP1 is connected to the first thin-film transistor Tr1 through a first drain contact hole. In addition, the second anode electrode 144-1 disposed in the first subpixel SP1 is connected to the second thin-film transistor Tr2 through a second drain contact hole.

[0170] In addition, the second subpixel SP2 also includes a first anode electrode 142-2 disposed in the first light-emitting portion EP1 and a second anode electrode 144-2 disposed in the second light-emitting portion EP2. The first anode electrode 142-2 disposed in the second subpixel SP2 is connected to the first thin-film transistor Tr1 through a first drain contact hole. In addition, the second anode electrode 144-2 disposed in the second subpixel SP2 is connected to the second thin-film transistor Tr2 through a second drain contact hole.

[0171] In addition, the third subpixel SP3 also includes a first anode electrode 142-3 disposed in the first light-emitting portion EP1 and a second anode electrode 144-3 disposed in the second light-emitting portion EP2. The first anode electrode 142-3 disposed in the third subpixel SP3 is connected to the first thin-film transistor Tr1 through a first drain contact hole. In addition, the second anode electrode 144-3 disposed in the third subpixel SP3 is connected to the second thin-film transistor Tr2 through a second drain contact hole.

[0172] In each of the first to third subpixels SP1, SP2, and SP3, at least one first opening 145a-1, 145a-2, and 145a-3 is provided on the first anode electrodes 142-1, 142-2, and 142-3. In each of the first to third subpixels SP1, SP2, and SP3, at least one second opening 145b-1, 145b-2, and 145b-3 is provided on the second anode electrodes 144-1, 144-2, and 144-3. In the XY plane, each of the first openings 145a-1, 145a-2, and 145a-3 may have a shape in which the length of each of the first openings 145a-1, 145a-2, and 145a-3 in the X direction is substantially the same as the length thereof in the Y direction, and the second openings 145b-1, 145b-2, and 145b-3 may have a polygonal shape in which the length of each of the second openings 145b-1, 145b-2, and 145b-3 in the X direction is greater than the length thereof in the Y direction. In addition, the surface area of ​​each of the second openings 145b-1, 145b-2, and 145b-3 may be greater than the surface area of ​​at least one of the first openings 145a-1, 145a-2, and 145a-3.

[0173] Specifically, in the first subpixel SP1, two first openings 145a-1 may be provided on the first anode electrode 142-1, and one second opening 145b-1 may be provided on the second anode electrode 144-1. The two first openings 145a-1 and one second opening 145b-1 may be spaced apart in the Y direction.

[0174] In the second subpixel SP2, two first openings 145a-2 may be provided on the first anode electrode 142-2 in the X direction, and one second opening 145b-2 may be provided on the second anode electrode 144-2. The two first openings 145a-2 and one second opening 145b-2 may be spaced apart in the Y direction.

[0175] In the third subpixel SP3, two first openings 145a-3 may be provided on the first anode electrode 142-3 in the X direction, and one second opening 145b-3 may be provided on the second anode electrode 144-3. The two first openings 145a-3 and one second opening 145b-3 may be spaced apart in the Y direction.

[0176] A hemispherical first lens 182-1, 182-2, 182-3 is provided in response to each of the first openings 145a-1, 145a-2, 145a-3, and a semi-cylindrical second lens 184-1, 184-2, 184-3 is provided in response to the second openings 145b-1, 145b-2, 145b-3.

[0177] Each of the first lenses 182-1, 182-2, and 182-3 is arranged to cover each of the first openings 145a-1, 145a-2, and 145a-3. On the XY plane surface, the surface area of ​​each of the first lenses 182-1, 182-2, and 182-3 can be larger than the surface area of ​​each of the first openings 145a-1, 145a-2, and 145a-3. In addition, each of the second lenses 184-1, 184-2, and 184-3 is arranged to cover each of the second openings 145b-1, 145b-2, and 145b-3. On the XY plane surface, the surface area of ​​each of the second lenses 184-1, 184-2, and 184-3 can be larger than the surface area of ​​each of the second openings 145b-1, 145b-2, and 145b-3.

[0178] Specifically, in the first subpixel SP1, two first lenses 182-1 may be provided to cover the two first openings 145a-1, and one second lens 184-1 may be provided to cover the one second opening 145b-1. In the second subpixel SP2, two first lenses 182-2 may be provided to cover each of the two first openings 145a-2, and one second lens 184-2 may be provided to cover the one second opening 145b-2. In addition, in the third subpixel SP3, two first lenses 182-3 may be provided to cover each of the two first openings 145a-3, and one second lens 184-3 may be provided to cover the one second opening 145b-3.

[0179] Therefore, the plurality of first lenses 182-1, 182-2, 182-3 correspond to the first light emitting portion EP1 of each sub-pixel SP1, SP2, SP3, and the plurality of second lenses 184-1, 184-2, 184-3 correspond to the second light emitting portion EP2 of each sub-pixel SP1, SP2, SP3.

[0180] As described above, in one embodiment of the light-emitting display device, hemispherical first lenses 182-1, 182-2, and 182-3 are provided in response to first anode electrodes 142-1, 142-2, and 142-3, and semi-cylindrical second lenses 184-1, 184-2, and 184-3 are provided in response to second anode electrodes 144-1, 144-2, and 144-3 to restrict the viewing angle. In this case, the directions in which the viewing angles of first lenses 182-1, 182-2, and 182-3 are restricted are different from the directions in which the viewing angles of second lenses 184-1, 184-2, and 184-3 are restricted. This allows for selective driving to achieve both wide and narrow viewing angles.

[0181] In the following, reference is made to Figure 5 The first light emitting diode ED1 and the second light emitting diode ED2 of the normal area NA are described.

[0182] Figure 5 It is along Figure 4 AA' and BB' cross-sectional views. Figure 5 is a cross-sectional view of the first light emitting diode ED1 and the second light emitting diode ED2 of the first sub-pixel SP1 in the normal area NA.

[0183] Although Figure 5 , only a cross-sectional view of the first subpixel SP1 is shown, but the second subpixel SP2 and the third subpixel SP3 may have the same structure as the first subpixel SP1, except that in the case of the second subpixel SP2 and the third subpixel SP3, the first light emitting portion EP1, the second light emitting portion EP2, the first anode electrodes 142-2, 142-3, the second anode electrodes 144-2, 144-3, the first lenses 182-2, 182-3, and the second lenses 184-2, 184-3 have different sizes, and the first anode electrodes 142-2, 142-3 and the second anode electrodes 144-2, 144-3 are connected to pixel circuits provided in corresponding subpixels.

[0184] Reference Figure 5 In the normal area NA, a transistor layer TRL may be provided on the substrate SUB, and a planarization layer PLN may be provided on the transistor layer TRL. A light-emitting diode layer EDL may be provided on the planarization layer PLN, an encapsulation layer ENCAP may be provided on the light-emitting diode layer EDL, a touch sensing layer TSL may be provided on the encapsulation layer ENCAP, and a lens layer LL may be provided on the touch sensing layer TSL.

[0185] The substrate SUB, which is an element for supporting various components included in the display device 100, can be made of an insulating material. The substrate SUB may include a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c. For example, the first substrate 110a and the second substrate 110b may be polyimide (PI) substrates. The interlayer insulating film 110c may be provided between the first substrate 110a and the second substrate 110b. As described above, the substrate SUB includes the first substrate 110a, the second substrate 110b, and the interlayer insulating film 110c to prevent moisture from penetrating.

[0186] First to third sub-pixels SP1, SP2, and SP3 are defined on the substrate SUB. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are defined on the substrate SUB. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 has a first light emitting portion EP1 and a second light emitting portion EP2.

[0187] In the normal area NA, various types of patterns 131, 132, 133, 134 for forming transistors such as driving transistors, insulating films 111a, 111b, 112, 113a, 113b, 114 and metal patterns TM, GM, 135 may be provided on the transistor layer TRL.

[0188] The driving transistor may include a first thin film transistor Tr1 corresponding to the first light emitting part EP1 and a second thin film transistor Tr2 corresponding to the second light emitting part EP2. The first and second thin film transistors Tr1 and Tr2 may include a gate electrode 121, a source electrode 122, a drain electrode 123, and an active layer 124, respectively.

[0189] Hereinafter, the stack structure of the transistor layer TRL is described in detail.

[0190] A multi-buffer layer 111a is disposed on the second substrate 110b, and a metal layer 125 may be disposed on the multi-buffer layer 111a. The metal layer 125 may function as a light shield and is referred to as a light-shielding layer.

[0191] An active buffer layer 111b may be disposed on the multi-buffer layer 111a and the metal layer 125, and an active layer 124 of the first and second thin film transistors Tr1 and Tr2 may be disposed on the active buffer layer 111b. For example, the active layer 124 may be formed of polycrystalline silicon (p-Si), amorphous silicon (a-Si), or an oxide semiconductor, but is not limited thereto.

[0192] A gate insulating film 112 may be disposed on the active layer 124. The gate insulating film 112 may be made of silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

[0193] In addition, a gate electrode 121 may be provided on the gate insulating film 112. The gate electrode 121 is provided on the gate insulating film 112 to overlap the active layer 124. The gate electrode 121 may be formed of various conductive materials such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof, but is not limited thereto.

[0194] A gate material layer GM may be provided on the gate insulating film 112 at a position different from the positions where the first and second thin film transistors Tr1 and Tr2 are formed.

[0195] A first interlayer insulating film 113a may be provided on the gate electrode 121 and the gate material layer GM. A metal pattern TM may be provided on the first interlayer insulating film 113a. A second interlayer insulating film 113b may be provided to cover the metal pattern TM provided on the first interlayer insulating film 113a.

[0196] A source electrode 122 and a drain electrode 123 may be provided on the second interlayer insulating film 113 b .

[0197] The source electrode 122 and the drain electrode 123 may be connected to one side and the other side of the semiconductor layer 134, respectively, through contact holes provided at the second interlayer insulating film 113b, the first interlayer insulating film 113a, and the gate insulating film 112. The source electrode 122 and the drain electrode 123 may be formed of various conductive materials such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof, but are not limited thereto.

[0198] The active layer 124 has a channel region that overlaps the gate electrode 121 . One of the source electrode 122 and the drain electrode 123 is connected to one side of the channel region, and the other is connected to the other side.

[0199] A passivation layer 114 may be disposed on the source electrode 122 and the drain electrode 123. The passivation layer 114 serves to protect the first and second thin film transistors Tr1 and Tr2 and is made of an inorganic film such as silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof.

[0200] A planarization layer PLN may be provided on the transistor layer TRL. The planarization layer PLN may include a first planarization layer 115a and a second planarization layer 115b. The planarization layer PLN protects the first and second thin film transistors Tr1 and Tr2 and planarizes their upper portions. The first planarization layer 115a may be provided on the passivation layer 114, and the connection electrode 135 may be provided on the first planarization layer 115a.

[0201] The connection electrode 135 may be connected to one of the source electrode 122 and the drain electrode 123 through a contact hole provided at the first planarization layer 115 a .

[0202] A second planarization layer 115 b may be disposed on the connection electrode 135 .

[0203] A light emitting diode layer EDL may be disposed on the second planarization layer 115 b .

[0204] Hereinafter, the stack structure of the light emitting diode layer EDL is described in detail.

[0205] In response to the first light emitting part EP1 and the second light emitting part EP2, a first light emitting diode ED1 and a second light emitting diode ED2 may be placed on the second planarization layer 115b. Figure 5 The first light emitting diode ED1 may include a first anode electrode 142-1, a first light emitting layer 152-1, and a cathode electrode 160 sequentially stacked on the second planarization layer 115b. In addition, the second light emitting diode ED2 may include a second anode electrode 144-1, a second light emitting layer 154-1, and a cathode electrode 160 sequentially stacked on the second planarization layer 115b.

[0206] A first anode electrode 142-1 and a second anode electrode 144-1, made of a relatively high work function conductive material, are formed on the second planarization layer 115b. The first anode electrode 142-1 is positioned in the first light emitting portion EP1, contacts the connection electrode 135 through a contact hole provided in the second planarization layer 115b, and is electrically connected to the first thin-film transistor Tr1. Furthermore, the second anode electrode 144-1 is positioned in the second light emitting portion EP2, contacts the connection electrode 135 through a contact hole provided in the second planarization layer 115b, and is electrically connected to the second thin-film transistor Tr2.

[0207] Each of the first anode electrode 142 - 1 and the second anode electrode 144 - 1 may be formed of a conductive transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0208] The display device 100 of one embodiment may be a top-emission display device, in which light from the plurality of light-emitting diodes ED1 and ED2 is output in opposite directions relative to the substrate SUB. Therefore, each of the first anode electrode 142-1 and the second anode electrode 144-1 may further include a reflective electrode or reflective layer formed of a highly reflective metal material below the conductive transparent material. For example, the reflective electrode or reflective layer may be made of an aluminum-palladium-copper (APC) alloy, silver (Ag), or aluminum (Al). In this case, each of the first anode electrode 142-1 and the second anode electrode 144-1 may have a three-layer structure of ITO / APC / ITO, ITO / Ag / ITO, or ITO / Al / ITO, but is not limited thereto.

[0209] A bank 116 made of an insulating material is formed on the first anode electrode 142-1 and the second anode electrode 144-1. For example, the bank 116 may be made of a polyimide resin, an acrylic resin, or a benzocyclobutene resin, but is not limited thereto. In the present disclosure, the bank 116 may have a single-layer structure, but may also have a double-layer structure. That is, the bank 116 may have a double-layer structure including a hydrophilic bank layer at its lower portion and a hydrophobic bank layer at its upper portion.

[0210] The bank 116 overlaps with edges of the first anode electrode 142 - 1 and the second anode electrode 144 - 1 and covers the edges of the first anode electrode 142 - 1 and the second anode electrode 144 - 1 .

[0211] A first light-emitting layer 152-1 and a second light-emitting layer 154-1 are formed on the first anode electrode 142-1 and the second anode electrode 144-1 exposed by the bank 116, respectively. The first light-emitting layer 152-1 can generate light with a brightness corresponding to the difference between the voltage of the first anode electrode 142-1 and the cathode electrode 160, and the second light-emitting layer 154-1 can generate light with a brightness corresponding to the difference between the voltage of the second anode electrode 144-1 and the cathode electrode 160. For example, the first light-emitting layer 152-1 and the second light-emitting layer 154-1 may include a light-emitting material layer (EML) containing a light-emitting material. The light-emitting material may include an organic material, an inorganic material, or a hybrid material.

[0212] The first and second light emitting layers 152-1 and 154-1 may have a multi-layer structure. For example, the first and second light emitting layers 152-1 and 154-1 may further include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer EIL.

[0213] Reference Figure 5The first light-emitting layer 152-1 of the first light-emitting diode ED1 and the second light-emitting layer 154-1 of the second light-emitting diode ED2 may be spaced apart from each other. However, the first light-emitting layer 152-1 and the second light-emitting layer 154-1 may also be provided as a common layer in the first light-emitting diode ED1 and the second light-emitting diode ED2. For example, the first light-emitting layer 152-1 on the first anode electrode 142-1 and the second light-emitting layer 154-1 on the second anode electrode 144-1 may be connected and formed integrally.

[0214] A cathode electrode 160 made of a relatively low work function conductive material is formed on the front surface of the substrate SUB, on the first light-emitting layer 152-1 and the second light-emitting layer 154-1. The cathode electrode 160 can be formed of aluminum, magnesium, silver, or alloys thereof. The cathode electrode 160 can be relatively thin to transmit light from the first light-emitting layer 152-1 and the second light-emitting layer 154-1. In addition, the cathode electrode 160 can be formed of a conductive transparent material such as indium gallium oxide (IGO), but is not limited thereto.

[0215] An encapsulation layer ENCAP may be placed on the light emitting diode layer EDL to prevent moisture or oxygen from penetrating from the outside into the first light emitting diode ED1 and the second light emitting diode ED2.

[0216] The encapsulation layer ENCAP may have a single-layer structure or a multi-layer structure. For example, the encapsulation layer ENCAP may include a first encapsulation layer 117a, a second encapsulation layer 117b, and a third encapsulation layer 117c.

[0217] At this time, the first encapsulation layer 117a and the third encapsulation layer 117c may include an inorganic film, and the second encapsulation layer 117b may include an organic film. The second encapsulation layer 117b may be the thickest among the first, second, and third encapsulation layers 117a, 117b, and 117c and serve as a planarization layer.

[0218] The first encapsulation layer 117a may be provided on the first and second light-emitting diodes ED1 and ED2 and suppress the penetration of moisture or oxygen. The first encapsulation layer 117a may be made of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiNxOy), or aluminum oxide (AllyOz), but is not limited thereto.

[0219] The second encapsulation layer 117b is disposed on the first encapsulation layer 117a and flattens its surface. In addition, the second encapsulation layer 117b can block foreign matter or particles that may be generated during manufacturing. The second encapsulation layer 117b can be made of an organic material such as silicon oxycarbon (SiOxCz), propylene, or epoxy resin, but is not limited thereto.

[0220] The third encapsulation layer 117c may be disposed on the second encapsulation layer 117b and, like the first encapsulation layer 117a, inhibits the penetration of moisture or oxygen. In this case, the third encapsulation layer 117c and the first encapsulation layer 117a may be formed to seal the second encapsulation layer 117b. Therefore, the third encapsulation layer 117c may more effectively reduce the penetration of moisture or oxygen into the first and second light-emitting diodes ED1 and ED2. The third encapsulation layer 117c may be made of an inorganic material such as, but is not limited to, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiNxOy), or aluminum oxide (AllyOz).

[0221] although Figure 5 Although not shown, a color filter may be provided on the encapsulation layer ENCAP, but is not limited thereto.

[0222] A touch sensing layer TSL may be disposed on the encapsulation layer ENCAP.

[0223] A touch buffer film 118 a may be disposed on the encapsulation layer ENCAP, and a touch line 170 may be disposed on the touch buffer film 118 a .

[0224] The touch line 170 may include a touch sensor metal 171 and a bridge metal 172 provided on different layers. A touch interlayer insulating film 118b may be provided between the touch sensor metal 171 and the bridge metal 172.

[0225] For example, the touch sensor metal 171 may include a first touch sensor metal, a second touch sensor metal, and a third touch sensor metal disposed adjacent to each other. Although the first touch sensor metal and the second touch sensor metal may be electrically connected to each other, if the third touch sensor metal is between the first and second touch sensor metals, the first and second touch sensor metals may be electrically connected to each other via a bridge metal 172 disposed on different layers. The bridge metal 172 may be insulated from the third touch sensor metal by the touch interlayer insulating film 118 b.

[0226] When forming the touch sensing layer TSL, liquid chemicals (developing solution or etching solution, etc.) used in the process or moisture from the outside may be generated. A touch buffer film 118 a is provided, and the touch sensing layer TSL is provided on the touch buffer film 118 a to prevent liquid chemicals or moisture from penetrating into the light-emitting layer including the organic material during the manufacturing of the touch sensing layer TSL.

[0227] As described above, the touch buffer film 118a can prevent damage to the light-emitting layer, which is susceptible to liquid chemicals or moisture. To prevent damage to the light-emitting layer, which is composed of organic materials and susceptible to high temperatures, the touch buffer film 118a can be formed at a predetermined temperature (e.g., 100°C or lower) and can be formed of an organic insulating material with a low dielectric constant of 1-3. For example, the touch buffer film 118a can be formed of an acrylic, epoxy, or siloxane-based material.

[0228] The display device 100 of this embodiment may be a flexible display device. When the flexible display device is bent, the encapsulation layer ENCAP may be damaged. In this case, the touch sensor metal 171 disposed on the touch buffer film 118a may break. To prevent damage to the encapsulation layer ENCAP and breakage of the touch sensor metal 171 and bridge metal 172 that constitute the touch line 170 despite bending of the flexible display device, the touch buffer film 118a of one embodiment may be made of an inorganic insulating material and provide planarization properties.

[0229] The touch sensing layer TSL includes a light-shielding pattern BM disposed on the touch buffer film 118a. The light-shielding pattern BM is formed to correspond to the adjacent first to third sub-pixels SP1, SP2, and SP3, or between the first and second light-emitting portions EP1 and EP2. The light-shielding pattern BM may be disposed to overlap the touch sensor metal 171 or the bridge metal 172.

[0230] The light shielding pattern BM may be a black matrix and made of black resin or chromium oxide, etc. Alternatively, the light shielding pattern BM may be made of metal. In addition, since the touch sensor metal 171 or the bridge metal 172 can perform a light shielding function, the light shielding pattern BM may be omitted if necessary.

[0231] A lens layer LL may be disposed on the touch sensing layer TSL.

[0232] A first lens 182-1 and a second lens 184-1 are provided in regions corresponding to the first and second light-emitting portions EP1 and EP2. The first and second lenses 182-1 and 184-1 may be provided to correspond to the openings formed by the light-blocking pattern BM, respectively. Thus, light generated by the first light-emitting diode ED1 may be emitted through the first lens 182-1 corresponding to the sub-pixel, and light generated by the second light-emitting diode ED2 of each sub-pixel may be emitted through the second lens 184-1 corresponding to the sub-pixel.

[0233] The first lens 182-1 and the second lens 184-1 can limit the viewing angle by refracting light in a specific direction. That is, the first lens 182-1 is provided in the first light-emitting portion EP1 and refracts light from the first light-emitting diode ED1 in a specific direction. In addition, the second lens 184-1 is provided in the second light-emitting portion EP2 and refracts light from the second light-emitting diode ED2 in a specific direction.

[0234] For example, the first lens 182-1, which is a hemispherical lens, has a semicircular cross-section on a planar surface. In this case, the direction of light emitted from the first light-emitting diode ED1 of the first subpixel SP1 is limited to the first direction and the second direction. That is, when the first light-emitting portion EP1 displays an image, a narrow field of view mode with a limited viewing angle can be achieved.

[0235] The second lens 184-1, which is a semi-cylindrical lens, has a rectangular cross-section in one direction and a semi-circular cross-section in the other direction. The semi-cylindrical lens may not limit the viewing angle in one direction but may limit the viewing angle in the other direction.

[0236] Reference Figure 4 , the second lens 184-1 can have a semi-cylindrical shape that is elongated in the X-axis direction. Specifically, the second lens 184-1 can have a rectangular cross-section in the X-axis direction and a semi-circular cross-section in the Y-axis direction. Therefore, the second lens 184-1 limits the viewing angle in the Y-axis direction, but does not limit the viewing angle in the X-axis direction. For example, the second light-emitting portion EP2 provided with the semi-cylindrical second lens 184-1 can have a narrow viewing angle of 30 degrees or less in the Y-axis direction and a wide viewing angle of 60 degrees or more in the X-axis direction.

[0237] Reference Figure 5 The lens protection layer 119 is disposed on the first lens 182-1 and the second lens 184-1 to protect the first lens 182-1 and the second lens 184-1. The lens protection layer 119 may be made of an organic insulating material and have a flat upper surface. In addition, the refractive index of the lens protection layer 119 may be lower than the refractive index of the first lens 182-1 and the refractive index of the second lens 184-1.

[0238] In an example, the lens protection layer 119 may be made of photo acryl or benzocyclobutene (BCB), polyimide (PI), or polyamide (PA), but is not limited thereto.

[0239] In addition, despite Figure 5Although not shown, the cover glass may be attached via an adhesive layer. The adhesive layer may attach each of the components of the display device 100 to each other and may be formed, for example, using an optically clear adhesive for displays such as a pressure-sensitive adhesive, an optically clear adhesive (OCA), an optically clear resin (OCR), etc., but is not limited thereto. The cover glass may protect the components of the display device 100 from external impact and prevent damage such as scratches.

[0240] In addition, Figure 5 , only a cross-sectional view of the first sub-pixel SP1 is shown, but the structures of the second sub-pixel SP2 and the third sub-pixel SP3 are substantially the same as the structure of the first sub-pixel SP1, except that in the case of the second sub-pixel SP2 and the third sub-pixel SP3, the first anode electrode 142-2 and the second anode electrode 144-2 of the second sub-pixel SP2, and the first anode electrode 142-3 and the second anode electrode 144-3 of the third sub-pixel SP3 are connected to the pixel circuit in the row in which the corresponding pixels are provided.

[0241] In the following, reference is made to Figures 6 to 8C The structure of the optical area of ​​the display device of one embodiment is described in detail. Hereinafter, for the convenience of description, the display area DA (ie, the display area DA1 including the normal area NA and the first optical area DA1) in the display panel DP of the display device 100 is referred to as Figure 1A and Figure 1B ) is described as an example, but the description of the first optical area DA1 may be applied to the second optical area DA2 in the same manner.

[0242] Figure 6 This is a plan view of a pixel in the first optical region of a display device according to one embodiment.

[0243] exist Figure 6 , only the third openings 145c-1, 145c-2, 145c-3, the fourth openings 145d-1, 145d-2, 145d-3, the third lenses 186-1, 186-2, 186-3, and the fourth lenses 188-1, 188-2, 188-3 at each of the first to third subpixels SP1, SP2, SP3 in the first optical area DA1 are shown.

[0244] As reference Figure 3 The first optical area DA1 may include a light-emitting area EA and a transmissive area TA. The light-emitting area EA of the first optical area DA1 includes a first light-emitting area EA1 and a second light-emitting area EA2. The first light-emitting area EA1 is a light-emitting area in the first optical area DA1 for achieving a narrow viewing angle, and the second light-emitting area EA2 is a light-emitting area in the first optical area DA1 for achieving a wide viewing angle.

[0245] Reference Figure 3 and Figure 6 , the first light-emitting areas EA1 and the transmissive areas TA are alternately arranged in the X and Y directions. In addition, the second light-emitting areas EA2 and the transmissive areas TA are alternately arranged in the X and Y directions. Therefore, the first light-emitting areas EA1 and the second light-emitting areas EA2 may be arranged continuously in a diagonal direction relative to the X and Y directions, but are not limited in the present disclosure, and the first light-emitting areas EA1, the second light-emitting areas EA2, and the transmissive areas TA may be arranged in various ways.

[0246] Similar to the light-emitting area of ​​the normal area NA, each of the first light-emitting area EA1 and the second light-emitting area EA2 includes first to third sub-pixels SP1, SP2, and SP3, and the first sub-pixel SP1 can be a red sub-pixel, the second sub-pixel SP2 can be a green sub-pixel, and the third sub-pixel SP3 can be a blue sub-pixel.

[0247] Typically, the first to third sub-pixels SP1, SP2, SP3 included in the light-emitting area of ​​the normal area NA, and the first to third sub-pixels SP1, SP2, SP3 included in the first light-emitting area EA1 and the second light-emitting area EA2 of the first optical area DA1 are configured to emit light of the same color, but are not limited thereto and may be configured differently depending on the design. Hereinafter, for ease of description, the first to third sub-pixels SP1, SP2, SP3 of the normal area NA and the first optical area DA1 are configured to emit light of the same color, for example.

[0248] Reference Figure 6 , first to third sub-pixels SP1, SP2, and SP3 are provided in the first emission area EA1. The first to third sub-pixels SP1, SP2, and SP3 in the first emission area EA1 include third anode electrodes 146-1, 146-2, and 146-3, respectively. Each of the third anode electrodes 146-1, 146-2, and 146-3 is connected to a third thin film transistor Tr3 provided in each of the first to third sub-pixels SP1, SP2, and SP3.

[0249] At each of the first to third subpixels SP1, SP2, and SP3 in the first light-emitting area EA1, at least one third opening 145c-1, 145c-2, and 145c-3 is provided on the third anode electrodes 146-1, 146-2, and 146-3. In an XY plane diagram, each of the third openings 145c-1, 145c-2, and 145c-3 may have a shape in which the length in the X direction is substantially the same as the length in the Y direction. The shape and size of the third openings 145c-1, 145c-2, and 145c-3 formed in the first light-emitting area EA1 may be the same as the shape and size of the first openings 145a-1, 145a-2, and 145a-3 in the normal area.

[0250] exist Figure 6 In the embodiment of the present invention, four third openings 145c-1, 145c-2, and 145c-3 can be respectively provided on the first to third sub-pixels SP1, SP2, and SP3 in the first light emitting area EA1. Specifically, the four third openings 145c-1 in the first sub-pixel can be provided in the X direction and spaced apart by a predetermined distance. The four third openings 145c-2 in the second sub-pixel can be spaced apart in the Y direction relative to the third opening 145c-1 of the first sub-pixel. Similarly, the four third openings 145c-3 in the third sub-pixel can be spaced apart in the Y direction relative to the third opening 145c-2 of the second sub-pixel.

[0251] In response to each of the third openings 145c-1, 145c-2, and 145c-3, a hemispherical third lens 186-1, 186-2, and 186-3 is provided. The third lenses 186-1, 186-2, and 186-3 formed in the first light emitting area EA1 may have the same shape and size as the first lenses 182-1, 182-2, and 182-3 in the normal area. Each of the third lenses 186-1, 186-2, and 186-3 is provided to cover each of the third openings 145c-1, 145c-2, and 145c-3. On the XY plane surface, the surface area of ​​each of the third lenses 186-1, 186-2, and 186-3 may be larger than the surface area of ​​each of the third openings 145c-1, 145c-2, and 145c-3.

[0252] Similar to the first emission area EA1, first to third sub-pixels SP1, SP2, and SP3 are also provided in the second emission area EA2. The first to third sub-pixels SP1, SP2, and SP3 in the second emission area EA2 include fourth anode electrodes 148-1, 148-2, and 148-3, respectively. Each of the fourth anode electrodes 148-1, 148-2, and 148-3 is connected to a fourth thin film transistor Tr4 provided in each of the first to third sub-pixels SP1, SP2, and SP3.

[0253] In each of the first to third sub-pixels SP1, SP2, and SP3 in the second light-emitting area EA2, a fourth opening 145d-1, 145d-2, and 145d-3 is provided on the fourth anode electrodes 148-1, 148-2, and 148-3. In an XY plane view, each of the fourth openings 145d-1, 145d-2, and 145d-3 may have a long polygonal shape with a length in the X direction greater than a length in the Y direction. The shape and size of the fourth openings 145d-1, 145d-2, and 145d-3 formed in the second light-emitting area EA2 may be the same as the shape and size of the second openings 145b-1, 145b-2, and 145b-3 in the normal area.

[0254] In response to each of the fourth openings 145d-1, 145d-2, and 145d-3, a semi-cylindrical fourth lens 188-1, 188-2, and 188-3 is provided. The fourth lenses 188-1, 188-2, and 188-3 formed in the second light-emitting area EA2 may have the same shape and size as the second lenses 184-1, 184-2, and 184-3 in the normal area. Each of the fourth lenses 188-1, 188-2, and 188-3 is provided to cover each of the fourth openings 145d-1, 145d-2, and 145d-3. On the XY plane surface, the surface area of ​​each of the fourth lenses 188-1, 188-2, and 188-3 may be larger than the surface area of ​​each of the fourth openings 145d-1, 145d-2, and 145d-3.

[0255] On a plane surface, the third anode electrodes 146-1, 146-2, 146-3 and the fourth anode electrodes 148-1, 148-2, 148-3 in the first light-emitting area EA1 and the second light-emitting area EA2 of the first optical area DA1 may have the same shape or similar shapes. However, the light-shielding pattern BM in the first light-emitting area EA1 and the second light-emitting area EA2 of the first optical area DA1 may have different shapes on a plane surface. Therefore, the shapes of the openings formed by the light-shielding pattern BM may be different.

[0256] In particular, the light-shielding pattern BM formed in the second light-emitting area EA2 may have a shape different from that of the light-shielding pattern BM formed in the normal area NA. Figure 4 and Figure 5 , the light shielding pattern BM formed in the light emitting area of ​​the normal area NA is shaped to surround the light emitting area of ​​each sub-pixel. For example, the light shielding pattern BM may form an opening wider than the first light emitting portion EP1 and the second light emitting portion EP2 to surround the first light emitting portion EP1 of the first light emitting diode ED1 and the second light emitting portion EP2 of the second light emitting diode ED2. Figure 4 The light-shielding pattern BM overlaps the first anode and the second anode, and is formed in both the X direction and the Y direction.

[0257] However, the light shielding pattern BM formed in the second light emitting area EA2 has a structure that is open in one direction and does not surround the light emitting area of ​​each sub-pixel. Figure 6 , the light-shielding pattern BM is not arranged in the first sub-pixel of the second light-emitting area EA2 in the X-axis direction, but is arranged around the light-emitting portion in the Y-axis direction. Therefore, both sides of the light-shielding pattern BM are open in the X-axis direction around the fourth anode. Therefore, on a plane surface, the embankment 116 defining the light-emitting portion of the fourth light-emitting diode can be exposed around the fourth anode in the X-axis direction and be seen. Therefore, the fourth openings 145d-1, 145d-2, 145d-3 of the second light-emitting area EA2 defined by the light-shielding pattern BM can be completely open in the X-axis direction in the second light-emitting area EA2 and have a larger surface area than the second openings 145b-1, 145b-2, 145b-3 of the normal area NA. As shown in FIG. Figure 6 As shown, since the semi-cylindrical fourth lenses 188-1, 188-2, and 188-3 arranged on the fourth openings 145d-1, 145d-2, and 145d-3 limit the viewing angle in the Y-axis direction but do not limit the viewing angle in the X-axis direction, when the shading pattern BM is configured to be open in the X-axis direction to achieve a wide viewing angle, the limitation of the viewing angle in the X-axis direction by the shading pattern BM can be solved, and a wider viewing angle can be provided in the X-axis direction.

[0258] As described above, in the display device of one embodiment, even in the first optical region including the transmissive region TA, hemispherical third lenses 186-1, 186-2, 186-3 are provided in response to the third anode electrodes 146-1, 146-2, 146-3, and semi-cylindrical fourth lenses 188-1, 188-2, 188-3 are provided in response to the fourth anode electrodes 148-1, 148-2, 148-3 to limit the viewing angle. In this case, the direction in which the third lenses 186-1, 186-2, 186-3 limit the viewing angle can be different from the direction in which the fourth lenses 188-1, 188-2, 188-3 limit the viewing angle, and wide and narrow viewing angles can be achieved based on selective driving.

[0259] In the following, reference is made to Figure 7 The fourth light emitting diode ED4 of the first optical area DA1 will be described in detail.

[0260] Figure 7 It is along Figure 6 C-C' cross-sectional view. Figure 7 is a cross-sectional view of the first sub-pixel SP1 of the second light emitting area EA2 and the transmission area TA of the first optical area DA1.

[0261] Each of the second light emitting area EA2 and the transmission area TA of the first optical area DA1 may basically include a substrate SUB, a transistor layer TRL, a planarization layer PLN, a light emitting diode layer EDL, an encapsulation layer ENCAP, a touch sensing layer TSL, and a protective layer 119. At this time, an optical electronic device 190 may be disposed under the substrate SUB in the first optical area DA1.

[0262] The substrate SUB, transistor layer TRL, planarization layer PLN, light emitting diode layer EDL, encapsulation layer ENCAP, touch sensing layer TSL and lens layer LL included in the first optical area DA1 are the same as those in the above reference. Figure 5 Components denoted by the same reference numerals in the normal area NA described above are substantially the same, and therefore, the same components will not be described.

[0263] As described above, each sub-pixel in the second light emitting area EA2 of the first optical area DA1 has a light shielding pattern BM shape different from the light shielding pattern BM shape in the normal area NA. Therefore, since the light shielding pattern BM is open in the X-axis direction on the plane surface, the second light emitting area EA2 does not have the light shielding pattern BM in its partial area, unlike the normal area NA. Figure 6 and Figure 7 , the light shielding pattern BM may not be provided on a portion of the touch electrode. Therefore, the end of the bank may be exposed in the X-axis direction while being covered by the light shielding pattern in the Y-axis direction.

[0264] Hereinafter, the transmissive area TA provided in the first optical area DA1 is described.

[0265] The substrate SUB and various types of insulating films 111a, 111b, 112, 113a, 113b, 114, 115a, 115b, 117a, 117b, 117c, PAC disposed in the second light emitting area EA2 of the first optical area DA1 may also be disposed in the transmission area TA of the first optical area DA1 in the same manner.

[0266] However, except for the insulating material disposed in the second light emitting area EA2 of the first optical area DA1 , a material layer having electrical or opaque properties may not be disposed in the transmission area TA of the first optical area DA1 .

[0267] For example, the bank 116 may not be provided in the transmission area TA. In the case where the bank 116 is a black bank or a colored bank having a black color, the bank 116 is not provided in the transmission area TA except for a portion near the first and second emission areas EA1 and EA2.

[0268] In addition, the metal material layers 135, 131, GM, TM, 132, 133, 125 and the semiconductor layer 134 associated with the transistor are not disposed in the transmission area TA. The anode included in the light-emitting diode ED may not be disposed in the transmission area TA, the cathode 160 may not be disposed in the transmission area TA except for a portion of the area near the first light-emitting area EA1 and the second light-emitting area EA2, and the light-emitting layer may be disposed in the transmission area TA or not. The touch sensor metal 171 and the bridge metal 172 included in the touch sensor are not disposed in the transmission area TA.

[0269] Since the transmission area TA in the first optical area DA1 overlaps the optical electronic device 190, it is necessary to ensure transmittance of the transmission area TA so that the optical electronic device 190 can operate normally. In one embodiment, to ensure transmittance of the transmission area TA, the cathode 160 is not disposed in the transmission area TA.

[0270] To this end, a deposition prevention layer (not shown) made of an organic material may be provided on the second planarization layer 115b and the light-emitting layer of the transmission area TA. The deposition prevention layer may serve to prevent the cathode 160 from being deposited. Since the cathode electrode material may not be deposited on the deposition prevention layer during the formation of the cathode electrode, the cathode electrode may be selectively formed on the substrate SUB. For example, the deposition prevention layer may be deposited using a mask (fine metal mask; FMM) to correspond to the transmission area TA. Specifically, the FMM is placed in such a way that the transmission area TA is exposed, and then the deposition prevention layer may be formed. In the case where the cathode 160 is deposited after the deposition prevention layer is provided on the light-emitting layer of the transmission area TA, the cathode 160 may not be deposited in the area where the deposition prevention layer is provided due to the low adhesion between the deposition prevention layer and the layer provided thereon.

[0271] In the display device 100 of one embodiment, optical areas DA1 and DA2 including a transmissive area TA are provided to provide various optical electronic devices 190 below the display panel. At this time, a plurality of lenses may be used to achieve: a wide viewing angle, in which a wide viewing angle is ensured based on a user's selective driving mode; and a narrow viewing angle, in which the viewing angle is limited to improve safety. However, in the case of limiting the viewing angle by using a lens, the optical area including the transmissive area may have a lower pixel aperture ratio than a normal area not including the transmissive area, and therefore, the life of the pixel may be reduced. Figure 3 As shown, when the pixel arrangement structure of the normal area NA is applied to the optical areas DA1 and DA2 including the transmission area TA by limiting the viewing angle using a lens, the aperture ratio of the sub-pixels in the optical areas DA1 and DA2 may be significantly reduced due to the need to ensure the transmission area TA.

[0272] However, in the display device 100 of one embodiment, the second light-emitting area EA2 providing a wide viewing angle and the first light-emitting area EA1 providing a narrow viewing angle in the optical areas DA1 and DA2 are separately arranged to significantly increase the aperture ratio per unit surface area. As the aperture ratio of the sub-pixels in the optical areas DA1 and DA2 increases, the current density in the light-emitting diode of each sub-pixel can be reduced, and thus, the life of the element can be increased.

[0273] For example, in the comparative example where the sub-pixel arrangement structure of the normal area is applied to the optical area, Figure 3 Compared to an embodiment where the subpixel arrangement structure shown is applied to the optical area, while the transmittance in the optical area remains the same, the aperture ratio of the subpixels can be increased, and the current density per subpixel can be reduced by approximately 50%. Consequently, the lifespan of the subpixels in the optical area can be improved.

[0274] Hereinafter, the configuration and driving method of the pixel circuit of a plurality of sub-pixels are described in detail.

[0275] The switching element constituting each of the plurality of sub-pixels may be implemented as a transistor having an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. In the embodiments provided below, a p-type transistor is provided as an example, but is not limited thereto.

[0276] A transistor is a three-electrode device consisting of a gate electrode, a source electrode, and a drain electrode. The source electrode is the electrode that supplies carriers to the transistor. Carriers in a transistor begin flowing from the source electrode. The drain electrode is the electrode from which carriers exit the transistor. That is, in a MOSFET, carriers flow from the source electrode to the drain electrode. In an n-type MOSFET (NMOS), since the carriers are electrons, the voltage at the source electrode is lower than the voltage at the drain electrode, allowing electrons to flow from the source electrode to the drain electrode. Since electrons flow from the source electrode to the drain electrode in an n-type MOSFET, current flows from the drain electrode to the source electrode. In a p-type MOSFET (PMOS), since the carriers are holes, the voltage at the source electrode is higher than the voltage at the drain electrode, allowing holes to flow from the source electrode to the drain electrode. Since holes flow from the source electrode to the drain electrode in a p-type MOSFET, current flows from the source electrode to the drain electrode. It is important to note that the source and drain electrodes of a MOSFET are not fixed. For example, the source and drain electrodes of a MOSFET can change depending on the supplied voltage. In the embodiments described below, the subject matter of the present disclosure is not limited to the source electrode and the drain electrode of the transistor.

[0277] Figure 8A is a circuit diagram of a sub-pixel in a normal area of ​​a display device according to one embodiment.

[0278] Each of the plurality of sub-pixels SP1 , SP2 , SP3 includes a first light emitting diode ED1 , a second light emitting diode ED2 , a driving transistor DT, first to eighth transistors T1 to T8 , and a capacitor Cst.

[0279] Each of the first light-emitting diode ED1 and the second light-emitting diode ED2 emits light by a drive current supplied from the drive transistor DT. Specifically, the anode electrode of the first light-emitting diode ED1 is connected to the seventh transistor T7, and the cathode electrode of the first light-emitting diode ED1 is connected to the input terminal of the low-potential drive voltage VSS. In addition, the anode electrode of the second light-emitting diode ED2 is connected to the eighth transistor T8, and the cathode electrode of the second light-emitting diode ED2 is connected to the input terminal of the low-potential drive voltage VSS.

[0280] The driving transistor DT controls the driving current supplied to each first light emitting diode ED1 based on the voltage Vsg between its source and gate. In addition, the source electrode of the driving transistor DT is connected to the input terminal of the high potential driving voltage VDD, the gate electrode is connected to the second node N2, and the drain electrode is connected to the first node N1.

[0281] The first transistor T1 supplies the data voltage Vdata supplied from the data line to the third node N3. The first transistor T1 includes a source electrode connected to the data line, a drain electrode connected to the third node N3, and a gate electrode connected to the first scan signal line transmitting the first scan signal Scan1. Therefore, the first transistor T1 supplies the data voltage Vdata supplied from the data line to the third node N3 in response to the first scan signal Scan1 of a low level as a turn-on level.

[0282] The second transistor T2 is diode-connected to the gate electrode and drain electrode of the driving transistor DT. The second transistor T2 includes a drain electrode connected to the second node N2, a source electrode connected to the first node N1, and a gate electrode connected to the second scan signal line transmitting the second scan signal Scan2. Therefore, the second transistor T2 is diode-connected to the gate electrode and drain electrode of the driving transistor DT in response to the second scan signal Scan2 at a low level, which is a conduction level.

[0283] The third transistor T3 supplies a reference voltage Vref to the third node N3. The third transistor T3 includes a source electrode connected to a reference voltage line transmitting the reference voltage Vref, a drain electrode connected to the third node N3, and a gate electrode connected to a first light emitting signal line transmitting the first light emitting signal EM1. Therefore, the third transistor T3 supplies the reference voltage Vref to the third node N3 in response to the first light emitting signal EM1 at a low level, which is a turn-on level.

[0284] The fourth transistor T4 forms a current path between the drive transistor DT and the first light-emitting diode ED1 or the second light-emitting diode ED2. The fourth transistor T4 includes a source electrode connected to the first node N1, a drain electrode connected to the fourth node N4, and a gate electrode connected to the first light-emitting signal line that transmits the first light-emitting signal EM1. The fourth transistor T4 forms a current path between the first node N1 and the fourth node N4 of the fourth transistor T4 in response to the first light-emitting signal EM1. Therefore, depending on whether the seventh transistor T7 and the eighth transistor T8 described below are turned on or off, the fourth transistor T4 forms a current path between the drive transistor DT and the first light-emitting diode ED1 or between the drive transistor DT and the second light-emitting diode ED2 in response to the first light-emitting signal EM1, which is a low level and is at a turn-on level.

[0285] The fifth transistor T5 supplies a reference voltage Vref to the anode electrode of the second light-emitting diode ED2. The fifth transistor T5 may include a source electrode connected to a reference voltage line supplying the reference voltage Vref, a drain electrode connected to the anode electrode of the second light-emitting diode ED2, and a gate electrode connected to a second scan signal line supplied with a second scan signal Scan2. The fifth transistor T5 can be turned on or off by the second scan signal Scan2. Therefore, the fifth transistor T5 can supply the reference voltage Vref to the anode electrode of the second light-emitting diode ED2 in response to the second scan signal Scan2 being at a low level, which is a conduction level.

[0286] The sixth transistor T6 supplies a reference voltage Vref to the anode electrode of the first light-emitting diode ED1. The sixth transistor T6 includes a source electrode connected to a reference voltage line supplying the reference voltage Vref, a drain electrode connected to the anode electrode of the first light-emitting diode ED1, and a gate electrode connected to a second scan signal line transmitting a second scan signal Scan2. The sixth transistor T6 can be turned on or off by the second scan signal Scan2. Therefore, the sixth transistor T6 can supply the reference voltage Vref to the anode electrode of the first light-emitting diode ED1 in response to the second scan signal Scan2 being at a low level, which is a conduction level.

[0287] The seventh transistor T7 forms a current path between the driving transistor DT and the first light-emitting diode ED1. The seventh transistor T7 includes a source electrode connected to the fourth node N4, a drain electrode connected to the anode electrode of the first light-emitting diode ED1, and a gate electrode connected to the second light-emitting signal line that transmits the second light-emitting signal EM2. In response to the second light-emitting signal EM2, the seventh transistor T7 forms a current path between the fourth node N4, which serves as the source electrode of the seventh transistor T7, and the first light-emitting diode ED1. Therefore, the seventh transistor T7 forms a current path between the driving transistor DT and the first light-emitting diode ED1 in response to the second light-emitting signal EM2, which is a low-level turn-on level.

[0288] The eighth transistor T8 forms a current path between the driving transistor DT and the second light-emitting diode ED2. The eighth transistor T8 includes a source electrode connected to the fourth node N4, a drain electrode connected to the anode electrode of the second light-emitting diode ED2, and a gate electrode connected to a third light-emitting signal line that transmits the third light-emitting signal EM3. In response to the third light-emitting signal EM3, the eighth transistor T8 forms a current path between the fourth node N4, which serves as the source electrode of the eighth transistor T8, and the second light-emitting diode ED2. Therefore, the eighth transistor T8 forms a current path between the driving transistor DT and the second light-emitting diode ED2 in response to the third light-emitting signal EM3 at a low level, which is a conduction level.

[0289] The capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3. That is, one electrode of the capacitor Cst is connected to the gate electrode of the driving transistor DT, and the other electrode of the capacitor Cst is connected to the first transistor T1 and the third transistor T3.

[0290] Figure 8B This is a circuit diagram of a sub-pixel in a first light-emitting region in a first optical region of a display device according to an embodiment.

[0291] Each of the plurality of sub-pixels SP1 , SP2 , SP3 includes a third light emitting diode ED3 , a driving transistor DT, first to fourth transistors T1 to T4 , sixth to seventh transistors T6 to T7 , and a capacitor Cst.

[0292] An anode electrode of the third light emitting diode ED3 is connected to the seventh transistor T7 , and a cathode electrode of the third light emitting diode ED3 is connected to an input terminal of the low potential driving voltage VSS.

[0293] The driving transistor DT controls the driving current supplied to the third light emitting diode ED3 according to the voltage Vsg between its source and gate. In addition, the source electrode of the driving transistor DT is connected to the input terminal of the high potential driving voltage VDD, the gate electrode is connected to the second node N2, and the drain electrode is connected to the first node N1.

[0294] The first transistor T1 supplies the data voltage Vdata supplied from the data line to the third node N3. The first transistor T1 includes a source electrode connected to the data line, a drain electrode connected to the third node N3, and a gate electrode connected to the first scan signal line transmitting the first scan signal Scan1. Therefore, the first transistor T1 supplies the data voltage Vdata supplied from the data line to the third node N3 in response to the first scan signal Scan1 of a low level as a turn-on level.

[0295] The second transistor T2 is diode-connected to the gate electrode and drain electrode of the driving transistor DT. The second transistor T2 includes a drain electrode connected to the second node N2, a source electrode connected to the first node N1, and a gate electrode connected to the second scan signal line transmitting the second scan signal Scan2. Therefore, the second transistor T2 is diode-connected to the gate electrode and drain electrode of the driving transistor DT in response to the second scan signal Scan2 at a low level, which is a conduction level.

[0296] The third transistor T3 supplies a reference voltage Vref to the third node N3. The third transistor T3 includes a source electrode connected to a reference voltage line transmitting the reference voltage Vref, a drain electrode connected to the third node N3, and a gate electrode connected to a first light emitting signal line transmitting the first light emitting signal EM1. Therefore, the third transistor T3 supplies the reference voltage Vref to the third node N3 in response to the first light emitting signal EM1 at a low level, which is a turn-on level.

[0297] The fourth transistor T4 forms a current path between the driving transistor DT and the third light-emitting diode ED3. The fourth transistor T4 includes a source electrode connected to the first node N1, a drain electrode connected to the seventh transistor T7, and a gate electrode connected to the first light-emitting signal line that transmits the first light-emitting signal EM1. The fourth transistor T4 forms a current path between the first node N1 of the seventh transistor T7 and the fourth transistor T4 in response to the first light-emitting signal EM1. Therefore, depending on whether the seventh transistor T7 is turned on or off, the fourth transistor T4 forms a current path between the driving transistor DT and the third light-emitting diode ED3 in response to the first light-emitting signal EM1, which is at a low level and has a conduction level.

[0298] The sixth transistor T6 supplies a reference voltage Vref to the anode electrode of the third light-emitting diode ED3. The sixth transistor T6 includes a source electrode connected to a reference voltage line supplying the reference voltage Vref, a drain electrode connected to the anode electrode of the third light-emitting diode ED3, and a gate electrode connected to a second scan signal line transmitting the second scan signal Scan2. The sixth transistor T6 can be turned on or off by the second scan signal Scan2. Therefore, the sixth transistor T6 can supply the reference voltage Vref to the anode electrode of the third light-emitting diode ED3 in response to the second scan signal Scan2 being at a low level, which is the on-level.

[0299] The seventh transistor T7 forms a current path between the driving transistor DT and the third light-emitting diode ED3. The seventh transistor T7 includes a source electrode connected to the fourth transistor T4, a drain electrode connected to the anode electrode of the third light-emitting diode ED3, and a gate electrode connected to a second light-emitting signal line that transmits the second light-emitting signal EM2. The seventh transistor T7 forms a current path between the fourth transistor T4 and the third light-emitting diode ED3 in response to the second light-emitting signal EM2. Therefore, the seventh transistor T7 forms a current path between the driving transistor DT and the third light-emitting diode ED3 in response to the second light-emitting signal EM2 at a low level, which is the conduction level.

[0300] The capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3. That is, one electrode of the capacitor Cst is connected to the gate electrode of the driving transistor DT, and the other electrode of the capacitor Cst is connected to the first transistor T1 and the third transistor T3.

[0301] Figure 8C This is a circuit diagram of a sub-pixel in a second light-emitting region in a first optical region of a display device according to an embodiment.

[0302] Each of the plurality of sub-pixels SP1 , SP2 , SP3 includes a fourth light emitting diode ED4 , a driving transistor DT, first to fifth transistors T1 to T5 , an eighth transistor T8 , and a capacitor Cst.

[0303] An anode electrode of the fourth light emitting diode ED4 is connected to the fourth transistor T4 , and a cathode electrode of the fourth light emitting diode ED4 is connected to an input terminal of the low potential driving voltage VSS.

[0304] The driving transistor DT controls the driving current supplied to the fourth light emitting diode ED4 according to the voltage Vsg between its source and gate. In addition, the source electrode of the driving transistor DT is connected to the input terminal of the high potential driving voltage VDD, the gate electrode is connected to the second node N2, and the drain electrode is connected to the first node N1.

[0305] The first transistor T1 supplies the data voltage Vdata supplied from the data line to the third node N3. The first transistor T1 includes a source electrode connected to the data line, a drain electrode connected to the third node N3, and a gate electrode connected to the first scan signal line transmitting the first scan signal Scan1. Therefore, the first transistor T1 supplies the data voltage Vdata supplied from the data line to the third node N3 in response to the first scan signal Scan1 of a low level as a turn-on level.

[0306] The second transistor T2 is diode-connected to the gate electrode and drain electrode of the driving transistor DT. The second transistor T2 includes a drain electrode connected to the second node N2, a source electrode connected to the first node N1, and a gate electrode connected to the second scan signal line transmitting the second scan signal Scan2. Therefore, the second transistor T2 is diode-connected to the gate electrode and drain electrode of the driving transistor DT in response to the second scan signal Scan2 at a low level, which is a conduction level.

[0307] The third transistor T3 supplies a reference voltage Vref to the third node N3. The third transistor T3 includes a source electrode connected to a reference voltage line transmitting the reference voltage Vref, a drain electrode connected to the third node N3, and a gate electrode connected to a first light emitting signal line transmitting the first light emitting signal EM1. Therefore, the third transistor T3 supplies the reference voltage Vref to the third node N3 in response to the first light emitting signal EM1 at a low level, which is a turn-on level.

[0308] The fourth transistor T4 forms a current path between the driving transistor DT and the fourth light-emitting diode ED4. The fourth transistor T4 includes a source electrode connected to the first node N1, a drain electrode connected to the eighth transistor T8, and a gate electrode connected to the first light-emitting signal line that transmits the first light-emitting signal EM1. In response to the first light-emitting signal EM1, the fourth transistor T4 forms a current path between the eighth transistor T8 and the first node N1 of the fourth transistor T4. Therefore, depending on whether the eighth transistor T8 is turned on or off, the fourth transistor T4 forms a current path between the driving transistor DT and the fourth light-emitting diode ED4 in response to the low-level first light-emitting signal EM1, which is the on-level.

[0309] The fifth transistor T5 supplies a reference voltage Vref to the anode electrode of the fourth light-emitting diode ED4. The fifth transistor T5 may include a source electrode connected to a reference voltage line supplying the reference voltage Vref, a drain electrode connected to the anode electrode of the fourth light-emitting diode ED4, and a gate electrode connected to a second scan signal line supplied with a second scan signal Scan2. The fifth transistor T5 can be turned on or off by the second scan signal Scan2. Therefore, the fifth transistor T5 can supply the reference voltage Vref to the anode electrode of the fourth light-emitting diode ED4 in response to the second scan signal Scan2 being at a low level, which is a conduction level.

[0310] The eighth transistor T8 forms a current path between the driving transistor DT and the fourth light-emitting diode ED4. The eighth transistor T8 includes a source electrode connected to the fourth transistor T4, a drain electrode connected to the anode electrode of the fourth light-emitting diode ED4, and a gate electrode connected to a third light-emitting signal line that transmits the third light-emitting signal EM3. The eighth transistor T8 forms a current path between the fourth transistor T4 and the fourth light-emitting diode ED4 in response to the third light-emitting signal EM3. Therefore, the eighth transistor T8 forms a current path between the driving transistor DT and the fourth light-emitting diode ED4 in response to the third light-emitting signal EM3 at a low level, which is a conduction level.

[0311] The capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3. That is, one electrode of the capacitor Cst is connected to the gate electrode of the driving transistor DT, and the other electrode of the capacitor Cst is connected to the first transistor T1 and the third transistor T3.

[0312] Figure 9 1 is a diagram for describing an example of driving of a normal area and a first optical area of ​​a display device according to one embodiment. Figure 9 In the embodiment, for the convenience of description, only the light emitting area, the transmission area, the circuit area, and the data lines constituting the normal area and the first optical area including the sub-pixels are described.

[0313] Reference Figure 9 The first light-emitting regions and the transmissive regions of the first optical region are alternately arranged in the row direction (X-axis direction) and the column direction (Y-axis direction), and the second light-emitting regions and the transmissive regions of the first optical region are alternately arranged in the row direction (X-axis direction) and the column direction (Y-axis direction). The unit pixels of the normal region are arranged to surround the first optical region.

[0314] The first data line DL1 is connected to the first column (the nth column), and the second data line DL2 is connected to the second column (the n+1th column). The sub-pixels of the first light-emitting area EA1 arranged in the first column are connected to the first data line DL1, and the sub-pixels of the second light-emitting area EA2 arranged in the second column are connected to the second data line DL2.

[0315] The first data line DL1 reaches the normal area, moves in the row direction (X-axis direction), and is connected to the light-emitting area of ​​the second column (n+1 column) in the normal area. In addition, although the second data line DL2 reaches the normal area, the second data line DL2 continues to extend in the column direction (Y-axis direction) and is connected to the light-emitting area of ​​the second column (n+1 column). The first data line DL1 and the second data line DL2 that have reached the normal area are connected to the second column and the third column placed on both sides thereof.

[0316] based on Figure 9 In the arrangement shown, the first data line DL1 transmits the second luminous signal to the sub-pixels in the first luminous region of the first optical region, and the second data line DL2 transmits the third luminous signal to the sub-pixels in the second luminous region of the first optical region. In addition, the first data line DL1 and the second data line DL2 that have reached the normal region can respectively transmit both the second luminous signal and the third luminous signal to the sub-pixels located on both sides thereof.

[0317] Figure 10 is a diagram showing an example of a display device according to an embodiment.

[0318] The display device 100 according to one embodiment may be disposed in at least a portion of a vehicle's instrument panel. The instrument panel includes components disposed on the front surfaces of the vehicle's front seats (e.g., the driver's seat, the passenger seat). For example, the instrument panel may include input components for operating various functional devices in the vehicle (e.g., the air conditioner, the audio system, the navigation system).

[0319] The display device 100 of one embodiment may be provided in a dashboard of a vehicle and may function as an input component for manipulating at least a portion of various functions of the vehicle. The display device 100 may provide various types of information about the vehicle, such as vehicle operating information (e.g., current speed, remaining fuel level, and travel distance) and information about vehicle components (e.g., tire wear).

[0320] The display device 100 may be provided across a driver's seat and a passenger seat provided in front of the vehicle. Users of the display device 100 may include the driver of the vehicle and a passenger on the passenger seat of the vehicle. Both the driver and the passenger may use the display device 100.

[0321] exist Figure 10 In FIG, only a portion of the display device 100 may be shown. Figure 10 , a display panel among various components included in the display device 100 may be shown. Specifically, Figure 10 For example, at least a portion of the display area and non-display area of ​​the display panel in the display device 100 is shown. Figure 10 Components other than those shown may be installed in the vehicle (or at least a portion of a vehicle).

[0322] Exemplary embodiments of the present disclosure may also be described as follows:

[0323] According to one aspect of the present disclosure, a display device is provided. The display device includes a substrate on which a plurality of sub-pixels are arranged. The substrate includes a first display area including a first light-emitting area, a second light-emitting area, and a transmissive area, and a second display area surrounding the first display area. Each of the sub-pixels arranged in the second display area includes: a first thin-film transistor and a second thin-film transistor; a first light-emitting diode including a first anode electrode, a first light-emitting layer, and a cathode electrode connected to the first thin-film transistor; a second light-emitting diode including a second anode electrode, a second light-emitting layer, and a cathode electrode connected to the second thin-film transistor and emitting light of the same color as the light emitted by the first light-emitting diode; a first lens corresponding to the first light-emitting diode and refracting light from the first light-emitting diode; and a second lens corresponding to the second light-emitting diode and refracting light from the second light-emitting diode. Each of the sub-pixels arranged in the first light-emitting area includes: a third thin-film transistor; a third light-emitting diode including a third anode electrode, a third light-emitting layer, and a cathode electrode connected to the third thin-film transistor; and a third lens corresponding to the third light-emitting diode and refracting light from the third light-emitting diode. Each of the sub-pixels disposed in the second light-emitting area includes: a fourth thin film transistor; a fourth light-emitting diode including a fourth anode electrode connected to the fourth thin film transistor, a fourth light-emitting layer, and a cathode electrode; and a fourth lens corresponding to the fourth light-emitting diode and refracting light from the fourth light-emitting diode.

[0324] The first light emitting layer and the second light emitting layer may be connected to each other and may be integrally formed.

[0325] The first lens and the third lens may be hemispherical lenses, and the second lens and the fourth lens may be semi-cylindrical lenses.

[0326] The display device can be selectively driven in a narrow field of view mode and a wide field of view mode. In the narrow field of view mode, the first LED emits light so that light from the first LED can be output in such a manner that the first lens limits the viewing angle of the light from the first LED with respect to a first direction and a second direction, and the third LED emits light so that light from the third LED can be output in such a manner that the third lens limits the viewing angle of the light from the third LED with respect to the first direction and the second direction. In the wide field of view mode, the second LED can emit light so that light from the second LED can be output in such a manner that the second lens limits the viewing angle of the light from the second LED only with respect to the first direction, and the fourth LED emits light so that light from the fourth LED can be output in such a manner that the fourth lens limits the viewing angle of the light from the fourth LED only with respect to the first direction.

[0327] The plurality of sub-pixels may include red, green, and blue sub-pixels. Each of the sub-pixels disposed in the first display area may have a size larger than that of each of the plurality of sub-pixels emitting light of a corresponding color disposed in the second display area.

[0328] The display device may further include a bank layer provided on the substrate and including a first opening exposing the first anode electrode, a second opening exposing the second anode electrode, a third opening exposing the third anode electrode, and a fourth opening exposing the fourth anode electrode. The number of the third openings in each of the sub-pixels provided in the first light-emitting region may be greater than the number of the first openings in each of the sub-pixels emitting light of the corresponding color provided in the second display region.

[0329] The number of the third lenses disposed in each of the sub-pixels of the first light emitting area may be greater than the number of the first lenses disposed in each of the sub-pixels of the second display area that emit light of a corresponding color.

[0330] The first light emitting regions and the transmission regions may be alternately arranged in a first direction and a second direction perpendicular to the first direction, and the second light emitting regions and the transmission regions may be alternately arranged in the first direction and the second direction.

[0331] The display device may further include: gate lines extending in a row direction; and data lines extending in a column direction and intersecting the gate lines. The data lines may include a first data line disposed in an nth column and connected to a third light-emitting diode of a sub-pixel in a first light-emitting region, and a second data line disposed in an n+1th column and connected to a fourth light-emitting diode of a sub-pixel in a second light-emitting region, where n is a natural number greater than or equal to 1.

[0332] When the second data line extends to the second display area, the second data line can continue to extend in the column direction. When the first data line extends to the second display area, the first data line can move in the row direction and extend close to the second data line in the (n+1)th column.

[0333] The first data line may be connected to the first light emitting diodes of the sub-pixels disposed at both sides of the first data line. The second data line may be connected to the second light emitting diodes of the sub-pixels disposed at both sides of the second data line.

[0334] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device comprising: A substrate is provided with a plurality of sub-pixels, and the substrate includes a first display area including a first light-emitting area, a second light-emitting area and a transmission area, and a second display area surrounding the first display area, wherein: Each of the sub-pixels arranged on the second display area includes: a first thin film transistor and a second thin film transistor; a first light emitting diode including a first anode electrode connected to the first thin film transistor, a first light emitting layer, and a cathode electrode; a second light emitting diode including a second anode electrode connected to the second thin film transistor, a second light emitting layer, and a cathode electrode, and emitting light of the same color as that of the first light emitting diode; and a first lens corresponding to the first light emitting diode and refracting light from the first light emitting diode, and a second lens corresponding to the second light emitting diode and refracting light from the second light emitting diode, Each of the sub-pixels disposed in the first light emitting area includes: a third thin film transistor; a third light emitting diode including a third anode electrode connected to the third thin film transistor, a third light emitting layer, and a cathode electrode; and a third lens corresponding to the third light emitting diode and refracting light from the third light emitting diode, Each of the sub-pixels disposed in the second light emitting area includes: a fourth thin film transistor; a fourth light emitting diode including a fourth anode electrode connected to the fourth thin film transistor, a fourth light emitting layer, and a cathode electrode; and a fourth lens corresponding to the fourth light emitting diode and refracting light from the fourth light emitting diode.

2. The display device according to claim 1, wherein The first light emitting layer and the second light emitting layer are connected to each other and formed integrally.

3. The display device according to claim 1, wherein The first lens and the third lens are hemispherical lenses, and The second lens and the fourth lens are semi-cylindrical lenses.

4. The display device according to claim 1, wherein The display device is selectively driven in a narrow field of view mode and a wide field of view mode, In the narrow field of view mode, the first light-emitting diode emits light so that the light from the first light-emitting diode is output in such a manner that the first lens limits the viewing angle of the light from the first light-emitting diode with respect to a first direction and a second direction, and the third light-emitting diode emits light so that the light from the third light-emitting diode is output in such a manner that the third lens limits the viewing angle of the light from the third light-emitting diode with respect to the first direction and the second direction, and In the wide field of view mode, the second LED emits light so that the light from the second LED is output in such a manner that the second lens limits the viewing angle of the light from the second LED only with respect to the first direction, and the fourth LED emits light so that the light from the fourth LED is output in such a manner that the fourth lens limits the viewing angle of the light from the fourth LED only with respect to the first direction.

5. The display device according to claim 1, wherein The plurality of sub-pixels include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and Each of the sub-pixels disposed in the first display area has a size larger than a size of each of the plurality of sub-pixels emitting light of a corresponding color disposed in the second display area. The display device according to claim 5 , wherein: The display device further includes a bank layer provided on the substrate and including a first opening for exposing the first anode electrode, a second opening for exposing the second anode electrode, a third opening for exposing the third anode electrode, and a fourth opening for exposing the fourth anode electrode. The number of the third openings of each of the sub-pixels disposed in the first light emitting area is greater than the number of the first openings of each of the sub-pixels emitting light of a corresponding color disposed in the second display area.

7. The display device according to claim 6, wherein: The number of the third lenses provided in each of the sub-pixels of the first light emitting area is greater than the number of the first lenses provided in each of the sub-pixels of the second display area that emit light of a corresponding color.

8. The display device according to claim 1, wherein The first light emitting regions and the transmission regions are alternately arranged in a first direction and a second direction perpendicular to the first direction, and The second light emitting areas and the transmission areas are alternately arranged in the first direction and the second direction.

9. The display device according to claim 8, further comprising: gate lines extending in a row direction; as well as data lines extending in a column direction and crossing the gate lines, The data lines include a first data line of the third light-emitting diode arranged in the nth column and connected to the sub-pixel of the first light-emitting area, and a second data line of the fourth light-emitting diode arranged in the n+1th column and connected to the sub-pixel of the second light-emitting area, wherein n is a natural number greater than or equal to 1.

10. The display device according to claim 9, wherein When the second data line extends to the second display area, the second data line continues to extend toward the column direction, and In a case where the first data line extends to the second display area, the first data line moves in the row direction and extends close to the second data line in the (n+1)th column.

11. The display device according to claim 10, wherein: The first data line is connected to the first light emitting diodes of the sub-pixels disposed at both sides of the first data line, and The second data line is connected to the second light emitting diodes of sub-pixels disposed at both sides of the second data line.

12. The display device according to claim 4, wherein In the narrow field of view mode, the first lens or the third lens limits the viewing angle of light to 30 degrees or less, and in the wide field of view mode, the second lens or the fourth lens limits the viewing angle of light to 60 degrees or more.

Images