Multi-signal efficient cooperative processing and intelligent control scheme guided by main and auxiliary chip architecture

Abstract

The invention relates to the technical field of signal processing and intelligent control of a heat management controller system of a battery swap station, in particular to a multi-signal efficient cooperative processing and intelligent control scheme guided by a main and auxiliary chip architecture. Comprising a processing chip, a water pump, a compressor, an electronic expansion valve, a fan, a temperature sensor, a pressure sensor, an AD signal acquisition module and a switch control device, the switch control device comprises a PTC heater, a fan coil and a fluorine path four-way valve, and the digital input end of the processing chip is connected with a device alarm switching value sampling module. The processing chip comprises a main chip and a plurality of auxiliary chips. In the aspect of control output, the main chip is directly responsible for execution of a control instruction with extremely strict real-time requirement, so that the timeliness of system response is ensured; and for a control task with a relatively low real-time requirement, output control is carried out by the auxiliary chip, so that the operation load of the main chip is reduced, and reasonable distribution and utilization of system resources are realized.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing and intelligent control of a thermal management controller system in a battery swap station, and in particular to a controller solution that uses a main chip and multiple auxiliary chips to collaboratively perform signal processing and logic control. Background Art

[0002] At present, thermal management systems in battery swap stations mostly use PLC modules for main control software development. Although modular control is one of its advantages, the specific programming environment and instruction set limit its application in complex algorithms and data processing tasks. Although ladder diagram programming is intuitive and easy to understand, when faced with scenarios such as large-scale data calculations and complex communication protocol analysis, PLC is less flexible than high-level programming languages. In order to achieve relevant functions, PLC often needs to use external devices or special programming techniques, which undoubtedly increases the complexity and development cost of the system. Existing multi-signal collaborative processing systems mostly use "FPGA+ARM core" to implement signal processing and device control, or use multi-core multi-threaded chips to achieve similar functions, but the initial investment cost is high, and the subsequent maintenance and replacement costs are also high. What is more prominent is that when the software is updated, the entire software often needs to be updated, which is not only time-consuming and labor-intensive, but may also cause new compatibility issues, bringing many challenges to the continuous optimization and upgrading of the system;

[0003] When faced with complex signals, the processing power of a single chip is insufficient to meet the demands of multi-tasking and parallel processing. Its limited functionality also prevents it from flexibly adapting to diverse application scenarios, significantly reducing control effectiveness. While multi-chip systems offer the potential for increased processing power, inefficient inter-chip communication can lead to significant data transmission delays, significantly increased power consumption, and difficulties in signal synchronization, significantly limiting overall system performance. Summary of the Invention

[0004] The present invention provides a multi-signal efficient collaborative processing and intelligent control solution led by a main-auxiliary chip architecture to solve the problems of insufficient processing capabilities of the above-mentioned traditional single-chip signal processing solution, which is difficult to cope with complex signals and multi-tasking scenarios; unreasonable design of multi-chip systems has problems such as low communication efficiency, high power consumption, and difficulty in signal synchronization; high development costs; and high costs of multi-signal collaborative processing systems, difficulty in software updates, and easy to cause compatibility issues.

[0005] The present invention provides a multi-signal efficient collaborative processing and intelligent control solution led by a main-auxiliary chip architecture, including a processing chip, a water pump, a compressor, an electronic expansion valve, a fan, a temperature sensor, a pressure sensor, an AD signal acquisition module and a switch control device. The switch control device includes a PTC heater, a fan coil unit and a fluorine four-way valve. The digital input end of the processing chip is connected to a device alarm switch quantity sampling module. The processing chip includes a main chip and multiple auxiliary chips. The multiple auxiliary chips are connected to the main chip through SPI communication. The main chip and the auxiliary chip both adopt ARM architecture single-threaded chips with main frequencies of 480MHZ and 72MHZ respectively. The main chip adopts Simulink+ARM underlying control architecture development model. The temperature sensor and the pressure sensor are both connected to the auxiliary chip through the AD signal acquisition module. The main chip is respectively connected to the electronic expansion valve and the fan through PWM control. The main chip is respectively communicated with the water pump and the compressor. The digital output end of the main chip is respectively connected to the PTC heater, the fan coil unit and the fluorine four-way valve. The auxiliary chip is connected to the two-way valve and the three-way valve through the LIN bus.

[0006] Preferably, the device alarm switch quantity sampling module is connected to the digital input terminal of the main chip.

[0007] Preferably, the water pump and the compressor are both connected to the main chip via RS-485 communication.

[0008] Preferably, the two-way valve and the three-way valve are connected to the processing chip through a closed-loop feedback mechanism. The two-way valve and the three-way valve feed back their current status to the system in real time. After the system confirms that the status information is correct, subsequent related components can act in sequence according to the established order.

[0009] Preferably, the circuit pins and signal allocations of the plurality of auxiliary chips remain unified.

[0010] The above technical solution provided by the embodiment of the present invention has the following advantages compared with the prior art:

[0011] 1. The structure provided by the present invention, through the core position and functional division of the main chip, the main chip as the core hub of the entire system, undertakes the important task of receiving and processing the data collected from each auxiliary chip, and is also responsible for executing complex algorithm operations, thereby making accurate control decisions. Taking the industrial control scenario as an example, the auxiliary chip focuses on the front-end acquisition and pre-processing of analog signals with relatively slow changes such as pressure and temperature, and then transmits these preliminarily processed data to the main chip as key input information for the main chip to run complex algorithms and make control decisions. In terms of control output, the main chip is directly responsible for executing control instructions with extremely strict real-time requirements to ensure the timeliness and accuracy of the system response; while for control tasks with relatively low real-time requirements, the auxiliary chip is responsible for output control, thereby effectively reducing the computing load of the main chip and realizing the reasonable allocation and efficient utilization of system resources. The system's device alarm switch quantity is directly collected by the main chip, and the controller will react immediately to protect the entire system, ensuring that the thermal management system can take protective action immediately in the event of device failure / loop failure;

[0012] 2. The structure provided by the present invention realizes communication coordination between the main and auxiliary chips through SPI. In order to achieve flexible coordination between high-speed and low-speed signal transmission between the main and auxiliary chips, this solution adopts SPI communication mode to connect the chips. By reasonably adjusting the SPI communication clock division coefficient, the SPI communication clock frequency is accurately reduced to a range that the auxiliary chip can stably handle. For example, when the main chip system clock is 480MHz, the division coefficient is set to 64. At this time, the SPI communication clock frequency becomes 7.5MHz, which is within the acceptable range of the auxiliary chip. This not only fully utilizes the potential advantages of SPI high-speed communication, but also fully takes into account the actual processing capabilities of the auxiliary chip, ensuring efficient and stable data transmission between the main and auxiliary chips.

[0013] 3. In the structure provided by the present invention, the auxiliary chip is also responsible for controlling the two-way valve and the three-way valve based on the LIN bus. In the operating logic of the thermal management system, the two-way valve and the three-way valve are the key executive components that are opened first when the system starts and the last to be activated when the system is closed, and the real-time control requirements are relatively low. In addition, in order to further enhance the accuracy and reliability of system control, the entire control system innovatively introduces a closed-loop feedback mechanism. The two-way valve and the three-way valve need to feed back their current status to the system in real time. After the system confirms that the status information is correct, the subsequent related components can act in sequence according to the established order, thereby ensuring that there will be no interference or delay in the control of core thermal management executive components such as compressors and water pumps, effectively improving the overall operating efficiency and stability of the system;

[0014] 4. The architecture provided by the present invention utilizes a main chip with a maximum operating frequency of 480 MHz, while the auxiliary chip operates at a frequency of 72 MHz. This combination not only fully leverages the main chip's powerful data processing capabilities and accelerates Simulink model execution and decision-making, but also achieves both system performance and cost control, effectively reducing overall system development and deployment costs. In this thermal management controller solution for battery swap stations, signal acquisition and output are primarily handled by the auxiliary chip. After comprehensive programming and rigorous verification of the auxiliary chip's signal acquisition, preprocessing, and control output programs are completed during the initial design phase, updates are largely unnecessary during long-term use, effectively reducing system maintenance costs and risks. In this system, the auxiliary chip and the main chip have distinct and clearly defined functional responsibilities. The main chip is primarily responsible for complex algorithm calculations, control decision-making, and signal acquisition and feedback processing for key components such as compressors and water pumps, while also directly controlling key AC system components. The auxiliary chip, on the other hand, focuses on acquiring and preprocessing analog signals such as pressure and temperature, and controlling tasks with lower real-time requirements, such as two-way and three-way valves, based on the LIN bus. This clear division of labor enables accurate and rapid fault location when a system failure occurs. For example, if a control strategy error occurs in the system, since the main chip is primarily responsible for the formulation and execution of the control strategy, technicians can quickly focus their troubleshooting on the main chip's program logic and control model. If a problem occurs in the signal acquisition link, the auxiliary chip and its related circuits can be checked first, given that the auxiliary chip is responsible for front-end acquisition.

[0015] 5. The structure provided by the present invention, the structure provided by the present invention, through the auxiliary chip program stability advantage, from the macro perspective of system operation, all control strategy formulation and output control of major components are run and calculated by the main chip. This design feature makes it extremely convenient in the subsequent strategy maintenance and upgrade process. Once the control strategy needs to be updated or the operation calculation logic needs to be optimized, it is only necessary to update the program and control model of the main chip, without the need for large-scale adjustments and program updates to all main and auxiliary chips. During the operation of the thermal management system, the efficiency of troubleshooting is a key factor in ensuring stable system operation and reducing downtime. This solution provides great convenience for troubleshooting through clear functional division of main and auxiliary chips and reasonable circuit design;

[0016] 6. The structure provided by the present invention features a highly consistent design of auxiliary chips, with uniform circuit pin configurations and signal assignments, and essentially identical corresponding programs. This standardized design not only significantly shortens the development cycle of auxiliary chips but also plays a crucial role in troubleshooting. When a problem with an auxiliary chip is suspected, since the characteristics of each auxiliary chip are consistent, a quick test can be performed by swapping auxiliary chips with the same function. If the problem disappears after the replacement, it can be preliminarily determined that the original chip is at fault. Furthermore, when troubleshooting problems with the devices controlled by the auxiliary chip, as well as with acquisition devices or circuits, the cause can be determined by flexibly changing the external wiring method. For example, by connecting a certain acquisition circuit to the corresponding pin of another auxiliary chip known to be functioning properly and observing the signal acquisition, if normal acquisition is achieved, it can be determined that the relevant circuit of the original auxiliary chip is at fault; otherwise, the problem may be with the acquisition device itself. This approach eliminates the need for in-depth analysis of complex circuits and programs, greatly improving troubleshooting efficiency. This solution offers excellent auxiliary chip expansion capabilities. During subsequent maintenance and upgrades of the thermal management system, if new signal acquisition or control functions need to be added, auxiliary chips can be easily added. Thanks to the consistent design of the auxiliary chips, newly added chips can be quickly integrated into the system without disrupting the existing system's troubleshooting process. Even if a fault occurs after expansion, the existing clear functional division of labor and standardized design still enable efficient fault location and troubleshooting, further enhancing the reliability and maintainability of the entire thermal management system and laying a solid foundation for the system's long-term stable operation.

[0017] 7. The structure provided by the present invention is to effectively solve the bottleneck problem of real-time signal transmission under the multi-chip architecture. This solution implements a hierarchical differentiated processing strategy for various types of signals in the initial design stage and subsequent verification links. In view of the fact that temperature signals usually have the characteristic of slow changes, the priority of their collected information in the entire system is set to the lowest; and pressure signals, especially dynamic pressure signals with a faster change rate, are of great significance for real-time feedback on the operating status of the system, so their priority is significantly improved. In the thermal management system, for key parameters such as water line pressure and fluorine line pressure, a complete alarm protection mechanism is established by accurately setting scientific and reasonable safety thresholds to fully guarantee the stability and reliability of the system operation. Such signals are mainly collected and pre-processed by auxiliary chips at the front end to ensure the accuracy and timeliness of the data;

[0018] 8. The structure provided by the present invention considers the selection of ARM-based primary and secondary chips. In this solution, both the primary and secondary chips utilize ARM-based single-threaded chips. Compared to the signal processing model of an FPGA+ARM architecture system, a multi-ARM system demonstrates more direct and concise control effects and signal acquisition. However, FPGAs possess true hardware-level parallel processing capabilities, enabling the parallel allocation of multiple complex tasks to different logic units for simultaneous execution based on design requirements, something ARM-based chips lack. To address this deficiency, this solution utilizes the Simulink+ARM underlying control architecture for the primary chip. Simulink provides developers with a highly intuitive graphical modeling environment, enabling rapid construction of various complex algorithm models covering a wide range of areas, including signal processing and advanced control algorithms. For ARM development, this innovative model significantly reduces the development threshold and shortens the development cycle. Developers no longer need to expend extensive effort writing underlying code to implement complex algorithmic logic. Instead, they simply build modules and configure parameters in the Simulink environment. Using the built-in code generation tools, they can automatically generate C or C++ code that runs stably on the ARM platform. For example, when designing digital filters, developers can easily complete filter design and parameter optimization using Simulink's extensive signal processing modules. The generated code can then be easily ported to run efficiently on ARM chips, effectively overcoming the inherent drawbacks of ARM in implementing complex algorithms, which is less intuitive and efficient than FPGA development. Although ARM primarily utilizes a serial processing architecture, Simulink's powerful modeling and simulation capabilities enable precise modeling and in-depth simulation of parallel processing tasks. Developers can cleverly decompose a complex task into multiple parallel subtask modules, performing comprehensive design and rigorous verification within the Simulink environment. This innovative approach allows developers to systematically optimize parallel processing algorithms in advance and rationally plan the allocation of computing resources on the ARM chip, significantly improving the overall processing efficiency of the entire system. Furthermore, by leveraging multithreading technology to implement some parallel functions on the ARM chip and optimizing multithreaded task scheduling and resource allocation through Simulink simulation, the parallel processing advantages of FPGAs can be effectively simulated to a certain extent, further improving system performance. The parallel processing capabilities of FPGAs are based on their underlying hardware architecture. Their large number of integrated configurable logic units enable simultaneous processing of multiple tasks, offering significant advantages in large-scale parallel data processing. Even if ARM chips use Simulink for algorithm optimization and multi-threaded design, they are essentially still based on software-level time-sharing multiplexing technology to simulate parallel processing. When processing large-scale parallel data, there is still a large gap compared with the hardware parallel processing capabilities of FPGA.However, in thermal management system application scenarios, since there are no tasks such as image processing that have extremely high requirements for large-scale parallel data processing, this gap can be ignored in practical applications, thus ensuring the feasibility and effectiveness of this solution in thermal management systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 This is a diagram of the main and auxiliary chip architecture of the present invention;

[0022] Figure 2 This is the AD acquisition port circuit principle diagram of the present invention;

[0023] Figure 3 This is the principle diagram of the main chip device fault collection and switch value output circuit of the present invention. DETAILED DESCRIPTION

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0025] Various embodiments of the present invention may be presented in the form of a range. It should be understood that the description in the form of a range is merely for convenience and brevity and should not be construed as a rigid limitation on the scope of the present invention. Therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single numerical values ​​within the range. For example, the range description from 1 to 6 should be considered to have specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5 and 6, regardless of the range. In addition, whenever a numerical range is indicated in the present invention, it is intended to include any quoted number (fractional or integer) within the indicated range. Unless otherwise specified, the various raw materials, reagents, instruments and equipment used in the present invention can be purchased commercially or can be prepared by existing equipment.

[0026] In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", specifically refer to the directions of the drawings in the accompanying drawings. In addition, in the present invention, the terms "including", "comprising", etc. mean "including but not limited to". In the present invention, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. In the present invention, "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. Wherein A and B can be singular or plural. In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one", "at least one of the following" or similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, "at least one of a, b, or c" or "at least one of a, b and c" can both mean: a, b, c, ab, i.e. a and b, ac, bc or abc, where a, b, c can be single or multiple.

[0027] like Figure 1-Figure 3As shown in the figure, the multi-signal efficient collaborative processing and intelligent control solution led by the main and auxiliary chip architecture includes a processing chip, a water pump, a compressor, an electronic expansion valve, a fan, a temperature sensor, a pressure sensor, an AD signal acquisition module and a switch control device. The switch control device includes a PTC heater, a fan coil unit and a fluorine four-way valve. The digital input end of the processing chip is connected to the device alarm switch quantity sampling module. The processing chip includes a main chip and multiple auxiliary chips. The multiple auxiliary chips are connected to the main chip through SPI communication. The main chip and the auxiliary chip both use ARM architecture single-threaded chips with main frequencies of 480MHZ and 72MHZ respectively. The main chip adopts Simulink+ARM underlying control architecture development model. The temperature sensor and pressure sensor are connected to the auxiliary chip through the AD signal acquisition module. The main chip is connected to the electronic expansion valve and fan respectively through PWM control. The main chip is communicated with the water pump and compressor respectively. The digital output end of the main chip is connected to the PTC heater, fan coil unit and fluorine four-way valve respectively. The auxiliary chip is connected to the two-way valve and the three-way valve through the LIN bus.

[0028] Specifically, the main chip used in this solution operates at a maximum frequency of 480MHz, while the auxiliary chip operates at 72MHz. This combination leverages the main chip's powerful data processing capabilities and accelerates Simulink model execution and decision-making, while simultaneously achieving both system performance and cost control, effectively reducing overall system development and deployment costs. In this battery swap station thermal management controller solution, the auxiliary chip primarily handles signal acquisition and output. After comprehensive programming and rigorous verification of the auxiliary chip's signal acquisition, preprocessing, and control output programs during the initial design phase, updates are virtually unnecessary during long-term operation, effectively reducing system maintenance costs and risks. In this system, the auxiliary chip and main chip have distinct and clearly defined functional responsibilities. The main chip is primarily responsible for complex algorithm calculations, control decision-making, and signal acquisition and feedback processing for key components such as compressors and water pumps, while also directly controlling key AC system components. The auxiliary chip, on the other hand, focuses on acquiring and preprocessing analog signals such as pressure and temperature, and controlling tasks with lower real-time requirements, such as two-way and three-way valves, via the LIN bus. This clear division of labor ensures accurate and rapid fault location when a system failure occurs. For example, if the system has a control strategy error, since the main chip is mainly responsible for the formulation and execution of the control strategy, technicians can quickly focus the troubleshooting on the program logic and control model of the main chip; if there is a problem in the signal acquisition link, since the auxiliary chip is responsible for the front-end acquisition work, the auxiliary chip and its related circuits can be checked first.

[0029] like Figure 1 As shown: the device alarm switch quantity sampling module is connected to the digital input terminal of the main chip.

[0030] Specifically: the system's device alarm switch quantity is directly collected by the main chip, and the controller will respond immediately to protect the entire system, ensuring that the thermal management system can take protective action immediately in the event of device failure / circuit failure.

[0031] like Figure 1 As shown: The water pump and compressor are connected to the main chip via RS-485 communication.

[0032] Specifically: For the signal processing of key components such as compressors and water pumps that are crucial to the operation of the thermal management system, large devices have large signal transmission volumes and are extremely susceptible to electromagnetic interference. This measure significantly improves the system's real-time response performance and anti-interference capabilities, ensuring the stability and accuracy of key signal transmission.

[0033] like Figure 1 As shown: Both the two-way valve and the three-way valve are connected to the processing chip through a closed-loop feedback mechanism. The two-way valve and the three-way valve feed back their current status to the system in real time. After the system confirms that the status information is correct, the subsequent related components can act in sequence according to the established order.

[0034] Specifically: The auxiliary chip is also responsible for controlling the two-way valve and three-way valve based on the LIN bus. In the operating logic of the thermal management system, the two-way valve and the three-way valve are the key actuators that are opened first when the system starts and the last to be activated when the system is closed. The demand for their real-time control is relatively low. In addition, to further enhance the accuracy and reliability of system control, the entire control system innovatively introduces a closed-loop feedback mechanism. The two-way valve and the three-way valve need to feed back their current status to the system in real time. After the system confirms that the status information is correct, the subsequent related devices can act in sequence according to the established order. This ensures that there will be no interference or delay in the control of core thermal management actuators such as compressors and water pumps, effectively improving the overall operating efficiency and stability of the system.

[0035] like Figure 1 As shown: the circuit pins and signal allocation of multiple auxiliary chips remain unified.

[0036] Specifically, the auxiliary chips feature highly consistent design, with uniform circuit pin configurations and signal assignments, and the corresponding programs are essentially the same. This standardized design not only significantly shortens the auxiliary chip development cycle but also plays a crucial role in troubleshooting. If a problem with an auxiliary chip is suspected, since all auxiliary chips have consistent characteristics, a quick test can be performed by swapping them with the same function. If the problem disappears after the swap, it can be preliminarily determined that the original chip is at fault. Furthermore, when troubleshooting issues with the devices controlled by the auxiliary chip, as well as with the acquisition components or circuits, flexible external wiring configurations can be employed to facilitate cause identification. For example, a specific acquisition circuit can be connected to the corresponding pins of a known, functioning auxiliary chip and observed. If signal acquisition is successful, the fault in the original auxiliary chip's circuitry can be determined; otherwise, the fault may lie with the acquisition component itself. This approach eliminates the need for in-depth analysis of complex circuits and programs, significantly improving troubleshooting efficiency. This solution offers excellent auxiliary chip scalability. During future maintenance and upgrades of the thermal management system, if new signal acquisition or control functions are required, auxiliary chips can be easily added. Thanks to the consistent design of the auxiliary chips, newly added chips can be quickly integrated into the system without disrupting the existing system troubleshooting process. Even if a fault occurs after the expansion, the existing clear functional division of labor and standardized design still enable efficient fault location and troubleshooting, further enhancing the reliability and maintainability of the entire thermal management system and laying a solid foundation for the long-term stable operation of the system.

[0037] Principle of Operation: To effectively address the bottleneck of real-time signal transmission in a multi-chip architecture, this solution implements a hierarchical, differentiated processing strategy for various signals during the initial design phase and subsequent verification. Given the typically slow-changing nature of temperature signals, their acquisition is given the lowest priority within the system. Pressure signals, however, particularly the more rapidly changing dynamic pressure signals, are given a significantly higher priority due to their critical role in providing real-time feedback on system operating status. Within the thermal management system, a comprehensive alarm protection mechanism is implemented by precisely setting scientifically appropriate safety thresholds for key parameters such as water and fluorine pressures, ensuring system stability and reliability. Front-end acquisition and preprocessing of these signals are primarily handled by the auxiliary chip, ensuring data accuracy and timeliness. Leveraging the auxiliary chip's program stability, from a macro perspective, all control strategy development and output control of key components are performed by the main chip. This design feature facilitates subsequent strategy maintenance and upgrades. Whenever the control strategy needs to be updated or the operational calculation logic needs to be optimized, only the main chip's program and control model need to be updated, eliminating the need for large-scale adjustments and program updates to all main and auxiliary chips. During thermal management system operation, efficient troubleshooting is critical to ensuring stable system operation and minimizing downtime. This solution significantly facilitates troubleshooting through a clear functional division of labor between the main and auxiliary chips and a rational circuit design. The auxiliary chips feature highly consistent design, with uniform pin configurations and signal assignments, and essentially identical corresponding programs. This standardized design not only significantly shortens the auxiliary chip development cycle but also plays a crucial role in troubleshooting. If a problem with an auxiliary chip is suspected, since all auxiliary chips have consistent characteristics, rapid testing can be performed by swapping them with the same function. If the problem disappears after replacement, it can be preliminarily determined that the original chip is at fault. Furthermore, when troubleshooting issues with the devices controlled by the auxiliary chip, acquisition components, or circuits, flexible external wiring configurations can be used to facilitate root cause identification. For example, connect a signal acquisition circuit to the corresponding pin of another auxiliary chip that is known to be working properly and observe the signal acquisition situation. If the acquisition is normal, it can be determined that there is a fault in the relevant circuit of the original auxiliary chip. Otherwise, the problem may be with the acquisition device itself. This method does not require in-depth analysis of complex circuits and programs, greatly improving troubleshooting efficiency. This solution has excellent auxiliary chip expansion capabilities. During the later maintenance and upgrade of the thermal management system, if new signal acquisition or control functions need to be added, auxiliary chips can be easily added. Due to the consistent design of the auxiliary chips, the newly added chips can be quickly integrated into the system without interfering with the existing system's troubleshooting process.Even if a fault occurs after the expansion, the original clear functional division and standardized design can still enable efficient fault location and troubleshooting, further enhancing the reliability and maintainability of the entire thermal management system and laying a solid foundation for the long-term stable operation of the system.

[0038] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is intended to be construed in the widest manner consistent with the principles and novel features claimed herein.

Claims

1. A multi-signal efficient collaborative processing and intelligent control solution driven by a master-slave chip architecture includes a processing chip, a water pump, a compressor, an electronic expansion valve, a fan, a temperature sensor, a pressure sensor, an AD signal acquisition module, and switch control devices. The switch control devices include a PTC heater, a fan coil unit, and a fluorine-circuit four-way valve. The digital input of the processing chip is connected to a device alarm switch sampling module. The solution is characterized by: The processing chip includes a main chip and multiple auxiliary chips. The multiple auxiliary chips are connected to the main chip through SPI communication. The main chip and the auxiliary chip both use ARM architecture single-threaded chips with main frequencies of 480MHZ and 72MHZ respectively. The main chip uses Simulink+ARM underlying control architecture development model. The temperature sensor and pressure sensor are connected to the auxiliary chip through an AD signal acquisition module. The main chip is connected to the electronic expansion valve and fan respectively through PWM control. The main chip is communicated with the water pump and compressor respectively. The digital output end of the main chip is connected to the PTC heater, fan coil and fluorine four-way valve respectively. The auxiliary chip is connected to the two-way valve and the three-way valve through the LIN bus.

2. The multi-signal efficient collaborative processing and intelligent control solution led by the master-slave chip architecture according to claim 1 is characterized by: The device alarm switch quantity sampling module is connected to the digital input terminal of the main chip.

3. The multi-signal efficient collaborative processing and intelligent control solution led by the master-slave chip architecture according to claim 1 is characterized by: The water pump and the compressor are both connected to the main chip via RS-485 communication.

4. The multi-signal efficient collaborative processing and intelligent control solution led by the master-slave chip architecture according to any one of claims 1 to 3, characterized in that: The two-way valve and the three-way valve are both connected to the processing chip through a closed-loop feedback mechanism. The two-way valve and the three-way valve feed back their current status to the system in real time. After the system confirms that the status information is correct, subsequent related components can act in sequence according to the established order.

5. The multi-signal efficient collaborative processing and intelligent control solution led by the master-slave chip architecture according to claim 4 is characterized by: The circuit pins and signal allocation of the plurality of auxiliary chips remain unified.

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