Processor, graphics card, computer equipment and register allocation method and device

Abstract

The invention discloses a processor, a graphics card, computer equipment and a register allocation method and device, and belongs to the technical field of register management. The processor comprises a plurality of registers and a resource management unit. The resource management unit is used for releasing the first register set into a first state under the condition that the first register set is used up by the first thread group belonging to the first working group, and the first state is used for indicating that the first register set supports reconfiguration to other thread groups belonging to the first working group; the first register set comprises at least one register in the plurality of registers; and the resource management unit is used for reconfiguring the first register set into a register set used by a second thread group in response to a reconfiguration request of the second thread group belonging to the first working group. The processor supports reconfiguration of the released register set to other thread groups in the working group, and the flexibility of register resource allocation is improved.

Description

Technical Field

[0001] The present application relates to the field of register management technology, and in particular to a processor, a graphics card, a computer device, and a register allocation method and apparatus. Background Art

[0002] In parallel computing tasks, it is usually necessary to allocate multiple consecutive registers to a task. These registers can be used for storage and processing of computing data during initialization, and can also be used for storage and processing of temporary computing data.

[0003] For some tasks with large register requirements, more registers will be initially allocated to them, but not all of these registers will be used at the beginning, resulting in low overall utilization of registers in the processor.

[0004] Therefore, how to allocate register resources to improve the utilization efficiency of register resources is an issue that needs to be solved urgently. Summary of the Invention

[0005] The present application provides a processor, graphics card, computer equipment, register allocation method and apparatus, and the technical solution is as follows.

[0006] According to one aspect of the present application, a processor is provided, comprising a plurality of registers and a resource management unit; the resource management unit being configured to release a first register set to a first state when a first thread group belonging to a first work group has finished using the first register set, the first state being configured to indicate that the first register set supports reconfiguration to other thread groups belonging to the first work group, the first register set including at least one register among the plurality of registers; The resource management unit is configured to reconfigure the first register set into a register set used by the second thread group in response to a configuration request from the second thread group belonging to the first work group.

[0007] According to one aspect of the present application, a graphics card is provided, comprising the above-mentioned processor.

[0008] According to one aspect of the present application, a computer device is provided, comprising the above-mentioned processor.

[0009] According to one aspect of the present application, a register allocation method is provided, the method being executed by a processor, the processor comprising a plurality of registers and a resource management unit; The method comprises: The resource management unit releases a first register set to a first state when a first thread group belonging to a first work group finishes using the first register set, the first state being used to indicate that the first register set supports reconfiguration to other thread groups belonging to the first work group, the first register set including at least one register of the plurality of registers; The resource management unit reconfigures the first register set into a register set used by the second thread group in response to a configuration request of the second thread group belonging to the first work group.

[0010] According to one aspect of the present application, a register allocation device is provided, the device comprising: a resource management module, configured to release a first register set to a first state when a first thread group belonging to a first work group has finished using the first register set, the first state being configured to indicate that the first register set supports reconfiguration to other thread groups belonging to the first work group, the first register set comprising one register among a plurality of registers; The resource management module is configured to reconfigure the first register set into a register set used by the second thread group in response to a configuration request from the second thread group belonging to the first work group.

[0011] The beneficial effects brought about by the technical solution provided in this application include at least the following.

[0012] The first register set released by the first thread group is allocated to other thread groups within the same workgroup via a resource allocation unit. For example, when a second thread group belonging to the first workgroup sends a configuration request, the first register set in the first state corresponding to the first workgroup is allocated to the second thread group. A discrete register resource allocation method is designed, which divides register resources into discrete register sets. This allows for the release of one or more register sets that have finished use, such as before the thread group ends, to avoid low register resource utilization due to long-term occupation of register sets during the thread group's lifecycle. On the other hand, it supports flexible circulation of register sets within the work group, so that for some tasks (such as AI computing tasks, indirect function call tasks, etc.), the expectation of lowering resource allocation can be achieved during the initial allocation, that is, fewer register sets can be allocated during the initial allocation. Since the reconfiguration of register sets within the work group is supported, when an instruction requiring a large number of register sets is executed, more register sets can be requested for the thread group through configuration requests before the instruction is executed. Compared with the traditional method of allocating more register sets during the initial allocation, the register sets released by other thread groups in the work group are obtained through configuration requests during the execution of the second thread group. This not only improves the flexibility of register set allocation, but also supports the normal operation of some tasks requiring a large number of register sets while ensuring high resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0014] Figure 1 A schematic diagram of a processor provided by an exemplary embodiment of the present application is shown; Figure 2 A schematic diagram of a processor provided by another exemplary embodiment of the present application is shown; Figure 3 A schematic diagram of a processor provided by yet another exemplary embodiment of the present application is shown; Figure 4 A schematic diagram of a state machine provided by an exemplary embodiment of the present application is shown; Figure 5 A schematic diagram of register management provided by an exemplary embodiment of the present application is shown; Figure 6 A schematic diagram showing the processing logic provided by an exemplary embodiment of the present application is shown; Figure 7 A flow chart of a register allocation method provided by an exemplary embodiment of the present application is shown; Figure 8 A structural block diagram of a register release allocation device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0015] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0016] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0017] The terms used in this disclosure are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0018] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, storage, and display, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the information such as the settings operations involved in this application is obtained with full authorization.

[0019] It should be understood that although the terms first, second, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter without departing from the scope of this disclosure. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0020] First, the relevant terms involved in this application are introduced.

[0021] Dead registers: Registers no longer used by a thread group. In other words, dead registers are registers that are no longer used during the lifetime of a thread group. Alternatively, dead registers are registers that are no longer used during the lifetime of a thread in a thread group. A wave is a SIMD (Single Instruction Multiple Data) thread bundle structure in the OpenCL (Open Computing Language) processing framework. In some processors, a wave is also called a wavefront, and a wave typically includes 32 or 64 threads. In CUDA (Compute Unified Device Architecture), a thread group is called a warp, and a warp typically includes 32 threads. Of course, the terms wave, warp, etc. mentioned above can also be referred to more generally as a thread group.

[0022] A workgroup is a term used to describe a group of threads that execute in parallel within the same compute unit. Typically, threads within a workgroup can share some data (such as data in shared memory). During hardware execution, threads within a workgroup are divided into one or more thread groups. These thread groups can be scheduled for execution on the same or different compute units.

[0023] In parallel computing tasks, a task typically requires the allocation of numerous register resources. These resources are used for initialization, storage, and processing of computational data, as well as for temporary computational data. However, in both discrete and continuous allocation scenarios, the long thread execution lifecycle can delay the release of some dead register resources, preventing new tasks from entering the core. This can reduce overall core utilization.

[0024] This is not good for tasks that use a lot of resources. Excessive resource usage will result in many resources not being fully utilized and the number of active thread groups in the processor cannot reach saturation.

[0025] On the other hand, as threads in AI and other applications consume more and more resources, and some scenarios require data transmission between multiple graphics cards, the programming model for cross-card communication leads to excessive register resource usage, which reduces the number of parallel thread groups and reduces register resource utilization efficiency, resulting in performance that cannot reach peak performance (peak perf) standards.

[0026] In indirect function calls, because it's impossible to accurately calculate the resource usage of the specific function being called at runtime, the compiler conservatively configures a high resource usage. During execution, some of these conservatively estimated resources are released early based on the compilation process. However, this can lead to wasted resources in the early stages of thread group execution, as these conservatively estimated resources aren't actually needed.

[0027] Therefore, the embodiments of the present application aim to release dead registers in advance for recycling based on the different lifecycles of registers used within the application. By releasing dead register resources in advance and recycling them immediately, the present application aims to improve register utilization and thread group occupancy by reconfiguring and allocating related registers without affecting the execution of the original thread group.

[0028] Figure 1 FIG. 1 is a schematic diagram of a processor provided by an exemplary embodiment of the present application. The processor 100 includes a plurality of registers 110 and a resource management unit 120 .

[0029] The resource management unit 120 is configured to release the first register set to a first state when a first thread group (wave) belonging to a first workgroup has finished using the first register set. The first state is configured to indicate that the first register set supports reconfiguration to other thread groups belonging to the first workgroup. The first register set includes at least one register.

[0030] The first work group includes at least two thread groups, and the at least two thread groups include the first thread group.

[0031] Optionally, at least two thread groups included in the first working group are used to execute the same task, or at least two thread groups included in the first working group are used to execute different tasks. The same task can be understood as a task that executes the same instruction but has different operands. Different tasks are tasks that execute different instructions, or have different task objectives, or tasks that correspond to different branches. If the task objective of the first task is a computing task and the task objective of the second task is a communication task, then the first task and the second task are different tasks. The division of task objectives can also be more fine-grained, such as if the task objective of the first task is a computing task for image filtering, and the task objective of the second task is a computing task for feature extraction. At this time, although the first task and the second task are both computing tasks, after further dividing the computing tasks, it can be determined that the first task and the second task are different tasks.

[0032] Optionally, the processor 100 initially allocates the same or different numbers of register sets to at least two thread groups in the first work group. For example, the number of register sets initially allocated to both the first thread group and the second thread group is 4; or the number of register sets initially allocated to the first thread group is 4, and the number of register sets initially allocated to the second thread group is 2.

[0033] Optionally, the processor 100 determines the number of register sets to initially allocate based on the tasks executed by the thread group. Exemplarily, the processor 100 allocates more register sets to computing tasks than to communication tasks.

[0034] In other embodiments, to avoid excessive resource allocation overhead, the processor 100 may allocate the same number of register sets to each thread group (or thread groups within each workgroup). For example, i register sets may be allocated to all thread groups within a workgroup; or i register sets may be allocated to all thread groups within a first workgroup, and j register sets may be allocated to all thread groups within a second workgroup. Here, i and j are both positive integers.

[0035] Optionally, the first thread group includes at least one thread; or the first thread group corresponds to at least one thread. A thread group is a scheduling unit for computing resources in the processor 100; or a thread group is an allocation unit for computing resources in the processor 100.

[0036] Optionally, the first thread group includes at least one thread, and both the first thread group and the thread are logical concepts. That is, the first thread group corresponds to a set of physical units in the processor, and one or more threads can be scheduled for execution on a physical unit in the processor. The physical unit can be called a computing unit, a computing core, a processing unit, etc. In other words, the processor 100 also includes multiple computing units, which are used to perform computing tasks.

[0037] Optionally, the computing resources include a plurality of registers 110. Optionally, the computing resources also include memory, cache, etc.

[0038] Optionally, the first state is used to indicate that the first register set supports reconfiguration to other thread groups belonging to the first workgroup. That is, the register set in the first state is a register set that supports reconfiguration to other thread groups belonging to the first workgroup; or, the first state is used to indicate that the current register set supports reconfiguration to other thread groups belonging to the first workgroup. If the current register set is released by a thread group in another workgroup, the first state is used to indicate that the current register set supports reconfiguration to other thread groups belonging to the same workgroup; or the first state is used to indicate that the current register set supports reconfiguration to different thread groups belonging to the same workgroup. Exemplarily, the first workgroup includes n thread groups. If the i-th thread group triggers the release of the first register set to the first state, the first register set supports reconfiguration to the j-th thread group belonging to the first workgroup, where j is any positive integer other than i, and j is less than n. i is a positive integer less than n.

[0039] Optionally, the first register set includes at least one register. That is, each register set includes at least one register.

[0040] For example, each register set includes 2 n registers, where n is 0 or a positive integer. For example, each register set includes 1 register; or, each register set includes 2 registers; or, each register set includes 4 registers; or, each register set includes 8 registers; or, each register set includes 16 registers, and so on.

[0041] It should be noted that the embodiment of the present application does not limit the number of registers included in each register set. The number of registers included in each register set can be set according to the requirements of the actual processing task (such as rendering task, model training task, video processing task, etc.).

[0042] Optionally, the register set may be implemented as a register row, a register group, a register file, a register cluster, a register window, etc. That is, the embodiment of the present application does not limit the implementation form of the register set.

[0043] Optionally, the register set is a logical set, meaning that when register resources are allocated to the first thread group, they are allocated in units of register sets, which does not necessarily mean that register resources exist in the form of sets in the processor 100. Generally speaking, in the processor 100, a register set is represented by multiple registers 110, and the processor 100 allocates at least one of these registers as a register set to the first thread group. However, this embodiment of the present application is not limited to this, and that is, register resources in the processor 100 may also exist in the form of register sets.

[0044] The resource management unit 120 is configured to reconfigure the first register set into a register set used by the second thread group in response to a configuration request from the second thread group belonging to the first work group.

[0045] Optionally, the first register set is reconfigured as a register set used by the second thread group, i.e., the first register set is allocated to the second thread group for use. For example, the register set used by the second thread group before the configuration request includes the second register set, the third register set, and the fourth register set. After the configuration request, the register set used by the second thread group includes the first register set, the second register set, the third register set, and the fourth register set.

[0046] Optionally, a workgroup is a unit for reconfiguring register sets in the processor 100. That is, it can be understood that the register sets used by all thread groups in the first workgroup are the register sets used by the first workgroup. The processor 100 supports reconfiguring free register sets in a workgroup into register sets for a thread group.

[0047] Optionally, before the second thread group sends the configuration request, the resource management unit 120 has already configured at least one register set for it. That is, the second thread group sends the configuration request during execution, and the configuration request can be called a reconfiguration request. In other words, the resource management unit 120 configures at least one register for the second thread group; in response to the reconfiguration request from the second thread group, the resource management unit 120 reconfigures the first register set to the register set used by the second thread group. That is, the first register set is added to the at least one register set.

[0048] In summary, the processor provided in the embodiment of the present application supports allocating the first register set released by the first thread group to other thread groups within the same workgroup via a resource allocation unit. For example, when the second thread group belonging to the first workgroup sends a configuration request, the first register set in the first state corresponding to the first workgroup is allocated to the second thread group. On the one hand, a discrete register resource allocation method is designed, that is, register resources are divided into discrete register sets, and when released, one or more register sets that have ended in use are supported for release. For example, these register sets can be released in advance before the thread group ends, thereby avoiding low resource utilization of register sets caused by long-term occupation of register sets during the life cycle of the thread group. On the other hand, it supports flexible circulation of register sets within the work group, so that for some tasks (such as AI computing tasks, indirect function call tasks, etc.), the expectation of lowering resource allocation can be achieved during the initial allocation, that is, fewer register sets can be allocated during the initial allocation. Since the reconfiguration of register sets within the work group is supported, when an instruction requiring a large number of register sets is executed, more register sets can be requested for the thread group through configuration requests before the instruction is executed. Compared with the traditional method of allocating more register sets during the initial allocation, the register sets released by other thread groups in the work group are obtained through configuration requests during the execution of the second thread group. This not only improves the flexibility of register set allocation, but also supports the normal operation of some tasks requiring a large number of register sets while ensuring high resource utilization.

[0049] The above shows that when the resource management unit 120 releases the first register set, it is released into the first state, and the first state is used to indicate that the first register set supports reconfiguration to other thread groups belonging to the first work group. In addition to the first state, more states can be set for the register set to indicate relevant information about the register set in the processor 100, as shown below.

[0050] 1. The status of the register set.

[0051] (1) Second state.

[0052] In some embodiments, the state of the register set further includes a second state, which is used to indicate that the register set is in a working state, or in other words, the second state is used to indicate that the register set is in a busy state, or the second state is used to indicate that the register set is being used by a thread group.

[0053] In some embodiments, the resource management unit 120 is configured to, in response to a configuration request of a second thread group belonging to the first work group, reconfigure the first register set into a register set used by the second thread group, and reconfigure the first register set into a second state, wherein the second state is used to indicate that the first register set is being used by the second thread group.

[0054] Optionally, the configuration request of the second thread group can be understood as the second thread group sending a configuration request to the resource management unit 120. The configuration request can be triggered after the second thread group executes the configuration instruction. Optionally, after the second thread group executes the configuration instruction, the second thread group is blocked, or the state of the second thread group is updated to a configuration blocking state. That is, the second thread group is blocked, and after waiting for the resource management unit 120 to complete the configuration operation for the second thread group, the configuration blocking state of the second thread group is released, and the instructions of the second thread group are continued to be emitted and executed. It should be understood that the above-mentioned configuration instruction can also be referred to as a reconfiguration instruction, the configuration blocking state can also be referred to as a reconfiguration blocking state, and the configuration operation can also be referred to as a reconfiguration operation.

[0055] Optionally, the first register set is reconfigured to the register set used by the second thread group, such as establishing an association relationship between the first register set and the second thread group. Exemplarily, an association relationship is established between the identifier of the first register set and the identifier of the second thread group; or, a register mapping management table is established, which register mapping management table is used to indicate which register sets are assigned to which thread groups. Furthermore, the register mapping management table can also be used to indicate the usage of registers in these register sets by the thread group. When the first register set is reconfigured to the register set used by the second thread group, the mapping relationship between the first register set and the second thread group is added to the register mapping management table. The mapping relationship between the first register set and the second thread group can be represented by the mapping relationship between the identifier of the first register set and the identifier of the second thread group, and of course it can also be represented in other ways, and the embodiments of the present application are not limited to this.

[0056] Optionally, the second state is used to indicate that the first register set is being used by the second thread group, that is, the first register set has been allocated to the second thread group for use, and before the second thread group finishes using it, it is no longer supported to be allocated to other thread groups.

[0057] In some embodiments, the execution of reconfiguration is subject to certain conditions. For example, the resource management unit 120 is configured to, in response to a configuration request from a second thread group belonging to a first work group, reconfigure at least one register set to a register set used by the second thread group, and reconfigure at least one register set to a second state, if the number of first sets is greater than or equal to the number of reconfigurations, where the at least one register set includes the first register set; wherein the number of first sets is the number of register sets in the first state corresponding to the first work group, the number of reconfigurations is the number of register sets requested by the configuration request, and the number of reconfigurations is the number of at least one register set.

[0058] In other embodiments, the resource management unit 120 is configured to respond to a configuration request of a second thread group belonging to the first work group, and skip the configuration request of the second thread group when the first set quantity is less than the reconfiguration quantity; and poll the configuration request of the next thread group.

[0059] Exemplarily, the processor 100 further includes a reallocation request and blocking information subunit. The reallocation request and blocking information subunit is used to store configuration requests of different thread groups of different work groups. Exemplarily, the reallocation request and blocking information subunit stores configuration requests of n thread groups. The configuration request of the second thread group is the k-th configuration request stored in the reallocation request and blocking information subunit. When the number of first sets is less than the reconfiguration number, that is, the number of idle sets in the first work group does not meet the configuration request of the second thread group, the configuration request of the second thread group is skipped; and the configuration request of the k+1-th thread group is processed in a polling manner. When the number of first sets is greater than or equal to the reconfiguration number, the resource management unit 120 reconfigures at least one register set to the register set used by the second thread group, and reconfigures at least one register set to the second state; the reallocation request and blocking information subunit deletes the stored k-th configuration request, or shifts the k+1-th configuration request to the n-th configuration request by one position to overwrite the k-th configuration request. After processing the configuration request of the second thread group, the value of k remains unchanged, that is, the kth configuration request (originally the k+1th configuration request) is still queried. It should be understood that in addition to the aforementioned forwarding method, other methods may also be used, such as directly modifying the sequence number corresponding to the configuration request, etc., and this embodiment of the application is not limited to this.

[0060] In summary, the processor provided in the embodiment of the present application, through the setting of the second state, enables a clearer distinction between the register sets corresponding to the workgroup. For a workgroup, its corresponding register set (i.e., the register set corresponding to the thread group belonging to the workgroup) includes a first state and a second state. The second state indicates that the thread group is using the register set, which means that the register set cannot be reconfigured to other thread groups within the workgroup. The first state is used to indicate that reconfiguration to other thread groups within the workgroup is supported. By setting the first state and the second state, the management of the register set corresponding to the workgroup is clarified, ensuring that the register set is in only one valid state at a time, avoiding concurrency conflicts.

[0061] In addition, by maintaining the number of first sets, the judgment of the configuration request for the thread group in the work group is guaranteed, that is, whether the number of register sets in the first state in the current work group is greater than the number requested by the configuration request of the thread group is judged to determine whether to support the reconfiguration of the register set in the first state to the thread group, thereby avoiding the situation where the thread group is continuously blocked waiting for the reconfiguration of the register set due to insufficient register sets to be reconfigured to the thread group, which in turn causes the register set in the work group to be occupied by the blocked thread group for a long time, resulting in reduced utilization of register resources.

[0062] (2) The first state and the third state.

[0063] In some embodiments, in addition to the second state indicating a working state and the first state indicating support for reconfiguration, a third state may also exist. This third state is used to indicate that the register set has been completely released, or in other words, the third state is used to indicate that the register set supports allocation to different work groups (or thread groups) in the processor 100.

[0064] In some embodiments, the resource management unit 120 is configured to release the first register set to the first state in response to a release request from the first thread group for the first register set.

[0065] Optionally, the release request of the first thread group for the first register set is triggered when the first thread group finishes using all registers in the first register set. The request may be a read instruction or a write instruction, or other instructions (such as a release instruction).

[0066] Exemplarily, the resource management unit 120 detects the usage of registers by the first thread group in real time, on a scheduled basis, or when triggered; or, the processor 100 further includes a detection unit, which is used to detect the usage of registers by the first thread group in real time, on a scheduled basis, or when triggered; and to notify the resource management unit 120 when the first thread group has finished using all registers in the first register set. Triggered detection refers to being triggered by an instruction or a signal. For example, when the resource management unit 120 receives a read instruction, the usage of the register indicated by the read instruction by the first thread group is detected, or the usage of all registers in at least two register sets by the first thread group is detected, or the usage of all registers in the register set corresponding to the register indicated by the read instruction by the first thread group is detected. The read instruction is used to read information from a register. It should be understood that the instruction may also be a write instruction, or other register-related instruction. The write instruction is used to write information into a register, and the information may be actual data or empty information.

[0067] Exemplarily, a register release instruction is provided for indicating that the first thread group has ended use of a register or register set, without requiring detection by the resource management unit 120 or the detection unit. For example, the processor 100 further includes an instruction issuing unit. The instruction issuing unit is configured to issue a register release instruction to the resource management unit 120, where the register release instruction indicates that the register or register set has ended use. The resource management unit 120 is configured to release the register set indicated by the register release instruction based on the register release instruction.

[0068] In other embodiments, the resource management unit 120 is used to release the second register set to a third state in response to a release request from the first thread group for the second register set, where the second register set includes at least one register from a plurality of registers, and the second register set and the first register set are register sets assigned to the first thread group, and the third state is used to indicate that the second register set supports the thread group within any work group assigned to the processor.

[0069] Optionally, the third state is used to indicate that the second register set supports the thread group within any work group assigned to the processor; or, the third state is used to indicate that the current register set supports the thread group within any work group assigned to the processor; or, the third state is used to indicate that the current register set supports the thread group within any work group assigned to the processor; or, the third state is used to indicate that the current register set supports the thread group assigned to the processor.

[0070] Optionally, allocation refers to the initial allocation of register sets to a thread group when it is created. Reconfiguration, on the other hand, refers to the reconfiguration of register sets already allocated to a workgroup to other thread groups within the workgroup. In other words, register sets in the third state are typically allocated to new thread groups within an existing workgroup, or to new thread groups within a new workgroup.

[0071] In some embodiments, the release request for releasing the first register set to the first state and the release request for releasing the second register set to the third state are the same request or different requests. For example, the release request for releasing the first register set to the first state is a first release request, and the release request for releasing the second register set to the third state is a second release request. The format of the first release request is the same as that of the second release request, such as the same parameter types required to be carried, but the parameter values ​​corresponding to each parameter type are different, such as the parameter type includes at least one of the following: a thread group identifier, a workgroup identifier, a register set identifier, a register identifier, and a reconfiguration parameter. For example, the reconfiguration parameter of the first release request is a first parameter, which is used to indicate that the register set is released to the first state, and the reconfiguration parameter of the second release request is a second parameter, which is used to indicate that the register set is released to the third state. Alternatively, the format of the first release request is different from that of the second request, such as the first release request carries reconfiguration information, which is used to indicate that the register set is released to the first state, while the second release request does not carry reconfiguration information.

[0072] Exemplarily, the resource management unit 120 is configured to release the first register set to a first state in response to a first release request from a first thread group for a first register set, wherein the first release request carries reconfiguration information, the reconfiguration information being used to indicate whether the first register set supports reconfiguration after release, or the reconfiguration information being used to indicate whether the first register set supports release to the first state, or the reconfiguration information being used to indicate that the first register set supports release to the first state. In other words, the reconfiguration information is used to indicate that the registers indicated by the release request support release to the first state.

[0073] Exemplarily, the resource management unit 120 is used to release the second register set to a third state in response to a second release request from the first thread group for the second register set, wherein the second release request does not carry reconfiguration information, and the reconfiguration information is used to indicate whether the first register set supports reconfiguration after release.

[0074] Optionally, the reconfiguration information is used to indicate whether the first register set supports reconfiguration after being released. If the release request carries reconfiguration information, it indicates that the release request is used to request that the register set be released to the first state. If the release request does not carry reconfiguration information, it indicates that the release request is not used to request that the register set be released to the first state. If a third state exists, then if the release request does not carry reconfiguration information, it indicates that the release request is used to request that the register set be released to the third state.

[0075] Optionally, the first and second release requests may be either early release requests or final release requests. An early release request is triggered when the thread group has not terminated, but the thread group has completed its use of n register sets or m register sets. A final release request is triggered when the thread group has terminated. That is, a final release request is triggered when the thread group has executed a termination instruction but the corresponding register sets have not been cleared.

[0076] In summary, the processor provided by the embodiment of the present application, through the setting of the third state, enables the register sets within the processor to be more clearly distinguished. For the processor, the register sets in the first state can be understood as the register sets allocated to the workgroup. These register sets are initially allocated to the thread groups within the workgroup. However, since most register sets are only used during part of the life cycle of the thread group, when the thread group has used up the registers in the register set or temporarily cannot use the registers in the register set, these register sets can be updated to the register sets in the first state through the first release request, so that the register sets that are temporarily not used or no longer used by these thread groups can be circulated within the workgroup, supporting the normal execution of some thread groups with large register resource requirements. The setting of the third state is based on another consideration, that is, when the register resources of the thread groups within the workgroup have been fully allocated, that is, when there are no thread groups lacking register resources, when the thread group releases the register set, the second release request can be used to release the register set to the processor, so that the processor can schedule more thread groups and improve the thread group occupancy rate. Furthermore, the settings of the first state and the third state can clarify the management of the register set in the processor, ensuring that the register set is in only one legal state at the same time, thereby avoiding concurrency conflicts.

[0077] In addition, the first release request and the second release request are distinguished by reconfiguration information, and the distinction between the two release requests is achieved with less information, which reduces the overhead of release request division and improves the indication efficiency of the release request.

[0078] In order to better manage the register resources of each work group and thread group in the processor 100, some parameters related to the register resources may be maintained in the processor 100. Specifically, as shown.

[0079] 2. Parameters related to register resources.

[0080] Exemplarily, the processor 100 may internally maintain the number of register sets that support allocation and the number of register sets that support reconfiguration.

[0081] (1) The number of first sets.

[0082] In some embodiments, a first set quantity is maintained for each workgroup, and the first set quantity is used to indicate the number of register sets in the first state corresponding to the workgroup. For example, the first set quantity of the first workgroup is used to indicate the number of register sets in the first state corresponding to the first workgroup. The first set quantity may change when a thread group within the first workgroup releases a register set, or when a thread group is reconfigured for a register set in the first state.

[0083] Exemplarily, when the first thread group belonging to the first work group releases a register set, the resource management unit 120 is used to respond to the first release request of the first thread group for n register sets, add n to the first set quantity to obtain an updated first set quantity, where n is a positive integer, the n register sets include the first register set, and the first set quantity is used to indicate the number of register sets in the first state corresponding to the first work group.

[0084] Optionally, the first release request carries identifiers of registers within the register set. Based on the register identifiers, the resource management unit 120 determines n register sets to be released. For example, the resource management unit 120 maintains a mapping relationship between registers and register sets. Based on this mapping relationship, the identifiers of the n register sets corresponding to the register identifiers are determined, thereby determining that the number of register sets released by the first release request is n. Alternatively, the first release request carries the identifiers of the n register sets to be released.

[0085] Optionally, the first release request carries the number of register sets to be released, or the number of register sets to be released is determined by the resource management unit 120 itself.

[0086] Exemplarily, in response to the configuration request of the second thread group, the resource management unit 120 reconfigures k register sets into registers used by the second thread group, where k is a positive integer and the k register sets include the first register set; subtracts k from the number of the first sets to obtain an updated number of the first sets.

[0087] Optionally, the k register sets may be released by the same thread group, such as the first thread group; or may be released by multiple different thread groups, such as the first thread group and the third thread group.

[0088] To summarize, the processor provided in the embodiment of the present application ensures the judgment of the configuration request for the thread group within the work group by maintaining the number of the first set, that is, judging whether the number of register sets in the first state within the current work group is greater than the number requested by the configuration request of the thread group, to determine whether to support the reconfiguration of the register set in the first state to the thread group, thereby avoiding the situation where the thread group is continuously blocked waiting for the reconfiguration of the register set due to insufficient register sets to be reconfigured to the thread group, which in turn causes the register set in the work group to be occupied by the blocked thread group for a long time, resulting in reduced utilization of register resources.

[0089] (2) The number of the second set.

[0090] In some embodiments, a second set number is maintained for the processor 100, and the second set number is used to indicate the number of register sets in the third state corresponding to the processor 100. The second set number may change when a thread group in any work group releases a register set, or when a register set is allocated to a newly created thread group.

[0091] Exemplarily, the resource management unit 120 is used to respond to a second release request from the first thread group for m register sets, add m to the second set quantity to obtain an updated second set quantity, where the m register sets include the second register set, and the second set quantity is used to indicate the number of register sets in the third state corresponding to the processor.

[0092] Optionally, the second release request carries identifiers of registers within the register set. Based on the identifiers of the registers, the resource management unit 120 determines m register sets to be released. For example, the resource management unit 120 maintains a mapping relationship between registers and register sets. Based on this mapping relationship, the identifiers of the m register sets corresponding to the register identifiers are determined, thereby determining that the number of register sets released by the second release request is m. Alternatively, the second release request carries the identifiers of the m register sets to be released.

[0093] Optionally, the second release request carries the number of register sets to be released, or the number of register sets to be released is determined by the resource management unit 120 itself.

[0094] In some embodiments, the processor 100 further includes an allocation management unit 130, such as Figure 2As shown. The allocation management unit 130 is configured to determine a first quantity, which is the number of register sets required by the third thread group; subtract the first quantity from the second quantity to obtain an updated second quantity, which is used to indicate the number of register sets in a third state corresponding to the processor, where the register sets in the third state support allocation to thread groups within any work group in the processor; the resource management unit 120 is configured to allocate the first number of register sets to the third thread group, where the first number of register sets are register sets in the third state; and update the state of the first number of register sets to a second state, where the second state indicates that the first number of register sets are being used by the third thread group.

[0095] Optionally, the allocation management unit 130 is responsible for maintaining the second set quantity. When the allocation management unit 130 updates the second set quantity, the first number of register sets may be allocated to the third thread group, such as by determining an identifier of the register set corresponding to the third thread group; or, the resource management unit 120 may allocate the first number of register sets to the third thread group.

[0096] Optionally, when allocating the first number of register sets to the third thread group, a mapping relationship between the third thread group and the first number of register sets should be determined. For example, the mapping relationship between the thread group and the register set is determined using a register mapping management table. Exemplarily, the resource management unit 120 is configured to add a mapping relationship between each register set in the first number of register sets and the third thread group to the register management mapping table.

[0097] Optionally, the register management mapping table includes at least one of the following parameters: a valid bit; an identifier of a thread group; an identifier of a register set; and a register set counter.

[0098] The valid bit indicates whether the current register set is occupied. The thread group identifier indicates the thread group that occupies the current register set. The register set identifier can be used to identify the registers belonging to the register set. The register set counter indicates the number of registers currently in use within the current register set.

[0099] In summary, the processor provided by the embodiment of the present application ensures the reasonable allocation of the processor's internal register set by maintaining the second set number. For example, if the second set number is used to determine whether to support scheduling a new thread group to execute the corresponding task, when the second set number is sufficient, more thread groups can be scheduled to increase the occupancy rate of the thread group in the processor. The maintenance of the second set number can ensure the normal allocation of the processor's internal register set, and avoid the situation where a new thread group is still scheduled when the register set is insufficient, resulting in register overflow, forcing some data that should be stored in the register to be stored in the memory, greatly increasing the memory access delay, and thus resulting in a reduction in the processor's computing performance. That is, the maintenance of the second set number is conducive to the processor scheduling thread groups according to the number of register sets currently supported for allocation, thereby improving the reliability of thread group scheduling.

[0100] (3) The number of the third set.

[0101] In some embodiments, a third set number is maintained for each thread group. The third set number is used to indicate the number of register sets currently in use by the thread group, i.e., the number of register sets in the second state corresponding to the thread group. For example, the third set number of a first thread group is used to indicate the number of register sets in the second state corresponding to the first thread group. This third set number may change when, for example, the first thread group releases a register set, a new thread group is initially allocated a register set, or a register set in the first state is reassigned to the thread group.

[0102] Exemplarily, the resource management unit 120 is used to respond to a first release request from the first thread group for n register sets by subtracting n from the third set quantity of the first thread group to obtain an updated third set quantity, where n is a positive integer, the n register sets include the first register set, and the third set quantity is used to indicate the number of register sets being used by the first thread group.

[0103] Exemplarily, the resource management unit 120 is used to respond to the second release request of the first thread group for m register sets, subtract m from the third set quantity of the first thread group to obtain an updated third set quantity, where m is a positive integer, the m register sets include the second register set, and the third set quantity is used to indicate the number of register sets being used by the first thread group.

[0104] In some embodiments, the processor 100 further includes an allocation management unit 130, such as Figure 2As shown. The allocation management unit 130 is configured to determine a first quantity, which is the number of register sets required by the third thread group; subtract the first quantity from the second quantity to obtain an updated second quantity, which is used to indicate the number of register sets in a third state corresponding to the processor, where the register sets in the third state support allocation to thread groups within any work group in the processor; the resource management unit 120 is configured to allocate the first number of register sets to the third thread group, where the first number of register sets are register sets in the third state; and update the state of the first number of register sets to a second state, where the second state indicates that the first number of register sets are being used by the third thread group.

[0105] Optionally, when the resource management unit 120 allocates the first number of register sets to the third thread group, the resource management unit 120 is configured to update the third set quantity of the third thread group to the first number, thereby obtaining an updated third set quantity, where the third set quantity indicates the number of register sets currently in use by the third thread group. That is, the third set quantity is initialized when the resource management unit 120 allocates register sets to the third thread group.

[0106] In some embodiments, the resource management unit 120 reconfigures k register sets into register sets used by the second thread group in response to the configuration request of the second thread group; adds k to the third set quantity of the second thread group to obtain an updated third set quantity.

[0107] In summary, the processor provided in the embodiments of the present application, by maintaining the third set number, enables the processor to dynamically monitor the number of register sets occupied by each thread group in the processor in real time. This allows the processor to dynamically schedule the execution of each thread group within the processor based on at least one of the number of register sets occupied by each thread group (the third set number of each thread group) and the number of idle register sets within the processor (the second set number). Furthermore, the processor can dynamically adjust the parallelism of the thread groups to ensure the overall thread group occupancy rate of the processor.

[0108] (4) Number of active thread groups.

[0109] In some embodiments, each work group includes at least one thread group. When all thread groups in the work group have been executed, the work group and the register set of the first state corresponding to the work group can be released, thereby avoiding the problem that the work group without active thread groups occupies the register set for a long time, resulting in reduced resource utilization. Therefore, an active thread group number can be maintained for each work group, so as to determine when to release the work group and the register set of the first state corresponding to the work group according to the change in the number of active thread groups. The number of active thread groups is used to indicate the number of thread groups in the work group that are in a working state, or the number of active thread groups is used to indicate the number of thread groups that have not yet ended in the work group. For example, the number of active thread groups corresponding to the first work group is used to indicate the number of thread groups in a working state in the first work group. Specifically, the number of active thread groups will change when thread groups are assigned to the work group, when thread groups are no longer used, etc.

[0110] Exemplarily, when allocating a third thread group to the first work group, or allocating a register set to the third thread group belonging to the first work group, or initially allocating a register set to the third thread group belonging to the first work group, the resource management unit 120 is used to add one to the number of active thread groups corresponding to the first work group to obtain an updated number of active thread groups, where the number of active thread groups is used to indicate the number of thread groups in working state in the first work group.

[0111] Optionally, when allocating the third thread group to the first work group, if the processor does not find the identifier of the first work group, the processor first records the identifier of the first work group, and then determines the number of active thread groups in the first work group, a mapping relationship between the identifier of the first work group and the identifier of the third thread group, and so on.

[0112] Exemplarily, the resource management unit 120 is configured to, in response to the termination of the fourth thread group in the first work group, reduce the number of active thread groups corresponding to the first work group by one to obtain an updated number of active thread groups, where the number of active thread groups is used to indicate the number of thread groups in working state in the first work group.

[0113] Optionally, the processor 100 further maintains a mapping relationship between workgroups and thread groups. For example, when a third thread group is assigned to a first workgroup, the resource management unit 120 is configured to determine a mapping relationship between the identifier of the first workgroup and the identifier of the third thread group. When the fourth thread group in the first workgroup is no longer in use, the resource management unit 120 is configured to delete or cancel the mapping relationship between the identifier of the first workgroup and the identifier of the third workgroup.

[0114] In some embodiments, when the number of active thread groups corresponding to a work group is zero, it is necessary to complete the recycling of register resources corresponding to the work group. This register resource mainly refers to the register set in the first state corresponding to the work group, that is, the register set that supports reconfiguration for the thread groups within the work group. Because although this part of the register set supports reconfiguration for the thread groups within the work group, it does not support being allocated to other work groups by the processor. Therefore, when there is no active thread group in the work group, the register set in the first state should be recycled for the processor.

[0115] Exemplarily, the processor 100 further includes an allocation management unit 130, such as Figure 2 As shown. The resource management unit 120 is configured to, when the number of active thread groups in the first workgroup is zero, determine a first set number for the first workgroup, and update the state of a register set corresponding to the first workgroup from the first state to the third state, where the number of active thread groups indicates the number of thread groups in the first workgroup that are in a working state, and the first register number is the number of register sets in the first state corresponding to the first workgroup; send the first set number to the allocation management unit 130; and the allocation management unit 130 is configured to add a second set number to the first set number to obtain an updated second set number, where the second set number is the number of register sets in the third state corresponding to the processor.

[0116] Optionally, updating the state of the register set corresponding to the first working group from the first state to the third state can be understood as releasing the register set in the register set of the first state that has a mapping relationship with the first working group to the third state; or, releasing the register set corresponding to the first working group to the third state.

[0117] In summary, the processor provided in the embodiment of the present application determines the life cycle of a workgroup by maintaining the number of active thread groups corresponding to each workgroup. Compared to a thread group, a workgroup is a new level mainly set up for reconfiguration requirements. A thread group can make termination judgments based on its register usage, whether the end instruction (END instruction) has been executed, etc. However, for a workgroup, there may not actually be a corresponding instruction. In this case, the number of active thread groups corresponding to the workgroup can be used to determine whether the register set corresponding to the workgroup needs to be released, thereby avoiding the problem of a workgroup without a working thread group occupying the register set for a long time, resulting in a decrease in the resource utilization of the register set. At the same time, the register set occupied by the workgroup is released in a timely manner, which can also ensure that the processor can schedule the thread group in a timely manner and improve the thread group occupancy rate. In addition, the number of active thread groups corresponding to the workgroup can also be used by the processor to dynamically schedule thread groups, such as timely scheduling new thread groups (such as thread groups with higher register requirements) for workgroups with a small number of active thread groups to improve the utilization rate of register sets within the workgroup.

[0118] In some embodiments, the plurality of registers 110 are a plurality of vector registers; or, the plurality of registers 110 are a plurality of scalar registers.

[0119] It should be noted that the embodiments of the present application do not limit the types of registers in the processor 100. The above-mentioned vector registers and scalar registers are only for illustration. In actual scenarios, the methods provided in the embodiments of the present application also support the allocation, release, and reconfiguration of other types of registers. The scope of protection of the embodiments of the present application is not limited thereto.

[0120] It should be noted that the "(1) Second state", "(2) First state and third state" in the above "1. Status of register sets", and the "(1) Number of first sets", "(2) Number of second sets", "(3) Number of third sets", and "(4) Number of active thread groups" in the "2. Related parameters of register resources" can be implemented as independent embodiments or as a combined embodiment. For example, “(1) the second state” in “1. the state of the register set” and “(2) the first state and the third state” and “(4) the number of active thread groups” in “1. the state of the register set” can be implemented in combination; or “(1) the second state” in “1. the state of the register set” and “(1) the number of first sets” in “2. the relevant parameters of register resources” can be implemented in combination; or “(1) the second state” in “1. the state of the register set” and “(2) the number of second sets” in “2. the relevant parameters of register resources” can be implemented in combination; or “(1) the second state” in “1. the state of the register set” and “(3) the number of third sets” in “2. the relevant parameters of register resources” can be implemented in combination; or “(1) the second state” in “1. the state of the register set” and “(4) the number of active thread groups” in “2. the relevant parameters of register resources” can be implemented in combination. "(1) The number of groups" can be implemented in combination; or, "(2) The first state and the third state" in "1. The state of the register set" and "(1) The number of first sets" in "2. Related parameters of register resources" can be implemented in combination; or, "(2) The first state and the third state" in "1. The state of the register set" and "(2) The number of second sets" in "2. Related parameters of register resources" can be implemented in combination; or, "(2) The first state and the third state" in "1. The state of the register set" and "(3) The number of third sets" in "2. Related parameters of register resources" can be implemented in combination; or, "(2) The first state and the third state" in "1. The state of the register set" and "(4) The number of active thread groups" in "2. Related parameters of register resources" can be implemented in combination; in addition to the two-by-two combination implementation shown above, three-by-three combination, four-by-four combination or six-by-six combination is also possible. For example, “(1) Second state” in “1. State of register set”, “(2) First state and third state” in “1. State of register set” and “(1) Number of first set” in “2. Related parameters of register resources” can be implemented in combination; or “(1) Second state” in “1. State of register set”, “(2) First state and third state” in “1. State of register set” and “(2) Number of second set” in “2. Related parameters of register resources” can be implemented in combination; or “(1) Second state” in “1. State of register set”, “(2) First state and third state” in “1. State of register set” and “2. Related parameters of register resources” can be implemented in combination."(3) The number of third sets" in "Related parameters of register resources" can be implemented in combination; or, "(1) The second state in "1. State of register set", "(2) The first state and the third state in "1. State of register set" and "(4) The number of active thread groups" in "2. Related parameters of register resources" can be implemented in combination; or, "(1) The second state in "1. State of register set", "(1) The number of first sets" in "2. Related parameters of register resources" and "(2) The number of second sets" in "2. Related parameters of register resources" can be implemented in combination; or, "(1) The second state in "1. State of register set", "(2) The first state and the third state in "2. Related parameters of register resources" and "(4) The number of active thread groups" in "2. Related parameters of register resources" can be implemented in combination; "(1) The first set number" in "2. Related parameters of register resources" and "(3) The third set number" in "2. Related parameters of register resources" can be implemented in combination; or, "(1) The second state" in "1. State of register set" and "(1) The first set number" in "2. Related parameters of register resources" and "(4) The number of active thread groups" in "2. Related parameters of register resources" can be implemented in combination; or, "(1) The second state" in "1. State of register set" and "(2) The second set number" in "2. Related parameters of register resources" and "(3) The third set number" in "2. Related parameters of register resources" can be implemented in combination; or, "(1) The second state" in "1. State of register set" and "(2) The second set number" in "2. Related parameters of register resources" and "(3) The third set number" in "2. Related parameters of register resources" can be implemented in combination; "(2) The second set number in "1. State of register set", "(2) The second set number in "2. Related parameters of register resources", and "(4) The number of active thread groups in "2. Related parameters of register resources" can be implemented in combination; or "(1) The second state in "1. State of register set", "(3) The third set number in "2. Related parameters of register resources", and "(4) The number of active thread groups in "2. Related parameters of register resources" can be implemented in combination; or "(2) The first state and the third state in "1. State of register set", "(1) The first set number in "2. Related parameters of register resources", and "(2) The second set number in "2. Related parameters of register resources" can be implemented in combination; Alternatively, “(2) The first state and the third state” in “1. State of register set”, “(1) The number of first sets” in “2. Related parameters of register resources”, and “(3) The number of third sets” in “2. Related parameters of register resources” may be implemented in combination; or “(2) The first state and the third state” in “1. State of register set”, “(1) The number of first sets” in “2. Related parameters of register resources”, and “(4) The number of active thread groups” in “2. Related parameters of register resources” may be implemented in combination; or “(2) The first state and the third state” in “1. State of register set”, “(2) The number of second sets” in “2. Related parameters of register resources”, and “(2) The number of third sets” in “2. Related parameters of register resources” may be implemented in combination."(3) The third set number" in "Related parameters of register resources" can be implemented in combination; or, "(2) The first state and the third state" in "1. State of register set", "(2) The second set number" in "2. Related parameters of register resources", and "(4) The number of active thread groups" in "2. Related parameters of register resources" can be implemented in combination; or, "(2) The first state and the third state" in "1. State of register set", "(3) The third set number" in "2. Related parameters of register resources", and "(4) The number of active thread groups" in "2. Related parameters of register resources" can be implemented in combination; or, "(1) The first set number" in "2. Related parameters of register resources", "(2) The second set number" in "2. Related parameters of register resources", and "(3) The third set number" in "2. Related parameters of register resources" can be implemented in combination; or, "2. Related parameters of register resources" can be implemented in combination; "(1) First set number" in "2. Related parameters of register resources", "(2) Second set number" in "2. Related parameters of register resources", and "(4) Number of active thread groups" in "2. Related parameters of register resources" can be implemented in combination; or "(1) First set number" in "2. Related parameters of register resources", "(3) Third set number" in "2. Related parameters of register resources", and "(4) Number of active thread groups" in "2. Related parameters of register resources" can be implemented in combination; or "(2) Second set number" in "2. Related parameters of register resources", "(3) Third set number" in "2. Related parameters of register resources", and "(4) Number of active thread groups" in "2. Related parameters of register resources" can be implemented in combination, and so on. The embodiments of the present application will not list the remaining combined implementation methods one by one, but the protection scope of the embodiments of the present application is not limited thereto.

[0121] In some embodiments, when processing graphics or computational tasks using a SIMD architecture, the initial computation may require a large amount of register resources due to the large number of registers used by the compiler-compiled instructions. These resources must be allocated before the program begins running for computational use. However, as branch conditions or program exits occur, some registers are no longer needed for computation, resulting in dead registers.

[0122] The existence of these dead registers will occupy the entire life cycle of the thread, causing the space to be unusable for a long time. They must wait until the thread ends and the other registers end together before they are released.

[0123] This will cause the entire allocated register resources of the thread to be in a strongly bound state during allocation and release, making it impossible for the thread warp to achieve a high degree of parallelism.

[0124] The structure of the processor is as follows Figure 3 As shown. In the related art, the allocation management unit 130 in the processor is responsible for managing resources. After the tasks are grouped by the allocation management unit 130, they are gradually sent to the task scheduling and distribution unit 150, and then enter the task management unit 160 through the task scheduling and distribution unit 150. The tasks are scheduled for execution by the task management unit 160, and the instruction transmission unit 140 fetches instructions, decodes, reads the instruction src and transmits it for execution. The execution unit 170 completes the execution and writes the result back to the instruction dst. When the END instruction is executed, the task (i.e., thread group) ends. At this time, END is sent to the task management unit 160, and the task management unit 160 instructs the resource management unit 120 to release the resources, and transmits the task number back to the allocation management unit 130, so that all register resources of the task (i.e., thread group) are released together, and then the entire task (i.e., thread group) information, including the task number, is recovered.

[0125] AI applications, however, face issues with the producer-consumer synchronization mechanism for computation and cross-card communication. This means some threads need to perform data computation, while others need to load and store data. If the same kernel processes these threads in branches, with one branch handling computation and the other handling data loading and storage, the kernel's compiled register resources will need to meet all computation and data loading and storage requirements. Furthermore, both the producer and consumer thread groups will occupy the same large number of dead registers throughout their lifecycles. However, the producer and consumer thread groups are interdependent, which in turn prolongs the lifecycles of both thread groups. This results in inefficient register resource utilization and low occupancy across the entire compute core, further reducing overall performance.

[0126] In an indirect call function, the compiler conservatively allocates redundant resource information to avoid too many resources being occupied for a long time and also needs to be released in advance.

[0127] The embodiments of the present application hope to solve the problem of early release of dead registers, solve the problem of register reconfiguration in application scenarios, and the problem of redundant resource waste caused by the conservative allocation strategy of indirect call function, improve resource utilization and thread group occupancy, thereby improving hardware performance.

[0128] The present embodiment of the present invention aims to release dead registers in advance for recycling based on the different lifecycles of registers used within the application. By releasing dead register resources in advance and immediately recycling them, the present invention aims to improve register utilization and thread group occupancy by reconfiguring and allocating related registers without affecting the execution of the original thread group.

[0129] Different applications (i.e., tasks) typically perform numerous register allocations, data transfers, and computations. Many of these operations require the use of numerous registers in the Arithmetic Logic Unit (ALU). These registers are allocated when the program starts and released when it ends. However, as operations complete, some registers are gradually used up, leading to the phenomenon of dead registers.

[0130] In AI applications, the dependency between compute threads and memory access threads in producer-consumer synchronization further prolongs the lifecycle of dead registers. Therefore, decoupling compute threads from memory access threads at the hardware level allows for reconfiguration and utilization of dead registers between workgroup threads, improving register utilization.

[0131] In this regard, the embodiment of the present application designs a management strategy for discrete resource allocation. Next, the method shown in the embodiment of the present application is further described using a register set as an example of a register row. In the allocation management unit 130, the total number of available register row allocations (i.e., the second set number mentioned above) is recorded. Register resources are allocated in rows. Each row can be configured with 2 or 4 registers at the logical level according to the requirements of each generation of processor architecture. It should be understood that it can also be more or less registers. A register counter is recorded for each row to indicate how many registers are still in use in the current row. When allocating register resources to a task, the number of rows that need to be allocated and the number of registers contained in the last row are calculated.

[0132] When a certain task is assigned a certain number of register rows, the resource management unit 120 needs to deduct the number of allocated rows from the number of available register rows. When a task is executed and encounters an operation to release some dead register resources, the number of dead register rows released in the current stage can be added back to the number of available register rows. When a task in a work group is executed and encounters an operation to release some dead register resources, but the register resources are set in the application program for use by other thread bundles in the work group and are not released for use by other work group tasks, only internal recycling is performed within the work group, and the valid work group, work group number information, grouping status information, the number of valid active tasks contained in the work group, and the current number of reconfigurable register rows in the work group are recorded. When a task is completed and exits, the number of released register rows carried by the task when it exits needs to be added back to the number of available register rows in the resource management. In this way, other tasks can be allocated and used again when they are scheduled to be executed.

[0133] In order to support register allocation, reconfiguration, early release of dead registers, release of dead registers at the end of a thread group, and release of dead registers at the end of a work group, the embodiment of the present application maintains the following tables to manage register row resources.

[0134] Maintain a thread group register row number table and record the total number of rows allocated for each task according to the thread group number.

[0135] A workgroup information table is maintained, recording the valid workgroup tag, the current workgroup number, the number of thread groups currently active on the current stream processor core, and the number of reconfigurable register rows belonging to the current task group. When a task is first assigned to a stream processor core, the workgroup number and related assignment information are recorded in the workgroup table.

[0136] Maintain a thread group number-register row address mapping table, which contains the row state machine and the work group number information, row valid register counter, address row number, etc.

[0137] The workgroup number uniquely identifies the current workgroup within the stream processor core. The task thread group number uniquely identifies the current task within the processor core. The row valid register counter indicates how many registers are still in use within the current register row. When the register count is reduced to 0, it can be released. The tail row is initialized with the register count passed down from the upstream allocation, so the initial value of the tail row is not necessarily full. The address row number identifies the row address location where the register contents are actually stored.

[0138] When the initial task allocation information arrives, the corresponding task number, workgroup number, number of tasks assigned to the stream processor core in the workgroup, and number of registers in the last row are passed down and updated in the corresponding table entries. Simultaneously, the number of valid registers in the row's initial and last rows are written to the corresponding counters. The register row state machine information is updated.

[0139] Next, we introduce the register row state machine.

[0140] The register row state machine contains the following three states. The specific state transition relationship is as follows: Figure 4 shown.

[0141] The first state (grouping) indicates that the register row has been released in advance by the thread group and belongs to the current work group, making it available for reconfiguration and use by other thread groups within the current work group. However, the register row has not yet been released and cannot be reconfigured or used by thread groups in other work groups.

[0142] The second state (waving) indicates that the current register row has been assigned to the corresponding thread group and the thread group is still in a valid state. This row can only be used by this thread group and cannot be released or used by any other thread group.

[0143] The third state (invalid) indicates that the current register row is not allocated or has been completely released.

[0144] Next, register release management is described.

[0145] During instruction execution, the use of a register is gradually completed. When a register resource is completed, the row valid register count value in the register management mapping table is updated. When the counter value of the row is 0, it indicates that the row can be released.

[0146] When a thread group is released without reconfiguration information, the register row state machine is updated from waving to invalid. At the same time, the number of reclaimed rows is passed to the upstream allocation management unit, and this number is added back to the allocation management unit's available register row allocation number for subsequent allocation. In this case, when the thread group ends, some register resources may not be reduced to 0. In this case, the number of register rows in the current thread group must be cleared and the number of register rows released this time must be added back to the allocation management unit's available register row allocation number.

[0147] When released from a thread group and there is reconfiguration information, the register row state machine is updated to the grouping state. At the same time, the number of reclaimed rows is subtracted from the row counter of the thread group, and the number of available rows in the work group is added to the row counter of the thread group. In this case, when the thread group ends, there may be a situation where some register resources have not been reduced to 0. In this case, the number of register rows of the current thread group needs to be cleared and the number of register rows released this time is added back to the number of available register rows allocated to the work group.

[0148] When a thread group ends its work group, the number of thread groups originally allocated to the work group and still valid on the current stream processor core is decremented by 1. When this value is decremented to 0, if the number of grouping status register rows in the work group is not 0, such as the value of the row is grouping_remain_X, all work group information in the work group information table must be cleared, and the value of the row grouping_remain_X is added back to the number of available register rows in the allocation management unit.

[0149] During each thread group execution release, a new thread group allocation request may appear. At this time, as long as the resources required by the thread group can meet its needs, it will be allocated normally without blocking and waiting.

[0150] Finally, reconfiguration management is introduced.

[0151] When the thread group executes the relevant reconfiguration instructions and enters the reconfiguration state, the thread group will enter the reconfiguration blocking state. At this time, the thread group sends resource information containing the thread group number, workgroup number request and the corresponding number of reconfiguration register rows required to the resource module. At this time, the reconfiguration management logic will look up the corresponding workgroup information table and compare the number of reconfiguration register rows with the number of available grouping rows. If it is not enough, the request will continue to be blocked; if it is enough, the corresponding number of available register rows will be reconfigured, and the thread group number of the corresponding row will be modified to the number of the newly requested thread group, and the row state machine state will be modified to waving to complete the reconfiguration information update. When the reconfiguration is completed, the thread group in the blocked state will be awakened to continue execution.

[0152] The complete process is as follows.

[0153] This embodiment of the application designs a discrete resource allocation management strategy that allocates register resources in rows. Each row can have 1, 2, 4, 8, 16, MAX_REG_CNT, and so on. When allocating registers, the register count generated by the upstream compiler is sent to the hardware through the driver. This embodiment of the application uses the row-based allocation of register resources as an example to illustrate.

[0154] The allocation management unit 130 maintains an available register row allocation quantity, which is used to indicate the current number of remaining available register rows.

[0155] When the hardware starts the task and allocates resources, it performs alignment when it gets the corresponding amount and calculates the number of rows to be allocated and the amount remaining in the last row. When the allocation is complete, the corresponding task number and the number of registers in the last row are updated in the register counter.

[0156] like Figure 5 As shown, a register management mapping table 30 is shown, in which a specific mapping is performed with 4 registers arranged in each row, as shown in FIG. Figure 5 As shown in the allocation table 40 in the register management mapping table 30, the valid bit is 1, indicating that the row is valid, the thread group 5 indicates that the number of the task thread group is 5, and the counter = 3 indicates that 3 registers in the address row 0 are being used.

[0157] Specifically, when a task is started, the allocation management unit 130 first determines whether the number of available register rows is sufficient. If it is sufficient, it subtracts the number of rows that need to be allocated, and carries the task thread group number, work group number, the number of thread groups currently valid for the work group allocation on the current stream processor core, and the number of tail row registers into the resource management unit 120.

[0158] The resource management unit 120 checks the work group information table to see if the current work group number exists. If not, the resource management unit 120 enters the current work group number, the number of thread groups currently active on the current stream processor core, and the number of reconfigurable register rows belonging to the current task group, and marks the current work group as active. If the work group number exists, no update is performed.

[0159] At the same time, the resource management unit 120 updates the thread group register row table and enters the allocated row number into the corresponding entry based on the thread group number. It also refreshes the thread group number-register row address mapping table, maps the corresponding idle row register management mapping table, updates the row state machine to waving, and enters the work group number and row valid register count. If the row is the last row, the valid register count is updated with the number of last row registers requested. For non-last rows, the valid register count is set to MAX_REG_CNT.

[0160] like Figure 6 As shown, after the allocation request 60 is sent, it is processed by the allocation logic 61 and management logic 62, and the work group information table 63, the thread group register row table 64, and the thread group number-register row address mapping table 65 are updated. At this time, the allocation management unit 130 sends the thread group to the task scheduling and distribution unit 150. After scheduling and distribution, it enters the task management unit 160.

[0161] The task management unit 160 schedules the thread groups in the ready state to enter the instruction issuing unit 140 for instruction fetching, decoding, and issuing. The instructions are then issued to the corresponding instruction execution unit 170 for execution.

[0162] During the instruction issuance process, access to the relevant registers is gradually completed. At this time, the SRC request for completing the read instruction for a particular register is sent to the resource management unit 120. After completing the address mapping using the thread group number-register row address mapping table 65, the resource management unit 120 accesses the corresponding register resource storage bank 66 to perform the data return operation. If the instruction is a write operation, the write access request and operation are directly completed.

[0163] At this time, if a similar release instruction such as {Ctrl.OP.RLS type=vector_reg, release_size} is executed, the thread group's vector register release operation is triggered. This may trigger a release request 67, which is processed by the release logic 68 and management logic 62, and updates the work group information table 63, the thread group register row table 64, the thread group number-register row address mapping table 65, etc.

[0164] At this time, it should be checked whether the state carried by the current thread group contains reconfiguration information. If there is reconfiguration information, the register information of the thread group is converted into the corresponding row number RELEASE_LINE based on the release_size size in the release instruction (usually expressed as the number of registers, such as {R3, R6}), and the row valid register count value is updated minus release_size. Based on the corresponding row number RELEASE_LINE, the corresponding row state machine is updated to update waving to the grouping state, and the total number of rows corresponding to the thread group is updated (minus RELEASE_LINE). The number of grouping rows of reconfigurable registers belonging to the current task group in the work group table is added to the corresponding row number RELEASE_LINE. If there is no reconfiguration information, the corresponding row state machine is updated to update waving to the invalid state. At this time, a request is sent to the allocation management unit 130 to add the corresponding row number RELEASE_LINE to the number of available register row allocations of the allocation management unit 130.

[0165] At this time, if the instruction is a resource reconfiguration instruction such as {Ctrl.OP.RECONF type=vector_reg, reconfig_size}, a reconfiguration request 69 is triggered. This reconfiguration request 69 is processed by the reconfiguration request and blocking information logic 70, the reconfiguration logic 71, and the management logic 62, and updates the work group information table 63, the thread group register row number table 64, the thread group number-register row address mapping table 65, etc.

[0166] Specifically, when a reconfiguration resource instruction is executed, the instruction issuing unit 140 first stops issuing instructions for the thread group and marks the thread group as blocked. The reallocation request and blocking information submodule records the reconfiguration requests from different thread groups in different work groups. At this time, the resource management unit 120 converts reconfig_size into the corresponding register line number RECONFIG_LINE, matches the corresponding work group number, and compares the register line number of the work group in the grouping state with RECONFIG_LINE. If grouping row resources are insufficient, the current reconfiguration request is skipped, and the next reconfiguration request and other reconfiguration requests in the blocking information submodule are processed in a polling scan. If grouping row resources are sufficient, the reconfiguration operation is performed: the number of grouping rows of registers that can be reconfigured belonging to the current task group in the work group information table 63 is subtracted by RECONFIG_LINE, and the number of rows of the thread group number in the thread group register row number table 64 for the thread group number requested for reconfiguration is added to RECONFIG_LINE. The thread group number of the corresponding row in the thread group number-register row address mapping table 65 is modified to the thread group number requested for reconfiguration, and the row state machine state is changed from grouping to waving to complete the reconfiguration information update. When the reconfiguration is complete, the blocked thread group is awakened to continue execution.

[0167] When the END instruction ends, the END signal is sent from the execution unit 170 that executes END to the task management unit 160. The task management unit 160 sends the thread group number information to the resource management unit 120. In this case, when the thread group ends, there may be a situation where the register resources have not been reduced to 0. At this time, it is necessary to clear all the register rows of the current thread group in the thread group register row table 64. If the thread group carries reconfiguration information, the number of register rows released this time will be added back to the number of available register rows allocated to the work group, and the waving state will be switched to the grouping state. If the thread group does not carry reconfiguration information, the operation of adding back to the number of available register rows allocated to the work group will not be performed, and the waving state will be switched to the invalid state. The number of thread groups that are still valid on the current stream processor core that was originally allocated by the work group in the resource management unit 120 needs to be reduced by 1. When this value decreases to 0, if the number of grouping status register rows in the work group is not 0, such as the value of the row is grouping_remain_X, all work group information in the work group information table must be cleared, the grouping status is switched to invalid, and the row value grouping_remain_X is added back to the number of available register rows allocated by the allocation management unit 130 to complete the resource recycling operation. Finally, the thread group is released.

[0168] The embodiments of the present application are mainly used to solve the dead register phenomenon during program execution. Through discrete allocation management strategies, resources are effectively and fully utilized. At the same time, reconfigurable operations are performed in the work group. By recycling dead registers in advance, register resource utilization and thread group occupancy are improved, thereby achieving the effect of improving performance.

[0169] The processor provided by the embodiment of the present application has the following key points: discrete register allocation management strategy before thread execution; dead register mark update during program execution; dead register marking and identification; misaligned tail line processing during allocation; early release management of register rows during program execution; register row reconfiguration resource management, row state machine management, and various table information maintenance management during program execution; register row reconfiguration state management and switching operations during program execution; register resource release management when the thread group exits; register resource release management when the program thread work group exits.

[0170] Figure 7 A flowchart of a register allocation method provided by an exemplary embodiment of the present application is shown. The method is executed by a processor provided by each of the above embodiments, the processor including: a plurality of registers and a resource management unit. The method includes at least one of the following steps.

[0171] Step 210: When the first thread group belonging to the first work group has finished using the first register set, the resource management unit releases the first register set to a first state, where the first state is used to indicate that the first register set supports reconfiguration to other thread groups belonging to the first work group, and the first register set includes at least one register among multiple registers.

[0172] The first work group includes at least two thread groups, and the at least two thread groups include the first thread group.

[0173] Optionally, at least two thread groups included in the first working group are used to execute the same task, or at least two thread groups included in the first working group are used to execute different tasks. The same task can be understood as a task that executes the same instruction but has different operands. Different tasks are tasks that execute different instructions, or have different task objectives, or tasks that correspond to different branches. If the task objective of the first task is a computing task and the task objective of the second task is a communication task, then the first task and the second task are different tasks. The division of task objectives can also be more fine-grained, such as if the task objective of the first task is a computing task for image filtering, and the task objective of the second task is a computing task for feature extraction. At this time, although the first task and the second task are both computing tasks, after further dividing the computing tasks, it can be determined that the first task and the second task are different tasks.

[0174] Optionally, the processor initially allocates the same or different numbers of register sets to at least two thread groups in the first work group. For example, the number of register sets initially allocated to both the first thread group and the second thread group is 4; or the number of register sets initially allocated to the first thread group is 4, and the number of register sets initially allocated to the second thread group is 2.

[0175] Optionally, the processor determines the number of register sets to initially allocate based on the tasks executed by the thread group. Exemplarily, the number of register sets allocated by the processor for computing tasks is greater than the number of register sets allocated for communication tasks.

[0176] In other embodiments, to avoid excessive resource allocation overhead, the processor may allocate the same number of register sets to each thread group (or thread groups within each workgroup). For example, i register sets may be allocated to all thread groups within a workgroup; or i register sets may be allocated to all thread groups within a first workgroup, and j register sets may be allocated to all thread groups within a second workgroup. Here, i and j are both positive integers.

[0177] Optionally, the first thread group includes at least one thread; or the first thread group corresponds to at least one thread. A thread group is a scheduling unit for computing resources in a processor; or a thread group is an allocation unit for computing resources in a processor.

[0178] Optionally, the first thread group corresponds to at least one thread, each thread being a physical unit in the processor. That is, the first thread group is a set of physical units in the processor. Threads may also be referred to as computing units, computing cores, processing units, etc. In other embodiments, the first thread group includes at least one thread, and both the first thread group and threads are logical concepts. That is, the first thread group corresponds to a set of physical units in the processor, and one thread corresponds to a physical unit in the processor. The physical unit may be referred to as a computing unit, computing core, processing unit, etc. That is, the processor further includes multiple computing units, which are used to perform computing tasks.

[0179] Optionally, the computing resources include a plurality of registers. Optionally, the computing resources also include memory, cache, etc.

[0180] Optionally, the first state is used to indicate that the first register set supports reconfiguration to other thread groups belonging to the first workgroup. That is, the register set in the first state is a register set that supports reconfiguration to other thread groups belonging to the first workgroup; or, the first state is used to indicate that the current register set supports reconfiguration to other thread groups belonging to the first workgroup. If the current register set is released by a thread group in another workgroup, the first state is used to indicate that the current register set supports reconfiguration to other thread groups belonging to the same workgroup; or the first state is used to indicate that the current register set supports reconfiguration to different thread groups belonging to the same workgroup. Exemplarily, the first workgroup includes n thread groups. If the i-th thread group triggers the release of the first register set to the first state, the first register set supports reconfiguration to the j-th thread group belonging to the first workgroup, where j is any positive integer other than i, and j is less than n. i is a positive integer less than n.

[0181] Optionally, the first register set includes at least one register. That is, each register set includes at least one register.

[0182] For example, each register set includes 2 n registers, where n is 0 or a positive integer. For example, each register set includes 1 register; or, each register set includes 2 registers; or, each register set includes 4 registers; or, each register set includes 8 registers; or, each register set includes 16 registers, and so on.

[0183] It should be noted that the embodiment of the present application does not limit the number of registers included in each register set. The number of registers included in each register set can be set according to the requirements of the actual processing task (such as rendering task, model training task, video processing task, etc.).

[0184] Optionally, the register set may be implemented as a register row, a register group, a register file, a register cluster, a register window, etc. That is, the embodiment of the present application does not limit the implementation form of the register set.

[0185] Optionally, the register set is a logical set, meaning that when register resources are allocated to the first thread group, they are allocated in units of register sets, which does not necessarily mean that register resources exist in the processor as a set. Generally speaking, in a processor, a register set is represented by multiple registers, and the processor 100 allocates at least one of these registers as a register set to the first thread group. However, this embodiment of the present application is not limited to this, meaning that register resources in the processor may also exist in the form of register sets.

[0186] Step 220 : In response to a configuration request from a second thread group belonging to the first work group, the resource management unit reconfigures the first register set into a register set used by the second thread group.

[0187] Optionally, the first register set is reconfigured as a register set used by the second thread group, i.e., the first register set is allocated to the second thread group for use. For example, the register set used by the second thread group before the configuration request includes the second register set, the third register set, and the fourth register set. After the configuration request, the register set used by the second thread group includes the first register set, the second register set, the third register set, and the fourth register set.

[0188] Optionally, a workgroup is a unit for reconfiguring register sets in a processor. That is, it can be understood that the register sets used by all thread groups within a first workgroup are the register sets used by the first workgroup. The processor supports reconfiguring free register sets within a workgroup into register sets for a thread group.

[0189] In summary, the method provided in the embodiment of the present application supports allocating the first register set released by the first thread group to other thread groups within the same workgroup via a resource allocation unit. For example, when the second thread group belonging to the first workgroup sends a configuration request, the first register set in the first state corresponding to the first workgroup is allocated to the second thread group. On the one hand, a discrete register resource allocation method is designed, that is, register resources are divided into discrete register sets, and one or more register sets that have ended in use are supported for release at the time of release. For example, they can be released in advance before the thread group ends, avoiding the low resource utilization of register sets caused by long-term occupation of register sets during the life cycle of the thread group. On the other hand, it supports flexible circulation of register sets within the work group, so that for some tasks (such as AI computing tasks, indirect function call tasks, etc.), the expectation of lowering resource allocation can be achieved during the initial allocation, that is, fewer register sets can be allocated during the initial allocation. Since the reconfiguration of register sets within the work group is supported, when an instruction requiring a large number of register sets is executed, more register sets can be requested for the thread group through configuration requests before the instruction is executed. Compared with the traditional method of allocating more register sets during the initial allocation, the register sets released by other thread groups in the work group are obtained through configuration requests during the execution of the second thread group. This not only improves the flexibility of register set allocation, but also supports the normal operation of some tasks requiring a large number of register sets while ensuring high resource utilization.

[0190] The above shows that when the resource management unit releases the first register set, it is released into the first state, and the first state is used to indicate that the first register set supports reconfiguration to other thread groups belonging to the first work group. In addition to the first state, more states can be set for the register set to indicate relevant information about the register set in the processor, as shown below.

[0191] 1. The status of the register set.

[0192] (1) Second state.

[0193] In some embodiments, the state of the register set further includes a second state, which is used to indicate that the register set is in a working state, or in other words, the second state is used to indicate that the register set is in a busy state, or the second state is used to indicate that the register set is being used by a thread group.

[0194] In some embodiments, the above step 220 can be implemented as follows: the resource management unit reconfigures the first register set into a register set used by the second thread group in response to a configuration request of the second thread group belonging to the first work group, and reconfigures the first register set into a second state, where the second state is used to indicate that the first register set is being used by the second thread group.

[0195] Optionally, the second state is used to indicate that the first register set is being used by the second thread group, that is, the first register set has been allocated to the second thread group for use, and before the second thread group finishes using it, it is no longer supported to be allocated to other thread groups.

[0196] In some embodiments, reconfiguration is performed under certain conditions. For example, in response to a configuration request from a second thread group belonging to a first work group, the resource management unit reconfigures at least one register set to a register set used by the second thread group, and reconfigures at least one register set to a second state, if the number of first sets is greater than or equal to the number of reconfigurations, where the at least one register set includes the first register set; wherein the number of first sets is the number of register sets in the first state corresponding to the first work group, the number of reconfigurations is the number of register sets requested by the configuration request, and the number of reconfigurations is the number of at least one register set.

[0197] In other embodiments, the resource management unit responds to the configuration request of the second thread group belonging to the first work group, and when the first set number is less than the reconfiguration number, skips the configuration request of the second thread group; and polls the configuration request of the next thread group.

[0198] (2) The first state and the third state.

[0199] In some embodiments, in addition to the second state indicating a working state and the first state indicating support for reconfiguration, a third state may also exist. This third state is used to indicate that the register set has been completely released, or in other words, the third state is used to indicate that the register set supports allocation to different work groups (or thread groups) in the processor.

[0200] In some embodiments, the resource management unit releases the first register set to the first state in response to a release request from the first thread group for the first register set.

[0201] Optionally, the release request of the first thread group for the first register set is triggered when the first thread group finishes using all registers in the first register set. The request may be a read instruction or a write instruction, or other instructions (such as a release instruction).

[0202] In other embodiments, the method further includes: the resource management unit releasing the second register set to a third state in response to a release request from the first thread group for the second register set, wherein the third state is used to indicate that the second register set supports the thread group within any work group assigned to the processor.

[0203] Optionally, the third state is used to indicate that the second register set supports the thread group within any work group assigned to the processor; or, the third state is used to indicate that the current register set supports the thread group within any work group assigned to the processor; or, the third state is used to indicate that the current register set supports the thread group within any work group assigned to the processor; or, the third state is used to indicate that the current register set supports the thread group assigned to the processor.

[0204] Optionally, allocation refers to the initial allocation of register sets to a thread group when it is created. Reconfiguration, on the other hand, refers to the reconfiguration of register sets already allocated to a workgroup to other thread groups within the workgroup. In other words, register sets in the third state are typically allocated to new thread groups within an existing workgroup, or to new thread groups within a new workgroup.

[0205] Exemplarily, the resource management unit releases the first register set to a first state in response to a first release request from the first thread group for the first register set, where the first release request carries reconfiguration information, and the reconfiguration information is used to indicate whether the first register set supports reconfiguration after release.

[0206] Exemplarily, the resource management unit releases the second register set to a third state in response to a second release request from the first thread group for the second register set, where the second release request does not carry reconfiguration information, and the reconfiguration information is used to indicate whether the first register set supports reconfiguration after release.

[0207] Optionally, the reconfiguration information is used to indicate whether the first register set supports reconfiguration after being released. If the release request carries reconfiguration information, it indicates that the release request is used to request that the register set be released to the first state. If the release request does not carry reconfiguration information, it indicates that the release request is not used to request that the register set be released to the first state. If a third state exists, then if the release request does not carry reconfiguration information, it indicates that the release request is used to request that the register set be released to the third state.

[0208] For details, please refer to "1. Status of register set" in the above embodiment.

[0209] In order to better manage the register resources of each work group and thread group within the processor, some register resource related parameters can be maintained within the processor, as shown in the following figure.

[0210] 2. Parameters related to register resources.

[0211] For example, the processor may support the number of register sets that can be allocated and the number of register sets that can be reconfigured.

[0212] (1) The number of first sets.

[0213] In some embodiments, a first set quantity is maintained for each workgroup, and the first set quantity is used to indicate the number of register sets in the first state corresponding to the workgroup. For example, the first set quantity of the first workgroup is used to indicate the number of register sets in the first state corresponding to the first workgroup. The first set quantity may change when a thread group within the first workgroup releases a register set, or when a thread group is reconfigured for a register set in the first state.

[0214] Exemplarily, when the first thread group belonging to the first work group releases a register set, the resource management unit responds to the first release request of the first thread group for n register sets, adds n to the first set quantity, and obtains an updated first set quantity, where n is a positive integer, and the n register sets include the first register set. The first set quantity is used to indicate the number of register sets in the first state corresponding to the first work group.

[0215] (2) The number of the second set.

[0216] In some embodiments, a second set number is maintained for each processor, indicating the number of register sets in the third state corresponding to the processor. The second set number may change when a thread group within any work group releases a register set, or when a register set is allocated to a newly created thread group.

[0217] Exemplarily, the resource management unit responds to the second release request of the first thread group for m register sets by adding m to the number of second sets to obtain an updated number of second sets, where the m register sets include the second register set, and the second set number is used to indicate the number of register sets in the third state corresponding to the processor.

[0218] In some embodiments, the processor further includes an allocation management unit, such as Figure 2As shown. The allocation management unit determines a first quantity, which is the number of register sets required by the third thread group; subtracts the first quantity from the second quantity to obtain an updated second quantity, which is used to indicate the number of register sets in a third state corresponding to the processor, where the register sets in the third state support allocation to thread groups within any work group in the processor; the resource management unit allocates the first number of register sets to the third thread group, where the first number of register sets are register sets in the third state; and updates the state of the first number of register sets to a second state, where the second state indicates that the first number of register sets are being used by the third thread group.

[0219] (3) The number of the third set.

[0220] In some embodiments, a third set number is maintained for each thread group. The third set number is used to indicate the number of register sets currently in use by the thread group, i.e., the number of register sets in the second state corresponding to the thread group. For example, the third set number of a first thread group is used to indicate the number of register sets in the second state corresponding to the first thread group. This third set number may change when, for example, the first thread group releases a register set, a new thread group is initially allocated a register set, or a register set in the first state is reassigned to the thread group.

[0221] Exemplarily, in response to a first release request from the first thread group for n register sets, the resource management unit subtracts n from the third set quantity of the first thread group to obtain an updated third set quantity, where n is a positive integer, the n register sets include the first register set, and the third set quantity is used to indicate the number of register sets being used by the first thread group.

[0222] Exemplarily, in response to the second release request of the first thread group for m register sets, the resource management unit subtracts m from the third set quantity of the first thread group to obtain an updated third set quantity, where m is a positive integer, the m register sets include the second register set, and the third set quantity is used to indicate the number of register sets being used by the first thread group.

[0223] In some embodiments, the processor further includes an allocation management unit, such as Figure 2As shown. The allocation management unit determines a first quantity, which is the number of register sets required by the third thread group; subtracts the first quantity from the second quantity to obtain an updated second quantity, which is used to indicate the number of register sets in a third state corresponding to the processor, where the register sets in the third state support allocation to thread groups within any work group in the processor; the resource management unit allocates the first number of register sets to the third thread group, where the first number of register sets are register sets in the third state; and updates the state of the first number of register sets to a second state, where the second state indicates that the first number of register sets are being used by the third thread group.

[0224] Optionally, when the resource management unit allocates the first number of register sets to the third thread group, the resource management unit is configured to update the third set quantity of the third thread group to the first number, thereby obtaining an updated third set quantity, where the third set quantity is used to indicate the number of register sets currently in use by the third thread group. That is, the third set quantity is initialized when the resource management unit allocates register sets to the third thread group.

[0225] In some embodiments, the resource management unit reconfigures k register sets into register sets used by the second thread group in response to a configuration request of the second thread group; and adds k to the third set quantity of the second thread group to obtain an updated third set quantity.

[0226] (4) Number of active thread groups.

[0227] In some embodiments, each work group includes at least one thread group. When all thread groups in the work group have been executed, the work group and the register set of the first state corresponding to the work group can be released, thereby avoiding the problem that the work group without active thread groups occupies the register set for a long time, resulting in reduced resource utilization. Therefore, an active thread group number can be maintained for each work group, so as to determine when to release the work group and the register set of the first state corresponding to the work group according to the change in the number of active thread groups. The number of active thread groups is used to indicate the number of thread groups in the work group that are in a working state, or the number of active thread groups is used to indicate the number of thread groups that have not yet ended in the work group. For example, the number of active thread groups corresponding to the first work group is used to indicate the number of thread groups in a working state in the first work group. Specifically, the number of active thread groups will change when thread groups are assigned to the work group, when thread groups are no longer used, etc.

[0228] Exemplarily, in response to the termination of the fourth thread group in the first work group, the resource management unit reduces the number of active thread groups corresponding to the first work group by one to obtain an updated number of active thread groups, where the number of active thread groups is used to indicate the number of thread groups in working state in the first work group.

[0229] Optionally, the processor further maintains a mapping relationship between workgroups and thread groups. For example, when a third thread group is assigned to a first workgroup, the resource management unit determines a mapping relationship between the identifier of the first workgroup and the identifier of the third thread group. When the fourth thread group in the first workgroup is no longer in use, the resource management unit is configured to delete or cancel the mapping relationship between the identifier of the first workgroup and the identifier of the third workgroup.

[0230] Exemplarily, the processor further includes an allocation management unit, such as Figure 2 As shown. When the number of active thread groups in the first workgroup is zero, the resource management unit determines the first set number of the first workgroup, and updates the state of the register set corresponding to the first workgroup from the first state to the third state, where the number of active thread groups indicates the number of thread groups in the first workgroup that are in a working state, and the first register number is the number of register sets in the first state corresponding to the first workgroup; sends the first set number to the allocation management unit; and the allocation management unit adds the second set number to the first set number to obtain an updated second set number, where the second set number is the number of register sets in the third state corresponding to the processor.

[0231] For details, please refer to "2. Related parameters of register resources" in the above embodiment, which will not be repeated here.

[0232] In some embodiments, the plurality of registers 110 are a plurality of vector registers; or, the plurality of registers 110 are a plurality of scalar registers.

[0233] It should be noted that the embodiments of the present application do not limit the types of registers in the processor, and the above-mentioned vector registers and scalar registers are only for illustration. In actual scenarios, the methods provided in the embodiments of the present application also support the allocation, release, and reconfiguration of other types of registers. The scope of protection of the embodiments of the present application is not limited to this.

[0234] Please refer to Figure 8 , which shows a block diagram of the register allocation device provided by an exemplary embodiment of the present application. This device has the functionality to implement the aforementioned register allocation method example. This functionality can be implemented by hardware, or by hardware executing corresponding software. This device can be the processor described above, or it can be provided within a processor. This device can include: a resource management module 410.

[0235] a resource management module 410 configured to release a first register set to a first state when a first thread group belonging to a first work group has finished using the first register set, the first register set including at least one register from the plurality of registers, the first state being configured to indicate that the first register set supports reconfiguration to other thread groups belonging to the first work group; The resource management module 410 is configured to reconfigure the first register set into a register set used by the second thread group in response to a configuration request from the second thread group belonging to the first work group.

[0236] In some embodiments, the resource management module 410 is used to reconfigure the first register set into a register set used by the second thread group in response to a configuration request of the second thread group belonging to the first work group, and to reconfigure the first register set into a second state, wherein the second state is used to indicate that the first register set is being used by the second thread group.

[0237] In some embodiments, the resource management module 410 is configured to, in response to a configuration request from a second thread group belonging to the first work group, reconfigure at least one register set to a register set used by the second thread group if the first set quantity is greater than or equal to the reconfiguration quantity, and reconfigure the at least one register set to a second state, the at least one register set including the first register set; The first set quantity is the quantity of register sets in the first state corresponding to the first working group, the reconfiguration quantity is the quantity of register sets requested by the configuration request, and the reconfiguration quantity is the quantity of the at least one register set.

[0238] In some embodiments, the resource management module 410 is configured to release the first register set to the first state in response to a release request from the first thread group for the first register set.

[0239] In some embodiments, the resource management module 410 is used to release the first register set to the first state in response to a first release request from the first thread group for the first register set, wherein the first release request carries reconfiguration information, and the reconfiguration information is used to indicate whether the first register set supports reconfiguration after release.

[0240] In some embodiments, the resource management module 410 is used to release the second register set to a third state in response to a release request from the first thread group for the second register set, wherein the third state is used to indicate that the second register set supports the thread group within any work group assigned to the processor.

[0241] In some embodiments, the resource management module 410 is used to release the second register set to the third state in response to a second release request from the first thread group for the second register set, wherein the second release request does not carry reconfiguration information, and the reconfiguration information is used to indicate whether the second register set supports reconfiguration after release.

[0242] In some embodiments, the resource management module 410 is used to respond to a first release request from the first thread group for the n register sets by adding n to the first set quantity to obtain an updated first set quantity, where n is a positive integer, and the n register sets include the first register set, and the first set quantity is used to indicate the number of register sets in the first state corresponding to the first working group.

[0243] In some embodiments, the resource management module 410 is used to respond to a second release request of the first thread group for the m register sets, add m to the second set quantity to obtain an updated second set quantity, where m is a positive integer, and the m register sets include a second register set, and the second set quantity is used to indicate the quantity of register sets in the third state corresponding to the processor.

[0244] In some embodiments, the resource management module 410 is used to respond to a first release request from the first thread group for the n register sets by subtracting n from the third set quantity of the first thread group to obtain an updated third set quantity, where n is a positive integer, the n register sets include the first register set, and the third set quantity is used to indicate the number of register sets being used by the first thread group.

[0245] In some embodiments, the resource management module 410 is used to, in response to the second release request of the first thread group for the m register sets, subtract m from the third set quantity of the first thread group to obtain an updated third set quantity, where m is a positive integer, the m register sets include the second register set, and the third set quantity is used to indicate the number of register sets being used by the first thread group.

[0246] In some embodiments, the apparatus further comprises an allocation management module; an allocation management module, configured to determine a first quantity, the first quantity being the number of register sets required by a third thread group; and subtract the first quantity from a second set quantity to obtain an updated second set quantity, the second set quantity being used to indicate the number of register sets in a third state corresponding to the processor, the register sets in the third state supporting allocation to thread groups within any work group in the processor; The resource management module 410 is configured to allocate the first number of register sets to the third thread group, where the first number of register sets are register sets in the third state; and update the state of the first number of register sets to a second state, where the second state is configured to indicate that the first number of register sets are being used by the third thread group.

[0247] In some embodiments, the resource management module 410 is configured to increase the number of active thread groups corresponding to the first work group by one to obtain an updated number of active thread groups, where the number of active thread groups indicates the number of thread groups in working state in the first work group.

[0248] In some embodiments, the resource management module 410 is configured to add a mapping relationship between each register set in the first number of register sets and the third thread group to a register management mapping table.

[0249] In some embodiments, the resource management module 410 is configured to update the third set quantity of the third thread group to the first quantity to obtain an updated third set quantity, where the third set quantity is used to indicate the number of register sets being used by the third thread group.

[0250] In some embodiments, the resource management module 410 is configured to determine a mapping relationship between the identifier of the first work group and the identifier of the third thread group.

[0251] In some embodiments, the resource management module 410 is used to, in response to the end of the fourth thread group in the first work group, reduce the number of active thread groups corresponding to the first work group by one to obtain an updated number of active thread groups, where the number of active thread groups is used to indicate the number of thread groups in working state in the first work group.

[0252] In some embodiments, the resource management module 410 is configured to, when the number of active thread groups in the first workgroup is zero, determine a first set number of the first workgroup, and update a state of a register set corresponding to the first workgroup from the first state to a third state, wherein the number of active thread groups indicates the number of thread groups in the first workgroup that are in a working state, and the first register number is the number of register sets in the first state corresponding to the first workgroup; and send the first set number to the allocation management module; The allocation management module is configured to add the second set quantity to the first set quantity to obtain an updated second set quantity, where the second set quantity is the quantity of the register set in the third state corresponding to the processor.

[0253] In some embodiments, the plurality of registers are a plurality of vector registers; or, the plurality of registers are a plurality of scalar registers.

[0254] On the other hand, an embodiment of the present application provides a graphics card, which includes the processor described in the above embodiments.

[0255] In another aspect, embodiments of the present application provide a computer device comprising the aforementioned processor. The computer device may be at least one of a portable computer, a desktop computer, a server, a server cluster, an artificial intelligence (AI) computing cluster, and a cloud computing cluster. The AI ​​computing cluster may also be referred to as an intelligent computing cluster or a smart computing cluster.

[0256] It should be understood that the "multiple" mentioned in this article refers to two or more. The character " / " generally indicates that the objects associated with each other are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution order between the steps. In some other embodiments, the above steps may also be executed in a non-numbered order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the opposite order to that shown in the figure. This embodiment of the application is not limited to this.

[0257] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A processor, characterized in that: The processor includes a plurality of registers and a resource management unit; the resource management unit being configured to release a first register set to a first state when a first thread group belonging to a first work group has finished using the first register set, the first state being configured to indicate that the first register set supports reconfiguration to other thread groups belonging to the first work group, the first register set including at least one register among the plurality of registers; The resource management unit is configured to reconfigure the first register set into a register set used by the second thread group in response to a configuration request from the second thread group belonging to the first work group.

2. The processor according to claim 1, wherein: The resource management unit is configured to, in response to a configuration request of a second thread group belonging to the first work group, reconfigure the first register set into a register set used by the second thread group, and reconfigure the first register set into a second state, wherein the second state is used to indicate that the first register set is being used.

3. The processor according to claim 2, wherein: the resource management unit being configured to, in response to a configuration request of a second thread group belonging to the first work group, reconfigure at least one register set into a register set used by the second thread group when the number of first sets is greater than or equal to the number of reconfigurations, and reconfigure the at least one register set into a second state, the at least one register set including the first register set; The first set quantity is the number of register sets in the first state corresponding to the first working group, the reconfiguration quantity is the number of register sets requested by the configuration request, and the number of the at least one register set is equal to the reconfiguration quantity.

4. The processor according to any one of claims 1 to 3, characterized in that: The resource management unit is configured to release the first register set to the first state in response to a release request from the first thread group for the first register set.

5. The processor according to claim 4, wherein: The resource management unit is used to release the first register set to the first state in response to a first release request from the first thread group for the first register set, wherein the first release request carries reconfiguration information, and the reconfiguration information is used to indicate that the register indicated by the release request supports release to the first state.

6. The processor according to any one of claims 1 to 3, characterized in that: The resource management unit is configured to release the second register set to a third state in response to a release request from the first thread group for the second register set, wherein the third state is configured to indicate that the second register set supports a thread group allocated to any work group in the processor.

7. The processor according to claim 6, wherein: The resource management unit is configured to release the second register set to the third state in response to a second release request from the first thread group for the second register set, wherein the second register set includes at least one register among the multiple registers, and the second register set and the first register set are register sets allocated to the first thread group. The second release request does not carry reconfiguration information, and the reconfiguration information is used to indicate that the register indicated by the release request supports release to the first state.

8. The processor according to claim 5, wherein: The resource management unit is used to respond to the first release request of the first thread group for n register sets, add n to the first set quantity to obtain an updated first set quantity, where n is a positive integer, and the n register sets include the first register set. The first set quantity is used to indicate the number of register sets in the first state corresponding to the first working group.

9. The processor according to claim 7, wherein: The resource management unit is used to respond to the second release request of the first thread group for m register sets, add m to the second set quantity to obtain an updated second set quantity, where m is a positive integer, and the m register sets include the second register set, and the second set quantity is used to indicate the quantity of register sets in the third state corresponding to the processor.

10. The processor according to claim 5, wherein: The resource management unit is used to, in response to a first release request for n register sets by the first thread group, subtract n from the third set quantity of the first thread group to obtain an updated third set quantity, where n is a positive integer, the n register sets include the first register set, and the third set quantity is used to indicate the number of register sets being used by the first thread group.

11. The processor according to claim 7, wherein: The resource management unit is configured to, in response to a second release request from the first thread group for m register sets, subtract m from the third set quantity of the first thread group to obtain an updated third set quantity, where m is a positive integer, the m register sets include the second register set, and the third set quantity is used to indicate the number of register sets being used by the first thread group.

12. The processor according to any one of claims 1 to 3, characterized in that: The processor further includes an allocation management unit; The allocation management unit is configured to determine a first quantity, the first quantity being the number of register sets required by the third thread group; subtract the first quantity from the second set quantity to obtain an updated second set quantity, the second set quantity being used to indicate the number of register sets in a third state corresponding to the processor, the register sets in the third state supporting allocation to the thread group within any work group in the processor; The resource management unit is configured to allocate the first number of register sets to the third thread group, where the first number of register sets are register sets in the third state; and update the state of the first number of register sets to a second state, where the second state is used to indicate that the first number of register sets are being used.

13. The processor according to claim 12, wherein: The resource management unit is configured to increase the number of active thread groups corresponding to the first work group by one to obtain an updated number of active thread groups, where the number of active thread groups indicates the number of thread groups in working state in the first work group.

14. The processor according to claim 12, wherein: The resource management unit is configured to add a mapping relationship between each register set in the first number of register sets and the third thread group to a register management mapping table.

15. The processor according to claim 12, wherein: The resource management unit is configured to update the third set quantity of the third thread group to the first quantity to obtain an updated third set quantity, where the third set quantity is used to indicate the quantity of register sets being used by the third thread group.

16. The processor according to claim 12, wherein: The resource management unit is configured to determine a mapping relationship between the identifier of the first work group and the identifier of the third thread group.

17. The processor according to any one of claims 1 to 3, characterized in that: The resource management unit is configured to, in response to the termination of the fourth thread group in the first work group, reduce the number of active thread groups corresponding to the first work group by one to obtain an updated number of active thread groups, where the number of active thread groups is used to indicate the number of thread groups in a working state in the first work group.

18. The processor according to any one of claims 1 to 3, characterized in that: The processor further includes an allocation management unit; the resource management unit being configured to, when the number of active thread groups in the first work group is zero, determine a first set number of the first work group, and update a state of a register set corresponding to the first work group from the first state to a third state, wherein the number of active thread groups indicates the number of thread groups in a working state in the first work group, and the first register number is the number of register sets in the first state corresponding to the first work group; sending the first set quantity to the allocation management unit; The allocation management unit is configured to add the second set quantity to the first set quantity to obtain an updated second set quantity, where the second set quantity is the quantity of the register set in the third state corresponding to the processor.

19. The processor according to any one of claims 1 to 3, characterized in that: The plurality of registers are a plurality of vector registers; or, the plurality of registers are a plurality of scalar registers.

20. A graphics card, characterized in that: The graphics card includes the processor according to any one of claims 1 to 19.

21. A computer device, characterized in that: The computer device comprises the processor according to any one of claims 1 to 19.

22. A register allocation method, characterized in that: The method is executed by the processor according to any one of claims 1 to 19, wherein the processor comprises a plurality of registers and a resource management unit; The method comprises: The resource management unit releases a first register set to a first state when a first thread group belonging to a first work group finishes using the first register set, the first state being used to indicate that the first register set supports reconfiguration to other thread groups belonging to the first work group, the first register set including at least one register of the plurality of registers; The resource management unit reconfigures the first register set into a register set used by the second thread group in response to a configuration request of the second thread group belonging to the first work group.

23. A register allocation device, characterized in that: The device comprises: a resource management module, configured to release a first register set to a first state when a first thread group belonging to a first work group has finished using the first register set, the first state being configured to indicate that the first register set supports reconfiguration to other thread groups belonging to the first work group, the first register set including at least one register from a plurality of registers; The resource management module is configured to reconfigure the first register set into a register set used by the second thread group in response to a configuration request from the second thread group belonging to the first work group.

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