A DSP-oriented VLIW scheduling and packing method

Abstract

The application discloses a DSP-oriented VLIW scheduling and packing method, which comprises the following steps: step 1, performing an LLVM IR optimization PASS sequence; step 2, constructing an instruction dependency graph (IDG); step 3, scheduling and packing before register allocation according to the global IDG; and step 4, reconstructing the IDG according to a register allocation result, and then scheduling and packing after the register allocation according to the reconstructed IDG. The application discloses a detailed IDG based on an SSA format, reveals potential parallelism between instructions, allows a compiler to identify opportunities for parallel execution at an earlier stage, avoids the parallelism loss problem introduced by the traditional method in the post-register allocation packing, and significantly improves the execution efficiency of a program on a DSP platform.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of compiler optimization, and particularly relates to a VLIW scheduling and packaging method for DSP. BACKGROUND

[0002] In digital signal processing (DSP), a very long instruction word (VLIW) architecture has become an important means to improve processing performance and optimize energy efficiency. The core advantage of the VLIW architecture lies in its ability to execute multiple operations simultaneously in each clock cycle, which greatly improves the execution speed of DSP applications. In addition, the VLIW architecture transfers the management of instruction-level parallelism from the hardware layer to the compiler layer, enabling static scheduling of independent instructions. This not only reduces the complexity of hardware design, but also reduces energy consumption and improves the performance per watt of the processor, significantly improving the energy efficiency ratio. The design concept of the VLIW architecture is based on its high customizability and reliance on compiler optimization strategies, allowing the processor to flexibly adapt to evolving application requirements while strictly meeting real-time requirements, which is crucial for the performance of modern electronic devices.

[0003] Although the VLIW architecture brings convenience in hardware design, it faces a series of complex challenges in the design and implementation of the compiler. On the one hand, the compiler not only has to handle complex instruction scheduling problems, but also has to efficiently allocate resources and fill instruction slots to ensure that the parallel execution capability of the processor is fully utilized. On the other hand, in the VLIW architecture, the compiler faces the task of statically allocating operations to processor functional units at compile time, which includes determining the transfer direction of branches and representing as many operations as possible within the limited coding space. These tasks pose high requirements on the performance and efficiency of the compiler. On the other hand, because all instruction flows must be determined at compile time, the static nature of the VLIW architecture limits the possibility of dynamic code adjustment and optimization, which requires the compiler to make more in-depth global optimization decisions during the compilation process to fully exploit the parallelism between instructions and maximize the performance of the VLIW processor.

[0004] In existing compiler technology, mainstream compilers such as GCC and LLVM use a method of VLIW packaging after register allocation. This method avoids considering register pressure during packaging, thereby simplifying the implementation process of VLIW packaging. However, instruction packaging after register allocation causes dependencies between instructions that were originally independent, such as if two originally independent instructions are allocated to the same register during register allocation, which prevents them from being executed simultaneously, reducing the parallelism of the processor. SUMMARY

[0005] In view of the deficiencies of the prior art, the purpose of the present application is to provide a DSP-oriented VLIW scheduling and packaging method, which improves the execution efficiency of the code on the DSP program.

[0006] In order to achieve the above-mentioned purpose, the present application adopts the following technical solutions to achieve it:

[0007] A DSP-oriented VLIW scheduling and packaging method, comprising the following steps:

[0008] Step 1, execute the sequence of LLVM IR optimization PASS;

[0009] Step 2, build an instruction dependency graph IDG, and the specific process is:

[0010] Step 2.1, input the SSA format instruction Function after instruction selection;

[0011] Step 2.2, traverse all basic blocks in the SSA format instruction Function;

[0012] Step 2.3, define the basic block as a set of sequentially executed instructions, and if the execution of one basic block can directly jump to another basic block, a directed edge is added between the two basic blocks;

[0013] Step 2.4, build a sequential directed edge for the instructions in the basic block;

[0014] Step 2.5, after traversing all basic blocks, delete the unreachable basic blocks and merge the continuously executed basic blocks to generate a control flow graph CFG;

[0015] Step 2.6, traverse each basic block in the flow graph CFG;

[0016] Step 2.7, do dependency analysis according to the information operation, operand and destination identifier contained in the SSA instruction;

[0017] Step 2.8, first create an empty IDG for each basic block, and then start traversing from the first instruction of the basic block;

[0018] Step 2.9, for each instruction traversed, check whether it produces an output, if yes, execute step 2.10, if not, execute step 2.11;

[0019] Step 2.10, find and record all subsequent instructions that directly depend on the output, and build a directed edge for these relationships in the IDG, from the instruction that produces the output to the instruction that uses the output;

[0020] Step 2.11, the instruction without output is regarded as a node without out-degree, and the next instruction of the control flow thereof is in the same level;

[0021] Step 2.12, after each instruction is completed, it is judged whether the current basic block is traversed completely, if yes, it indicates that the analysis of all instructions in the basic block is completed, then step 2.13 is executed, if not, it jumps to step 2.8 to continue the execution;

[0022] Step 2.13, the instruction dependence graph IDG is outputted;

[0023] Step 2.14, after the instruction dependence graph IDG of each basic block is outputted, the control flow graph CFG is updated, and the basic block currently traversed is marked as having been constructed;

[0024] Step 2.15, it is judged whether the CFG graph is traversed completely, if not, it jumps to step 2.6 to continue to traverse the next basic block according to the flow direction of the CFG, and the same process is repeated until all basic blocks in the CFG are processed, if yes, step 2.16 is executed;

[0025] Step 2.16, the instruction dependence graphs IDG of the respective basic blocks are combined into a global instruction dependence graph IDG;

[0026] Step 3, according to the global instruction dependence graph IDG, the scheduling and packing before register allocation are performed;

[0027] Step 4, according to the register allocation result, the instruction dependence graph IDG is reconstructed, and the scheduling and packing after register allocation are performed according to the reconstructed instruction dependence graph IDG.

[0028] Further, the PASS execution order of step 1 is: dead code elimination, execution constant propagation, inline expansion, loop optimization and dead code elimination.

[0029] Further, the loop optimization includes loop unrolling and loop merging.

[0030] Further, step 3 specifically includes the following steps:

[0031] Step 3.1, a first free instruction without predecessor node is selected from the global instruction dependence graph IDG as a seed node, and the seed node is taken as a starting point of the packing process;

[0032] Step 3.2, according to the global instruction dependence graph IDG, the remaining free instructions are selected to construct a free instruction list;

[0033] Step 3.3, the instructions in the free instruction list which have not been packed and do not exist the dependence relationship with the seed node are taken as packable instructions, and the instructions are added to a packing instruction list.

[0034] Step 3.4, calculate the score of the packable instruction;

[0035] Step 3.5, after calculating the score of one packable instruction, determine whether the free instruction list is traversed, if not, return to step 3.2, if yes, execute step 3.6;

[0036] Step 3.6, determine whether the packable instruction list is empty, if yes, it means that the current seed node cannot be parallel with the remaining instructions, then it will be packed alone, if not, execute step 3.7;

[0037] Step 3.7, select the instruction with the highest score in the packable instruction list as the candidate instruction;

[0038] Step 3.8, update the packable instruction list, mark the instruction with the highest current score as packed;

[0039] Step 3.9, evaluate the feasibility of allocating functional units through the sensing function unit pressure, if the functional units cannot be allocated, jump to step 3.7, otherwise, execute step 3.10;

[0040] Step 3.10, determine whether the length of the packed data packet exceeds the number of hardware inherent execution units, if not, execute step 3.11, if yes, return to step 3.7;

[0041] Step 3.11, pack the packable instructions, complete the creation of one data packet;

[0042] Step 3.12, after completing the creation of one data packet, make a judgment on the register pressure, if the data packet causes excessive register allocation pressure, jump to step 3.1, otherwise, execute step 3.13;

[0043] Step 3.13, delete the confirmed packable instructions from the global instruction dependency graph IDG to obtain the updated global instruction dependency graph IDG.

[0044] Further, the formula for calculating the score of the packable instruction in step 3.4 is:

[0045] Score=w×Suc_Nodes-(1-w)×(Inst_Distance+|Max_Slot-Inst_Slot|)

[0046] In the formula, Suc_Nodes represents the number of instruction successor nodes, Inst_Distance represents the distance of the instruction relative to the entry node, Max_Slot represents the longest delay of the instructions in the current data packet, Inst_Slot represents the current instruction delay, the absolute value of the difference between Max_Slot and Inst_Slot represents the matching degree of the total delay of the current instruction and the instructions in the data packet, and w is a weight.

[0047] Further, the specific process of reconstructing the instruction dependency graph IDG according to the register allocation result in step 4 is that the instructions after register allocation are input, and then the instruction dependency graph is reconstructed according to steps 2.2-2.16.

[0048] Further, the scheduling and packing process after register allocation according to the reconstructed instruction dependency graph IDG in step 4 is steps 3.1-3.13.

[0049] Compared with the prior art, the present application has the following technical effects:

[0050] The present application adopts the instruction set based on the static single assignment (SSA) format to construct the instruction dependency graph (IDG), and the IDG discloses the dependency relationship between instructions, so that the compiler can more accurately understand the structure and behavior of the program code before register allocation, thereby performing effective instruction scheduling and packing before register allocation, and using the constructed dependency graph, the compiler can identify the opportunity of parallel execution in advance, thereby generating a more compact and efficient machine instruction sequence, optimizing the execution order of instructions, reducing unnecessary operations, avoiding the parallelism loss problem introduced by the traditional method after packing after register allocation, and improving the execution efficiency of the code on the DSP.

[0051] The present application improves the running speed of the program by reducing the empty operations and invalid instructions in the code and optimizing the parallel execution degree of the instructions, thereby significantly improving the execution efficiency and performance of the machine code generated by the compiler. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1 The overall flowchart of the present application is shown in the figure;

[0053] Figure 2 The PASS sequence of the present application optimized on the LLVM IR is shown in the figure;

[0054] Figure 3 The flowchart of constructing the instruction dependency graph (IDG) of the present application is shown in the figure;

[0055] Figure 4 The SSA instruction and its IDG diagram example of the present application are shown in the figure;

[0056] Figure 5This is a flowchart of the instruction packaging algorithm of the present invention. Detailed Implementation

[0057] The specific content of the present invention will be further explained in detail below with reference to the embodiments.

[0058] like Figure 1 As shown, a VLIW scheduling and packaging method for DSP includes the following steps:

[0059] Step 1: Optimize the PASS execution order in LLVM IR, such as... Figure 2 As shown, the optimized PASS execution order is: dead code elimination, execution constant propagation, inline unrolling, loop optimization, and dead code elimination. This general PASS enhances the performance of subsequent VLIW (Very Long Instruction Word) packing. The specific process is as follows:

[0060] Step 1.1: Perform Dead Code Elimination (DCE) to remove obviously invalid code and simplify subsequent optimization steps.

[0061] Step 1.2: Perform constant propagation. Since some constant values ​​become more obvious after the removal of invalid code, they can be propagated. Therefore, constant propagation is performed after dead code elimination.

[0062] Step 1.3: Performing inline expansion helps to further uncover optimization opportunities, such as constant propagation and further dead code elimination, while also preparing more context for loop unrolling and other loop optimizations.

[0063] Step 1.4: Perform loop optimization, including loop unrolling and loop merging. Loop optimization is usually performed after inlining because the overhead of function calls has been reduced at this time, so the compiler has more information to optimize the loop structure. Loop optimization, such as reducing the number of loop iterations and improving the efficiency of each iteration, lays a solid foundation for deep instruction-level parallel processing.

[0064] Step 1.5: Perform dead code elimination. Due to the optimization steps in Steps 1.1 to 1.4, especially loop optimization, new unreachable code may be introduced or some code may become redundant. Therefore, dead code elimination needs to be performed again to remove invalid code.

[0065] Step 2: Construct the instruction dependency graph (IDG), such as Figure 3As shown, first construct a control flow graph CFG for each basic block in the program, the process starts from analyzing the structure of the program to identify the control flow relationship between basic blocks, and then according to the control flow graph CFG, construct the instruction dependency graph IDG, the specific process is:

[0066] Step 2.1, input the SSA format instruction Function after instruction selection;

[0067] Step 2.2, traverse all basic blocks in the SSA format instruction Function;

[0068] Step 2.3, define a basic block as a set of sequentially executed instructions, which starts from an entry point and ends when a control flow changing instruction (branch or jump) is encountered, specifically, if the execution of a basic block can directly jump to another basic block, a directed edge is added between the two basic blocks;

[0069] Step 2.4, within a basic block, the control flow relationship is sequential, except for branches at the entry and exit of the basic block, the instructions within the basic block are executed in the order they appear in the program, and sequential directed edges are constructed for the instructions within the basic block;

[0070] Step 2.5, after traversing all basic blocks, delete unreachable basic blocks and merge consecutive basic blocks to generate the control flow graph CFG;

[0071] Step 2.6, according to the output control flow graph CFG, traverse each basic block in the control flow graph CFG in the process of constructing the instruction dependency graph IDG;

[0072] Step 2.7, according to the information contained in the SSA instruction, operation, operand, and destination identifier, do dependency analysis, specifically, as shown in the first instruction of the SSA instruction, sub is a specific operation, %reg1 and %reg2 are operands, and %reg3 is a destination identifier; Figure 4

[0073] Step 2.8, first create an empty IDG for each basic block, and then traverse each instruction from the first instruction of the basic block;

[0074] Step 2.9, for each instruction traversed, check whether it produces an output (e.g., writes to a register or memory), if yes, execute step 2.10, if no, execute step 2.11;

[0075] Step 2.10, find and record all subsequent instructions that directly depend on the output, and construct directed edges for these relationships in the IDG, pointing from the instruction that produces the output to the instruction that uses the output;

[0076] ​Step 2.11, the instruction without output is regarded as a part of the basic block logic sequence, but does not directly participate in the data dependency construction, but is regarded as a node without out-degree, and is at the same level as the next instruction of its control flow;

[0077] Step 2.12, after each instruction is completed, it is judged whether the current basic block is completed, if yes, it indicates that the analysis of all instructions in the basic block is completed, then step 2.13 is executed, if no, it jumps to step 2.8 to continue to execute;

[0078] Step 2.13, the instruction dependency graph IDG is outputted;

[0079] Step 2.14, after the instruction dependency graph IDG of each basic block is outputted, the control flow graph CFG is updated, and the current traversed basic block is marked as having been constructed;

[0080] Step 2.15, it is judged whether the CFG graph is completed, if no, it jumps to step 2.6 to continue to traverse the next basic block according to the flow direction of the CFG, and the same process is repeated until all basic blocks in the CFG are processed, if yes, step 2.16 is executed;

[0081] Step 2.16, the instruction dependency graphs IDG of various basic blocks are combined into a global instruction dependency graph IDG;

[0082] The global instruction dependency graph IDG accurately represents the instruction dependency relationship of the entire program, including the data flow and control flow across the basic blocks, and provides dependency information for the subsequent VLIW stage, according to the constructed global instruction dependency graph IDG, the instructions that can be executed in parallel and the instructions that must be executed in a specific order can be accurately identified, such as Figure 4 As shown in the figure, the solid line represents the dependency between two instructions, and the dashed line represents the control flow relationship between the instructions, through analysis, taking the first seed (i.e. vertex 1, which is the first instruction in the critical path) as an example, 1 and 4 cannot be packaged together due to the dependency relationship, but 1 can be packaged with 2 and 3, according to the control flow relationship, the packaging algorithm continues to traverse down to explore the packaging opportunity between 4 and 5 and 6, because 5 and 4 have no dependency, therefore 5 can be packaged with 4, but there is a dependency between 5 and 6, so 6 is executed alone;

[0083] Step 3, according to the global instruction dependency graph IDG, the scheduling and packaging before register allocation are performed, as shown in Figure 5 The specific process is as follows:

[0084] Step 3.1, select the first free instruction without predecessor (i.e. without other instruction dependencies) from the global instruction dependency graph IDG as a seed node, which is neither dependent nor independent, representing an instruction that can be executed immediately;

[0085] Step 3.2, select the remaining free instructions according to the global instruction dependency graph IDG, and construct all selected free instructions into a free instruction list;

[0086] Step 3.3, add the instructions in the free instruction list that have not been packaged and do not have a dependency relationship with the seed node to the package instruction list as packageable instructions;

[0087] Step 3.4, calculate the packageable instruction score, the formula is:

[0088] Score = w x Suc_Nodes - (1-w) x (Inst_Distance + |Max_Slot-Inst_Slot|)

[0089] The instruction score is determined by four attributes, where: Suc_Nodes represents the number of successor nodes of the instruction, which has a positive effect on the score, instructions with more successor nodes have more near dependencies, so when the seed node is an upper node or a same layer node, the instruction is preferred, reducing the impact on subsequent packaging; Inst_Distance represents the distance of the instruction relative to the entry node, which has a negative effect on the score, instructions that are relatively far from the entry node have longer dependency chains, and have a greater impact on subsequent packaging, compared to those nearby, independent instructions; Max_Slot represents the longest delay of the instructions in the current package, Inst_Slot represents the current instruction delay, and the absolute value of the difference between Max_Slot and Inst_Slot represents the matching degree of the total delay of the current instruction and the instructions in the data package, which has a negative effect on the score, therefore, in order to improve the running efficiency of the packaged instructions, the absolute value should be as small as possible, in addition, a weight parameter w is introduced, through multiple tests, a suitable weight parameter w is determined according to experience;

[0090] Step 3.5, after calculating the score of each packageable instruction, determine whether the free instruction list has been traversed, if not, return to step 3.2, if yes, execute step 3.6;

[0091] Step 3.6, when the free instruction list is empty, determine whether the packageable instruction list is empty, if yes, it means that the current seed node cannot be parallel with the remaining instructions, then package it separately, if not, execute step 3.7;

[0092] Step 3.7, select the instruction with the highest score in the packable instruction list as a candidate instruction, and update the highest score instruction;

[0093] Step 3.8, update the packable instruction list, and mark the instruction with the highest current score as packed;

[0094] Step 3.9, after adding the candidate instruction, evaluate the feasibility of assigning a functional unit through the perception function unit pressure, if the register pressure is too large to assign a functional unit, jump to step 3.7, otherwise, execute step 3.10;

[0095] Step 3.10, judge whether the length of the packed data packet exceeds the limit, there is a fixed number of execution units in hardware design, each execution unit executes one instruction in each clock cycle, if an instruction word exceeds the upper limit of the number of instructions that can be executed in parallel by hardware in one cycle, then the instruction word cannot be completely executed in parallel by hardware, therefore, if the result is no, execute step 3.11, if yes, return to step 3.7;

[0096] Step 3.11, pack the packable instructions into a data packet;

[0097] Step 3.12, after completing the creation of each data packet, judge the register pressure, if the data packet causes excessive register allocation pressure, jump to step 3.1, otherwise, execute step 3.13;

[0098] As shown in Figure 4 , when instructions 1, 2, and 3 are packed, 4 and 5 are packed, but 4 and 5 packing causes register pressure, then back to before 4 and 5 packing, execute 4 alone, and then pack 5; again, judge the register pressure, if there is no excessive register pressure, continue to pack, if there is excessive register pressure, take out 5 alone, repeat the above process, and judge the register pressure after each packing;

[0099] Step 3.13, delete the confirmed packable instructions from the global instruction dependency graph IDG, and obtain an updated global instruction dependency graph IDG;

[0100] Step 4, reconstruct the instruction dependency graph IDG according to the register allocation result, and perform scheduling and packing after register allocation according to the reconstructed instruction dependency graph IDG;

[0101] After the register allocation is completed, the algorithm inputs the instructions after register allocation according to the latest register allocation, and reconstructs the instruction dependency graph IDG according to steps 2.2-2.16, which fully considers the actual register allocation result to ensure that the subsequent packing decision is based on the most accurate dependency information. After the graph construction is completed, the algorithm follows the same packing principle as the scheduling and packing process before register allocation in steps 3.1-3.13 to determine the new packing starting point, traverse the free instructions, select the candidate instructions, and perform scheduling and packing after register allocation according to the calculated score (which comprehensively considers the weight, penalty, and register pressure influence). After each packing, the influence of the current packing scheme on the register pressure is evaluated. If the register pressure is too high, the initial state of the instruction packing in the group is revoked, the first instruction is executed alone, and the subsequent instructions are repacked and reevaluated for register pressure. Once it is confirmed that the instruction packing in the group will not cause excessive register pressure, the packing scheme is confirmed, and the same packing and evaluation process is applied to the subsequent instructions.

[0102] The embodiment fully utilizes the dependency relationship between instructions, considers factors such as register allocation pressure, available functional unit pressure, and instruction packing restrictions, uses instruction dependency graph construction and feedback mechanisms, generates assembly instructions optimized by instruction scheduling, and improves the parallelism of instructions to alleviate the parallelism loss problem caused by instruction packing after register allocation, and improves the execution efficiency of programs on the current DSP VLIW architecture.

Claims

1. A DSP-oriented VLIW scheduling and packing method, characterized by, Comprising the following steps: Step 1, the execution order of LLVM IR optimization PASS; Step 2, build the instruction dependency graph IDG, the specific process is: Step 2.1, input the SSA format instruction Function after instruction selection; Step 2.2, traverse all basic blocks in the SSA format instruction Function; Step 2.3, define the basic block as a set of sequentially executed instructions, if the execution of one basic block can directly jump to another basic block, add a directed edge between the two basic blocks; Step 2.4, build the sequential directed edge of the instructions in the basic block; Step 2.5, after traversing all basic blocks, delete the unreachable basic blocks and merge the continuously executed basic blocks to generate the control flow graph CFG; Step 2.6, traverse each basic block in the control flow graph CFG; Step 2.7, do dependency analysis according to the information operation, operand and destination identifier contained in the SSA instruction; Step 2.8, first create an empty IDG for each basic block, and then traverse each instruction from the first instruction of the basic block; Step 2.9, for each instruction traversed, check whether it produces output, if yes, execute step 2.10, if not, execute step 2.11; Step 2.10, find and record all subsequent instructions that directly depend on the output, and build a directed edge for these relationships in the IDG, pointing from the instruction producing the output to the instruction using the output; Step 2.11, treat the instruction without output as a node without out-degree, which is at the same level as the next instruction of its control flow; Step 2.12, after completing each instruction, determine whether the current basic block has been traversed, if yes, it means that the analysis of all instructions in the basic block has been completed, then execute step 2.13, if not, jump to step 2.8 to continue execution; Step 2.13, output the instruction dependency graph IDG; Step 2.14, after outputting the instruction dependency graph IDG of each basic block, update the control flow graph CFG and mark the currently traversed basic block as having been constructed; Step 2.15, determine whether the CFG graph has been traversed, if not, jump to step 2.6 to continue traversing the next basic block according to the flow direction of the CFG, repeat the same process until all basic blocks in the CFG have been processed, if yes, execute step 2.16; Step 2.16, combine the instruction dependency graphs IDG of each basic block into a global instruction dependency graph IDG; Step 3, according to the global instruction dependency graph IDG, perform scheduling and packing before register allocation; Step 4, according to the register allocation result, reconstruct the instruction dependency graph IDG, and then perform scheduling and packing after register allocation according to the reconstructed instruction dependency graph IDG.

2. The DSP-oriented VLIW scheduling and packing method of claim 1, wherein, The PASS execution order of step 1 is: dead code elimination, execution constant propagation, inline expansion, loop optimization and dead code elimination.

3. The DSP-oriented VLIW scheduling and packing method of claim 2, wherein, The loop optimization includes loop unrolling and loop merging.

4. The DSP-oriented VLIW scheduling and packing method of claim 1, wherein, The step 3 specifically comprises the following steps: Step 3.1, selecting a first free instruction without a predecessor node from the global instruction dependency graph IDG as a seed node, taking it as a starting point of the packing process; Step 3.2, selecting the remaining free instructions according to the global instruction dependency graph IDG to construct a free instruction list; Step 3.3, taking an instruction in the free instruction list which has not been packed and does not have a dependency relationship with the seed node as a packable instruction, and adding it to the packable instruction list; Step 3.4, calculating the score of the packable instruction; Step 3.5, after calculating the score of each packable instruction, determining whether the free instruction list has been traversed, if not, returning to step 3.2, if yes, executing step 3.6; Step 3.6, determining whether the packable instruction list is empty, if yes, representing that the current seed node cannot be parallel with the remaining instructions, then packing it alone, if not, executing step 3.7; Step 3.7, selecting an instruction with the highest score from the packable instruction list as a candidate instruction; Step 3.8, updating the packable instruction list, and marking the instruction with the highest score as having been packed; Step 3.9, evaluating the feasibility of allocating a functional unit by sensing the pressure of the functional unit, if the functional unit cannot be allocated, jumping to step 3.7, otherwise, executing step 3.10; Step 3.10, determining whether the length of the packed data packet exceeds the number of hardware inherent execution units, if not, executing step 3.11, if yes, returning to step 3.7; Step 3.11, packing the packable instruction to complete the creation of a data packet; Step 3.12, after completing the creation of a data packet, judging the register pressure, if the data packet causes excessive register allocation pressure, jumping to step 3.1, otherwise, executing step 3.13; Step 3.13, deleting the confirmed packable instruction from the global instruction dependency graph IDG to obtain an updated global instruction dependency graph IDG.

5. The DSP-oriented VLIW scheduling and packing method of claim 4, wherein, The formula for calculating the score of the packable instruction in step 3.4 is: Score=w×Suc_Nodes-(1-w)×(Inst_Distance+Max_Slot-Inst_Slot|) In the formula, Suc_Nodes represents the number of instruction successor nodes, Inst_Distance represents the distance of the instruction relative to the entry node, Max_Slot represents the longest delay of the instruction in the current data packet, Inst_Slot represents the current instruction delay, and the absolute value of the difference between Max_Slot and Inst_Slot represents the matching degree of the total delay of the current instruction and the instructions in the data packet, and w is the weight.

6. The DSP oriented VLIW scheduling and packing method of claim 4 or 5, characterized in that, The specific process of reconstructing the instruction dependency graph IDG according to the register allocation result in step 4 is: inputting the instruction after register allocation, and then reconstructing the instruction dependency graph according to steps 2.2-2.

16.

7. The DSP oriented VLIW scheduling and packing method of claim 6, wherein, The scheduling and packing process after register allocation according to the reconstructed instruction dependency graph IDG in step 4 is step 3.1-3.13.

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