Register allocation

Abstract

The invention relates to register allocation. The shader program can include a condition portion that executes only in response to a particular condition being satisfied. The use of the condition portion may require different numbers of registers. Thus, this use of the condition portion potentially causes overallocation of registers. Accordingly, there is provided a method of rendering in a graphics processing system using a shader program having a condition segment applied only in response to satisfaction of a condition, the method comprising: compiling, by a compiler, the program, the compiling comprising identifying the condition segment; reading, by the resource allocator, constants that determine a result of the condition; determining, by the resource allocator, whether the condition is satisfied; and allocating, by the resource allocator, a number of registers.

Description

[0001] This application claims priority from UK patent application 2403620.4 filed on 13 March 2024. Technical Field

[0002] The present disclosure relates to graphics processing systems, and more particularly to graphics processing systems that implement shading programs with conditional sections. Background Art

[0003] A graphics processing system is typically configured to receive graphics data, for example, from an application running on a computer system, and to render the graphics data to provide a rendered output. For example, the graphics data provided to the graphics processing system may describe geometric shapes within a three-dimensional (3D) scene to be rendered, and the rendered output may be a rendered image of the scene. Some graphics processing systems (which may be referred to as "tile-based" graphics processing systems) use a rendering space that is subdivided into a plurality of tiles. A "tile" is a section of the rendering space and can have any suitable shape, but is typically rectangular (wherein the term "rectangular" includes squares). As is known in the art, subdividing the rendering space into tile segments has many benefits. For example, subdividing the rendering space into tile segments allows an image to be rendered in a tile-by-tile manner, wherein the graphics data for the tile can be temporarily stored "on chip" during the rendering of the tile, thereby reducing the amount of data transferred between the system memory and the chip of the graphics processing unit (GPU) implementing the graphics processing system.

[0004] Tile-based graphics processing systems typically operate in two phases: a geometry processing phase and a rendering phase. In the geometry processing phase, graphics data for rendering is analyzed to determine, for each tile in the tile set, which graphics data items exist within the tile. The graphics data items may include geometric primitives, such as triangles. Then, in the rendering phase (e.g., the rasterization phase), the tile can be rendered by processing those graphics data items determined to exist within the particular tile (without processing graphics data items determined not to exist within the particular tile during the geometry processing phase).

[0005] When rendering an image by rasterization, graphics data items are sampled to determine coverage, for example to determine which pixels of a tile are covered by triangle primitives. A fragment may be generated for each sample location, and the fragment is shaded (using a shader program, which may also be referred to as a 'shader' or 'shader program') to determine the color of the pixel of the image. Graphics shader programs may also be used at other stages in the graphics pipeline (e.g., vertex shaders, geometry shaders, or tessellation shaders), or may be used in other types of graphics rendering (such as ray tracing shaders), and other types of shader programs (such as compute shaders) may be used to perform other types of tasks on the GPU. Such shader programs may produce direct output (such as shaded fragments), but may also produce output more indirectly (such as by calling other shader programs).

[0006] Shader programs are becoming increasingly complex and include optional sections. For example, a specific section of code might be used to apply a specific technique that might not be used every time the shader is executed. Conditional statements that access constants stored in memory are used to determine whether a specific section of code is used for a specific task using the shader program.

[0007] Shaders use many registers, and optional sections of a shader will require registers. However, for some shader executions, the optional sections will not be used. Therefore, the registers allocated to those sections are not used and are allocated unnecessarily. This unnecessary allocation can affect rendering performance if it means there are not enough free registers to allocate to other shader programs that would otherwise be able to run.

[0008] One solution to this problem is to compile the shader program multiple times, each time satisfying a different combination of conditional statements. Once the constants for the conditional statements required for a particular shading task using the shader program are known, the correctly compiled version of the program can be accessed. This alleviates unnecessary register allocations. However, as the number of different conditional statements (and associated conditional sections) increases, the number of compiled programs increases exponentially, which in turn becomes cumbersome.

[0009] Therefore, there is a need to provide a method of executing a shader program having conditional sections without over-allocating registers and without generating and storing an unnecessary number of compiled shader programs. Summary of the Invention

[0010] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0011] In a graphics processing system, multiple different shading programs can be executed by a single processor on multiple threads. In some shading programs, there may be one or more conditional parts of the program that are executed (or not executed) based on conditional statements. The conditional parts require corresponding registers, and if the conditional parts are not used, the registers are also not used. This uses registers unnecessarily. However, there are a finite number of available registers, so efficient allocation of the registers will optimize performance. The present invention provides a method for preventing over-allocation of registers for unused conditional parts of shading programs.

[0012] According to a first aspect, there is provided a method of executing a shader program in a graphics processing system, the shader program having a conditional section that is applied only in response to a condition being satisfied, the method comprising:

[0013] Compiling the program by a compiler, the compilation including identifying a conditional section;

[0014] A constant that determines the result of a condition read by the resource allocator;

[0015] The resource allocator determines whether the conditions are met;

[0016] A certain number of registers are allocated by the resource allocator.

[0017] In some embodiments, a shader program may render the scene, and thus the method is a method of rendering using a shader program.

[0018] Optionally, the method further comprises executing the shader program by the processor.The processor may optionally be a single instruction multiple data (SIMD) processor, such as a general purpose shader.

[0019] Optionally, the method further comprises storing, by the resource allocator, the constant in one of the allocated registers.

[0020] Optionally, the method further comprises:

[0021] The processor reads a constant stored in a register;

[0022] The processor determines whether the condition is met;

[0023] The conditional section is executed or not executed in response to the determination.

[0024] Optionally, the method further comprises sending, by the compiler, the first number of registers, the second number of registers, and the condition to the resource allocator.

[0025] Optionally, allocating comprises allocating the first number of registers or the second number of registers based on determining whether a condition is satisfied.

[0026] Optionally, the method further comprises defining, by the compiler, a first number of registers to be allocated when the condition is met and a second number of registers to be allocated when the condition is not met, and wherein allocating comprises allocating the first number of registers or the second number of registers.

[0027] Optionally, the shader program has a plurality of conditional sections, each section being applied only in response to a condition being satisfied, and wherein:

[0028] Compiling includes identifying a plurality of conditional sections;

[0029] The defining includes defining a plurality of numbers of registers, defining a different number of registers for each combination of conditions that are met;

[0030] Reading includes reading a plurality of constants upon which the conditions are based;

[0031] Determining includes determining whether each of a plurality of conditions is satisfied; and

[0032] Allocating includes allocating a register from the plurality of registers based on the determination.

[0033] According to a second aspect of the present invention, there is provided a graphics processing system configured to execute a shader program, wherein the graphics processing system comprises logic configured to:

[0034] Compiling the program by a compiler, the compilation including identifying a conditional section;

[0035] A constant that determines the result of a condition read by the resource allocator;

[0036] The resource allocator determines whether the conditional statement is satisfied;

[0037] A number of registers is allocated by a resource allocator based on the determination.

[0038] In some embodiments, a shader program renders a scene.

[0039] Optionally, the logic is further configured to execute a shader program.The logic may include a single instruction multiple data processor.

[0040] Optionally, the logic is further configured to store the constant in one of the allocated registers.

[0041] Optionally, the logic is further configured to:

[0042] The processor reads a constant stored in a register;

[0043] The processor determines whether the condition is satisfied; and

[0044] The conditional section is executed or not executed in response to the determination.

[0045] Optionally, the logic is further configured to send, by the compiler, the first number of registers, the second number of registers, and the condition to the resource allocator.

[0046] Optionally, allocating comprises allocating the first number of registers or the second number of registers based on determining whether a condition is satisfied.

[0047] Optionally, the logic is further configured to define, by a compiler, a first number of registers to be allocated when the condition is met and a second number of registers to be allocated when the condition is not met, and wherein allocating comprises allocating the first number of registers or the second number of registers.

[0048] Optionally, the shader program has a plurality of conditional sections, each section being applied only in response to a condition being satisfied, wherein:

[0049] Compiling includes identifying a plurality of conditional sections;

[0050] The defining includes defining a plurality of numbers of registers, defining a different number of registers for each combination of conditions that are met;

[0051] Reading includes reading a plurality of constants upon which the conditions are based;

[0052] Determining includes determining whether each of a plurality of conditions is satisfied; and

[0053] Allocating includes allocating a register from the plurality of registers based on the determination.

[0054] According to a third aspect, there may be provided a graphics processing system configured to perform the method of the first aspect or any of the foregoing variations.

[0055] A graphics processing system may be embodied in hardware on an integrated circuit. A method of manufacturing a graphics processing system at an integrated circuit manufacturing system may be provided. An integrated circuit definition dataset may be provided that, when processed in the integrated circuit manufacturing system, configures the system to manufacture the graphics processing system. A non-transitory computer-readable storage medium may be provided that has a computer-readable description of the graphics processing system stored thereon that, when processed in the integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the graphics processing system.

[0056] An integrated circuit manufacturing system may be provided, the integrated circuit manufacturing system comprising: a non-transitory computer-readable storage medium having stored thereon a computer-readable description of a graphics processing system; a layout processing system configured to process the computer-readable description to generate a circuit layout description of an integrated circuit embodying the graphics processing system; and an integrated circuit generation system configured to manufacture the graphics processing system based on the circuit layout description.

[0057] A computer program code for performing any of the methods described herein may be provided. A non-transitory computer readable storage medium may be provided having computer readable instructions stored thereon, which, when executed in a computer system, cause the computer system to perform any of the methods described herein.

[0058] As will be apparent to the skilled person, the features described above may be combined as appropriate and with any aspect of the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Examples will now be described in detail with reference to the accompanying drawings, in which:

[0060] Figure 1 A graphics processing system is shown;

[0061] Figure 2 shows that it can be obtained by Figure 1 A method for implementing a graphics processing system of a graphics processing system;

[0062] Figure 3 A method according to the invention is described;

[0063] Figure 4 An alternative method according to the invention is depicted;

[0064] Figure 5 A method according to the present invention for a shader program having multiple conditional sections is depicted;

[0065] Figure 6 A computer system is shown in which a graphics processing system is implemented; and

[0066] Figure 7 An integrated circuit fabrication system for producing an integrated circuit including a graphics processing system is shown.

[0067] The accompanying drawings show various examples. It will be appreciated by those skilled in the art that the element boundaries (e.g., boxes, groups of boxes, or other shapes) shown in the accompanying drawings represent one example of boundaries. In some examples, it may be the case that one element can be designed as multiple elements, or multiple elements can be designed as one element. Where appropriate, common reference numerals are used throughout the accompanying drawings to indicate similar features. DETAILED DESCRIPTION

[0068] The following description is presented by way of example to enable any person skilled in the art to make and use the invention. The invention is not limited to the embodiments described herein, and various modifications to the disclosed embodiments will be apparent to those skilled in the art.

[0069] As described above, the use of conditional sections within shader programs provides greater flexibility in the scope of application of a particular shader program. Thus, a shader program can have many different conditional sections, and sometimes can have conditional sections nested within conditional sections. Conditional sections are executed based on constants associated with the task that calls the shader. The following description specifically considers fragment shader programs, but it will be understood that this is by way of example, and that other types of shader programs may also contain conditional sections, and the methods described herein may also be applied to those other types of shader programs.

[0070] Shader programs are compiled by a compiler, typically in the CPU, outside of the GPU. Compilation is very time-consuming, so it's done early. Specifically, compilation begins before any constants on which any conditional statements are based are known. Compilation includes limiting the number of registers used by the program.

[0071] In one approach, the constants are not known at compile time, so the current system compiles the program and the resource allocator then allocates registers based on all conditional sections being executed, i.e., registers are allocated for all conditional sections. However, if the task that calls the shader does not execute all (or any) of the conditional sections, there may be many redundant registers.

[0072] There are a finite number of available registers, so allocating registers that may not be used would unnecessarily tie up registers. To optimize efficiency, shading units perform multiple interleaved threads. Therefore, a limited number of registers can limit the number of tasks and cause inefficiencies in shading units.

[0073] As mentioned above, an alternative possibility is to compile different programs for different versions of the program with different conditional parts. However, this may require a large number of compiled programs, which may become cumbersome and require a large amount of computing resources to compile.

[0074] Another alternative possibility would be to wait to compile the shader program until the constant that indicates whether to execute the conditional part is known. However, compiling a program is a relatively long process, so waiting until the constant is known can significantly slow down the entire process.

[0075] Another alternative is to allocate registers only when needed. However, this has the disadvantage that storage is not optimized.

[0076] The present disclosure proposes a way to correctly allocate the number of registers without hindering or slowing down the entire process.

[0077] Embodiments will now be described by way of example only.

[0078] General system

[0079] Figure 1 An exemplary graphics processing system 100 is shown. Exemplary graphics processing system 100 is a tile-based graphics processing system. As described above, a tile-based graphics processing system uses a rendering space that is subdivided into a plurality of tiles. A tile is a segment of the rendering space and can have any suitable shape, but is typically rectangular (wherein the term "rectangular" includes squares). Tile segments within the rendering space are typically of the same shape and size.

[0080] System 100 includes memory 102, geometry processing logic 104, and rendering logic 106. As is known in the art, geometry processing logic 104 and rendering logic 106 can be implemented on a GPU and can share some processing resources. Geometry processing logic 104 includes a geometry acquisition unit 108; primitive processing logic 109, which in turn includes geometry transformation logic 110 and a culling / clipping unit 112; primitive block assembly logic 113; and a tiling unit 114. Rendering logic 106 includes a parameter acquisition unit 116; a sampling unit 117 including hidden surface removal (HSR) logic 118; and a texturing / shading unit 120. Exemplary system 100 is a so-called "deferred rendering" system because texturing / shading is performed after hidden surface removal. However, a tile-based system need not be a deferred rendering system, and although this disclosure uses a tile-based deferred rendering system as an example, the concepts presented are also applicable to non-deferred (referred to as immediate mode) rendering systems or non-tile-based systems. Memory 102 may be implemented as one or more physical memory blocks and includes graphics memory 122 ; transformed parameter memory 124 ; control list memory 126 ; and frame buffer 128 .

[0081] Figure 2 The operation of a tile-based rendering system such as Figure 1Flowchart of a method for rendering a scene (system shown in FIG). The geometry processing logic 104 performs a geometry processing phase, wherein the geometry acquisition unit 108 acquires geometry data (e.g., previously received from the application for which rendering is being performed) from the graphics memory 122 (in step S202) and passes the acquired data to the primitive processing logic 109. The geometry data includes graphics data items (i.e., geometry items) that describe the geometry to be rendered. For example, the geometry items may represent geometric shapes that describe the surfaces of structures in the scene. The geometry items may be in the form of primitives (typically triangles, but primitives can be other 2D shapes and may also be lines or points to which textures may be applied). Primitives may be defined by their vertices, and vertex data describing the vertices may be provided, where a combination of vertices describes a primitive (e.g., a triangle primitive is defined by vertex data for three vertices). An object may be composed of one or more such primitives. In some examples, an object may be composed of thousands or even millions of such primitives. A scene typically contains many objects. A geometry item may also be a mesh (formed from multiple primitives, such as a quadrilateral comprising two triangle primitives sharing an edge). A geometry item may also be a patch, where the patch is described by control points, and where the patch is subdivided to generate multiple subdivided primitives.

[0082] In step S204, the geometry processing logic 104 pre-processes the geometry items, for example, by transforming the geometry items into screen space, performing vertex shading, performing geometry shading, and / or performing tessellation, as applicable to the corresponding geometry items. Specifically, the primitive processing logic 109 (and its subunits) can operate on the geometry items and, in doing so, can utilize state information retrieved from the graphics memory 122. For example, the transformation logic 110 in the primitive processing logic 109 can transform the geometry items into rendering space and can apply lighting / attribute processing as known in the art. The resulting data can be passed to the culling / clipping unit 112, which can cull and / or clip any geometry that falls outside the viewing frustum. The remaining transformed geometry items (e.g., primitives) are provided from the primitive processing logic 109 to the primitive block assembly logic 113, which groups the geometry items into blocks, also known as "primitive blocks," for storage. A primitive block is a data structure in which data associated with one or more primitives (e.g., transformed geometry data associated with one or more primitives) is stored together. For example, each block can include up to N primitives and up to M vertices, where the values ​​of N and M are implementation design choices. For example, N can be 24 and M can be 16. Each block can be associated with a block ID so that the blocks can be easily identified and referenced. Primitives typically share vertices with other primitives, so storing the vertices of a primitive in a block allows the vertex data to be stored once in the block, where multiple primitives in the primitive block can reference the same vertex data in the block. In step S206, the primitive block with the transformed geometry data items is provided to the memory 102 for storage in the transformed parameter memory 124. The transformed geometry items and information about how to pack them into primitive blocks are also provided to the tiling unit 114. In step S208, the tiling unit 114 generates control flow data for each tile in the rendering space, wherein the control flow data for the tile includes a control list of identifiers of transformed primitives to be used for rendering the tile, i.e., a list of identifiers of transformed primitives located at least partially within the tile. The collection of control lists of identifiers of transformed primitives for each tile may be referred to as a "control flow list" or "display list." In step S210, the control flow data for the tile is provided to the memory 102 for storage in the control list memory 126. Thus, after the geometry processing phase (i.e., after step S210), the transformed primitives to be rendered are stored in the transformed parameter memory 124, and control flow data indicating which of the transformed primitives are present in each tile in the tile is stored in the control list memory 126. In other words, for a given geometry item, the geometry processing phase is completed before the rendering phase begins, and the results of that phase are stored in the memory.

[0083] During the rendering phase, the rendering logic 106 renders geometric items (primitives) on a tile-by-tile basis. In step S212, the parameter fetch unit 116 receives control stream data for the tile, and in step S214, the parameter fetch unit 116 fetches the indicated transformed primitives from the transformed parameter memory 124, as indicated by the control stream data for the tile. In step S216, the rendering logic 106 renders the fetched primitives by sampling the primitives to determine primitive fragments representing the primitives at discrete sample points within the tile, and then performing hidden surface removal and texturing / shading on the primitive fragments. Specifically, the fetched transformed primitives are provided to the sampling unit 117 (which may also access state information from graphics memory or stored with the transformed primitives), which performs sampling and determines the primitive fragments to be shaded. As part of determining the primitive fragments to be shaded, the sampling unit 117 uses hidden surface removal (HSR) logic 118 to remove primitive fragments that are hidden (e.g., hidden by other primitive samples). Methods for performing sampling and hidden surface removal are known in the art. The term "sampling" is used herein to describe the process of generating discrete fragments from geometric items (e.g., primitives), but this process may sometimes be referred to as "rasterization" or "scan conversion." As described above, Figure 1 The system 100 is a deferred rendering system and therefore performs hidden surface removal before texturing / shading. However, other systems may render fragments to determine which fragments are visible in the scene before performing hidden surface removal.

[0084] Fragments not removed by the HSR logic 118 are provided from the sampling unit 117 to the texturing / shading unit 120, where texturing and / or shading are applied. The texturing / shading unit 120 is typically configured to efficiently process multiple fragments in parallel. This can be accomplished by identifying fragments that require the same processing (e.g., need to run the same shader) and treating them as instances of the same task (which are then run in parallel in, for example, a SIMD (Single Instruction, Multiple Data) processor). To assist with this, in some embodiments, fragments from the same primitive can be provided to the texturing / shading unit 120 in so-called 'micro-tiles', which are groups of fragments. For example, a micro-tile can correspond to a 4×4 array of sample points corresponding to a particular area of ​​rendering space and can therefore (depending on the primitive coverage within the micro-tile) include up to 16 fragments. Therefore, if each fragment is shaded separately, the micro-tile can include up to 16 task instances. It should be understood that these micro-tiles are separate from the 'tiles' used in tile-based rendering. As explained above, a tile is a subdivision of the overall rendering space, where graphics data can be temporarily stored "on-chip" during tile rendering. A microtile represents the results of sampling (and optionally, hidden surface removal) of part or all of a particular primitive. In other words, several microtiles can represent a single primitive, and many primitives can exist in a single tile.

[0085] Despite Figure 1 Not shown, the texturing / shading unit 120 may receive texture data and / or constants associated with shading from the memory 102 in order to apply texturing to the primitive fragments, as is known in the art. The texture data and / or constants may be stored and accessed by the texturing / shading unit (or associated resource allocator) as necessary. As is known in the art, the texturing / shading unit 120 may apply further processing (e.g., alpha blending and other processing) to the primitive fragments in order to determine the rendered pixel values ​​of the image. A rendering phase is performed on each tile in the tile so that the entire image can be rendered while determining the pixel values ​​of the entire image. In step S218, the rendered pixel values ​​are provided to the memory 102 for storage in the frame buffer 128. The rendered image may then be used in any suitable manner, such as displayed on a display screen, stored in a memory, sent to another device, and so on.

[0086] The texturing / shading unit 120 may include a resource allocator 121 and a shader execution unit 122. The resource allocator allocates resources used by the shader execution unit when executing a program. The shader execution unit 122 may be a programmable processor. In many examples, this programmable processor is a single instruction multiple data (SIMD) processor, which allows the same instruction to be executed on multiple fragments, for example, using the same constants and texture data. Certain programmable processors are typically multitasking processors that perform multiple tasks and switch between them. The use of multiple tasks allows the resources of the texturing / shading unit 120 to be optimized and their utilization to be optimized. The resource allocator 121 and the shader execution unit 122 may be tightly integrated so that the entire texturing / shading unit 120 can be viewed as a processor that handles its own resource allocation and runs shader programs. Alternatively, the resource allocator 121 and the shader execution unit 122 may be more separated within the entire texturing / shading unit 120 so that the entire texturing / shading unit 120 can be viewed as including a processor in the form of a shader execution unit 122 and a resource allocator 121.

[0087] The shader execution unit 122 can execute a large number of different programs, and before the shader execution unit 122 can execute a program, resources must be allocated to the program. Specifically, registers must be allocated to the program. The number of registers available to the texturing / shading unit 120 is limited, and if all registers are allocated, the number of concurrent tasks may be limited, and redundancy of general-purpose shaders may occur.

[0088] For any given application, there are multiple shader programs, and different shader programs operate to, for example, shade different surfaces. When a particular shader program is identified, it is compiled. Since compilation is a resource-intensive task, this typically occurs on a separate CPU, but it can also occur on a GPU. As described above, the compilation of a program can take a significant amount of time, and therefore, once a shader program is identified, compilation of the program is typically started. Specifically, compilation is time-consuming and therefore begins shortly after the shader program is identified.

[0089] Figure 3The method of the present invention is depicted, wherein a shader program having a conditional statement is prepared for execution. A selected shader program is identified and sent to a compiler. At step 401, the compiler compiles the shader program. According to the present invention, as part of the compilation, the compiler identifies a conditional section at step 401a. If the conditional section is executed in response to a condition being met, the shader program will require a first number of registers. However, if the conditional section is not executed because the condition is not met, only a second number of registers is required. As will be understood, the first number of registers is generally greater than the second number of registers. The condition includes, for example, comparing a constant to a predefined value. The constant is determined in early processing of the graphics metadata and can be stored in memory and / or passed to the texturing / shading unit 120.

[0090] At step 402, the compiler defines a first number of registers and a second number of registers. This information is sent to the resource allocator 121. Details of the condition may also be sent by the compiler to the resource allocator. As described above, compilation is generally time consuming and is therefore performed in advance to avoid adversely affecting the speed of the process. Constants indicating whether the conditional section is to be executed are stored in a memory, such as memory 102 or a specific transformation parameter memory 124. As part of preparing the shading task for execution, the resource allocator reads the constant at step 403. At step 404, the resource allocator determines whether the condition is met. The constant can be a value, and the condition can involve a comparison of the value with a predefined threshold (for example, to determine whether the value is above, below, or equal to the threshold), or the condition can be binary.

[0091] If the condition is met, the resource allocator allocates a first number of registers at step 405. If the condition is not met, the resource allocator allocates a second number of registers.

[0092] Advantageously, resource allocation is a fast process that can be performed shortly before the shader program is executed, so the correct number of registers are allocated without hindering the overall rendering.

[0093] Once the registers have been allocated to the task, the shader execution unit 122 can execute the shader program and use the registers allocated by the resource allocator in step 405 or 406. The shader execution unit 122 will execute the shader program, and when it encounters a conditional statement, it will read the constant from the memory 102 to determine which execution path to take. Since the resource allocator 121 allocates the number of registers for the task based on reading the same constant, the texturing / shading unit 120 will have sufficient registers for the specific execution path indicated by the value of the constant.

[0094] Figure 4An alternative method of the present invention is depicted. Steps 401, 402, 403, 404, 405 and 406 are similar to Figure 3 . However, at step 501, once the resource allocator has allocated a register in step 405 or 406, the constant (read at step 403) is stored in one of the allocated registers. This allows the shader execution unit 122 to read the constant while executing the shader program without accessing external memory, which can be resource-intensive and time-consuming.

[0095] Subsequently, when the shader execution unit 122 is executing the shader program, the constant is read from the allocated register at step 502. Based on the constant, the shader execution unit 122 then determines whether a condition is satisfied at step 503. If the condition is satisfied, the conditional section is executed at step 504. If the condition is not satisfied, the conditional section is not executed.

[0096] For ease of understanding, Figure 3 and Figure 4 We have described processing shaders using a single conditional section. However, a shader program may have many conditional sections. In the case of multiple conditional sections, a similar process occurs for each condition. Furthermore, there may be nested conditions, such that some conditions are only considered if earlier conditions are met. An example of additional registers is given in Table 1, where condition 3.2 is nested within condition 3.1 and is only evaluated if condition 3.1 is met:

[0097] Conditional Section Number of additional registers 1 2 2 8 3.1 4 3.2 12

[0098] While information can be passed to resource allocator 121 in the form of a table or data, it can also be passed in the form of a program. Resource allocator 121 can execute the program. Thus, a compiler can compile a simple program that instructs the resource allocator how to calculate the number of registers based on one or more constants. This program can then be executed by the resource allocator, which then allocates the calculated number of registers. This arrangement is particularly useful for complex scenarios with nested conditional sections.

[0099] Figure 5 An embodiment for compiling a program with multiple conditional sections is depicted. The program is compiled 601 and the conditional section is identified 601a. ​​At step 602, the number of registers for the different conditions to be met is defined. This can be done by defining the additional registers required to meet each condition (Table 1) or the total number of registers required to meet the different conditions (Table 2).

[0100] The resource allocator then reads the first constant 603 and determines whether a condition is met at step 604. It determines whether additional conditions exist at step 607. If additional conditions exist, the next constant is read at step 605 and the condition is evaluated at step 604. This operation is repeated until all constants have been read and the corresponding conditions have been evaluated.

[0101] Once all conditions have been evaluated, the number of registers is allocated 608 based on the conditions met. Figure 5 Similar to the arrangement depicted in , constants retrieved by resource allocator 121 may be stored in allocated registers to speed up retrieval and reading of the constants by shader execution unit 122 when executing a shader program.

[0102] In this way, the correct number of registers can be allocated to shader programs with multiple conditional sections.

[0103] Figure 6 1 shows a computer system in which the graphics processing system described herein can be implemented. The computer system includes a CPU 1102, a GPU 1104, a memory 1106, a neural network accelerator (NNA) 1108, and other devices 1114, such as a display 1116, a speaker 1118, and a camera 1122. Processing blocks 1110 and 1111 (corresponding to processing blocks 104 and 106) are implemented on GPU 1104. In other examples, one or more of the depicted components can be omitted from the system, and / or processing block 1110 can be implemented on CPU 1102 or within NNA 1108. The components of the computer system can communicate with each other via a communication bus 1120. Memory area 1112 (corresponding to memory 102) is implemented as part of memory 1106.

[0104] Figure 1 The graphics processing system is shown as including a plurality of functional blocks. This is for illustrative purposes only and is not intended to define a strict division between the different logical elements of such an entity. Each functional block may be provided in any suitable manner. It should be understood that the intermediate values ​​described herein formed by the graphics processing system need not be physically generated by the graphics processing system at any point in time and may simply represent logical values ​​that conveniently describe the processing performed by the graphics processing system between its inputs and outputs.

[0105] The graphics processing system described herein can be embodied in hardware on an integrated circuit. The graphics processing system described herein can be configured to perform any of the methods described herein. Generally speaking, any of the functions, methods, techniques, or components described above can be implemented in software, firmware, hardware (e.g., fixed logic circuitry), or any combination thereof. The terms "module," "function," "component," "element," "unit," "block," and "logic" may be used herein to generally refer to software, firmware, hardware, or any combination thereof. In the case of a software implementation, a module, function, component, element, unit, block, or logic represents program code that, when executed on a processor, performs a specified task. The algorithms and methods described herein can be performed by one or more processors executing code that causes the processor to perform the algorithm / method. Examples of computer-readable storage media include random access memory (RAM), read-only memory (ROM), optical disks, flash memory, hard disk storage, and other memory devices that can use magnetic, optical, or other technologies to store instructions or other data and are accessible by a machine.

[0106] As used herein, the terms computer program code and computer-readable instructions refer to any type of executable code for a processor, including code expressed in machine language, interpreted language, or scripting language. Executable code includes binary code, machine code, byte code, code that defines an integrated circuit (e.g., a hardware description language or netlist), and code expressed in programming language code such as C, Java, or OpenCL. Executable code can be, for example, any type of software, firmware, script, module, or library that, when properly executed, processed, interpreted, compiled, or run in a virtual machine or other software environment, causes a processor of a computer system supporting the executable code to perform the tasks specified by the code.

[0107] A processor, computer, or computer system may be any kind of device, machine, or specialized circuit, or a collection or portion thereof, that has processing capabilities such that it can execute instructions. A processor may be or include any kind of general-purpose or specialized processor, such as a CPU, GPU, NNA, system on a chip, state machine, media processor, application-specific integrated circuit (ASIC), programmable logic array, field-programmable gate array (FPGA), etc. A computer or computer system may include one or more processors.

[0108] The present invention is also intended to encompass software that defines the configuration of hardware as described herein, such as HDL (Hardware Description Language) software, such as used in designing integrated circuits, or for configuring programmable chips to perform desired functions. That is, a computer-readable storage medium may be provided having encoded thereon computer-readable program code in the form of an integrated circuit definition data set, which, when processed (i.e., executed) in an integrated circuit manufacturing system, configures the system to manufacture a graphics processing system configured to perform any of the methods described herein, or to manufacture a graphics processing system that includes any of the devices described herein. The integrated circuit definition data set may be, for example, an integrated circuit description.

[0109] Thus, a method of manufacturing a graphics processing system as described herein at an integrated circuit manufacturing system may be provided. In addition, an integrated circuit definition data set may be provided that, when processed in an integrated circuit manufacturing system, enables the method of manufacturing a graphics processing system to be performed.

[0110] The integrated circuit definition data set may be in the form of computer code, for example, as a netlist, code for configuring a programmable chip, as a hardware description language that defines hardware suitable for fabrication at any level in the integrated circuit, including as register transfer level (RTL) code, as a high-level circuit representation (e.g., Verilog or VHDL), and as a low-level circuit representation (e.g., OASIS (RTM) and GDSII). A higher-level representation (e.g., RTL) that logically defines hardware suitable for fabrication in the integrated circuit may be processed at a computer system configured to generate a manufacturing definition of the integrated circuit in the context of a software environment that includes definitions of circuit elements and rules for combining those elements to generate a manufacturing definition of the integrated circuit so defined by the representation. As is typically the case when software is executed at a computer system to define a machine, one or more intermediate user steps (e.g., providing commands, variables, etc.) may be required to configure the computer system to generate a manufacturing definition of the integrated circuit in order to execute the code that defines the integrated circuit in order to generate the manufacturing definition of the integrated circuit.

[0111] Now refer to Figure 7 An example of processing an integrated circuit definition dataset at an integrated circuit manufacturing system to configure the system to manufacture a graphics processing system is described.

[0112] Figure 7An example of an integrated circuit (IC) manufacturing system 1202 configured to manufacture a graphics processing system as described in any of the examples herein is shown. Specifically, the IC manufacturing system 1202 includes a layout processing system 1204 and an integrated circuit generation system 1206. The IC manufacturing system 1202 is configured to receive an IC definition dataset (e.g., defining a graphics processing system as described in any of the examples herein), process the IC definition dataset, and generate an IC (e.g., embodying a graphics processing system as described in any of the examples herein) based on the IC definition dataset. Processing the IC definition dataset configures the IC manufacturing system 1202 to manufacture integrated circuits embodying a graphics processing system as described in any of the examples herein.

[0113] The layout processing system 1204 is configured to receive and process an IC definition data set to determine a circuit layout. Methods for determining a circuit layout based on an IC definition data set are known in the art and may, for example, involve synthesizing RTL code to determine a gate-level representation of the circuit to be generated, such as for logic components (e.g., NAND, NOR, AND, OR, MUX, and FLIP-FLOP components). By determining the location information of the logic components, the circuit layout can be determined from the gate-level representation of the circuit. This can be done automatically or with user input to optimize the circuit layout. When the layout processing system 1204 has determined the circuit layout, the layout processing system may output the circuit layout definition to the IC generation system 1206. The circuit layout definition may be, for example, a circuit layout description.

[0114] As is known in the art, IC generation system 1206 generates an IC based on a circuit layout definition. For example, IC generation system 1206 may implement a semiconductor device manufacturing process to generate the IC, which may involve a multi-step sequence of photolithography and chemical processing steps during which electronic circuits are gradually formed on a wafer made of semiconductor material. The circuit layout definition may be in the form of a mask that can be used in a photolithography process used to generate the IC based on the circuit definition. Alternatively, the circuit layout definition provided to IC generation system 1206 may be in the form of computer-readable code that IC generation system 1206 can use to generate a suitable mask for generating the IC.

[0115] The various processes performed by IC manufacturing system 1202 may all be performed at a single location, such as by one party. Alternatively, IC manufacturing system 1202 may be a distributed system, such that some processes may be performed at different locations and by different parties. For example, some of the following stages may be performed at different locations and / or by different parties: (i) synthesizing RTL code representing an IC definition data set to form a gate-level representation of a circuit to be generated; (ii) generating a circuit layout based on the gate-level representation; (iii) generating a mask based on the circuit layout; and (iv) using the mask to manufacture the integrated circuit.

[0116] In other examples, processing of an integrated circuit definition data set in an integrated circuit manufacturing system can configure the system to manufacture a graphics processing system without processing the IC definition data set to determine a circuit layout. For example, the integrated circuit definition data set can define a configuration of a reconfigurable processor such as an FPGA, and processing of the data set can configure the IC manufacturing system to generate a reconfigurable processor having the defined configuration (e.g., by loading the configuration data into the FPGA).

[0117] In some embodiments, the integrated circuit manufacturing definition data set, when processed in the integrated circuit manufacturing system, can cause the integrated circuit manufacturing system to generate the device as described herein. Figure 7 Configuring an integrated circuit fabrication system in the manner described may enable fabrication of the devices described herein.

[0118] In some examples, the integrated circuit definition dataset may include software that runs on, or in combination with, the hardware defined at the dataset. The IC production system may be further configured by the integrated circuit definition dataset to load firmware onto the integrated circuit according to the program code defined at the integrated circuit definition dataset during fabrication of the integrated circuit, or to otherwise provide the integrated circuit with program code for use with the integrated circuit.

[0119] Compared to known embodiments, the concepts set forth in this application can improve performance in devices, equipment, modules and / or systems (and in the methods implemented herein). Performance improvements can include one or more of improved computing performance, reduced latency, increased throughput and / or reduced power consumption. During the manufacture of such devices, equipment, modules and systems (e.g., in integrated circuits), a trade-off can be made between performance improvements and physical implementations to improve manufacturing methods. For example, a trade-off can be made between performance improvements and layout area to match the performance of known embodiments, but using less silicon. For example, this can be accomplished by reusing functional blocks in a serial manner or sharing functional blocks between elements of a device, device, module and / or system. In contrast, the concepts set forth in this application that result in improvements to the physical implementations of devices, equipment, modules and systems (e.g., reduced silicon area) can be weighed against performance improvements. This can be accomplished, for example, by manufacturing multiple instances of a module within a predefined area budget.

[0120] The applicant hereby independently discloses each individual feature described herein, as well as any combination of two or more such features, to the extent that such feature or combination can be implemented in view of the common general knowledge of a person skilled in the art based on the present specification as a whole, regardless of whether such feature or combination of features solves any problem disclosed herein. In view of the foregoing description, it will be clear to a person skilled in the art that various modifications can be made within the scope of the present invention.

Claims

1. A method of executing a shader program in a graphics processing system, the shader program having a conditional section that is applied only in response to a condition being satisfied, the method comprising: Compiling the program by a compiler, wherein the compiling includes identifying the conditional section; reading, by the resource allocator, a constant that determines the outcome of the condition; determining, by the resource allocator, whether the condition is satisfied; A number of registers is allocated by the resource allocator based on the determination.

2. The method according to any one of the preceding claims, further comprising: The constant is stored by the resource allocator in one of the allocated registers.

3. The method according to claim 2, further comprising: reading, by a processor, the constant stored in the register; determining, by the processor, whether the condition is satisfied; The conditional section is executed or not executed in response to the determination.

4. The method according to any one of the preceding claims, further comprising: The first number of registers, the second number of registers, and the condition are sent by the compiler to the resource allocator.

5. The method according to any one of the preceding claims, wherein allocating comprises allocating the first number of registers or the second number of registers depending on whether the condition is met.

6. The method according to any one of the preceding claims, further comprising: A first number of registers to be allocated when the condition is met and a second number of registers to be allocated when the condition is not met are defined by the compiler, and wherein allocating includes allocating the first number of registers or the second number of registers.

7. A method according to any one of the preceding claims, wherein the shader program has a plurality of conditional sections, each section being applied only in response to a condition being satisfied, wherein: Compiling includes identifying the plurality of conditional sections; Reading includes reading a plurality of constants on which the condition is based; Determining includes determining whether each of a plurality of conditions is satisfied; and Allocating includes allocating a number of registers based on the determining. 8 . The method of claim 7 , further comprising defining a plurality of numbers of registers, a different number of registers for each combination of conditions that are met, and allocating comprises allocating one of the plurality of registers.

9. A graphics processing system configured to execute a shader program, wherein the graphics processing system comprises logic configured to: Compiling the program by a compiler, the compiling including identifying a conditional section; A constant that determines the result of a condition read by the resource allocator; Determining, by the resource allocator, whether a conditional statement is satisfied; A number of registers is allocated by the resource allocator based on the determination. 10 . The graphics processing system of claim 9 , wherein allocating comprises allocating a first number of registers or a second number of registers based on determining whether the condition is satisfied. 11 . A graphics processing system, configured to execute the method according to claim 1 .

12. The graphics processing system according to any one of claims 9 to 11, comprising: A CPU configured to compile the shader program; as well as A GPU is configured to calculate the number of registers required.

13. The graphics processing system of any one of claims 9 to 12, wherein the graphics processing system is embodied in hardware on an integrated circuit.

14. A computer readable code configured to cause the method according to any one of claims 1 to 8 to be performed when the code is executed.

15. A computer-readable storage medium having encoded thereon the computer-readable code according to claim 14.

Images