A timing path analysis method and system

Abstract

The application provides a timing path analysis method and system, which finds out a critical path by analyzing a timing margin of each timing source point, starting path analysis from a timing source point with the smallest timing margin, and stopping the analysis when the number of critical paths reaches the number required by a user, thereby reducing analysis of many useless paths, saving analysis time, and when the number of paths reaches the requirement, the paths are critical paths. Compared with the prior art, in which all paths need to be analyzed to find out critical paths, the analysis time is greatly shortened, and the effect is very obvious, especially when the number of devices is large.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of FPGA, and particularly relates to a timing path analysis method and system. BACKGROUND

[0002] EDA (Electronic design automation) software is an indispensable part when using FPGA, and timing analysis is important, which can verify whether a designed circuit meets the design requirements. The commonly mentioned timing analysis is static timing analysis (STA) for short. Full-path timing analysis can display all input points to registers, registers to registers, and registers to output points to the customer. It plays a crucial role in designing an effective circuit for the customer.

[0003] When performing STA, the circuit is first abstracted into a topological structure in the form of a graph, and the components in the circuit are abstracted. The entire circuit is a netlist, each component is abstracted into a cell, and the information of the ports, pins and registers on the cell is abstracted into points. The purpose of timing analysis is to find hidden timing problems, and according to the timing analysis results, the logic or constraint conditions are optimized to make the design achieve timing closure. It is very complex to find an effective path in a timing netlist composed of millions or billions of points, and there is a method to reduce the number of calculations while achieving the purpose.

[0004] The timing netlist is a directed graph with connection relationship and delay created according to user design and timing model. The source point of the timing path must be the output port of the register, and the target point must be the input port of the register. According to this characteristic, the source point and target point of all timing paths are recorded.

[0005] The critical path in a digital circuit usually refers to the longest path in timing, that is, the path that determines the highest running speed of the circuit. For FPGA, it may involve factors such as wiring delay between logic blocks, delay of combinational logic, and clock skew. Timing slack (S) is used as the criterion for judging the critical path, and the smaller the timing slack, the more critical the timing path. Timing slack = required time (r) - arrival time (A).

[0006] The existing timing path analysis is to analyze all timing source points, find the most critical path, and each path will be effective detailed path information. Only the critical path is saved in the timing report, which causes a lot of time waste, and most of the time is spent on generating useless timing paths.

[0007] There are two categories of paths in the timing report, timing slack information sequence path and timing path without timing slack information. Timing path with timing slack includes simultaneous clock path, cross clock path and asynchronous clock path. Clock path without timing slack includes user ignore path and unconstrained path. SUMMARY

[0008] The main problem solved by the present application is how to quickly find an effective path in a timing netlist. The present application provides a timing path analysis method and system.

[0009] To solve the above technical problems, the technical solution adopted is:

[0010] A timing path analysis method, comprising the following steps:

[0011] Step 1: create a timing netlist according to the timing model and the information of the user netlist, the timing netlist including timing points and directed timing edges, the timing points being used to represent devices, and the directed timing edges being used to represent the connection relationship of the devices and the signal direction;

[0012] Step 2: calculate the timing slack of each timing source point, and sort the timing source points according to the timing slack from small to large;

[0013] Step 3: start analyzing the timing path from the timing source point with the smallest timing slack in the fan-out direction to find the critical path;

[0014] Step 4: when the number of critical paths reaches the number required by the user, stop analyzing and generate a timing report.

[0015] Further, the method for creating a timing netlist is:

[0016] Step 1.1: obtain the connection relationship of the internal input port to the output port of the device according to the timing model and create the internal connection of the device;

[0017] Step 1.2: obtain the connection between devices according to the user netlist and create the connection relationship between devices to obtain the timing netlist. When creating, if the device has a register, the output port of the register is taken as the source point of the timing path, and the input port of the register is taken as the target point of the timing path.

[0018] Further, the calculation method of the timing slack of each timing source point is:

[0019] Step 2.1: Layering the timing points in the timing netlist, all source points are in the first layer, and the fanout points are in the layer one more than the current layer, taking the fanout points as the current timing point, and the layer of the fanout points of the current timing point is one more than the layer of the current timing point, and so on, so that each timing point has layer information, and for a fanout timing point with multiple timing points of different layers, the layer of the fanout timing point is saved as one more than the maximum layer of its predecessor points;

[0020] Step 2.2: Classify the timing points according to the layer information, and put the timing points of the same layer into the same container, and sort the containers according to the layer information;

[0021] Step 2.3: Calculate the arrival time of the timing point:

[0022] Traverse all containers in order of layer from small to large, when traversing each container, traverse each timing point in the container and calculate the arrival time of each timing point, the arrival time of each timing point is the arrival time of the current timing point plus the signal delay, the arrival time of all timing points in the first container is 0, and after all timing points in each container are traversed, the next container is continued to be traversed;

[0023] Step 2.4: Calculate the required time of the timing point:

[0024] Traverse all containers in order of layer from large to small, when traversing each container, traverse each timing point in the container and calculate the required time of each timing point, if the current timing point is a timing target point, get the required time according to the target register, otherwise, the required time of the current timing point is the required time of the fanout point of the current timing point minus the signal delay, after all timing points in each container are traversed, the next container is continued to be traversed;

[0025] Step 2.5: After all containers are traversed, the timing slack of each timing source point is obtained by subtracting the arrival time from the required time.

[0026] Further, the method for finding the critical path is:

[0027] Step 3.1: Sort the timing slacks of each timing source point from small to large;

[0028] Step 3.2: sequentially from the source point with the smallest timing slack, create a timing sub-network for the source point, the timing sub-network refers to taking the fan-out point of the current source point as the connection timing point of the current source point, then taking the fan-out point as the current point, finding the fan-out point of the current point as the connection timing point of the current point, repeating this step until the current point has no fan-out point, obtaining the timing sub-network of the current source point, when the fan-out point is the target point of the timing path, recording into the target point list;

[0029] Step 3.3: create the predecessor point, delay and jump state information for the timing point in the timing sub-network;

[0030] Step 3.4: obtain the target point from the target point list respectively, pass through the predecessor point of each target point, then take the predecessor point as the current point, and pass through the predecessor point of the current point to obtain the timing point of a timing path between each target point and the timing source point;

[0031] Step 3.5: obtain the driving clock according to the source point and the target point of each timing path, obtain the clock period as the required time according to the driving clock, obtain the arrival time as the delay of the target point, and calculate the timing slack of each timing path;

[0032] Step 3.6: compare the timing slacks of the multiple timing paths from one source point, and select the path with the smallest timing slack as the critical path of the current source point.

[0033] Further, when creating the timing sub-network for each timing source point, the level information of each timing point in the sub-network is the same as the level information in the timing netlist.

[0034] Further, the method for creating the predecessor point, delay and jump state information for the timing point in the timing sub-network is:

[0035] Step 3.3.1: generate the delay information of the timing source point, the delay information of the timing source point includes the rising edge delay and the falling edge delay;

[0036] Step 3.3.2: create the delay information for the fan-out point of the timing source point, the predecessor point of the fan-out point is the timing source point, and the delay of the fan-out point is the fan-out delay of the timing source point;

[0037] Step 3.3.3: traverse the timing sub-network, starting from the second layer timing point of the timing sub-network, find the fan-out point of the current timing point from the timing sub-network according to the delay information of the current timing point, then the predecessor point of the fan-out point is the current timing point, and the delay information of the fan-out point is the timing delay of the current timing point plus the fan-out delay of the current timing point;

[0038] Step 3.3.4: sequentially traverse the timing points in the timing sub-network level, after the traversal is completed, make each timing point have the predecessor point and the delay information.

[0039] Further, the fan-out delay of the current timing point needs to take the rising edge delay or the falling edge delay of the fan-out signal according to the jump state of the current timing point and the jump state of the fan-out signal.

[0040] Further, when generating the timing report, the device and port names used in the timing path are obtained, and the device name and port hash table are created respectively, the timing path saves the hash value corresponding to the device name and port name, when displaying the timing path, according to the hash value, the device name and port are looked up in the hash table, and the path information is displayed to the timing report.

[0041] The application also provides a timing path analysis system using the steps of the timing path analysis method.

[0042] By using the above technical solution, the application has the following beneficial effects:

[0043] The timing path analysis method and system provided by the application find the critical path by starting path analysis from the timing source point with the smallest timing margin, and stop the analysis when the number of critical paths reaches the number required by the user, thereby reducing the analysis of many useless paths, saving the analysis time, and when the number of paths reaches the requirement, these paths are the critical paths, compared with the prior art which needs to analyze all paths to find the critical path, the analysis time is greatly shortened, especially when the number of devices is large, the effect is very obvious. Taking 100 million gate circuits as an example, the time used by the traditional analysis method is 540 seconds, and the time used after using the method of the application is 32 seconds. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 The system flowchart of the application is shown in the figure;

[0045] Figure 2 The timing network represents the intention;

[0046] Figure 3 The timing network represents the intention;

[0047] Figure 4 The timing network represents the intention; DETAILED DESCRIPTION

[0048] The technical solutions of the application will be described clearly and completely in combination with the drawings, obviously, the described embodiments are part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the application.

[0049] Figures 1 to 4 A specific embodiment of a timing path analysis method of the present application is shown in the flow chart of Fig. 1, which comprises the following steps: Figure 1

[0050] Step 1: Create a timing netlist according to the information of the timing model and the user netlist, the timing netlist comprising timing points and directed timing edges, the timing points being used to represent devices and the directed timing edges being used to represent the connection relationship of the devices and the signal direction.

[0051] In this embodiment, the method of creating the timing netlist is as follows:

[0052] Step 1.1: Obtain the connection relationship of the internal input ports to the output ports of the device according to the timing model and create the internal connection of the device. In the timing model, the basic information of the device is saved, such as the port name and type, the internal connection relationship of the input port to the output port, and the internal connection delay. By loading the timing model, the internal connection relationship of the device can be obtained.

[0053] Step 1.2: Obtain the connection between devices according to the user netlist and create the connection relationship between devices to obtain the timing netlist. When creating, if the device has a register, the output port of the register is taken as the source point of the timing path and the input port of the register is taken as the target point of the timing path. The user netlist is a description of the connection relationship generated according to the user code. By loading the user netlist, the connection relationship between devices can be obtained. As shown in the timing netlist of Fig. 2, the connection relationship between the three devices and the internal connection relationship of the devices can be seen. Figure 2

[0054] Step 2: Calculate the timing slack of each timing source point and sort the timing source points according to the timing slack of each timing source point from small to large.

[0055] A complete timing path is composed of multiple signals, and one signal can also be part of multiple paths. In the layout and routing stage, it is impossible to determine which information belongs to a timing path and which signals are the critical path signals. According to the characteristics of the timing path in this embodiment, the information on a path has consistent timing slack. The arrival time can be pushed from the source point of the timing path to the rear, and the required time can be pushed from the target point of the timing path to the front. The arrival time and the required time of each timing point are recorded. According to the arrival time and the required time of each timing point, the timing slack of each timing point can be calculated, and the timing slack of the timing source point can also be known.

[0056] In this embodiment, the calculation method of the timing slack of each timing source point is as follows:

[0057] ​​Step 2.1: Layering the timing points in the timing netlist, all source points are in the first layer, the fanout points are in the layer next to the current layer, the fanout points are the current timing points, the layer of the fanout points of the current timing points is the layer of the current timing points plus one, and so on, so that each timing point has layer information. For a fanout timing point with multiple timing points of different layers, the layer of the fanout timing point is saved as the layer of the timing point with the largest layer among the predecessor points plus one. Since the calculation of timing slack is a process of calculating delay from front to back and from back to front, in order to facilitate the push process from front to back and from back to front, the embodiment layers the timing points in the timing netlist and divides the containers, which is convenient for calculation.

[0058] Step 2.2: Classifying the timing points according to the layer information, putting the timing points of the same layer into the same container, and sorting the containers according to the layer information.

[0059] Step 2.3: Calculating the arrival time of the timing points, as shown in Figure 3 , traversing all containers in order of layer from small to large, when traversing each container, traversing each timing point in the container and calculating the arrival time of each timing point, the arrival time of each timing point is the arrival time of the current timing point plus the signal delay, the arrival time of all timing points in the first container is 0, and after all timing points in each container are traversed, the next container is continued to be traversed.

[0060] Step 2.4: Calculating the required time of the timing points, as shown in Figure 4 , traversing all containers in order of layer from large to small, when traversing each container, traversing each timing point in the container and calculating the required time of each timing point, if the current timing point is a timing target point, the required time is obtained according to the target register, otherwise the required time of the current timing point is the required time of the fanout point of the current timing point minus the signal delay, after all timing points in each container are traversed, the next container is continued to be traversed.

[0061] The required time usually refers to the time within which the target register can receive data. It is usually the clock period plus the clock path delay of the target register, which can be equivalent to the input port of the register, i.e. the target point of the timing path. Since the lengths of the timing paths are not the same, the layers of the timing target points are not the same, and when traversing each layer container, the timing target point may be encountered, and the required time of the target point needs to be obtained. The required time of other points of the timing path is the required time of the fanout point minus the signal delay.

[0062] Step 2.5: After all containers are traversed, the timing slack of each timing source point is obtained by subtracting the arrival time from the required time of each timing source point.

[0063] In this embodiment, after obtaining the timing margin of each timing source point, all timing source points are sorted from small to large, and the sorted timing path source points are saved into a specified file.

[0064] Step 3: Starting from the timing source point with the smallest timing margin, the timing path is analyzed along the fan-out point direction to find the critical path.

[0065] The analysis of the timing path aims to find the critical path in all timing paths. The analysis starts from the timing source point with the smallest timing margin because the timing margin is the standard for measuring whether the circuit is in timing violation. The smaller the timing margin, the more critical the path. The timing margins of the timing points on the critical path are the same. Therefore, the critical path can be found by finding the timing source point with the smallest timing margin.

[0066] The analysis process of a timing path: there can be a large number of timing paths from the source point to the target point. The timing analysis finds a path with the longest delay as the timing path. When the path with the longest delay meets the timing requirement, other paths must meet the timing requirement. Therefore, according to the hierarchy of the netlist, the embodiment pushes the timing points layer by layer backward so that the timing points can obtain the predecessor point and delay information. When the target point is reached, the information of all complete timing paths can be obtained. However, the timing netlist is very large, and there is a lot of useless information when traversing the hierarchy of the netlist, which wastes a lot of time. In order to solve this problem, the embodiment sorts the timing margins of the timing source points, and starts to analyze from the timing source point with the smallest timing margin. When the number of timing paths meets the user's requirement, the analysis is stopped, thereby saving the analysis time.

[0067] In this embodiment, starting from the timing source point with the smallest timing margin, the timing path is analyzed along the fan-out point direction to find the critical path.

[0068] Step 3.1: The timing margins of the timing source points are sorted from small to large.

[0069] Step 3.2: Starting from the timing source point with the smallest timing margin, a timing sub-net for the source point is created. The timing sub-net refers to taking the fan-out point of the current source point as the connection timing point of the current source point, taking the fan-out point as the current point, taking the fan-out point of the current point as the connection timing point of the current point, repeating the step until the current point has no fan-out point, obtaining the timing sub-net of the current source point, and recording the target point list when the fan-out point is the target point of the timing path.

[0070] In this embodiment, a separate timing sub-net is created for each timing source point, so that each timing source point only performs path analysis in its own sub-net, without traversing and analyzing all points in each hierarchy in the timing netlist, so that useless traversal is avoided and the analysis time is saved.

[0071] When the timing subnet is created for each timing source point, the hierarchy information of each timing point in the subnet is the same as that in the timing netlist. Although the timing subnet is created, the hierarchy of the timing subnet in the timing netlist is the same, only the timing points related to the timing source point are extracted to form the timing subnet, and the timing points unrelated to the timing source point do not need to be traversed and analyzed, thereby saving the analysis time.

[0072] Step 3.3: Create the predecessor point, delay and transition state information for the timing points in the timing subnet.

[0073] In this embodiment, the method for creating the predecessor point, delay and transition state information for the timing points in the timing subnet is as follows:

[0074] Step 3.3.1: Generate the delay information of the timing source point, which includes the rising edge delay and the falling edge delay.

[0075] Step 3.3.2: Create the delay information for the fanout point of the timing source point, the predecessor point of the fanout point is the timing source point, and the delay of the fanout point is the fanout delay of the timing source point.

[0076] Step 3.3.3: Traverse the timing subnet, starting from the second layer timing point of the timing subnet, find the fanout point of the current timing point according to the delay information of the current timing point, then the predecessor point of the fanout point is the current timing point, and the delay information of the fanout point is the timing delay of the current timing point plus the fanout delay of the current timing point. As shown in Table 1 and Table 2, the fanout delay of the current timing point needs to be taken as the rising edge delay or the falling edge delay of the fanout signal according to whether the current timing source point is at the rising edge or the falling edge, and the transition state of the current timing point and the transition state of the fanout signal.

[0077] Table 1 Rising edge delay of timing source point

[0078]

[0079] Table 2 Falling edge delay of timing source point

[0080]

[0081] Step 3.3.4: Traverse the timing points in the hierarchy of the timing subnet in turn, and after the traversal is completed, each timing point has the predecessor point and the delay information.

[0082] Step 3.4: Obtain the target points from the target point list respectively, pass through the predecessor points of the target points, then take the predecessor points as the current points, and then pass through the predecessor points of the current points to obtain the timing points of a timing path between each target point and the timing source point.

[0083] Step 3.5: Obtain driving clock according to source point and target point of each timing path, obtain clock period as required time according to driving clock, obtain time delay of target point as arrival time, and calculate timing margin of each timing path;

[0084] Step 3.6: Compare timing margins of multiple timing paths from one source point, and select the path with the smallest timing margin as the critical path of the current source point.

[0085] Step 4: Stop analysis and generate timing report when the number of critical paths reaches the number required by the user.

[0086] In the embodiment, when generating the timing report, the device and port names used in the timing path are obtained, and a device name and port hash table are created respectively. The timing path saves the hash value corresponding to the device name and port name. When displaying the timing path, the device name and port are looked up in the hash table according to the hash value, and the path information is displayed to the timing report. The existing timing path saves the serial number of the timing point. The timing report needs to display the device name type and input / output port information passed by the timing path. These information needs to be obtained from the timing netlist according to the serial number of the timing point. A device may exist in many timing paths. If the information of this device is saved in each path, it will cause data redundancy and waste storage space. By saving the hash value corresponding to the device name and port name in the timing path, the storage space can be reduced and data redundancy can be avoided.

[0087] The application also provides a timing path analysis system using the timing path analysis method.

[0088] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the application, and not to limit them; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. A timing path analysis method, characterized in that: The following steps are involved: Step 1: Create a timing netlist based on the timing model and user netlist information. The timing netlist includes timing points and directed timing edges. Timing points are used to represent devices, and directed timing edges are used to represent device connection relationships and signal directions. Step 2: Calculate the timing margin of each timing source point and sort the timing sources from small to large according to their timing margin. The calculation method for the timing margin of each timing source point is: Step 2.1: Layer the timing points in the timing netlist. All source points are in the first layer. The fan-out point level is the current level plus 1. The fan-out point is used as the current timing point. The level of the fan-out point of the current timing point is plus 1 based on the level of the current timing point. This is repeated in this way, so that each timing point has level information. For a fan-out timing point that is a timing point of multiple different levels, the level of the fan-out timing point is saved as the maximum level of its predecessor point plus 1. Step 2.2: Classify the time series points according to the hierarchical information, put the time series points of the same level into the same container, and sort the containers according to the hierarchical information; Step 2.3: Calculate the arrival time of the timing point: Traverse all containers in ascending order from the smallest level. When traversing each container, it is necessary to traverse each time point in the container and calculate the arrival time of each time point. The arrival time of each time point is the arrival time of the current time point plus the signal delay. The arrival time of all time points in the first-level container is 0. After traversing all time points in each container, continue to traverse the next container. Step 2.4: Calculate the required time for the timing point: Traverse all containers from largest to smallest hierarchically. When traversing each container, traverse each timing point in the container and calculate the required time for each timing point. If the current timing point is the timing target point, obtain the required time based on the target register. Otherwise, subtract the signal delay from the required time of the fan-out point of the current timing point as the required time for the current timing point. After traversing all timing points in each container, continue traversing the next container. Step 2.5: After all containers are traversed, subtract the arrival time from the required time of each timing source to obtain the timing margin of each timing source. Step 3: Analyze the timing path from the timing source point with the minimum timing margin along the fan-out point direction to find the critical path; Step 4: When the number of critical paths reaches the number required by the user, stop the analysis and generate a timing report.

2. A timing path analysis method according to claim 1, characterized in that: The method to create a timing netlist is: Step 1.1: Obtain the connection relationship between the device's internal input port and output port based on the timing model and create the connection within the device; Step 1.2: Obtain the connections between devices based on the user netlist and create the connection relationship between the devices to obtain the timing netlist. When creating, if the device has a register, use the output port of the register as the source point of the timing path and the input port of the register as the target point of the timing path.

3. The timing path analysis method according to claim 2, wherein: Starting from the timing source point with the minimum timing margin and analyzing the timing path along the fan-out point direction, the method to find the critical path is: Step 3.1: Sort the timing margins of each timing source point from small to large; Step 3.2: Starting from the source point with the smallest timing margin, create a timing subnet for the source point. The timing subnet is to use the fan-out point of the current source point as the connection timing point of the current source point, then use the fan-out point as the current point, find the fan-out point of the current point as the connection timing point of the current point, and repeat this step until the current point has no fan-out point. The timing subnet of the current source point is obtained. When the fan-out point is the target point of the timing path, it is recorded in the target point list; Step 3.3: Create predecessor point, delay and transition state information for the timing point in the timing subnet; Step 3.4: Get the target points from the target point list, pass through the predecessor points of each target point, and then use the predecessor points as the current point. Then, push forward through the predecessor points of the current point to obtain the timing points of a timing path between each target point and the timing source point. Step 3.5: Obtain the driving clock based on the source and destination points of each timing path. Calculate the clock period based on the driving clock as the required time, and use the delay at the destination point as the arrival time to calculate the timing margin of each timing path. Step 3.6: Compare the timing margins of multiple timing paths starting from a source point and select the path with the smallest timing margin as the critical path of the current source point.

4. A timing path analysis method according to claim 3, characterized in that: When creating a timing subnet for each timing source point, the hierarchical information of each timing point in the subnet is the same as the hierarchical information in the timing netlist.

5. A timing path analysis method according to claim 4, characterized in that: The method for creating predecessor point, delay and transition state information for the timing point in the timing subnet is: Step 3.3.1: Generate the delay information of the timing source point. The delay information of the timing source point includes rising edge delay and falling edge delay; Step 3.3.2: Create delay information for the fan-out point of the timing source point. The predecessor point of the fan-out point is the timing source point, and the delay of the fan-out point is the fan-out delay of the timing source point. Step 3.3.3: Traverse the timing subnet, starting from the second-layer timing point of the timing subnet. Based on the delay information of the current timing point, find the fan-out point of the current timing point in the timing subnet. The predecessor point of the fan-out point is the current timing point, and the delay information of the fan-out point is the timing delay of the current timing point plus the fan-out delay of the current timing point. Step 3.3.4: Traverse the timing points in the timing subnet hierarchy in sequence. After the traversal is completed, each timing point has predecessor point and delay information.

6. A timing path analysis method according to claim 5, characterized in that: The fan-out delay at the current timing point needs to take the rising edge delay or falling edge delay of the fan-out signal according to whether the current timing source point is at the rising edge or falling edge, the transition state of the current timing point, and the transition state of the fan-out signal.

7. A timing path analysis method according to claim 6, characterized in that: When generating a timing report, the device and port names used in the timing path are obtained, and device name and port hash tables are created respectively. The timing path stores the hash values ​​corresponding to the device names and port names. When displaying the timing path, the device name and port are searched in the hash table based on the hash values, and the path information is displayed in the timing report.

8. A timing path analysis system, characterized in that: The method is implemented by using each step of a timing path analysis method according to any one of claims 1 to 7.

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