Wafer defect detection method and related equipment

Abstract

The invention discloses a wafer defect detection method and related equipment, and relates to the technical field of data processing, and the method comprises the steps: receiving a preset first resolution image of a corresponding wafer collected by a camera in response to a wafer defect detection instruction, and carrying out the parallel processing of the preset first resolution image based on a CPU-GPU cooperative calculation strategy, determining a binary mask corresponding to the preset first resolution image according to the preset first resolution image, and judging whether the wafer has defects or not based on a preset wafer defect judgment rule and the binary mask so as to obtain a wafer defect detection result. According to the method and the device, the preset first resolution image is processed in parallel through a CPU-GPU cooperative computing strategy, so that the image processing speed is improved, and the real-time performance of wafer defect detection is improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a wafer defect detection method and related equipment. Background Art

[0002] As semiconductor manufacturing processes evolve towards smaller nodes and 3D stacking technologies (such as the popularization of hybrid bonding processes), wafer defect detection has become a core factor affecting product yield and cost.

[0003] In related technologies, wafer defect inspection equipment uses high-resolution TDI line scan cameras (such as Teledyne's 16k / 5μm resolution Linea HS2 series) for image acquisition. Its single image data throughput is as high as 16G pixels / second. Although it can capture micron-level defects (such as Micro LED grain scratches below 50μm), the massive amount of data causes the real-time performance of traditional processing algorithms to be significantly reduced.

[0004] The above content is only used to assist in understanding the technical solution of this application and does not constitute an admission that the above content is related technology. Summary of the Invention

[0005] The main purpose of this application is to provide a wafer defect detection method and related equipment, aiming to solve the technical problem of how to improve the real-time performance of wafer defect detection.

[0006] To achieve the above objectives, the present application proposes a wafer defect detection method, which includes: In response to a wafer defect detection instruction, a receiving camera captures a preset first resolution image of a corresponding wafer; Based on a CPU-GPU collaborative computing strategy, the preset first resolution image is processed in parallel to determine a binary mask corresponding to the preset first resolution image; Based on the preset wafer defect judgment rule and the binary mask, it is judged whether the wafer has defects to obtain a wafer defect detection result.

[0007] In one embodiment, the step of processing the preset first resolution image in parallel based on a CPU-GPU collaborative computing strategy to determine a binary mask corresponding to the preset first resolution image further includes: Based on a preset image size, performing a block operation on the preset first resolution image to obtain a plurality of target sub-images; Based on the wafer defect detection instruction and the CPU-GPU collaborative computing strategy, calling the local CPU to generate a wafer defect detection subtask corresponding to each target sub-image, and assigning the wafer defect detection subtask to multiple CUDA thread blocks corresponding to the local GPU; Based on the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, multiple target sub-images are processed in parallel to determine a binary mask corresponding to the preset first resolution image.

[0008] In one embodiment, the step of processing a plurality of target sub-images in parallel based on the plurality of CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block further includes: Based on the shared memory strategy, the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, the FAST corner point of each target sub-image is detected in parallel to obtain the target FAST corner point corresponding to each target sub-image; Determine a BRIEF descriptor corresponding to each target sub-image based on the target FAST corner point; Based on the BRIEF descriptor, an initial binary mask of each target sub-image block is calculated.

[0009] In one embodiment, the step of performing a block operation on the preset first resolution image based on a preset image size to obtain a plurality of target sub-images further includes: Performing pyramid downsampling on the preset first resolution image to reduce the resolution of the preset first resolution image to obtain a preset second resolution image; Using a two-dimensional Gaussian filter kernel to suppress noise on the preset second resolution image to obtain a target image; Based on a preset image size, a block operation is performed on the target image to obtain a plurality of target sub-images.

[0010] In one embodiment, the BRIEF descriptor is a binary vector, and the step of determining the BRIEF descriptor corresponding to each target sub-image based on the target FAST corner point further includes: Get an initialized BRIEF descriptor string, where each character corresponding to the initialized BRIEF descriptor string is 0; Based on the multiple threads included in the CUDA thread block and the target FAST corner point, performing a determine-modify atomic operation on multiple characters in the initialized BRIEF descriptor string in parallel to determine a BRIEF descriptor corresponding to each target sub-image; The step of performing the judgment-modification atomic operation on multiple characters in the initialized BRIEF descriptor string in parallel includes: Determine whether each character in the initialized BRIEF descriptor string meets the modification requirements; If satisfied, the character that meets the modification requirement will be changed from 0 to 1.

[0011] In one embodiment, the step of determining whether a wafer has defects based on a preset wafer defect determination rule and the binary mask to obtain a wafer defect detection result further includes: Optimizing the initial binary mask based on a connected domain identification optimization strategy to obtain a target binary mask; Based on the target binary mask and preset defect judgment rules, judging whether each target sub-image has defects, and obtaining multiple initial judgment results; Based on all the initial judgment results, determine whether the wafer has defects and obtain the wafer defect detection result.

[0012] In one embodiment, the step of optimizing the initial binary mask based on the connected domain identification optimization strategy to obtain a target binary mask further includes: Based on the connected domain identification optimization strategy and the preset small image block size, each target sub-image is divided into multiple small image blocks, wherein the small image blocks are independently marked with connected domains in the GPU shared memory; Determine the label of each pixel in each small image block, merge equivalent labels based on atomic operations, and obtain the initial merge result; Based on a tree-like recursive merging strategy and a 3D thread block index, boundary pixels of adjacent small image blocks are merged layer by layer to optimize the initial merging result and obtain a target binary mask.

[0013] In addition, to achieve the above-mentioned purpose, the present application also proposes a wafer defect detection device, which includes: A receiving module, configured to receive an image of a corresponding wafer captured by a camera at a preset first resolution in response to a wafer defect detection instruction; A data processing module, configured to process the preset first resolution image in parallel based on a CPU-GPU collaborative computing strategy to determine a binary mask corresponding to the preset first resolution image; The judgment module is used to judge whether the wafer has defects based on preset wafer defect judgment rules and the binary mask to obtain a wafer defect detection result.

[0014] In one embodiment, the data processing module further includes: A first blocking unit is configured to perform a blocking operation on the image with the preset first resolution based on a preset image size to obtain a plurality of target sub-images; A calling unit is configured to call a local CPU to generate a wafer defect detection subtask corresponding to each target sub-image based on the wafer defect detection instruction and the CPU-GPU collaborative computing strategy, and to allocate the wafer defect detection subtask to multiple CUDA thread blocks corresponding to the local GPU; A data processing unit is configured to process a plurality of target sub-images in parallel based on the plurality of CUDA thread blocks and the wafer defect detection sub-task corresponding to each CUDA thread block, so as to determine a binary mask corresponding to the preset first resolution image.

[0015] In one embodiment, the data processing module further includes: A detection unit is configured to detect the FAST corner points of each target sub-image in parallel based on a shared memory strategy, the multiple CUDA thread blocks, and a wafer defect detection subtask corresponding to each CUDA thread block, to obtain a target FAST corner point corresponding to each target sub-image; A first determining unit is configured to determine a BRIEF descriptor corresponding to each target sub-image based on the target FAST corner point; A calculation unit is used to calculate an initial binary mask of each target sub-image block based on the BRIEF descriptor.

[0016] In one embodiment, the data processing module further includes: a resolution reduction unit, configured to perform pyramid downsampling on the preset first resolution image to reduce the resolution of the preset first resolution image to obtain a preset second resolution image; a noise suppression unit, configured to perform noise suppression on the preset second resolution image using a two-dimensional Gaussian filter kernel to obtain a target image; The second blocking unit is configured to perform a blocking operation on the target image based on a preset image size to obtain a plurality of target sub-images.

[0017] In one embodiment, the data processing module further includes: An acquiring unit, configured to acquire an initialized BRIEF descriptor string, wherein each character corresponding to the initialized BRIEF descriptor string is 0; a first modifying unit, configured to perform a determination-modification atomic operation on a plurality of characters in the initialized BRIEF descriptor string in parallel based on a plurality of threads included in the CUDA thread block and the target FAST corner point, so as to determine a BRIEF descriptor corresponding to each target sub-image; The step of performing the judgment-modification atomic operation on multiple characters in the initialized BRIEF descriptor string in parallel includes: A first judging unit, configured to judge whether each character in the initialized BRIEF descriptor string meets a modification requirement; The second modification unit is used to modify the character that meets the modification requirement from 0 to 1 if the requirement is met.

[0018] In one embodiment, the judgment module further includes: an optimization unit, configured to optimize the initial binary mask based on a connected domain identification optimization strategy to obtain a target binary mask; A second judgment unit is configured to judge whether each target sub-image has a defect based on the target binary mask and a preset defect judgment rule, and obtain a plurality of initial judgment results; The second determination unit is configured to determine whether the wafer has defects based on all initial judgment results, and obtain a wafer defect detection result.

[0019] In one embodiment, the judgment module further includes: a partitioning unit, configured to partition each target sub-image into a plurality of small image blocks based on a connected domain identification optimization strategy and a preset small image block size, wherein the small image blocks are independently subjected to connected domain labeling in a GPU shared memory; A third determining unit is used to determine the label of each pixel in each small image block, merge equivalent labels based on atomic operations, and obtain an initial merged result; The merging unit is used to merge the boundary pixels of adjacent small image blocks layer by layer based on a tree-like recursive merging strategy and a 3D thread block index to optimize the initial merging result and obtain a target binary mask.

[0020] In addition, to achieve the above-mentioned purpose, the present application also proposes a wafer defect detection device, which includes: a memory, a processor, and a computer program stored on the memory and runnable on the processor, and the computer program is configured to implement the steps of the wafer defect detection method described above.

[0021] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by the processor, the steps of the wafer defect detection method described above are implemented.

[0022] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the steps of the wafer defect detection method described above.

[0023] One or more technical solutions proposed in this application have at least the following technical effects: This application proposes a wafer defect detection method and related equipment, which relate to the field of data processing technology. Compared to related technologies, wafer defect detection equipment uses high-resolution TDI line scan cameras (such as Teledyne's 16k / 5μm resolution Linea HS2 series) for image acquisition. Its single-image data throughput is as high as 16G pixels / second. Although it can capture micron-level defects (such as Micro LED die scratches below 50μm), the massive amount of data significantly reduces the real-time performance of traditional processing algorithms. In this application, first, in response to a wafer defect detection instruction, a camera captures a preset first-resolution image of the corresponding wafer. Then, based on a CPU-GPU collaborative computing strategy, the preset first-resolution image is processed in parallel to determine a binary mask corresponding to the preset first-resolution image. Finally, based on preset wafer defect judgment rules and the binary mask, a determination is made as to whether the wafer has defects to obtain a wafer defect detection result. This application utilizes a CPU-GPU collaborative computing strategy to parallelly process the preset first-resolution image, thereby increasing the image processing speed and, in turn, improving the real-time performance of wafer defect detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 A schematic diagram of a process flow provided for the first embodiment of the wafer defect detection method of the present application; Figure 2 A schematic diagram of a process flow provided for the second embodiment of the wafer defect detection method of the present application; Figure 3 A schematic diagram of a process flow provided for Example 3 of the wafer defect detection method of the present application; Figure 4 This is a schematic diagram of the module structure of the wafer defect detection device according to an embodiment of the present application; Figure 5 This is a schematic diagram of the device structure of the hardware operating environment involved in the wafer defect detection method in the embodiment of the present application.

[0027] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0028] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0029] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0030] The main solutions of the embodiments of this application are: In this embodiment, for ease of description, the following description is made with the wafer defect detection equipment as the execution subject.

[0031] Due to related technologies: Wafer defect inspection equipment uses high-resolution TDI line scan cameras (such as Teledyne's 16k / 5μm resolution Linea HS2 series) for image acquisition. Its single image data throughput is as high as 16G pixels / second. Although it can capture micron-level defects (such as Micro LED grain scratches below 50μm), the massive amount of data causes the real-time performance of traditional processing algorithms to be significantly reduced.

[0032] The present application provides a solution that: first, in response to a wafer defect detection instruction, receives a preset first resolution image of the corresponding wafer captured by a camera; then, based on a CPU-GPU collaborative computing strategy, processes the preset first resolution image in parallel to determine a binary mask corresponding to the preset first resolution image; finally, based on a preset wafer defect judgment rule and the binary mask, determines whether the wafer has defects to obtain a wafer defect detection result. The present application uses a CPU-GPU collaborative computing strategy to process the preset first resolution image in parallel, thereby increasing the speed of image processing and, in turn, increasing the real-time performance of wafer defect detection.

[0033] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, mobile phone, etc., or an electronic device capable of performing the above functions, such as a wafer defect detection device. The following uses a wafer defect detection device as an example to illustrate this embodiment and the following embodiments.

[0034] Based on this, the embodiment of the present application provides a wafer defect detection method, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the wafer defect detection method of the present application.

[0035] In this embodiment, the wafer defect detection method includes steps S100 to S300: Step S100, in response to a wafer defect detection instruction, receiving a camera to capture a preset first resolution image of a corresponding wafer; It's important to note that a wafer defect inspection instruction is a clear command that initiates the wafer defect inspection process. In semiconductor manufacturing, wafers are the fundamental material for chip manufacturing, and inspecting for defects (such as scratches, particle contamination, and crystal structure defects) on wafers is crucial for ensuring product quality. This instruction may be manually entered by an operator or automatically issued by an automated system based on the production process.

[0036] In this embodiment, the system receives image data from a camera. The camera is part of the inspection system and can be a high-magnification TDI camera, used to capture images of the wafer. The camera's function is to capture the wafer surface in the form of an image for subsequent analysis.

[0037] It should be noted that the "preset first resolution image" means that the image resolution is pre-set, not the camera's default resolution or a randomly selected resolution. "First resolution" indicates a specific resolution level, designed to meet certain inspection accuracy requirements. For example, detecting large defects may not require very high resolution, while detecting tiny crystal defects may require a higher resolution. This resolution is set based on the specific requirements of the inspection task and is a key parameter in the inspection process.

[0038] Furthermore, when the system receives a command to initiate wafer defect inspection, it receives an image of the wafer being inspected, captured by the camera at a predetermined resolution (a first resolution). This process is part of the automated inspection system and ensures that wafers are inspected to predetermined accuracy and standards.

[0039] Step S200: Based on a CPU-GPU collaborative computing strategy, the preset first resolution image is processed in parallel to determine a binary mask corresponding to the preset first resolution image; It should be noted that the CPU (Central Processing Unit) is the main processor of a computer, which is good at handling complex logical operations and sequential execution tasks. It is usually used to control the flow of programs, execute algorithms, etc.

[0040] It should be noted that GPU (graphics processing unit) was originally used for graphics rendering, but with the development of technology, GPU has been widely used in general computing tasks due to its parallel processing capabilities, especially when processing large amounts of data and parallel tasks.

[0041] It's important to note that the "CPU-GPU collaborative computing strategy" is a computing architecture that leverages the strengths of both the CPU and the GPU by distributing tasks. The CPU handles complex logic control and serial tasks, while the GPU handles parallel computing tasks, such as pixel-level operations in image processing. This collaborative strategy can significantly improve computing efficiency, especially when processing large amounts of data or complex tasks.

[0042] It's important to note that parallel processing refers to the simultaneous processing of multiple tasks or pieces of data. In image processing, this means operating on multiple parts of an image simultaneously, rather than processing each pixel one at a time. Parallel processing can significantly reduce processing time, especially when using GPUs, which excel at processing large amounts of data simultaneously.

[0043] It's important to note that in image processing, a binary mask is a special image in which the pixel values ​​can only be 0 (black) or 1 (white). It's often used to represent specific areas or features within an image. For example, in defect detection, a binary mask can be used to mark the location of a defect, with white pixels representing the defective area and black pixels representing the non-defective area.

[0044] Specifically, the step of processing the preset first resolution image in parallel based on the CPU-GPU collaborative computing strategy to determine the binary mask corresponding to the preset first resolution image further includes steps S210 to S230: Step S210, performing a block operation on the preset first resolution image based on a preset image size to obtain a plurality of target sub-images; It's important to note that the preset image size refers to pre-set image size parameters. These parameters define how the original image is split into multiple sub-images. For example, you can specify the width and height (in pixels) of each sub-image, or the number of rows and columns of sub-images to split the image into.

[0045] It's important to note that tile partitioning is the process of dividing a large image into multiple smaller sub-images. This operation is very common in image processing, especially when processing large images. Tiling can simplify computational complexity and improve processing efficiency. For example, in image analysis, feature extraction, or deep learning, large images are often partitioned into multiple smaller tiles, each of which is then processed separately.

[0046] As you can understand, the result of the blocking operation is multiple smaller image blocks, called "target sub-images." Each sub-image contains a portion of the original image, but is smaller in size, making it easier to process. For example, if a 1024×1024 pixel image is split into 64×64 pixel sub-images, 256 target sub-images (16×16) are obtained.

[0047] Specifically, the step of performing a block operation on the preset first resolution image based on the preset image size to obtain a plurality of target sub-images further includes steps S211 to S213: Step S211, performing pyramid downsampling on the preset first resolution image to reduce the resolution of the preset first resolution image to obtain a preset second resolution image; Pyramid downsampling is an image downsampling technique inspired by the concept of an image pyramid. An image pyramid is a multi-resolution representation method that generates a series of images of varying resolutions by progressively reducing the resolution of an image. Pyramid downsampling typically involves smoothing filtering (filtering the original image to reduce high-frequency components and prevent aliasing during the downsampling process) and downsampling (subtracting every other pixel from the filtered image to generate a lower-resolution image. For example, subtracting every other pixel would reduce the image's width and height by half).

[0048] It should be noted that the purpose of downsampling is to reduce the resolution of an image to a lower level. This is usually done to meet the needs of subsequent processing, such as reducing the amount of calculation, increasing processing speed, or adapting to the input image resolution requirements of certain algorithms.

[0049] The preset second resolution is the target resolution after downsampling. It is pre-set. This resolution is usually lower than the first resolution, but the specific value depends on the application scenario and requirements.

[0050] Step S212, using a two-dimensional Gaussian filter kernel to perform noise suppression on the preset second resolution image to obtain a target image; Gaussian filtering is a commonly used image smoothing technique that filters images based on a Gaussian function (normal distribution function). The Gaussian filter kernel is a two-dimensional matrix whose values ​​are weights calculated using the Gaussian function.

[0051] The Gaussian filter kernel is a two-dimensional matrix that performs a weighted average of each pixel in an image and its neighborhood. This filtering method can effectively smooth an image while preserving its key features.

[0052] Image noise refers to unwanted, random interference signals in an image. It may originate from sensor noise, environmental interference, or other factors during the image acquisition process. The goal of noise suppression is to reduce these interferences to make the image clearer and smoother. Gaussian filtering is an effective noise suppression method because it smooths out random noise by taking a weighted average of the pixels and their neighborhood.

[0053] Convolution of an image with a Gaussian filter kernel can effectively reduce noise in the image. The weight distribution of the Gaussian filter kernel makes the neighboring pixels of the central pixel contribute to the value of the central pixel, thereby smoothing out local random variations.

[0054] The target image is the final image after noise suppression. This image is smoother than the original preset second resolution image, with noise suppressed while retaining the main features of the image.

[0055] As can be understood, a two-dimensional Gaussian filter kernel is used to perform noise suppression on the preset second-resolution image obtained in the previous step. Through the convolution operation of the Gaussian filter kernel, the noise in the image is smoothed out, ultimately resulting in a clearer and smoother target image. This processing method is suitable for scenarios where image noise reduction is required while preserving the image's key features, such as in tasks such as image analysis, object detection, or image enhancement.

[0056] Step S213 : performing a block operation on the target image based on a preset image size to obtain a plurality of target sub-images.

[0057] Step S220: Based on the wafer defect detection instruction and the CPU-GPU collaborative computing strategy, calling the local CPU, generating a wafer defect detection subtask corresponding to each target sub-image, and assigning the wafer defect detection subtask to multiple CUDA thread blocks corresponding to the local GPU; In this step, the system generates an independent wafer defect inspection subtask for each target sub-image, which means that each sub-image will be processed separately to detect possible defects.

[0058] The wafer defect detection subtask is an inspection task for each target sub-image. The goal of each subtask is to check whether there are defects in the sub-image, such as scratches, particle contamination, or crystal structure defects.

[0059] CUDA thread blocks: CUDA is a parallel computing platform and programming model developed by NVIDIA for computing on NVIDIA GPUs. In CUDA, thread blocks are the basic unit of parallel execution, and each thread block contains multiple threads. By distributing tasks across multiple thread blocks, the parallel computing capabilities of the GPU can be fully utilized.

[0060] In this embodiment, based on wafer defect detection instructions and a CPU-GPU collaborative computing strategy, the system first invokes the local CPU to generate wafer defect detection subtasks for each target sub-image. The system then distributes these subtasks to multiple CUDA thread blocks on the local GPU, efficiently executing them using the GPU's parallel computing capabilities. This task allocation and parallel processing mechanism can significantly improve wafer defect detection efficiency, especially when processing a large number of sub-images.

[0061] Step S230 : Based on the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, multiple target sub-images are processed in parallel to determine a binary mask corresponding to the preset first resolution image.

[0062] In the previous steps, the system has decomposed the wafer defect inspection task into multiple subtasks and assigned these subtasks to different CUDA thread blocks. Each thread block is responsible for processing the defect inspection task of a specific target sub-image.

[0063] It should be noted that in a GPU, due to its powerful parallel computing capabilities, multiple CUDA thread blocks can simultaneously process multiple target sub-images. This parallel processing method can significantly improve processing speed, especially when processing large amounts of data.

[0064] In this embodiment, based on the wafer defect detection subtasks assigned to each CUDA thread block in the previous step, the system leverages the parallel computing capabilities of the GPU to simultaneously process multiple target sub-images. This ultimately generates a binary mask corresponding to the initial image, marking the defect locations. This parallel processing approach can significantly improve defect detection efficiency, especially when processing high-resolution images or large amounts of image data.

[0065] Specifically, the step of processing multiple target sub-images in parallel based on the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block further includes steps S231 to S233: Step S231, based on the shared memory strategy, the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, parallelly detecting the FAST corner points of each target sub-image to obtain the target FAST corner points corresponding to each target sub-image; It should be noted that in CUDA programming, shared memory is a high-speed memory located on the GPU that can be quickly accessed by all threads in the same thread block. The use of shared memory can significantly improve data access speed, especially when processing image data, because there is usually spatial locality between image pixels (adjacent pixels are often accessed together).

[0066] FAST (Features from Accelerated Segment Test) is a fast corner detection algorithm. It identifies corners by detecting local brightness changes in pixels within an image. The FAST algorithm boasts fast computational speed, making it suitable for real-time applications and large-scale image processing.

[0067] It is understandable that since the FAST corner detection task for each target sub-image is independent, the parallel computing capability of the GPU can be utilized to perform corner detection on multiple target sub-images simultaneously. Each CUDA thread block can independently process the FAST corner detection task for a target sub-image.

[0068] Target FAST corner points are the output of the FAST corner detection algorithm. For each target sub-image, the FAST algorithm detects corner points and outputs them as detection results. These corner points can be used for subsequent image analysis, such as feature matching, object recognition, or defect detection.

[0069] In this embodiment, the system leverages a shared memory strategy and the parallel computing capabilities of the GPU to simultaneously process multiple target sub-images using multiple CUDA thread blocks. Each thread block is responsible for detecting FAST corner points in a single target sub-image. In this way, the system efficiently generates a set of FAST corner points corresponding to each target sub-image. This parallel processing approach can significantly improve the speed of corner detection, especially when processing a large number of sub-images.

[0070] Step S232, determining a BRIEF descriptor corresponding to each target sub-image based on the target FAST corner point; BRIEF (Binary Robust Independent Elementary Features) is a binary feature descriptor used to describe the local information of feature points in an image. Its main advantages are fast computation, high storage efficiency, and robustness to changes in illumination and viewpoint. It generates binary strings by comparing the brightness of pairs of pixels within the neighborhood of a feature point. These strings can then be used for feature matching.

[0071] In this application, for each target sub-image, the system will calculate a BRIEF descriptor for each detected FAST corner point. The specific steps are as follows: Step 1: Select pixel pairs: In the neighborhood of each FAST corner point, select a set of predefined pixel pairs. The positions of these pixel pairs are fixed and are usually determined during algorithm design.

[0072] Step 2, compare brightness: For each pair of pixels, compare their brightness. If the brightness of one pixel is greater than the brightness of the other pixel, record a "1" in the descriptor, otherwise record a "0".

[0073] Step 3: Generate a binary string: Generate a binary string through the above comparison, which is the BRIEF descriptor.

[0074] In this embodiment, based on the FAST corner points detected in each target sub-image in the previous step, the system calculates a BRIEF descriptor for each corner point. These descriptors are in binary form and are used to describe the local features of the corner point. In this way, the system can efficiently generate feature descriptors for each target sub-image, which can be used for subsequent tasks such as feature matching, object recognition, or defect detection.

[0075] Step S233 : Calculate an initial binary mask of each target sub-image block based on the BRIEF descriptor.

[0076] In this embodiment, the system will use the BRIEF descriptor to generate an initial binary mask for each target sub-image block. The specific steps may include: Feature matching: Match the BRIEF descriptor in the current target sub-image block with known feature descriptors (e.g., standard templates or marked defect features).

[0077] Threshold determination: Based on the matching results, determine which pixels belong to the feature area of ​​interest (for example, the defect area). Usually, a threshold is set, and only pixels with a matching degree higher than the threshold are marked as 1 (white), and the rest are marked as 0 (black).

[0078] Generate a binary mask: Based on the above judgment, a binary image is generated, in which white pixels represent the detected feature areas and black pixels represent the background or other non-feature areas.

[0079] It will be appreciated that in this embodiment, the system uses the BRIEF descriptors calculated in the previous steps to generate an initial binary mask for each target sub-image block. This binary mask marks possible defects or other feature areas of interest in the image through feature matching and threshold determination. The generated initial binary mask can be used for subsequent analysis or processing, such as defect detection, feature statistics, or image segmentation.

[0080] Step S300 , based on a preset wafer defect judgment rule and the binary mask, it is judged whether the wafer has defects to obtain a wafer defect detection result.

[0081] Preset wafer defect judgment rules are a set of predefined rules used to determine whether a wafer has defects. These rules are typically developed based on the wafer's manufacturing process, quality standards, and defect characteristics. For example, rules may include: minimum or maximum defect area limits, defect shape characteristics (such as circular, linear, etc.), defect distribution density (such as the number of defects per unit area), defect grayscale or color characteristics, and contrast thresholds between defects and normal areas.

[0082] In this embodiment, the system needs to determine whether there are defects on the wafer by combining preset judgment rules and information in the binary mask. The specific steps may include: Analyze binary mask: Check the distribution of white pixels in the binary mask to determine the preliminary location and shape of the defect.

[0083] Apply judgment rules: Verify each possible defect area according to preset rules. For example, check whether the defect area is within the allowable range, whether the shape is as expected, and whether the contrast is sufficient.

[0084] Comprehensive judgment: Based on the above analysis and verification results, it is finally determined whether the wafer has defects.

[0085] Furthermore, it's important to note that wafer defect inspection results are the final output of the entire defect inspection process. These results typically provide a clear judgment, such as "wafer defective" or "wafer free." Furthermore, these results include detailed information such as the specific location, number, and type of defects.

[0086] In this embodiment, the system analyzes and determines whether a wafer has defects based on the preset wafer defect judgment rules and the binary mask generated in the previous steps. This determines the presence of defects and ultimately yields a wafer defect detection result. The preset judgment rules provide a basis for judgment, while the binary mask provides preliminary defect location information. The combination of the two enables efficient and accurate defect detection.

[0087] This embodiment provides a wafer defect detection method and related equipment, relating to the field of data processing technology. Compared to related technologies, wafer defect detection equipment uses a high-resolution TDI line scan camera (such as Teledyne's 16k / 5μm resolution Linea HS2 series) for image acquisition. Its single-image data throughput is as high as 16G pixels / second. Although it can capture micron-level defects (such as Micro LED die scratches below 50μm), the massive amount of data significantly reduces the real-time performance of traditional processing algorithms. In this application, first, in response to a wafer defect detection instruction, a camera is received to capture a preset first-resolution image of the corresponding wafer. Then, based on a CPU-GPU collaborative computing strategy, the preset first-resolution image is processed in parallel to determine a binary mask corresponding to the preset first-resolution image. Finally, based on preset wafer defect judgment rules and the binary mask, a determination is made as to whether the wafer has defects to obtain a wafer defect detection result. This application utilizes a CPU-GPU collaborative computing strategy to parallelly process the preset first-resolution image, thereby increasing the speed of image processing and, thereby, improving the real-time performance of wafer defect detection.

[0088] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above embodiment 1 can be referred to the above introduction and will not be described in detail later. Figure 2 , the BRIEF descriptor is a binary vector, and the step of determining the BRIEF descriptor corresponding to each target sub-image based on the target FAST corner point further includes steps A100 to A200: Step A100, obtaining an initialized BRIEF descriptor string, wherein each character corresponding to the initialized BRIEF descriptor string is 0; Step A200, based on the multiple threads included in the CUDA thread block and the target FAST corner point, performing a determine-modify atomic operation on the multiple characters in the initialized BRIEF descriptor string in parallel to determine the BRIEF descriptor corresponding to each target sub-image; It's important to note that in the CUDA programming model, thread blocks are the basic unit of parallel execution. Each thread block contains multiple threads, which can share resources within the thread block (such as shared memory) and work collaboratively. The number of threads in each thread block can be configured based on hardware and task requirements. These threads can execute in parallel, improving computational efficiency.

[0089] In the BRIEF descriptor string, each character corresponds to a binary bit (0 or 1). These bits are modified based on the local characteristics of the FAST corner points. Leveraging CUDA's parallel computing capabilities, multiple threads can simultaneously operate on multiple characters (i.e., bits in the BRIEF descriptor string). This parallel processing significantly improves computational efficiency.

[0090] Specifically, the operation is performed on each bit in the BRIEF descriptor string. The specific steps are as follows: Detection: For each FAST corner point, select a pair of pixels (the positions of these pixels are predefined) and compare their brightness. If the brightness of one pixel is greater than the brightness of the other pixel, the corresponding bit needs to be set to 1, otherwise it remains 0.

[0091] Modification: Based on the judgment result, the corresponding bit in the BRIEF descriptor string is modified. Because multiple threads may access and modify the same string simultaneously, atomic operations are required to ensure data consistency and correctness. Atomic operations are indivisible operations that prevent conflicts when multiple threads modify the same data simultaneously.

[0092] It's important to note that in CUDA, atomic operations are used to ensure thread-safe modifications to shared data. For example, atomic operations like atomicAdd and atomicExch can be used to safely update integers or floating-point numbers. When manipulating binary bits, atomic operations can be used to ensure that modifications to each bit are not interfered with by other threads.

[0093] Specifically, the step of performing the judgment-modification atomic operation on multiple characters in the initialized BRIEF descriptor string in parallel includes steps A210 to A220: Step A210, determining whether each character in the initialized BRIEF descriptor string meets the modification requirements; Step A220: If the condition is met, the character that meets the modification requirement is changed from 0 to 1.

[0094] As will be appreciated, in this embodiment, multiple threads within a CUDA thread block are used to process the FAST corner points in each target sub-image in parallel, updating each bit in the initialized BRIEF descriptor string through atomic check-and-modify operations. Ultimately, the system generates a BRIEF descriptor for each FAST corner point in each target sub-image. This parallel processing approach can significantly speed up BRIEF descriptor generation, especially when processing a large number of corner points and sub-images.

[0095] Based on the first and second embodiments of the present application, in the third embodiment of the present application, the same or similar contents as those in the first and second embodiments can be referred to above and will not be described in detail. Figure 3 The step of determining whether a wafer has defects based on a preset wafer defect determination rule and the binary mask to obtain a wafer defect detection result further includes steps B100 to B300: Step B100, optimizing the initial binary mask based on the connected domain identification optimization strategy to obtain a target binary mask; It should be noted that in a binary image, a connected domain is a group of interconnected pixels that have the same value (usually white pixels, indicating the target area). For example, in a binary mask, a connected domain may represent a single defect, an object, or a feature area.

[0096] Connected component identification is used to identify and label all connected components in a binary image. This is typically achieved using a connected component labeling algorithm (such as a scan-based algorithm or a queue-based algorithm). Each connected component is assigned a unique identifier.

[0097] Optimization strategies refer to methods for analyzing and processing connected domains in order to improve the quality of the initial binary mask. Optimization strategies include: Removing small connected domains: If the area of ​​some connected domains is smaller than a preset threshold, they may be considered as noise or unimportant features and can be removed.

[0098] Merge similar connected domains: If the distance between two connected domains is less than a certain threshold, they can be merged into a larger connected domain.

[0099] Shape analysis and filtering: The shape characteristics of the connected domain (such as aspect ratio, circularity, etc.) are used to determine whether it meets the expected characteristics. Those that do not meet the requirements can be removed or adjusted.

[0100] Contrast enhancement: By analyzing the contrast between the connected domain and the background, the saliency of the target area is further enhanced.

[0101] It should be noted that the target binary mask is the final optimized binary mask, which more accurately represents the target area (such as defects, objects, etc.) in the image. The target binary mask is the basis for subsequent image analysis or processing (such as defect detection and object recognition).

[0102] In this embodiment, the initial binary mask is processed using a connected component identification optimization strategy to remove noise, merge similar regions, and adjust the shape, thereby obtaining a more accurate target binary mask. This optimization process can significantly improve the quality of the binary mask, making it more suitable for subsequent image analysis and processing tasks.

[0103] Specifically, the step of optimizing the initial binary mask based on the connected domain identification optimization strategy to obtain the target binary mask further includes steps B110 to B130: Step B110: dividing each target sub-image into a plurality of small image blocks based on a connected component identification optimization strategy and a preset small image block size, wherein the small image blocks are independently subjected to connected component identification in a GPU shared memory; Step B120: determine the label of each pixel in each small image block, merge equivalent labels based on atomic operations, and obtain an initial merged result; Step B130 : Based on the tree-like recursive merging strategy and the 3D thread block index, the boundary pixels of adjacent small image blocks are merged layer by layer to optimize the initial merging result and obtain a target binary mask.

[0104] The preset tile size refers to the size of the tiles (tiles) used to divide an image into when processing it. The tile size is pre-set and typically determined based on the image size and processing requirements. For example, if the image is large, it can be divided into multiple smaller tiles for parallel processing on the GPU.

[0105] In this application, each target sub-image is further divided into smaller regions (tiles). This division allows each tile to be processed independently, leveraging the parallel computing capabilities of the GPU. This significantly improves processing speed, especially when processing large images.

[0106] It should be noted that each small image block is loaded into the GPU's shared memory and connected components are marked independently. This means that the processing of each small image block will not interfere with each other and can be executed in parallel. The connected component marking process generally includes: Scan pixels in small image blocks: Check the pixel values ​​in small image blocks one by one.

[0107] Assign labels: Assign a unique label to each connected domain.

[0108] Optimize labels: Optimize strategies based on connected domain identification, such as removing small connected domains and merging similar connected domains.

[0109] In this embodiment, each target sub-image is divided into multiple smaller tiles based on preset tile sizes. Each tile is then loaded into the GPU's shared memory, and connected component labeling is performed independently. This approach leverages the GPU's parallel computing capabilities to efficiently process each tile, while also improving the efficiency and accuracy of connected component labeling. This method is particularly suitable for processing large images or scenarios requiring rapid processing.

[0110] Step B200, judging whether each target sub-image has defects based on the target binary mask and preset defect judgment rules, and obtaining multiple initial judgment results; Step B300: Based on all the initial judgment results, determine whether the wafer has defects and obtain the wafer defect detection result.

[0111] The initial judgment result is the judgment result of each target sub-image, indicating whether the sub-image has defects. The initial judgment result can be "defects exist" or "no defects".

[0112] In this application, the initial judgment results of all target sub-images are combined to determine whether the entire wafer has defects. This step usually includes: Count the number of defects: Count the number of defects marked as "existing defects" in all sub-images.

[0113] Evaluate defect distribution: Analyze the distribution of defects on the wafer, such as whether they are concentrated in a certain area.

[0114] Apply comprehensive judgment rules: Determine whether the entire wafer meets quality standards based on preset comprehensive judgment rules (for example, the maximum number of defects allowed, the uniformity of defect distribution, etc.).

[0115] It's important to note that wafer defect inspection results are the final output of the entire wafer defect inspection process. These results are typically a clear judgment, such as "wafer defective" or "wafer free." They may also include detailed information such as the specific location, number, and type of defects.

[0116] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the wafer defect detection method of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0117] This application also provides a wafer defect detection device, please refer to Figure 4 , the wafer defect detection device comprises: A receiving module 10, configured to receive an image of a corresponding wafer captured by a camera at a preset first resolution in response to a wafer defect detection instruction; A data processing module 20 is configured to process the preset first resolution image in parallel based on a CPU-GPU collaborative computing strategy to determine a binary mask corresponding to the preset first resolution image; The judgment module 30 is used to judge whether the wafer has defects based on preset wafer defect judgment rules and the binary mask to obtain a wafer defect detection result.

[0118] In one embodiment, the data processing module further includes: A first blocking unit is configured to perform a blocking operation on the image with the preset first resolution based on a preset image size to obtain a plurality of target sub-images; A calling unit is configured to call a local CPU to generate a wafer defect detection subtask corresponding to each target sub-image based on the wafer defect detection instruction and the CPU-GPU collaborative computing strategy, and to allocate the wafer defect detection subtask to multiple CUDA thread blocks corresponding to the local GPU; A data processing unit is configured to process a plurality of target sub-images in parallel based on the plurality of CUDA thread blocks and the wafer defect detection sub-task corresponding to each CUDA thread block, so as to determine a binary mask corresponding to the preset first resolution image.

[0119] In one embodiment, the data processing module further includes: A detection unit is configured to detect the FAST corner points of each target sub-image in parallel based on a shared memory strategy, the multiple CUDA thread blocks, and a wafer defect detection subtask corresponding to each CUDA thread block, to obtain a target FAST corner point corresponding to each target sub-image; A first determining unit is configured to determine a BRIEF descriptor corresponding to each target sub-image based on the target FAST corner point; A calculation unit is used to calculate an initial binary mask of each target sub-image block based on the BRIEF descriptor.

[0120] In one embodiment, the data processing module further includes: a resolution reduction unit, configured to perform pyramid downsampling on the preset first resolution image to reduce the resolution of the preset first resolution image to obtain a preset second resolution image; a noise suppression unit, configured to perform noise suppression on the preset second resolution image using a two-dimensional Gaussian filter kernel to obtain a target image; The second blocking unit is configured to perform a blocking operation on the target image based on a preset image size to obtain a plurality of target sub-images.

[0121] In one embodiment, the data processing module further includes: An acquiring unit, configured to acquire an initialized BRIEF descriptor string, wherein each character corresponding to the initialized BRIEF descriptor string is 0; a first modifying unit, configured to perform a determination-modification atomic operation on a plurality of characters in the initialized BRIEF descriptor string in parallel based on a plurality of threads included in the CUDA thread block and the target FAST corner point, so as to determine a BRIEF descriptor corresponding to each target sub-image; The step of performing the judgment-modification atomic operation on multiple characters in the initialized BRIEF descriptor string in parallel includes: A first judging unit, configured to judge whether each character in the initialized BRIEF descriptor string meets a modification requirement; The second modification unit is used to modify the character that meets the modification requirement from 0 to 1 if the requirement is met.

[0122] In one embodiment, the judgment module further includes: an optimization unit, configured to optimize the initial binary mask based on a connected domain identification optimization strategy to obtain a target binary mask; A second judgment unit is configured to judge whether each target sub-image has a defect based on the target binary mask and a preset defect judgment rule, and obtain a plurality of initial judgment results; The second determination unit is configured to determine whether the wafer has defects based on all initial judgment results, and obtain a wafer defect detection result.

[0123] In one embodiment, the judgment module further includes: a partitioning unit, configured to partition each target sub-image into a plurality of small image blocks based on a connected domain identification optimization strategy and a preset small image block size, wherein the small image blocks are independently subjected to connected domain labeling in a GPU shared memory; A third determining unit is used to determine the label of each pixel in each small image block, merge equivalent labels based on atomic operations, and obtain an initial merged result; The merging unit is used to merge the boundary pixels of adjacent small image blocks layer by layer based on a tree-like recursive merging strategy and a 3D thread block index to optimize the initial merging result and obtain a target binary mask.

[0124] The wafer defect detection device provided in this application utilizes the wafer defect detection method of the above-described embodiment to solve the technical problem of wafer defect detection. Compared with related technologies, the beneficial effects of the wafer defect detection device provided in this application are the same as those of the wafer defect detection method provided in the above-described embodiment. Other technical features of the wafer defect detection device are the same as those disclosed in the above-described embodiment and are not further described here.

[0125] The present application provides a wafer defect detection device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the wafer defect detection method in the above-mentioned embodiment one.

[0126] Reference below Figure 5 , which shows a schematic diagram of the structure of a wafer defect detection device suitable for implementing the embodiments of the present application. The wafer defect detection device in the embodiments of the present application may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 5 The wafer defect detection device shown is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0127] like Figure 5As shown, the wafer defect inspection equipment may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in a read-only memory (ROM) 1002 or programs loaded from a storage device 1003 into a random access memory (RAM) 1004. RAM 1004 also stores various programs and data required for the operation of the wafer defect inspection equipment. Processing device 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to I / O interface 1006: input devices 1007, such as a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008, such as a liquid crystal display (LCD), speaker, vibrator, etc.; storage device 1003, such as a magnetic tape or hard disk; and communication devices 1009. The communication device 1009 can allow the wafer defect inspection apparatus to communicate wirelessly or wired with other equipment to exchange data. Although the figure shows a wafer defect inspection apparatus with various systems, it should be understood that it is not required to implement or have all of the systems shown. More or fewer systems may be implemented or have alternatively.

[0128] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program comprising program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0129] The wafer defect detection device provided by this application, which employs the wafer defect detection method of the above-mentioned embodiment, can solve the technical problems. Compared with the related art, the beneficial effects of the wafer defect detection device provided by this application are the same as those of the wafer defect detection method provided by the above-mentioned embodiment, and the other technical features of the wafer defect detection device are the same as those disclosed in the method of the above-mentioned embodiment, and are not further described here.

[0130] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0131] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0132] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, a computer program) stored thereon, wherein the computer-readable program instructions are used to execute the wafer defect detection method in the above-mentioned embodiment.

[0133] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0134] The computer-readable storage medium may be included in the wafer defect detection device; or it may exist independently without being assembled into the wafer defect detection device.

[0135] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the wafer defect inspection device, the wafer defect inspection device: In response to a wafer defect detection instruction, a receiving camera captures a preset first resolution image of a corresponding wafer; Based on a CPU-GPU collaborative computing strategy, the preset first resolution image is processed in parallel to determine a binary mask corresponding to the preset first resolution image; Based on the preset wafer defect judgment rule and the binary mask, it is judged whether the wafer has defects to obtain a wafer defect detection result.

[0136] Computer program code for performing the operations of the present application may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0137] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0138] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0139] The computer-readable storage medium provided in this application stores computer-readable program instructions (i.e., a computer program) for executing the aforementioned wafer defect detection method, thereby resolving the technical issues surrounding wafer defect detection. Compared to related technologies, the beneficial effects of the computer-readable storage medium provided in this application are similar to those of the wafer defect detection method provided in the aforementioned embodiments, and are not further elaborated here.

[0140] The present application also provides a computer program product, comprising a computer program, which implements the steps of the above-mentioned wafer defect detection method when executed by a processor.

[0141] The computer program product provided in this application can solve the technical problem of wafer defect detection. Compared with the related art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the wafer defect detection method provided in the above embodiment, which will not be repeated here.

[0142] The above description is only part of the embodiments of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made by using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A wafer defect detection method, characterized in that: The wafer defect detection method comprises: In response to a wafer defect detection instruction, a receiving camera captures a preset first resolution image of a corresponding wafer; Based on a CPU-GPU collaborative computing strategy, the preset first resolution image is processed in parallel to determine a binary mask corresponding to the preset first resolution image; Based on the preset wafer defect judgment rule and the binary mask, it is judged whether the wafer has defects to obtain a wafer defect detection result.

2. The wafer defect detection method according to claim 1, wherein: The step of processing the preset first resolution image in parallel based on the CPU-GPU collaborative computing strategy to determine the binary mask corresponding to the preset first resolution image further includes: Based on a preset image size, performing a block operation on the preset first resolution image to obtain a plurality of target sub-images; Based on the wafer defect detection instruction and the CPU-GPU collaborative computing strategy, calling the local CPU to generate a wafer defect detection subtask corresponding to each target sub-image, and assigning the wafer defect detection subtask to multiple CUDA thread blocks corresponding to the local GPU; Based on the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, multiple target sub-images are processed in parallel to determine a binary mask corresponding to the preset first resolution image.

3. The wafer defect detection method according to claim 2, wherein: The step of processing a plurality of target sub-images in parallel based on the plurality of CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block further includes: Based on the shared memory strategy, the multiple CUDA thread blocks and the wafer defect detection subtask corresponding to each CUDA thread block, the FAST corner point of each target sub-image is detected in parallel to obtain the target FAST corner point corresponding to each target sub-image; Determine a BRIEF descriptor corresponding to each target sub-image based on the target FAST corner point; Based on the BRIEF descriptor, an initial binary mask of each target sub-image block is calculated.

4. The wafer defect detection method according to claim 3, wherein: The step of performing a block operation on the preset first resolution image based on the preset image size to obtain a plurality of target sub-images further includes: Performing pyramid downsampling on the preset first resolution image to reduce the resolution of the preset first resolution image to obtain a preset second resolution image; Using a two-dimensional Gaussian filter kernel to suppress noise on the preset second resolution image to obtain a target image; Based on a preset image size, a block operation is performed on the target image to obtain a plurality of target sub-images.

5. The wafer defect detection method according to claim 3, wherein: The BRIEF descriptor is a binary vector, and the step of determining the BRIEF descriptor corresponding to each target sub-image based on the target FAST corner point further includes: Get an initialized BRIEF descriptor string, where each character corresponding to the initialized BRIEF descriptor string is 0; Based on the multiple threads included in the CUDA thread block and the target FAST corner point, performing a determine-modify atomic operation on multiple characters in the initialized BRIEF descriptor string in parallel to determine a BRIEF descriptor corresponding to each target sub-image; The step of performing the judgment-modification atomic operation on multiple characters in the initialized BRIEF descriptor string in parallel includes: Determine whether each character in the initialized BRIEF descriptor string meets the modification requirements; If satisfied, the character that meets the modification requirement will be changed from 0 to 1.

6. The wafer defect detection method according to claim 1, wherein: The step of determining whether a wafer has defects based on a preset wafer defect judgment rule and the binary mask to obtain a wafer defect detection result further includes: Optimizing the initial binary mask based on a connected domain identification optimization strategy to obtain a target binary mask; Based on the target binary mask and preset defect judgment rules, judging whether each target sub-image has defects, and obtaining multiple initial judgment results; Based on all the initial judgment results, determine whether the wafer has defects and obtain the wafer defect detection result.

7. The wafer defect detection method according to claim 6, wherein: The step of optimizing the initial binary mask based on the connected domain identification optimization strategy to obtain a target binary mask further includes: Based on the connected domain identification optimization strategy and the preset small image block size, each target sub-image is divided into multiple small image blocks, wherein the small image blocks are independently marked with connected domains in the GPU shared memory; Determine the label of each pixel in each small image block, merge equivalent labels based on atomic operations, and obtain the initial merge result; Based on a tree-like recursive merging strategy and a 3D thread block index, boundary pixels of adjacent small image blocks are merged layer by layer to optimize the initial merging result and obtain a target binary mask.

8. A wafer defect detection device, characterized in that: The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the wafer defect detection method according to any one of claims 1 to 7.

9. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the wafer defect detection method according to any one of claims 1 to 7 are implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the wafer defect detection method according to any one of claims 1 to 7 are implemented.

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