Display circuit, gating circuit and related device

Abstract

The embodiment of the invention provides a display circuit, a gating circuit and a related device, and relates to the technical field of terminals. The display circuit comprises a first pixel circuit comprising a first element, a display driving integrated circuit used for outputting a control signal, a first GOA circuit used for outputting a first signal, and a gating circuit connected with the control end of the first element. The gating circuit is used for outputting a first scanning signal according to the first signal and the control signal; when the first signal is the third level and the control signal is converted from the second level to the first level, the first scanning signal is the sixth level; and when the first signal is at the third level and the control signal is converted from the first level to the second level, the first scanning signal is at the fifth level until the level of the first signal is switched. Thus, when the control signal jumps, the scanning signal is output or the scanning signal of the sixth level is output according to the level change of the first signal, the situation that the pulse of the scanning signal is cut off or abnormal occurs is reduced, and display stripes are reduced.

Description

Technical Field

[0001] The present application relates to the field of terminal technology, and in particular to a display circuit, a gating circuit and related devices. Background Art

[0002] Currently, electronic devices can display images at different refresh rates in different areas of the display screen to reduce power consumption. For example, dynamic images are displayed in areas corresponding to high refresh rates, and static images are displayed in areas corresponding to low refresh rates.

[0003] However, when an electronic device refreshes a portion of the display, stripes may appear. Summary of the Invention

[0004] Embodiments of the present application provide a display circuit, a gating circuit, and related devices for use in the field of terminal technology. The gating circuit can output a scanning signal in accordance with the level change of a first signal when a control signal transitions, thereby reducing the occurrence of scan signal pulses being cut off and display streaks. Alternatively, the gating circuit can output a low-level scanning signal when a control signal transitions, thereby reducing the occurrence of scan signal pulses caused by control signal transitions and, in turn, display streaks.

[0005] In a first aspect, embodiments of the present application provide a display circuit. The display circuit includes: a first pixel circuit, a display driver integrated circuit, a first GOA circuit, and a gating circuit; the first GOA circuit and the display driver integrated circuit are both electrically connected to the gating circuit, which is electrically connected to a control terminal of a first element in the first pixel circuit. When the first element is enabled, the first pixel circuit refreshes its display.

[0006] The display driver integrated circuit is used to output a control signal, wherein when the control signal is at a first level, the first pixel circuit refreshes the display; when the control signal is at a second level, the first pixel circuit does not refresh the display; the first GOA circuit is used to output a first signal, wherein when the first signal is at a third level, the first pixel circuit scans and refreshes; when the first signal is at a fourth level, the first pixel circuit does not scan and refresh.

[0007] The gating circuit is used to output a first scanning signal according to the first signal and the control signal, wherein when the first scanning signal is at the fifth level, the first element is turned on so that the first pixel circuit refreshes the display; when the first scanning signal is at the sixth level, the first element is turned off so that the first pixel circuit does not refresh the display.

[0008] Among them, when the first signal is at the third level, if the control signal is converted from the second level to the first level, the first scanning signal is at the sixth level; in this way, when the control signal Ctrol is level-switched, the pulse width of the first scanning signal is not affected by the control signal, and thus the display of the first pixel circuit is not affected, thereby reducing stripes during partition display.

[0009] Alternatively, when the first signal is at the third level, if the control signal is converted from the first level to the second level, the first scanning signal is at the fifth level until the first signal is converted from the third level to the fourth level; in this way, the time for which the first scanning signal maintains the fifth level is related to the first signal, and the pulse width of the first scanning signal is not affected by the jump of the control signal, and thus the display of the first pixel circuit is not affected, thereby reducing the stripes during partition display.

[0010] Alternatively, when the first signal is at the fourth level, the first scanning signal is at the sixth level. Thus, when the first signal is at the fourth level, the first scanning signal maintains the sixth level, and the first pixel circuit does not refresh the display.

[0011] Taking the example that the first level can be a high level, the second level is a low level; the third level is a high level, the fourth level is a low level; the fifth level is a high level, and the sixth level is a low level, when the control signal jumps from high to low, the scanning signal is output according to the level change of the first signal, thereby reducing the situation where the pulse of the scanning signal is cut off and reducing display stripes; when the control signal jumps from low to high, a low-level scanning signal is output; the occurrence of scanning signal pulses caused by the control signal jump is reduced, thereby reducing display stripes.

[0012] In an embodiment of the present application, when the first pixel circuit refreshes its display, the first element is enabled. The first element may be an oxide transistor in the pixel circuit. It is understood that if the first region refreshes its display and the second region does not, the first element in the pixel circuit of the first region is enabled, while the first element in the pixel circuit of the second region is disabled. The first element may correspond to a transistor in the pixel circuit for data writing, a transistor for threshold compensation, or a transistor for resetting.

[0013] Taking the display screen as an example of row-driven display, the control signal may correspond to the control signal Ctrol hereinafter. The first signal may correspond to the row drive signal Gatei hereinafter. The first scan signal may correspond to the scan signal Scan4 , the scan signal Scan5 , or the scan signal Scan3 hereinafter. The first GOA circuit may be the GOA circuit corresponding to the row drive signal Gatei . The first pixel circuit may be the pixel circuit corresponding to the row drive signal Gatei . Specific limitations are not provided herein.

[0014] In one possible implementation, the display circuit also includes: a second GOA circuit and a second pixel circuit, the second GOA circuit being used to output a second signal, wherein the second pixel circuit scans and refreshes when the second signal is at a seventh level; the second pixel circuit does not scan and refresh when the second signal is at an eighth level, and the scan refresh of the second pixel circuit is earlier than the scan refresh of the first pixel circuit; a gating circuit being specifically used to store a first voltage when the first signal is at a fourth level and the second signal is at a seventh level, the first voltage being the voltage of the control signal; the gating circuit being specifically used to control the first scan signal to be at a fifth level when the first signal is at a third level and the first voltage is at a first level; or, the gating circuit being specifically used to control the first scan signal to be at a sixth level when the first signal is at a third level and the first voltage is at a second level; or, the gating circuit being specifically used to control the first scan signal to be at a sixth level when the first signal is at a fourth level and the first voltage is at a second level.

[0015] In the embodiment of the present application, the second GOA circuit may be a GOA circuit corresponding to the cascaded row drive signal. The second pixel circuit may be a pixel circuit corresponding to the cascaded row drive signal. The second signal may correspond to the cascaded row drive signal Gatej described below. The seventh level may be a high level, and the eighth level may be a low level.

[0016] When the second pixel circuit is scanned and refreshed, the voltage of the control signal is pre-stored, and the first scanning signal is confirmed based on the voltage and the first signal. In this way, when the first signal is subsequently at the first level, the first scanning signal is not affected by the switching of the control signal level, thereby reducing the occurrence of pulse interruption or abnormality of the first scanning signal and reducing the phenomenon of stripes on the display screen.

[0017] In one possible implementation, the gating circuit includes: an energy storage unit, a selection unit and a driving unit; the energy storage unit is electrically connected to the input end of the selection unit, and the output end of the selection unit is electrically connected to the driving unit; the energy storage unit is used to store the first voltage when the first signal is at the fourth level and the second signal is at the seventh level; the selection unit is used to output the ninth level when the first signal is at the third level and the first voltage is at the first level; and the driving unit is used to output the fifth level when the selection unit outputs the ninth level, so that the first scanning signal is at the fifth level.

[0018] Alternatively, the selection unit is used to output the tenth level when the first signal is at the third level and the first voltage is at the second level; or to output the tenth level when the first signal is at the fourth level; the driving unit is used to output the sixth level when the selection unit outputs the tenth level, so that the first scanning signal is at the sixth level.

[0019] In some embodiments, the ninth level may correspond to a low level, and the tenth level may correspond to a high level.Figure 7 、 Figure 11 、 Figure 13 or Figure 14A The gating circuit in .

[0020] In this way, the gating circuit can be composed of three parts, so that when the second pixel circuit is refreshed, the voltage of the control signal is pre-stored and the first scanning signal is confirmed based on the voltage and the first signal.

[0021] In one possible implementation, the energy storage unit includes: a first field effect unit, a second field effect unit and a storage unit; the control end of the first field effect unit is controlled by a first signal, and the control end of the second field effect unit is controlled by a second signal; the first end of the first field effect unit is used to input a control signal, the second end of the first field effect unit is electrically connected to the first end of the second field effect unit, and the second end of the second field effect unit is electrically connected to the storage unit; the first field effect unit is used to be turned on when the first signal is a fourth level to transmit the control signal; the second field effect unit is used to be turned on when the second signal is a seventh level to transmit the control signal; the storage unit is used to store a first voltage when both the first field effect unit and the second field effect unit are turned on, and the first voltage is the voltage of the control signal.

[0022] The first field effect unit, the second field effect unit and the storage unit are connected in series. In this way, the control signal can be transmitted to the energy storage unit for storage according to the control of the first signal and the control of the second signal.

[0023] In this way, the voltage of the control signal can be pre-stored when the second pixel circuit is scanned and refreshed (the second signal is at the seventh level). When the first pixel circuit is scanned and refreshed (the second signal is at the seventh level), the voltage of the control signal is stopped from being stored, thereby reducing the change in the first voltage caused by the jump of the control signal.

[0024] In some embodiments, the positions of the first field effect unit and the second field effect unit can be interchanged. For example, the first field effect unit is located between the second field effect unit and the memory unit.

[0025] In one possible implementation, the first field effect unit includes a first transistor, the second field effect unit includes a second transistor, and the storage unit includes a capacitor; the gate of the first transistor is used to input a first signal, the gate of the second transistor is used to input a second signal, the second electrode of the first transistor is used to input a control signal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the first electrode of the second transistor is electrically connected to the capacitor; wherein, when the first signal is at the fourth level and the second signal is at the seventh level, the first transistor and the second transistor are turned on, so that the capacitor is charged to the first voltage. The energy storage unit may correspond to the following Figure 7 、 Figure 11 、 Figure 13or Figure 14A The energy storage unit in the first transistor may correspond to transistor T1 or transistor T11; the second transistor may correspond to transistor T2 or transistor T12; and the capacitor may correspond to capacitor C1 or capacitor C3.

[0026] In this way, the structure is simple, the size is small, and it is easy to implement.

[0027] In one possible implementation, the selection unit includes: a third field effect unit, a fourth field effect unit, a fifth field effect unit and a sixth field effect unit; the control end of the fourth field effect unit is the input end of the selection unit, and the second end of the fifth field effect unit is the output end of the selection unit; the control end of the third field effect unit and the control end of the fifth field effect unit are both controlled by a first signal; the control end of the fourth field effect unit and the control end of the sixth field effect unit are both controlled by a first voltage; the first end of the fifth field effect unit and the first end of the sixth field effect unit are both electrically connected to the first voltage source, and the second end of the fifth field effect unit and the second end of the sixth field effect unit are both electrically connected to the first end of the fourth field effect unit; the second end of the fourth field effect unit is electrically connected to the first end of the third field effect unit, and the second end of the third field effect unit is electrically connected to the second voltage source.

[0028] The third field effect unit is used to be turned on when the first signal is at the third level, so as to connect the second voltage source and the fourth field effect unit; the fourth field effect unit is used to be turned on when the first voltage is at the first level, so as to connect the third field effect unit and the output end of the selection unit, so that the selection unit outputs the ninth level; the fifth field effect unit is used to be turned on when the first signal is at the fourth level, so as to connect the second voltage source and the output end of the selection unit, so that the selection unit outputs the tenth level; the sixth field effect unit is used to be turned on when the first voltage is at the second level, so as to connect the second voltage source and the output end of the selection unit, so that the selection unit outputs the tenth level.

[0029] The first voltage source is used to provide the tenth level, and the second voltage source is used to provide the ninth level. In some embodiments, the first voltage source is a positive voltage source (eg, positive voltage source VGH), and the second voltage source is a negative voltage source (eg, negative voltage source VGL).

[0030] The third field effect unit, the fourth field effect unit, and the fifth field effect unit are connected in series, and the fifth field effect unit and the sixth field effect unit are connected in parallel. In this way, the output logic judgment of the scanning signal can be realized according to the first voltage and the first signal.

[0031] In some embodiments, the positions of the third field effect unit and the fourth field effect unit can be interchanged. For example, the fourth field effect unit is located between the third field effect unit and the fifth field effect unit.

[0032] In one possible implementation, the third field effect unit includes a third transistor, the fourth field effect unit includes a fourth transistor, the fifth field effect unit includes a fifth transistor, and the sixth field effect unit includes a sixth transistor; the gate of the third transistor and the gate of the fifth transistor are electrically connected and controlled by a first signal; the gate of the fourth transistor and the gate of the sixth transistor are electrically connected and controlled by a first voltage.

[0033] The first electrode of the fifth transistor and the first electrode of the sixth transistor are both electrically connected to the first voltage source, the second electrode of the fifth transistor and the second electrode of the sixth transistor are both electrically connected to the first electrode of the fourth transistor; the second electrode of the fourth transistor is electrically connected to the first electrode of the third transistor, and the second electrode of the third transistor is electrically connected to the second voltage source.

[0034] Among them, when the first signal is at the third level, the fifth transistor is turned off and the third transistor is turned on; when the first voltage is at the first level, the sixth transistor is turned off and the fourth transistor is turned on; when the first voltage is at the second level, the sixth transistor is turned on and the fourth transistor is turned off; when the first signal is at the fourth level, the fifth transistor is turned on and the third transistor is turned off.

[0035] The selection unit may correspond to the following Figure 7 、 Figure 11 、 Figure 13 or Figure 14A The third transistor to the fourth transistor may correspond to the transistor T3 to the transistor T4 or the transistor T13 to the transistor T14, respectively.

[0036] In this way, the structure is simple, the size is small, and it is easy to implement.

[0037] In one possible implementation, the driving unit includes: a seventh field effect unit and an eighth field effect unit; the first end of the seventh field effect unit is electrically connected to the first voltage source, the second end of the seventh field effect unit is electrically connected to the first end of the eighth field effect unit, and the second end of the eighth field effect unit is electrically connected to the second voltage source.

[0038] When the polarity of the seventh field effect unit is opposite to that of the eighth field effect unit, the control end of the seventh field effect unit and the control end of the eighth field effect unit are both electrically connected to the output end of the selection unit; or, the control end of the seventh field effect unit is electrically connected to the output end of the selection unit, and the control end of the eighth field effect unit is controlled by the first signal or electrically connected to the first node, wherein the level change trend of the first node is the same as the level change trend of the first signal.

[0039] In this way, the output of the first scanning signal can be achieved.

[0040] In one possible implementation, the seventh field effect unit includes: a seventh transistor; the eighth field effect unit includes: and an eighth transistor; the first electrode of the seventh transistor is electrically connected to the first voltage source, the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor, and the second electrode of the eighth transistor is electrically connected to the second voltage source; when the polarity of the seventh transistor and the eighth transistor is opposite, the gate of the seventh transistor and the gate of the eighth transistor are both electrically connected to the selection unit; or, when the polarity of the seventh transistor and the eighth transistor is the same, the gate of the seventh transistor is electrically connected to the selection unit; the gate of the eighth transistor is used to input the first signal or to be electrically connected to the first node, and the level change trend of the first node is the same as the level change trend of the first signal.

[0041] The drive unit may correspond to the following Figure 7 、 Figure 11 、 Figure 13 or Figure 14A The seventh transistor may correspond to the transistor T7 or the transistor T17; and the eighth transistor may correspond to the transistor T8 or the transistor T18.

[0042] In this way, the structure is simple, the size is small, and it is easy to implement.

[0043] In one possible implementation, neither the seventh field effect unit nor the eighth field effect unit includes an oxide thin film transistor, which can reduce voltage deviation caused by long-term use of the transistor and improve the stability of the gating circuit.

[0044] In a possible implementation manner, the first node is located in a first GOA circuit.

[0045] In one possible implementation, the first GOA circuit includes: a ninth field effect unit and a tenth field effect unit; the ninth field effect unit, the tenth field effect unit, and the eighth field effect unit have the same polarity; the first end of the ninth field effect unit is electrically connected to the third voltage source, the second end of the ninth field effect unit is electrically connected to the first end of the tenth field effect unit, the second end of the tenth field effect unit is electrically connected to the fourth voltage source, and the gate of the eighth field effect unit is electrically connected to the control end of the tenth field effect unit; the first end of the tenth field effect unit is used to output the first signal.

[0046] The third voltage source is used to provide the tenth level, and the fourth voltage source is used to provide the ninth level. In some embodiments, the third voltage source is a positive voltage source (eg, positive voltage source VGH), and the fourth voltage source is a negative voltage source (eg, negative voltage source VGL).

[0047] The third voltage source may be the same as or different from the first voltage source, and the fourth voltage source may be the same as or different from the second voltage source, without specific limitation herein.

[0048] In this way, the first node is the gate of the transistor in the GOA for outputting a low level, which can increase the voltage difference between the control terminal and the second terminal of the eighth field effect unit, which is beneficial to the conduction of the eighth field effect unit and reduces the loss of the eighth field effect unit.

[0049] In one possible implementation, the ninth field effect unit includes a ninth transistor, the tenth field effect unit includes a tenth transistor; the ninth transistor, the tenth transistor, and the eighth transistor have the same polarity; the first electrode of the ninth transistor is electrically connected to the third voltage source, the second electrode of the ninth transistor is electrically connected to the first electrode of the tenth transistor, the second electrode of the tenth transistor is electrically connected to the fourth voltage source, the gate of the eighth transistor is electrically connected to the control terminal of the tenth transistor; the first electrode of the tenth transistor is used to output the first signal. The first GOA circuit may correspond to the following Figure 11 The ninth transistor may correspond to the transistor a9; and the tenth transistor may correspond to the transistor a16.

[0050] In this way, the structure is simple, the size is small, and it is easy to implement.

[0051] In one possible implementation, the selection circuit is further used to control the first scanning signal according to the reset signal; wherein, when the reset signal is at the eleventh level, the first scanning signal is at the sixth level so that the first element is reset; when the reset signal is at the twelfth level, the first element is not reset.

[0052] In this way, the gating circuit can also reset the first element, thereby improving the accuracy of subsequent pixel circuit display.

[0053] In one possible implementation, the gating circuit further includes a reset unit; a control terminal of the reset unit is controlled by a reset signal, a first terminal of the reset unit is electrically connected to a fifth voltage source, and a second terminal of the reset unit is electrically connected to an input terminal of the selection unit; the reset unit is configured to connect the fifth voltage source and the selection unit when the reset signal is at an eleventh level, so that the selection unit outputs a ninth level and the first scan signal is at a fifth level. The fifth voltage source is configured to provide the first level. In some embodiments, the fifth voltage source is a positive voltage source.

[0054] In this way, reset control is achieved through the reset unit, which is simple and easy to implement.

[0055] In one possible implementation, the reset unit includes: an eleventh transistor; the first electrode of the eleventh transistor is electrically connected to the second voltage source, the second electrode of the eleventh transistor is electrically connected to the selection unit of the gating circuit, and the gate of the eleventh transistor is used to input the reset signal; wherein, when the reset signal is an eleventh level, the eleventh transistor is turned on to connect the fifth voltage source and the input end of the selection unit; when the reset signal is a twelfth level, the eleventh transistor is turned off.

[0056] The reset unit may correspond to the following Figure 14A The eleventh transistor may correspond to the transistor T9. Thus, the structure is simple, the size is small, and it is easy to implement.

[0057] In a second aspect, an embodiment of the present application provides a gating circuit, including: the gating circuit in the display circuit described in the first aspect or any possible implementation manner of the first aspect.

[0058] In a third aspect, an embodiment of the present application provides a display panel, comprising: a display circuit described in the first aspect or any possible implementation manner of the first aspect.

[0059] In a fourth aspect, an embodiment of the present application provides a display screen, comprising: a display circuit described in the first aspect or any possible implementation manner of the first aspect.

[0060] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising: a display circuit described in the first aspect or any possible implementation manner of the first aspect.

[0061] It should be understood that the second to sixth aspects of the present application correspond to the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A schematic structural diagram of a display panel provided in an embodiment of the present application;

[0063] Figure 2 A schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0064] Figure 3 A schematic diagram of an interface for displaying partitions on a display screen provided in an embodiment of the present application;

[0065] Figure 4 is a schematic diagram of the structure of a row driving circuit in a possible design;

[0066] Figure 5 A timing diagram of turning on and off the oxide TFT in a pixel circuit corresponding to a possible design;

[0067] Figure 6 A schematic structural diagram of a row driving circuit provided in an embodiment of the present application;

[0068] Figure 7 A schematic structural diagram of a gating circuit provided in an embodiment of the present application;

[0069] Figure 8A for Figure 7 The working principle diagram of the gating circuit shown in the following scenario of display area 1;

[0070] Figure 8B for Figure 7 The working principle diagram of the gating circuit shown in the display area 1 under the scene 2;

[0071] Figure 8C for Figure 7 The working principle diagram of the gating circuit shown in the display area 1 under the scenario 3;

[0072] Figure 8D for Figure 7 Schematic diagram of waveforms of various signals in the gating circuit shown in display area 1;

[0073] Figure 9A for Figure 7 The working principle diagram of the gating circuit shown in the following scenario of display area 2;

[0074] Figure 9B for Figure 7 The working principle diagram of the gating circuit shown in the display area 2 under the scene 2;

[0075] Figure 9C for Figure 7 The working principle diagram of the gating circuit shown in the display area 2 under the scene 3;

[0076] Figure 9D for Figure 7 The working principle diagram of the gating circuit shown in the display area 2 under the fourth scene;

[0077] Figure 9E for Figure 7 Schematic diagram of waveforms of various signals in the gating circuit shown in display area 2;

[0078] Figure 10A for Figure 7 The working principle diagram of the gating circuit shown is at the junction of display area 2 and display area 3;

[0079] Figure 10B for Figure 7 The working principle diagram of the gating circuit shown in the second scenario at the junction of the display area 2 and the display area 3;

[0080] Figure 10C for Figure 7 The working principle diagram of the gating circuit shown in scenario three is at the junction of display area two and display area three;

[0081] Figure 10D for Figure 7The working principle diagram of the gating circuit shown in the fourth scenario at the junction of the display area 2 and the display area 3;

[0082] Figure 10E for Figure 7 A schematic diagram of waveforms of various signals in the gating circuit at the junction of the display area 2 and the display area 3 is shown;

[0083] Figure 11 A schematic diagram of the structure of a GOA circuit provided in an embodiment of the present application;

[0084] Figure 12 A waveform diagram of a GOA circuit provided in an embodiment of the present application;

[0085] Figure 13 A schematic structural diagram of a gating circuit provided in an embodiment of the present application;

[0086] Figure 14A A schematic structural diagram of another gating circuit provided in an embodiment of the present application;

[0087] Figure 14B for Figure 14A Schematic diagram of the waveforms of the reset signal and the scan signal in the gating circuit shown. DETAILED DESCRIPTION

[0088] To facilitate a clear description of the technical solutions of the embodiments of the present application, some of the terms and technologies involved in the embodiments of the present application are briefly introduced below:

[0089] 1. Refresh rate

[0090] The refresh rate refers to the number of times the electron beam repeatedly scans the image on the display, measured in Hertz (Hz). In other words, the refresh rate indicates how many times the image on the display is refreshed per second. The higher the refresh rate of a display, the smoother the dynamic image.

[0091] 2. Transistor

[0092] A transistor is a component that includes at least three terminals: a gate (G), a drain (D), and a source (S). In the description of a transistor, the first terminal can be a drain and the second terminal can be a source, or the first terminal can be a source and the second terminal can be a drain. When using transistors with opposite polarity or when the direction of current changes, the functions of "source" and "drain" are sometimes interchanged, and it can also be understood that "source" and "drain" can be interchanged.

[0093] 3. Other terms

[0094] In the embodiments of this application, terms such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the terms "first chip" and "second chip" are used solely to distinguish between different chips and do not define their order. Those skilled in the art will understand that terms such as "first" and "second" do not define the quantity or execution order, and do not necessarily define differences.

[0095] It should be noted that in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0096] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, a--c, bc, or abc, where a, b, c can be single or multiple.

[0097] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection. "Electrical connection" includes situations where constituent elements are connected together through elements with some electrical function. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0098] 4. Electronic devices

[0099] The electronic devices of the embodiments of the present application may include handheld devices with display functions, vehicle-mounted devices, etc. For example, some electronic devices are: mobile phones, tablet computers, PDAs, laptop computers, mobile internet devices (MIDs), wearable devices (e.g., smart watches, smart glasses, smart bracelets or smart jewelry, etc.), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), and so on. assistant, PDA), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, vehicle-mounted devices, terminal devices in a 5G network, or terminal devices in a future evolved public land mobile communication network (public land mobile network, PLMN), etc., the embodiments of the present application are not limited to this.

[0100] The electronic devices in the embodiments of the present application may also be referred to as: terminal equipment, user equipment (UE), mobile station (MS), mobile terminal (MT), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent or user device, etc.

[0101] In a possible implementation, an electronic device includes a display panel. Figure 1 FIG. 1 shows a schematic diagram of the structure of the display panel. Figure 1As shown, the display panel includes a display area 101 , a peripheral driving circuit 102 and a display driver integrated circuit (DDIC) 103 . The DDIC 103 is connected to the peripheral driving circuit 102 , and the peripheral driving circuit 102 is connected to the display area 101 .

[0102] The display area 101 is used to display images. The display area 101 may include an array of multiple pixel circuits 1011. Pixel circuits 1011 may include thin-film transistors and light-emitting elements. The thin-film transistors drive the light-emitting elements to emit light. The light-emitting elements may serve as sub-pixels in the display panel. The electronic device displays images on the display panel by driving and controlling the corresponding pixel circuits in the display area 101.

[0103] The peripheral driver circuit 102 is used to generate drive signals (e.g., light emission control signals for pixel circuits, reset signals for pixel circuits, scan signals for pixel circuits, etc.) based on signals from the DDIC 103 to drive the display area 101 to display images. Specifically, the peripheral driver circuit 102 can transmit the drive signals to each pixel circuit in the display area 101 via leads to control whether the light-emitting elements in the pixel circuits emit light.

[0104] like Figure 1 As shown, the peripheral driving circuit 102 may include a row driving circuit 1021 and a column driving circuit 1022 . Both the row driving circuit 1021 and the column driving circuit 1022 are electrically connected to the DDIC 103 .

[0105] The row driving circuit 1021 is configured to generate a row driving signal for driving the pixel circuit 1011 corresponding to a row of pixels in the display area 101 according to a signal from the DDIC 103 .

[0106] The row driver circuit 1021 can be understood as a linear controller with a single direction. The row driver circuit 1021 can scan from the first row of pixels to the last row of pixels in the display area 101, or vice versa. When displaying a frame of image, after the first row of pixels is bright, it must remain bright until the last row of pixels is also bright, in order to display and refresh the entire frame.

[0107] The column driver circuit 1022 is used to linearly load the data signal directly or indirectly (eg, via a time shifter) to the pixel circuit 1011 corresponding to a column of pixels according to the signal from the DDIC 103 , ie, load the data signal sequentially according to the order of the columns in the display area 101 .

[0108] It is understandable that the peripheral driving circuit 102 is usually located at the frame of the electronic device, so as to reduce the obstruction of the display panel in the electronic device and improve the display range and display effect of the electronic device.

[0109] In some embodiments, the pixel circuit 1011 may utilize low-temperature polycrystalline oxide (LTPO) technology that combines low-temperature polysilicon (LTPS) and indium gallium zinc oxide (IGZO). The present embodiment does not specifically limit the structure of the pixel circuit 1011.

[0110] For example, Figure 2 This is a schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application. Figure 2 As shown, the pixel circuit 1011 includes a light emitting element 201, a storage capacitor Cst, and a plurality of thin film transistors (TFTs).

[0111] The light-emitting element may include an organic light-emitting diode (OLED). There is no specific limitation on the light-emitting element. The plurality of thin film transistors may include a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q6, a transistor M1, and a transistor M2.

[0112] like Figure 2 As shown, the gate of transistor Q1 is connected to the first electrode of oxide transistor M1, the first electrode of oxide transistor M2, and one end of storage capacitor Cst. The first electrode of transistor Q1 is connected to the second electrode of transistor Q2, the first electrode of transistor Q5, and the second electrode of transistor Q6. The second electrode of transistor Q1 is connected to the first electrode of transistor Q3 and the second electrode of oxide transistor M1. The first electrode of transistor Q2 and the other end of storage capacitor Cst are both connected to a first power supply VDD. The second electrode of transistor Q3 is connected to the anode of light-emitting element 201 and the first electrode of transistor Q4. The cathode of light-emitting element 201 is connected to a second power supply VSS. The second electrode of oxide transistor M2 is used to receive a reset voltage Vref1. The second electrode of transistor Q4 is used to receive a reset voltage Vref2. The second electrode of transistor Q5 is used to receive a reset voltage Vref3. The first electrode of transistor Q6 is used to receive a data signal Data.

[0113] In this embodiment, the gates of transistors Q2 and Q3 are both used to receive a scan signal Scan1 , which may also be referred to as a light emitting control signal, an EM signal, or the like.

[0114] The gates of transistors Q4 and Q5 are both used to receive a scan signal Scan2. The scan signal Scan2 may also be referred to as a reset signal of the pixel circuit, a ResetP signal, or the like.

[0115] The gate of transistor Q6 is used to receive a scan signal Scan3, which may also be referred to as a Gate P signal.

[0116] The gate of the oxide transistor M1 is configured to receive a scan signal Scan4 , which may also be referred to as a GateN signal.

[0117] The gate of the oxide transistor M2 is configured to receive a scan signal Scan5 , which may also be referred to as a ResetN signal.

[0118] In the embodiment of the present application, transistor Q1 is a driving thin-film transistor (DTFT) that drives the light-emitting element to emit light. Transistor M1 is a compensation transistor that controls the charging of storage capacitor Cst and the conduction of transistor Q1. Transistor M1 and transistor M2 may include oxide transistors. Transistors Q1 to Q6 may include low-temperature polysilicon (LTPS) transistors.

[0119] It should be noted that Figure 2 In the pixel circuit shown, transistors M1 and M2 are used to control the on / off state of transistor Q1, thereby controlling the lighting or extinguishing of light-emitting element 201, and further controlling the pixel corresponding to light-emitting element 201 to be bright or dark. Alternatively, it can be understood that when the electronic device refreshes the display, transistors M1 and M2 are enabled. The more times transistors M1 and M2 are enabled per unit time, the higher the corresponding refresh rate.

[0120] When transistor M2 is turned on, it can be said that transistor M2 is enabled. When transistor M2 is not turned on or is in the off state, it can be said that transistor M2 is disabled. When transistor M1 is turned on, it can be said that transistor M1 is enabled. When transistor M1 is not turned on or is in the off state, it can be said that transistor M1 is disabled.

[0121] It is understandable that the above Figure 2Any transistor in the pixel circuit shown can be replaced with a field-effect unit. The field-effect unit may include multiple parallel transistors, or include a chip with corresponding functions, etc. The replacement structure of the transistor is not specifically limited here. The embodiments of the present application do not limit the specific structure of the pixel circuit.

[0122] In some embodiments, the electronic device can control different areas of the display screen to display at different refresh rates (also known as partitioned display) according to the display screen requirements to reduce power consumption.

[0123] For example, Figure 3 This is a schematic diagram of an interface for a partitioned display screen provided by an embodiment of the present application. For example, an electronic device drives and controls pixel circuits in a row-driven manner, and a display screen includes k rows of pixels. Figure 3 As shown, the display screen can be divided into display area 1 301, display area 2 302, and display area 303. Display area 1 101 corresponds to the 1st to (n-1)th rows of pixels in the display screen; display area 2 302 corresponds to the nth to mth rows of pixels in the display screen; and display area 303 corresponds to the m+1th to kth rows of pixels in the display screen.

[0124] Among them, display area 1 301 and display area 3 303 are both low-frequency display areas with corresponding low refresh rates (for example, 10 Hz); display area 2 302 is a high-frequency display area with corresponding high refresh rates (for example, 120 Hz).

[0125] Taking the display screen displaying the video interface as an example, the display area 1 301 can display a status bar, the display area 2 302 can display a video screen, and the display area 3 303 can display a return key, a home key, etc.

[0126] It is understandable that in order to achieve low-frequency display in display area 1 301 and display area 3 303, and high-frequency display in display area 2 302, it is necessary to control the refresh rate of each display area. The refresh rate of each display area is related to the operating frequency of the pixel circuit corresponding to each pixel.

[0127] by Figure 3 The pixel circuits in Figure 2 Taking the pixel circuit shown in FIG. 1 as an example, the electronic device can control the refresh rate by reducing the number of times the transistor M1 and the transistor M2 are enabled.

[0128] For example, Figure 2Taking the pixel circuit shown as an example, the operating frequency of the pixel circuit is related to the driving frequency of transistor Q1, which is related to the conduction state (enablement number) of transistors M1 and M2. Whether transistors M1 and M2 are enabled is related to scan signals Scan4 and Scan5.

[0129] It can be understood that each time the display is refreshed, the scan signal Scan4 and the scan signal Scan5 are input to the pixel circuit, so that the transistor M1 and the transistor M2 are turned on (transistor M1 and transistor M2 are enabled), thereby controlling the driving frequency of the transistor Q1 and further controlling the operating frequency of the pixel circuit.

[0130] Alternatively, it can be understood that in order to achieve refresh of different display areas of the display screen, it is crucial to control the on and off of the oxide TFTs (eg, oxide transistors M1 and M2 ) in the pixel circuit.

[0131] The following describes the partition display control of the electronic device by taking the scan signal Scan5 corresponding to the oxide transistor M2 as an example.

[0132] In the embodiment of the present application, the electronic device can adjust the row driving signal output by the gate driver on array (GOA) circuit of the array substrate through the control signal Ctrol to achieve partitioned refresh display of the pixel circuit.

[0133] For example, Figure 4 Figure 1 is a schematic diagram of the structure of a row drive circuit in a possible design. Figure 4 As shown, taking the scan signal Scan5 as an example, the row driving circuit corresponding to each row of pixel units includes: a GOA circuit 401 and transistors DT1 to DT8.

[0134] The input terminal of the GOA circuit 401 is used to input the cascaded row drive signal Gatej. The output terminal of the GOA circuit 401 is electrically connected to the gate of the transistor DT7 and the gate of the transistor DT8. The gate of the transistor DT1 and the gate of the transistor DT2 are electrically connected and are used to input the control signal Ctrol from the DDIC.

[0135] Case 1: The control signal Ctrol is at a low level.

[0136] In this case, since the control signal Ctrol is at a high level, transistor DT1 is turned off and transistor DT2 is turned on, and the positive voltage source PVGH2 outputs a voltage to node N1. Transistor DT6 is turned off and transistor DT5 is turned on. The GOA circuit 401 outputs a low level.

[0137] Case 2: the control signal Ctrol is at a high level, and Gatei is at a low level.

[0138] In this case, since the control signal Ctrol is at a high level, transistor DT1 is turned on and transistor DT2 is turned off. Since Gatei is at a low level, transistor DT7 is turned off, transistor DT8 is turned on, and the positive voltage source PVGH outputs the gate of transistor DT3. Transistor DT3 is turned off, transistor DT4 is turned on, and positive voltage source PVGH2 outputs a voltage to node N1. Transistor DT6 is turned off, and transistor DT5 is turned on. GOA circuit 401 outputs a low level.

[0139] Case 3: the control signal Ctrol is at a high level, and Gatei is at a high level.

[0140] In this case, since the control signal Ctrol is at a high level, the transistor DT2 is turned off, the transistor DT1 is turned on, and the negative voltage source PVGL outputs the second electrode of the transistor DT3. The positive voltage source PVGH outputs the transistor DT3 off and the transistor DT4 is turned on.

[0141] Because Gatei is high, transistor DT7 turns on, transistor DT8 turns off, and negative voltage source PVGL outputs to the gates of transistors DT3 and DT4. Transistor DT4 turns off, transistor DT3 turns on, and negative voltage source PVGL2 outputs to node N1. Transistor DT6 turns on, and transistor DT5 turns off. GOA circuit 401 outputs a high level.

[0142] Thus, when the control signal Ctrol is low, the display will not be refreshed; when the control signal Ctrol is high and Scan5 is high, the display will not be refreshed. The electronic device can control the pixel circuits corresponding to different areas to refresh the display through the control signal Ctrol.

[0143] It can be understood that when the high-frequency display area is refreshed and the low-frequency display area is not refreshed, the control signal Ctrol is a high level in the high-frequency display area and the control signal Ctrol is a low level in the low-frequency display area, thereby realizing non-refresh of the low-frequency display area and realizing partitioned display.

[0144] It can be understood that when both the high-frequency display area and the low-frequency display area are refreshed, the control signal Ctrol from the DDIC is continuously high, thereby achieving refresh of the low-frequency display area and the high-frequency display area.

[0145] However, at the junction of the high-frequency display area and the low-frequency display area, when the control signal Ctrol switches its level, the pulse of the row drive signal Gatei may be cut off, and the pulse width of the scanning signal Scan5(i) may be shortened. As a result, the voltage at the gate of the transistor Q1 may be different, causing abnormal brightness of the light-emitting element and stripes to appear when the electronic device refreshes the display.

[0146] It should be noted that the brightness of pixels is affected by the pulse width of the scan signal Scan5. Wider pulse widths result in higher brightness, while narrower pulse widths result in lower brightness. When the pulses of the row drive signal Gatei are cut off, the brightness of the pixels in that row decreases, resulting in the appearance of streaks on the display.

[0147] For example, Figure 5 The following is a possible design corresponding to the on and off timing diagram of the oxide TFT in a pixel circuit. Take the high-frequency display area corresponding to the nth row of pixel circuits and the mth row of pixels as an example. Figure 5 As shown, when the high-frequency display area is refreshed and the low-frequency display area is not refreshed, the control signal Ctrol is high from moment B to moment E, and is low before moment B or after moment E, and the pulse width of the control signal Ctrol is much larger than the pulse width of the scan signal Scan5.

[0148] From time A to time B, Gate(n-1) is high, while the control signal Ctrol is low, causing Scan5(n-1) to be low. From time B to time C, Gate(n-1) is high, while the control signal Ctrol is high, causing Scan5(n-1) to be high. Compared to the pulse width corresponding to Gate(n-1), the pulse width corresponding to Scan5(n-1) is shorter, resulting in a shorter illuminated time for the pixel circuit in row n-1, causing stripes to appear.

[0149] From time D to time E, Gate(n) is high, and the control signal Ctrol is high, causing Scan5(n) to be low. From time E to time F, Gate(n) is high, and the control signal Ctrol is low, causing Scan5(n) to be low. Compared to the pulse width corresponding to Gate(m), the pulse width corresponding to Scan5(m) is shorter, resulting in a shorter lighting period for the pixel circuit in row m, causing stripes to appear.

[0150] from Figure 5It can be seen that at the junction of the high-frequency display area and the low-frequency display area (for example, the pixel circuit in the n-1th row or the pixel circuit in the mth row), due to the jump of the control signal Ctrol, the pulse corresponding to the scanning signal Scan5 is abnormally cut off, the pulse width is small, and the corresponding luminous duration of the pixel circuit is short, and the pixel circuit in this row is darker, causing stripes to appear on the display panel.

[0151] In view of this, embodiments of the present application provide a gating circuit and related devices. Taking scan signal Scan5(i) as an example, the gating circuit can control scan signal Scan5(i) to maintain a low level when control signal Ctrol jumps, or control the voltage change trend of scan signal Scan5(i) to be the same as the voltage change trend of row drive signal Gatei. In this way, the pulse width of scan signal Scan5(i) is not affected by the jump of control signal Ctrol, and thus the display of pixel circuits in row i is not affected, reducing stripes during partition display.

[0152] Specifically, when the control signal Ctrol jumps from high to low, the scanning signal Scan5(i) is output according to the level change of the row drive signal Gatei, thereby reducing the situation where the pulse of the scanning signal Scan5(i) is cut off and reducing display stripes; when the control signal Ctrol jumps from low to high, a low-level scanning signal is output, thereby reducing the occurrence of scanning signal pulses caused by the jump of the control signal Ctrol, thereby reducing display stripes.

[0153] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above technical problems. The following specific embodiments can be implemented independently or in combination with each other. For the same or similar concepts or processes, some embodiments may not be described in detail.

[0154] For example, Figure 6 This is a schematic diagram of the structure of a row driving circuit provided in an embodiment of the present application. Figure 6 As shown, the row driving circuit may include: a GOA circuit 601 and a gate circuit 602. The GOA circuit 601 is electrically connected to the DDIC 103, and the gate circuit 602 is electrically connected to the GOA circuit 601, the DDIC 103 and the pixel circuit 1011.

[0155] The GOA circuit 601 is used to generate a row driving signal for driving the pixel circuits 1011 corresponding to a row of pixels.

[0156] It should be noted that each row of pixel circuits in the display area corresponds to a GOA circuit 601. Typically, multiple GOA circuits 601 are connected in cascade. Specifically, the output of the GOA circuit 601 corresponding to the pixel circuit in the i-th row is Gatei, and the input of the GOA circuit 601 corresponding to the pixel circuit in the i-th row can be the cascaded row drive signal Gatej. The row drive signal Gatej corresponds to the pixel circuit in the j-th row. i and j are both integers, and i is greater than j. When j is 0, the row drive signal Gate0 is a preset value.

[0157] Exemplarily, taking i as 3 and j as 2, the input of the GOA circuit 601 corresponding to the i-th row pixel circuit is the cascaded row drive signal Gate2; the output of the GOA circuit 601 corresponding to the i-th row pixel circuit is the row drive signal Gate3.

[0158] It is understood that during the display process, the GOA circuit 601 generates Gatei based on the cascaded row drive signal Gatej and the clock signal to achieve pulse movement to achieve row-by-row scanning of the pixel circuit. The GOA circuit 601 can also be understood as a shift register.

[0159] In the embodiment of the present application, the gating circuit 602 is used to output the scanning signal Scan5(i) corresponding to the i-th row pixel circuit according to the row driving signal Gatei from the GOA circuit 601, the cascaded row driving signal Gatej, and the control signal Ctrol from the DDIC 103, so as to control the corresponding oxide TFT in the pixel circuit 1011 to be turned on or off.

[0160] For example, taking i as 3 and j as 2, the selection circuit 602 outputs the scanning signal Scan5(3) corresponding to the third row pixel circuit according to the row driving signal Gate3 from the GOA circuit 601, the cascaded row driving signal Gate2, and the control signal from the DDIC 103, so as to control the corresponding oxide TFT in the third row pixel circuit 1011 to be turned on or off.

[0161] In the embodiment of the present application, the gating circuit 602 is configured to control the scan signal Scan5(i) to maintain a low level when the control signal Ctrol is switched from a low level to a high level.

[0162] Specifically, the gate circuit 602 may control the output scan signal Scan5(i) to be low level when the voltage of the row driving signal Gatei is high level and the control signal Ctrol is switched from low level to high level.

[0163] In this way, when the control signal Ctrol switches its level, the pulse width of the scan signal Scan5(i) is not affected by the control signal Ctrol, and thus the display of the pixel circuit in the i-th row is not affected, thereby reducing stripes during partition display.

[0164] The gating circuit 602 is further configured to control the scanning signal Scan5(i) and the row driving signal Gatei to have the same voltage variation trend when the control signal Ctrol is switched from a high level to a low level.

[0165] Specifically, when the voltage of the row driving signal Gatei is high and the control signal Ctrol is switched from high to low, the gating circuit 602 can control the output scanning signal Scan5(i) to be high until the row driving signal Gatei is low.

[0166] In this way, when the row drive signal Gatei switches from a high level to a low level, the scanning signal Scan5(i) also switches from a high level to a low level. The pulse width of the scanning signal Scan5(i) is not affected by the control signal Ctrol, and thus the display of the pixel circuit in the i-th row is not affected, thereby reducing the stripes during the partition display.

[0167] In the embodiment of the present application, the gating circuit 602 can control the output scanning signal Scan5(i) to have the same level change trend as the row driving signal Gatei when the control signal Ctrol is at a high level. In this way, a high-frequency refresh of the display area can be achieved.

[0168] In the embodiment of the present application, the gating circuit 602 can control the scan signal Scan5(i) by cascading the row drive signal Gatej, the row drive signal Gatei, and the control signal Ctrol. Alternatively, the gating circuit 602 can control the scan signal Scan5(i) by any method, which is not specifically limited herein.

[0169] In some embodiments, the gating circuit 602 may pre-store the voltage of the control signal Ctrol when the cascaded row drive signal Gatej is at a high level, and control the scan signal Scan5(i) based on the pre-stored voltage and the row drive signal Gatei. For example, when the pre-stored voltage is at a low level, the output scan signal Scan5(i) is controlled to be at a low level; when the pre-stored voltage is at a high level, the output scan signal Scan5(i) is controlled to have the same level change trend as the row drive signal Gatei.

[0170] In this way, by pre-storing the voltage control output of the control signal Ctrol, the scanning signal Scan5(i) output by the selection circuit 602 can be unaffected by the level switching of the control signal Ctrol when the row drive signal Gatei is at a high level, thereby reducing the situation where the pulse width of the scanning signal Scan5(i) is insufficient and reducing the phenomenon of stripes on the display screen.

[0171] For example, Figure 7 This is a schematic diagram of the structure of a gating circuit provided in an embodiment of the present application. Figure 7 As shown, the gating circuit includes: an energy storage unit 701, a selection unit 702 and a driving unit 703. The energy storage unit 701 is electrically connected to the selection unit 702, and the selection unit 702 is electrically connected to the driving unit 703.

[0172] Energy storage unit 701 is configured to store the voltage of control signal Ctrol when row drive signal Gatei is low and the cascaded row drive signal Gatej is high. Thus, when row drive signal Gatei is high, scan signal Scan5(i) can be controlled based on the pre-stored voltage of control signal Ctrol. Consequently, scan signal Scan5 is not affected by level switching of control signal Ctrol.

[0173] Exemplarily, the energy storage unit 701 may include: a transistor T1, a transistor T2, and a capacitor C1. The transistor T1, the transistor T2, and the capacitor C1 are connected in series.

[0174] Exemplarily, the gate of transistor T1 is configured to receive a row drive signal Gatei from the GOA circuit. The gate of transistor T2 is configured to receive a cascaded row drive signal Gatej. A first electrode of transistor T1 is electrically connected to a second electrode of transistor T2. The second electrode of transistor T1 is configured to receive a control signal Ctrol. A first electrode of transistor T2 is connected to a first electrode of capacitor C1, forming a node N2. The second electrode of capacitor C1 is connected to a negative voltage source VGL.

[0175] It can be understood that when the row driving signal Gatei is at a low level and the cascaded row driving signal Gatej is at a high level, the transistor T1 is turned on, the transistor T2 is turned on, and the capacitor C1 stores the voltage of the control signal Ctrol.

[0176] It should be noted that the above-mentioned transistors T1 and T2 can be replaced by a field effect unit. The field effect unit may include multiple parallel transistors, or include a chip with corresponding functions, etc. The replacement structure of transistors T1 and T2 is not specifically limited here. The above-mentioned capacitor C1 can be replaced by a storage unit. The storage unit may include multiple parallel capacitors or any structure with the function of storing voltage, which is not specifically limited here.

[0177] The selection unit 702 is configured to output a low level or a high level based on the row drive signal Gatei and the voltage stored in the capacitor C1. Specifically, the selection unit 702 outputs a low level when the row drive signal Gatei is high and the voltage stored in the capacitor C1 is high; outputs a high level when the row drive signal Gatei is high and the voltage stored in the capacitor C1 is low; and outputs a high level when the row drive signal Gatei is low.

[0178] like Figure 7 As shown, selection unit 702 may include transistors T3 through T6. The gate of transistor T3 is connected to the gate of transistor T5, forming a node N4. Node N4 is configured to receive a row drive signal Gatei from the GOA circuit. The gates of transistor T4 and transistor T6 are connected to form a node N2, which is electrically connected to the first electrode of capacitor C1. Transistors T3, T4, and T5 are connected in series, while transistor T6 is connected in parallel with transistor T5.

[0179] In the embodiment of the present application, the transistor T3 and the transistor T5 are transistors with opposite polarities, and the transistor T6 and the transistor T4 are transistors with opposite polarities.

[0180] Exemplarily, the first electrode of transistor T3 is electrically connected to the second electrode of transistor T4, which is connected to a negative voltage source VGL. The first electrode of transistor T4 is electrically connected to the second electrodes of transistors T5 and T6, forming a node N3. Node N3 is configured to output the output terminal of selection unit 702. The first electrode of transistor T5 and the first electrode of transistor T6 are both connected to a positive voltage source VGH.

[0181] In this embodiment, the positive voltage source VGH is used to output a high level, such as a DC voltage greater than 0, such as 7V or 8V. The negative voltage source VGL is used to output a low level, such as a DC voltage less than or equal to 0, such as -7V or -8V.

[0182] It is understood that the positions of transistors T3 and T4 can be interchanged. For example, the first electrode of transistor T4 is electrically connected to the second electrode of transistor T3, and the second electrode of transistor T4 is connected to the negative voltage source VGL. The first electrode of transistor T3 is electrically connected to the second electrode of transistor T5 and the second electrode of transistor T6, forming a node N3.

[0183] It should be noted that the transistors T3 to T6 can be replaced by a field effect unit, which can include multiple parallel transistors or a chip with corresponding functions. The replacement structure of the transistors T3 to T6 is not specifically limited here.

[0184] The driving unit 703 is used to output a scanning signal (eg, scanning signal Scan5(i)) of the corresponding oxide TFT to the pixel circuit according to the high level or low level from the selecting unit 702, thereby controlling the corresponding oxide TFT (eg, transistor M2) to be turned on or off.

[0185] Specifically, the driving unit 703 is configured to output a low-level scanning signal when the selecting unit 702 outputs a high level and the row driving signal Gatei is a low level; or, the driving unit 703 is configured to output a high-level scanning signal when the selecting unit 702 outputs a low level.

[0186] In some embodiments, the driving unit 703 includes two transistors: one transistor is used to control the output of a high-level scanning signal when it is turned on; and the other transistor is used to control the output of a low-level scanning signal when it is turned on.

[0187] For example, Figure 7 As shown, the driving unit 703 may include a transistor T7 and a transistor T8. When the transistor T7 is turned on, it is used to control the output of a high-level scanning signal; when the transistor T8 is turned on, it is used to control the output of a low-level scanning signal.

[0188] Figure 7 In the illustrated driving unit, the gate of transistor T7 is electrically connected to node N3 of selection unit 702. The second electrode of transistor T7 is electrically connected to the first electrode of transistor T8, forming node N5. Node N5 serves as the output terminal of driving unit 703. The first electrode of transistor T7 is connected to positive voltage source VGH. The second electrode of transistor T8 is connected to negative voltage source VGL.

[0189] It should be noted that the transistors T7 and T8 can be replaced by a field effect unit, which can include multiple parallel transistors or a chip with corresponding functions. The replacement structure of the transistors T7 and T8 is not specifically limited here.

[0190] It should be noted that the structural division of the gating circuit described above is merely exemplary. In some embodiments, the gating circuit may further be divided into an energy storage unit and a selection unit. The energy storage unit may include transistors T1, T2, and capacitor C1; the selection unit may include transistors T3 through T8. Alternatively, the gating circuit may further be divided into a selection unit and a drive unit. The selection unit may include transistors T1 through T6 and capacitor C1; the drive unit may include transistors T7 and T8. This is not specifically limited here.

[0191] The following combination 8A to 10E Yes Figure 7 The working principle of the gating circuit shown in the figure is described in different situations.

[0192] For example, the above Figure 3 Taking the display panel area division shown in FIG. 1 as an example, for display area 1 301 , for example, the pixel circuits in rows 1 to (n-1), the following situations are included:

[0193] In case 1, the control signal Ctrol and the row driving signals Gate(n-2) and Gate(n-1) are all at low levels.

[0194] In case 2, the control signal Ctrol and the row driving signal Gate(n-1) are both at a low level, and the row driving signal Gate(n-2) is at a high level.

[0195] In case three, the control signal Ctrol is at a low level, and the row driving signals Gate(n-2) and Gate(n-1) are both at a high level.

[0196] Correspondingly, see Figures 8A to 8D , Figures 8A to 8C They are Figure 7 The working principle diagram of the gating circuit shown in the display area is in case 1 to case 3. Figure 8D yes Figure 7 Schematic diagram of waveforms of various signals in the gating circuit in display area 1.

[0197] like Figure 8A As shown, in case 1 of display area 1 301, when i is greater than or equal to 1 and less than or equal to n-1, since the row drive signal Gatei and the cascaded row drive signal Gatej are both at a low level, transistors T3 and T2 are both turned off, and transistor T5 is turned on, causing the high level output by the positive voltage source VGH to be applied to node N3. Since node N3 is electrically connected to the gate of transistor T7, transistor T7 is turned off. Since the row drive signal Gatei is at a low level, transistor T8 is turned on, and the low level output by the negative voltage source VGL is applied to node N5. The gating circuit 602 corresponding to the pixel circuit in the i-th row outputs a low level.

[0198] like Figure 8B As shown, in case 2 of display area 1 301, when i is greater than or equal to 1 and less than or equal to n-1, due to the low level of row drive signal Gatei, transistor T3 is turned off and transistor T1 is turned on. Due to the high level of the cascaded row drive signal Gatej, transistor T2 is turned on, causing the control signal Ctrol to be applied to node N2. Since the control signal Ctrol is low, the voltage at node N2 is low, thus turning on transistor T6 and applying the high level output by positive voltage source VGH to node N3. At the same time, capacitor C1 stores the voltage at node N2.

[0199] In addition, transistor T5 is turned on under the control of the row drive signal Gatei, causing the high level output by the positive voltage source VGH to be applied to node N3. Because transistor T5 is connected in parallel with transistor T6, the voltage at node N3 is close to the high level output by the positive voltage source VGH. Because node N3 is electrically connected to the gate of transistor T7, transistor T7 is turned off. Because the row drive signal Gatei is at a low level, transistor T8 is turned on, and the low level output by the negative voltage source VGL is applied to node N5. The selection circuit 602 corresponding to the pixel circuit in the i-th row outputs a low level.

[0200] like Figure 8C As shown, in case three of display area 1 301, when i is greater than or equal to 1 and less than or equal to n-1, since the row drive signal Gatei is at a high level, transistors T1 and T5 are both turned off. However, the voltage at node N2 remains low due to capacitor C1, so transistor T4 is turned off and transistor T6 is turned on, causing the high level output by positive voltage source VGH to be applied to node N3. Since node N3 is electrically connected to the gate of transistor T7, transistor T7 is turned off. Since the row drive signal Gatei is at a high level, transistor T8 is turned off. Since both transistors T7 and T8 are turned off, the voltage at node N5 remains unchanged and is the low level output by negative voltage source VGL. The gating circuit 602 corresponding to the pixel circuit in the i-th row outputs a low level.

[0201] like Figure 8D As shown, Ctrol is the control signal of DDIC, Gate(n-2) is the row driving signal of the pixel circuit corresponding to the n-2th row of pixels, Gate(n-1) is the row driving signal of the pixel circuit corresponding to the n-1th row of pixels, and Out(1) to Out(n-1) are the scanning signals Scan5(1) to Scan5(n-1) output by the selection circuit 602 corresponding to the 1st to (n-1)th row of pixels respectively.

[0202] It is understandable that, for various situations of the display area 1 301, such as the above-mentioned situation 1 to situation 3, when the control signal Ctrol is at a low level, no matter whether the row driving signals Gatei and Gatej generated by the GOA circuit are at a high level or a low level, the gating circuit 602 will continue to output a low level, for example Figure 8D The scan signals Out(1) to Out(n-1) shown control the corresponding oxide TFTs in the pixel circuit to turn off, so that the display area 1 301 maintains low-frequency display.

[0203] It can be understood that display area three 303 and display area one 301 are both low-frequency display areas, and the situation in display area three 303 is roughly the same as that in display area one 301. The working principle of the selection circuit 602 in display area three 303 can be found in the relevant description of display area one 301, and will not be repeated here.

[0204] In this embodiment, for the display area 2 302 , for example, the pixels in the nth to (m-1)th rows, the following situations are included:

[0205] In case 1, the control signal Ctrol and the row driving signal Gate(n-1) are both at a high level, and the row driving signal Gate(n) is at a low level.

[0206] In case 2, the control signal Ctrol and the row driving signals Gate(n-1) and Gate(n) are all at high level.

[0207] In case three, the control signal Ctrol and the row driving signal Gate(n) are both at a high level, and the row driving signal Gate(n-1) is at a low level.

[0208] In case 4, the control signal Ctrol is at a high level, and the row driving signals Gate(n-1) and Gate(n) are both at a low level.

[0209] Correspondingly, see Figures 9A to 9E , 9A to 9D They are Figure 7 The diagram shows the working principle of the gating circuit 602 in the display area 2 under the first to fourth cases. Figure 9E yes Figure 7 FIG. 6 is a schematic diagram showing waveforms of various signals in the gating circuit 602 in the display area 2. FIG.

[0210] like Figure 9A As shown, in case 1 of the display area 2 302 , when i is greater than or equal to n and less than or equal to m−1, since the row driving signal Gatei is at a low level, the transistor T3 is turned off and the transistor T1 is turned on.

[0211] Since the cascaded row drive signal Gatej is at a high level, transistor T2 is turned on, and the control signal Ctrol is applied to node N2. Since the control signal Ctrol is at a high level, the voltage of N2 is also at a high level. At the same time, capacitor C1 stores the voltage of node N2.

[0212] Furthermore, transistor T5 is turned on under the control of row drive signal Gatei, causing the high level outputted by positive voltage source VGH to be applied to node N3. Since node N3 is electrically connected to the gate of transistor T7, transistor T7 is turned off. Since row drive signal Gatei is at a low level, transistor T8 is turned on, and the low level outputted by negative voltage source VGL is applied to node N5. Consequently, the gate circuit 602 outputs a low level.

[0213] like Figure 9B As shown, in case 2 of the display area 2 302 , when i is greater than or equal to n and less than or equal to m−1, since the row driving signal Gatei is at a high level, the transistors T1 and T5 are both turned off, and the transistor T3 is turned on.

[0214] Because the row drive signal Gatej is high, transistor T2 is turned on. The voltage at node N2 remains high due to capacitor C1, so transistor T6 is turned off and transistor T4 is turned on, causing the low voltage output from negative voltage source VGL to be applied to node N3. Because node N3 is electrically connected to the gate of transistor T7, transistor T7 is turned on. Because the row drive signal Gatei is high, transistor T8 is turned off. Transistor T7 is turned on, while transistor T8 is turned off, causing the high voltage output from positive voltage source VGH to be applied to node N5. Consequently, the gating circuit 602 outputs a high voltage.

[0215] like Figure 9C As shown, in case three of the display area 2 302 , when i is greater than or equal to n and less than or equal to m−1, since the row driving signal Gatei is at a high level, the transistors T1 and T5 are both turned off, and the transistor T3 is turned on.

[0216] Because the row drive signal Gatej is at a low level, transistor T2 is turned off. However, the voltage at node N2 remains high due to capacitor C1, turning off transistor T6 and turning on transistor T4. This causes the low voltage output from negative voltage source VGL to be applied to node N3. Because node N3 is electrically connected to the gate of transistor T7, transistor T7 is turned on. Because the row drive signal Gatei is at a high level, transistor T8 is turned off. Transistor T7 is turned on, while transistor T8 is turned off, causing the high voltage output from positive voltage source VGH to be applied to node N5. Consequently, the gating circuit 602 outputs a high voltage.

[0217] like Figure 9DAs shown, in case 4 of display area 2 302, when i is greater than or equal to n and less than or equal to m-1, since row drive signals Gatei and Gatej are both low, transistors T3 and T2 are both off, and transistor T5 is turned on, causing the high level output by positive voltage source VGH to be applied to node N3. Because it is electrically connected to the gate of transistor T7, transistor T7 is turned off. Since row drive signal Gatei is high, transistor T8 is turned on, causing the low level output by negative voltage source VGL to be applied to node N5. As a result, the gating circuit 602 outputs a low level.

[0218] like Figure 9E As shown, Ctrol is the control signal of DDIC, Gate(n-1) is the row drive signal of the pixel circuit corresponding to the n-1th row of pixels, Gate(n) is the row drive signal of the pixel circuit corresponding to the nth row of pixels, and Out(n) is the scan signal Scan5(n) output by the selection circuit 602 corresponding to the nth to (m-1)th rows of pixels.

[0219] It should be noted that the change principle of Out(n+1) to Out(m-1) corresponding to the pixel circuit in the n+1th row to the pixel circuit in the m-1th row is similar to the change principle of Out(n) corresponding to the pixel circuit in the nth row. Please refer to the change principle of Out(n) corresponding to the pixel circuit in the nth row for details, which will not be repeated here.

[0220] It can be understood that, for various situations in the display area 2 302, such as the above-mentioned situations 1 to 3, when the control signal Ctrol is at a high level and the row drive signal Gatei generated by the GOA circuit is at a high level, the gating circuit 602 outputs a high level. When the row drive signal Gatei generated by the GOA circuit is at a low level, the gating circuit 602 outputs a low level. Since the pulse width of the control signal Ctrol is much larger than the pulse width of the row drive signal Gatei, the scanning signal output by the gating circuit 602 corresponding to each row of pixel circuits has the same phase and pulse width as the row drive signal Gatei, for example Figure 9E The scanning signals Out(n) to Out(m-1) are shown.

[0221] In the embodiment of the present application, for the junction of the display area 2 302 and the display area 3 203, for example, the m-th row of pixels, the following situations are included:

[0222] In case 1, the control signal Ctrol and the row driving signals Gate(m) and Gate(m-1) are all at high levels.

[0223] In case 2, the control signal Ctrol is at a low level, and the row driving signals Gate(m) and Gate(m-1) are both at a high level.

[0224] In case three, the control signal Ctrol and the row driving signal Gate(m-1) are both at a low level, and the row driving signal Gate(m) is at a high level.

[0225] In case 4, the control signal Ctrol and the row driving signals Gate(m) and Gate(m-1) are all at low levels.

[0226] Correspondingly, see Figures 10A to 10E , 10A to 10D They are Figure 7 The diagram shows the working principle of the gating circuit 602 under situations 1 to 4 at the junction of the display area 2 and the display area 3. Figure 10E yes Figure 7 FIG. 6 is a schematic diagram showing waveforms of various signals in the gating circuit 602 at the junction of the display area 2 and the display area 3. FIG.

[0227] like Figure 10A As shown, in case 1 at the junction of display area 2 302 and display area 3 203, when i is equal to m, since the row driving signal Gatei is high, transistors T1 and T5 are both turned off, and transistor T3 is turned on under the control of the row driving signal Gatei.

[0228] Because the cascaded row drive signal Gatej is at a high level, transistor T2 is turned on. The voltage at node N2 remains high due to capacitor C1, so transistor T6 is turned off and transistor T4 is turned on, causing the low voltage output from negative voltage source VGL to be applied to node N3. Because node N3 is electrically connected to the gate of transistor T7, transistor T7 is turned on. Because the row drive signal Gatei is at a high level, transistor T8 is turned off. Transistor T7 is turned on, while transistor T8 is turned off, causing the high voltage output from positive voltage source VGH to be applied to node N5. Consequently, gating circuit 602 outputs a high voltage.

[0229] like Figure 10B As shown, in case 2 at the junction of display area 2 302 and display area 3 203, when i equals m, due to the high level of row drive signal Gatei, transistor T3 is turned on, and transistors T1 and T5 are both turned off. Since transistor T1 is turned off, a jump in control signal Ctrol does not change the voltage at node N2. Furthermore, since the cascaded row drive signal Gatej is high, transistor T2 is turned on. However, the voltage at node N2 remains high due to capacitor C1, transistor T6 is turned off, and transistor T4 is turned on, causing the low level output by negative voltage source VGL to be applied to node N3. Since node N3 is electrically connected to the gate of transistor T7, transistor T7 is turned on. Since row drive signal Gatei is high, transistor T8 is turned off. Transistor T7 is turned on, while transistor T8 is turned off, causing the high level output by positive voltage source VGH to be applied to node N5. As a result, the gating circuit 602 outputs a high level.

[0230] like Figure 10C As shown, in case three at the junction of display areas 2 and 3, when i equals m, due to the high level of row drive signal Gatei, transistor T3 is turned on, while transistors T1 and T5 are both turned off. Since transistor T1 is turned off, a jump in control signal Ctrol does not change the voltage at node N2. Furthermore, since row drive signal Gatej is low, transistor T2 is turned off. However, the voltage at node N2 remains high due to capacitor C1, so transistor T6 is turned off and transistor T4 is turned on, causing the low level output by negative voltage source VGL to be applied to node N3. Since node N3 is electrically connected to the gate of transistor T7, transistor T7 is turned on. Since row drive signal Gatei is high, transistor T8 is turned off. Transistor T7 is turned on and transistor T8 is turned off, causing the high level output by positive voltage source VGH to be applied to node N5. As a result, the gating circuit 602 outputs a high level.

[0231] like Figure 10D As shown, in case 4 at the junction of display areas 2 and 3, when i equals m, since row drive signal Gatei and the cascaded row drive signal Gatej are both low, transistors T3 and T2 are both turned off. Transistor T5 is turned on, applying the high level output by positive voltage source VGH to node N3. Since node N3 is electrically connected to the gate of transistor T7, transistor T7 is turned off. Since row drive signal Gatei is low, transistor T8 is turned on, applying the low level output by negative voltage source VGL to node N5. As a result, the gating circuit 602 outputs a low level.

[0232] like Figure 10E As shown, Ctrol is the control signal of DDIC, Gate(m-1) is the row driving signal of the pixel circuit corresponding to the m-1th row of pixels, Gate(m) is the row driving signal of the pixel circuit corresponding to the mth row of pixels, and Out(m) is the scanning signal Scan5(m) output by the selection circuit 602 corresponding to the mth row of pixels.

[0233] It can be understood that, for various situations at the junction of the display area 2 302 and the display area 3 203, such as the above-mentioned situations 1 to 4, when the control signal Ctrol jumps, that is, changes from a high level to a low level, if the row drive signal Gatei generated by the GOA circuit is a high level, the gate circuit 602 outputs a high level. If the row drive signal Gatei generated by the GOA circuit is a low level, the gate circuit 602 outputs a low level, for example Figure 10EAs a result, the scanning signal output by the gating circuit 602 is consistent with the row driving signal Gatei, and the row driving signal Gatei will not be abnormally cut off due to the jump of the control signal Ctrol, thereby reducing the appearance of display stripes and improving the display effect.

[0234] above Figure 7 In the embodiment shown, the gate of the transistor T8 is connected to the node N4, and the gating circuit controls the on and off of the transistor T8 through the row driving signal Gatei.

[0235] In some other embodiments, the gate of the transistor T8 may be connected to another node, and the level change trend of the node is the same as the level change trend of the row driving signal Gatei.

[0236] For example, the gate of the transistor T8 may also be electrically connected to the gate of the TFT for outputting a low level in the GOA circuit (eg, Figure 11 shown).

[0237] It should be noted that the GOA circuit includes a TFT for outputting a low level and a TFT for outputting a high level, thereby controlling the output row drive signal Gatei. The voltage variation trend of the gate of the TFT for outputting a low level is the same as that of the row drive signal Gatei. Thus, the gate of transistor T8 can be electrically connected to the gate of the TFT for outputting a low level in the GOA circuit to achieve the above-mentioned function.

[0238] For ease of understanding, the level variation trend of the row driving signal Gatei and the gate of the TFT for outputting a low level is described below in conjunction with a specific GOA circuit.

[0239] like Figure 11 As shown, the GOA circuit includes transistors a1 to a17 and capacitors b1 to b3.

[0240] The first electrode of transistor a1 is electrically connected to the first electrode of transistor a2, and the first electrode of transistor a1 is used to input the cascaded row drive signal Gatej. The second electrode of transistor a1, the first electrode of transistor a4, the gate of transistor a10, the gate of transistor a11, and the first electrode of transistor a15 are electrically connected. The gates of transistor a1 and transistor a2 are used to input the clock signal clk1. The second electrode of transistor a4 is connected to the positive voltage source VGH. The gate of transistor a4 is used to input a reset signal. In some embodiments, the GOA circuit may not include transistor a4. This is not specifically limited here.

[0241] The second electrode of transistor a2 is electrically connected to the first electrode of transistor a3 . The second electrode of transistor a3 , the gate of transistor a12 , and the gate of transistor a14 are electrically connected. The gate of transistor a3 is connected to the negative voltage source VGL.

[0242] The gates of transistor a1 , transistor a2 , and transistor a5 are used to input the clock signal clk1 ; the gates of transistor a3 , transistor a6 , and transistor a5 are connected to the negative voltage source VGL.

[0243] The second electrode of transistor a5 is connected to the negative voltage source VGL, the first electrode of transistor a5, the second electrode of transistor a10, the second electrode of transistor a6 and the gate of transistor a13 are electrically connected; the first electrode of transistor a10 is electrically connected to the second electrode of transistor a11;

[0244] The gate of transistor a6, the gate of transistor a15, and the second electrode of transistor a16 are all connected to the negative voltage source VGL. The first electrode of transistor a6, the gate of transistor a7, and one end of capacitor b2 are electrically connected;

[0245] The first electrode of transistor a7, the gate of transistor a8, and the second electrode of transistor a12 are all used to input clock signal clk2; the second electrode of transistor a7, the second electrode of transistor a8, and the other end of capacitor b2 are electrically connected;

[0246] A first electrode of transistor a8, a gate of transistor a9, and one end of capacitor b3 are electrically connected; the first electrode of transistor a9 and the other end of capacitor b3 are both connected to a positive voltage source VGH; a second electrode of transistor a9 is electrically connected to a first electrode of transistor a16, and the second electrode of transistor a9 is used to output a row drive signal Gatei;

[0247] The first electrode of transistor a12, the second electrode of transistor a13 and one end of capacitor b1 are electrically connected; the gate of transistor a12, the other end of capacitor b1, the gate of transistor a14 and the first electrode of transistor a14 are electrically connected;

[0248] The first electrode of transistor a13 is connected to the positive voltage source VGH. The second electrode of transistor a14, the second electrode of transistor a15 and the gate of transistor a16 are electrically connected to form a node N6. The gate of transistor a15 and the second electrode of transistor a16 are both connected to the negative voltage source VGL.

[0249] The transistor a9 is a TFT for outputting a low level, and the transistor a16 is a TFT for outputting a high level. The gate voltage variation trend of the transistor a16 (ie, the voltage variation trend of the node N6) is the same as the voltage variation trend of Gatei.

[0250] It can be understood that transistor a16 is turned on when node N6 is at a low level, and transistor a9 is turned off when node N6 is at a high level. Due to the GOA circuit principle, when transistor a9 is off and transistor a16 is on, Gatei is at a low level; when transistor a9 is on and transistor a16 is off, Gatei is at a high level.

[0251] For example, Figure 12 Schematic diagram of waveforms of voltage changes at node N6 and Gatei in a GOA circuit provided in an embodiment of the present application.

[0252] like Figure 12 As shown, the phases of clock signals clk1 and clk2 are opposite. Before time A, row driving signal Gatej is at a low level; from time A to time B, row driving signal Gatej is at a high level; after time B, row driving signal Gatej is at a low level.

[0253] The GOA circuit outputs a row driving signal Gatei under the control of the clock signal clk1 , the clock signal clk2 and the row driving signal Gatei.

[0254] From time A to time C, the row drive signal Gatei output by the GOA circuit is at a low level; the node N6 is at a low level; from time C to time B, the row drive signal Gatei output by the GOA circuit is at a high level; the node N6 is at a high level; from time B to time E, the row drive signal Gatei output by the GOA circuit is at a high level; the node N6 is at a high level; after time E, the row drive signal Gatei output by the GOA circuit is at a low level; the node N6 is at a low level.

[0255] from Figure 12 It can be seen that the voltage change trend of the node N6 (i.e., the gate of the TFT for outputting a low level) is the same as the voltage change trend of the row drive signal Gatei, and thus the gate of the transistor T8 is electrically connected to the gate of the TFT for outputting a low level in the GOA circuit, which can also achieve the above function.

[0256] It is understood that due to the on-off characteristics of transistor a16, when the row drive signal Gatei is at a low level, the voltage of node N6 (e.g., -10V) is lower than the voltage of the row drive signal Gatei (e.g., -7V). This increases the voltage difference between the gate and the second electrode of transistor T8, which facilitates the conduction of transistor T8 and reduces the loss of transistor T8.

[0257] It is understandable that the above Figure 7 and Figure 11The illustrated embodiment uses a drive unit comprising two LTPS TFTs as an example. LTPS TFTs are small and have high electron mobility, which can reduce the size of the GOA circuit, thereby achieving high resolution on the display screen. High electron mobility also reduces the drive voltage and power consumption of LTPS TFTs. However, LTPS TFTs have high leakage current and are therefore expensive.

[0258] In addition, the LTPS TFT Mob is larger, and the margin is larger after Vth offset. After NBTS negative bias, the output capacity is less affected. Figure 7 and Figure 11 The gating circuit shown has a smaller negative bias and better stability after being used for a period of time.

[0259] In some embodiments, the driving unit may also include: an LTPS TFT and an oxide transistor. It should be noted that the oxide TFT has the characteristics of low leakage current and low cost, which can reduce the power consumption of the electronic device.

[0260] For example, Figure 13 This is a structural diagram of another gating circuit provided in an embodiment of the present application. Figure 13 As shown, the gating circuit includes transistors T11 to T18 and a capacitor C3.

[0261] The connection and working principle of transistors T11 to T17 can refer to the corresponding description of transistors T1 to T7, and the connection and working principle of capacitor C3 can refer to the corresponding description of capacitor C1, which will not be repeated here.

[0262] The gate of the transistor T18 is electrically connected to the gate of the transistor T17 and further connected to the node N3. The first electrode of the transistor T18 is electrically connected to the second electrode of the transistor T17. The second electrode of the transistor T18 is connected to the negative voltage source VGL.

[0263] The transistor T18 is turned on when the voltage at the node N3 is at a high level, and is turned off when the voltage at the node N3 is at a low level.

[0264] Figure 13 The working principle of the gating circuit shown is similar to that of the gating circuit in the above embodiment, and will not be described in detail here.

[0265] Based on the above embodiment, the gating circuit may further include a reset unit. The reset unit is electrically connected to the selection unit. The reset unit is configured to control the conduction of the corresponding oxide TFT in the pixel circuit. Thus, after the display screen is powered on and before the pixel circuit refreshes, the reset unit can reset the corresponding oxide TFT in the pixel circuit, thereby reducing display deviation of the pixel circuit.

[0266] It should be noted that in the pixel circuit, since the oxide TFT also has leakage current (also known as off-state current, Ioff) in the off state, charge will accumulate in the oxide TFT. In the embodiment of the present application, a reset unit is provided in the gating circuit. The gating circuit can output a high level to reset the corresponding oxide TFT in the pixel circuit, releasing its accumulated charge, thereby improving the stability of the oxide TFT in the pixel circuit.

[0267] For example, Figure 14A This is a structural diagram of a gating circuit provided in another embodiment of the present application. Figure 14A As shown, the gating circuit 602 further includes: a reset unit 1401 .

[0268] like Figure 14A As shown, the reset unit 1401 includes a transistor T9, a gate of the transistor T9 is used to receive the reset signal RST1, a first electrode of the transistor T9 is electrically connected to the node N2 and the first electrode of the transistor T2, and a second electrode of the transistor T9 is connected to the positive voltage source VGH.

[0269] When reset unit 1401 is reset, because row drive signal Gatei is high and reset signal RST1 is low, transistor T9 is turned on under the control of reset signal RST1, applying the high level output by positive voltage source VGH to node N2. Because the voltage at node N2 is high, transistor T4 is turned on, and transistor T3 is turned on under the control of row drive signal Gatei, applying the low level output by negative voltage source VGL to node N3, turning on transistor T7. Because row drive signal Gatei is high, transistor T8 is turned off.

[0270] The transistor T7 is turned on and the transistor T8 is turned off, and the high level output by the positive voltage source VGH is applied to the node N5; thus, the gating circuit outputs a high level.

[0271] above Figure 14A The transistor T9 in the shown gating circuit is only used as an example. The transistor T9 can be replaced by a reset unit of other structures, for example, a unit of multiple parallel transistors, a chip with corresponding functions, etc. The embodiment of the present application does not limit the specific structure of the gating circuit.

[0272] Figure 14B 14 is a schematic diagram of waveforms of the reset signal and the scan signal in the drive selection circuit shown in FIG.

[0273] like Figure 14BAs shown, RST1 is the reset signal of the reset unit, which is at a low level during reset. Out is the scan signal output by the gating circuit. Scan signal Out is at a high level when the reset unit 1401 is reset, turning on the corresponding oxide TFT in the pixel circuit. This can release the charge in the corresponding oxide TFT in the pixel circuit, thereby improving the stability of the oxide TFT in the pixel circuit.

[0274] It can be understood that when the electronic device performs partition display, the scanning signal Scan4 can also be controlled by the control signal Ctrol. The implementation principle of the selection circuit corresponding to the scanning signal Scan4 is similar to the selection circuit corresponding to the scanning signal Scan5. For details, please refer to the above corresponding description and will not be repeated here.

[0275] In some embodiments, the scan signal Scan3 may also be controlled by the control signal Ctrol. The implementation principle of the gating circuit corresponding to the scan signal Scan3 is similar to that of the gating circuit corresponding to the scan signal Scan5. For details, please refer to the above corresponding description and will not be repeated here.

[0276] When an electronic device refreshes an image frame for display on a display panel, it can drive and control the pixel circuits using either a row drive mode or a column drive mode. The principles of the two modes are similar. The method of driving and controlling the pixel circuits using the column drive mode is not described here in detail.

[0277] It can be understood that the above embodiment is described by taking the control signal indicating refresh display at a high level as an example. The control signal can also indicate refresh display at a low level. The implementation principle of the specific circuit is similar to the principle of indicating refresh display at a high level, and will not be described in detail here.

[0278] The above embodiment is described by taking the row drive signal indicating scan refresh at a high level as an example. The row drive signal can also indicate scan refresh at a low level. The implementation principle of the specific circuit is similar to the principle of indicating refresh display when the control signal is at a high level, and will not be described in detail here.

[0279] The gating circuit of the embodiment of the present application has been described above. The following describes the apparatus for performing the above method provided by the embodiment of the present application. Those skilled in the art will understand that the method and apparatus can be combined and referenced with each other, and the relevant apparatus provided by the embodiment of the present application can perform the steps in the above method.

[0280] An embodiment of the present application provides a display panel, which includes: the above-mentioned gating circuit.

[0281] An embodiment of the present application provides a display screen, which includes: the above-mentioned gating circuit.

[0282] In the embodiments of the present application, the display screen may be a foldable display screen or a non-foldable display screen, and the display screen includes a display panel. The display panel may be an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Mini-LED, a Micro-LED, a Micro-OLED, a quantum dot light-emitting diode (QLED), or the like.

[0283] An embodiment of the present application provides an electronic device, comprising: any one of the possible gating circuits described above. The specific form of the electronic device can refer to the corresponding description above and will not be repeated here.

[0284] It should be noted that the module names involved in the embodiments of the present application can be defined as other names as long as the functions of each module can be achieved, and there is no specific restriction on the names of the modules.

[0285] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0286] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable device to produce a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0287] The above specific implementation methods further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of the present invention should be included in the scope of protection of the present invention.

Claims

1. A display circuit, characterized in that: include: a first pixel circuit, a display driver integrated circuit, a first GOA circuit, and a gating circuit; the first GOA circuit and the display driver integrated circuit are both electrically connected to the gating circuit, the gating circuit is electrically connected to a control terminal of a first element in the first pixel circuit, and the first pixel circuit refreshes the display when the first element is enabled; The display driver integrated circuit is used to output a control signal, wherein when the control signal is at a first level, the first pixel circuit refreshes the display; when the control signal is at a second level, the first pixel circuit does not refresh the display; The first GOA circuit is configured to output a first signal, wherein the first pixel circuit is scanned and refreshed when the first signal is at a third level; and the first pixel circuit is not scanned and refreshed when the first signal is at a fourth level; the gating circuit is configured to output a first scanning signal according to the first signal and the control signal, wherein when the first scanning signal is at a fifth level, the first element is turned on so that the first pixel circuit refreshes the display; and when the first scanning signal is at a sixth level, the first element is turned off so that the first pixel circuit does not refresh the display; Wherein, when the first signal is at the third level, if the control signal is converted from the second level to the first level, the first scanning signal is at the sixth level; Alternatively, when the first signal is at the third level, if the control signal is converted from the first level to the second level, the first scanning signal is at the fifth level until the first signal is converted from the third level to the fourth level; Alternatively, when the first signal is at the fourth level, the first scanning signal is at the sixth level.

2. The display circuit according to claim 1, wherein: The display circuit further includes: a second GOA circuit and a second pixel circuit, wherein the second GOA circuit is configured to output a second signal, wherein the second pixel circuit is scanned and refreshed when the second signal is at a seventh level; and the second pixel circuit is not scanned and refreshed when the second signal is at an eighth level, and the scanning and refreshing of the second pixel circuit is earlier than the scanning and refreshing of the first pixel circuit; The gating circuit is specifically configured to store a first voltage when the first signal is at the fourth level and the second signal is at the seventh level, where the first voltage is the voltage of the control signal; The gating circuit is specifically configured to control the first scanning signal to be at the fifth level when the first signal is at the third level and the first voltage is at the first level; Alternatively, the gating circuit is specifically configured to control the first scanning signal to be at the sixth level when the first signal is at the third level and the first voltage is at the second level; Alternatively, the gating circuit is specifically configured to control the first scanning signal to be at the sixth level when the first signal is at the fourth level.

3. The display circuit according to claim 2, wherein: The gating circuit includes: an energy storage unit, a selection unit and a driving unit; the energy storage unit is electrically connected to the input end of the selection unit, and the output end of the selection unit is electrically connected to the driving unit; the energy storage unit being configured to store the first voltage when the first signal is at the fourth level and the second signal is at the seventh level; the selecting unit is configured to output a ninth level when the first signal is at the third level and the first voltage is at the first level; the driving unit is configured to output the fifth level when the selecting unit outputs the ninth level, so that the first scanning signal is at the fifth level; Alternatively, the selection unit is used to output the tenth level when the first signal is the third level and the first voltage is the second level; or to output the tenth level when the first signal is the fourth level; and the driving unit is used to output the sixth level when the selection unit outputs the tenth level, so that the first scanning signal is the sixth level.

4. The display circuit according to claim 3, wherein: The energy storage unit includes: a first field effect unit, a second field effect unit and a storage unit; The control end of the first field effect unit is controlled by the first signal, and the control end of the second field effect unit is controlled by the second signal; the first end of the first field effect unit is used to input the control signal, the second end of the first field effect unit is electrically connected to the first end of the second field effect unit, and the second end of the second field effect unit is electrically connected to the storage unit; The first field effect unit is configured to be turned on when the first signal is at the fourth level to transmit the control signal; The second field effect unit is configured to be turned on when the second signal is at the seventh level, so as to transmit the control signal; The storage unit is configured to store a first voltage when the first field effect unit and the second field effect unit are both turned on, where the first voltage is the voltage of the control signal.

5. The display circuit according to claim 4, wherein: The first field effect unit includes a first transistor, the second field effect unit includes a second transistor, and the memory cell includes a capacitor; The gate of the first transistor is used to input the first signal, the gate of the second transistor is used to input the second signal, the second electrode of the first transistor is used to input the control signal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the first electrode of the second transistor is electrically connected to the capacitor; When the first signal is at the fourth level and the second signal is at the seventh level, the first transistor and the second transistor are turned on, so that the capacitor is charged to the first voltage.

6. The display circuit according to claim 5, characterized in that: The selection unit includes: a third field effect unit, a fourth field effect unit, a fifth field effect unit and a sixth field effect unit; the control end of the fourth field effect unit is the input end of the selection unit, and the second end of the fifth field effect unit is the output end of the selection unit; The control end of the third field effect unit and the control end of the fifth field effect unit are both controlled by the first signal; the control end of the fourth field effect unit and the control end of the sixth field effect unit are both controlled by the first voltage; The first end of the fifth field effect unit and the first end of the sixth field effect unit are both electrically connected to the first voltage source, the second end of the fifth field effect unit and the second end of the sixth field effect unit are both electrically connected to the first end of the fourth field effect unit; the second end of the fourth field effect unit is electrically connected to the first end of the third field effect unit, and the second end of the third field effect unit is electrically connected to the second voltage source; the third field effect unit is configured to be turned on when the first signal is at the third level, so as to connect the second voltage source and the fourth field effect unit; the fourth field effect unit is configured to be turned on when the first voltage is at the first level, so as to connect the third field effect unit and the output end of the selection unit, so that the selection unit outputs the ninth level; the fifth field effect unit is configured to be turned on when the first signal is at the fourth level, so as to connect the second voltage source and the output terminal of the selection unit, so that the selection unit outputs the tenth level; The sixth field effect unit is configured to be turned on when the first voltage is at the second level, so as to connect the second voltage source and the output terminal of the selection unit, so that the selection unit outputs the tenth level.

7. The display circuit according to claim 6, wherein: The third field effect unit includes a third transistor, the fourth field effect unit includes a fourth transistor, the fifth field effect unit includes a fifth transistor, and the sixth field effect unit includes a sixth transistor; The gate of the third transistor is electrically connected to the gate of the fifth transistor and is controlled by the first signal; the gate of the fourth transistor is electrically connected to the gate of the sixth transistor and is controlled by the first voltage; The first electrode of the fifth transistor and the first electrode of the sixth transistor are both electrically connected to the first voltage source, the second electrode of the fifth transistor and the second electrode of the sixth transistor are both electrically connected to the first electrode of the fourth transistor; the second electrode of the fourth transistor is electrically connected to the first electrode of the third transistor, and the second electrode of the third transistor is electrically connected to the second voltage source; Wherein, when the first signal is at the third level, the fifth transistor is turned off and the third transistor is turned on; when the first voltage is at the first level, the sixth transistor is turned off and the fourth transistor is turned on; When the first voltage is at the second level, the sixth transistor is turned on and the fourth transistor is turned off; When the first signal is at the fourth level, the fifth transistor is turned on and the third transistor is turned off.

8. The display circuit according to any one of claims 3 to 7, characterized in that: The driving unit includes: a seventh field effect unit and an eighth field effect unit; The first end of the seventh field effect unit is electrically connected to the first voltage source, the second end of the seventh field effect unit is electrically connected to the first end of the eighth field effect unit, and the second end of the eighth field effect unit is electrically connected to the second voltage source; When the polarity of the seventh field effect unit is opposite to that of the eighth field effect unit, the control end of the seventh field effect unit and the control end of the eighth field effect unit are both electrically connected to the output end of the selection unit; Alternatively, the control end of the seventh field effect unit is electrically connected to the output end of the selection unit, and the control end of the eighth field effect unit is controlled by the first signal or electrically connected to the first node, wherein the level change trend of the first node is the same as the level change trend of the first signal.

9. The display circuit according to claim 8, wherein: The seventh field effect unit includes: a seventh transistor; the eighth field effect unit includes: and an eighth transistor; A first electrode of the seventh transistor is electrically connected to a first voltage source, a second electrode of the seventh transistor is electrically connected to a first electrode of the eighth transistor, and a second electrode of the eighth transistor is electrically connected to a second voltage source; When the polarities of the seventh transistor and the eighth transistor are opposite, the gate of the seventh transistor and the gate of the eighth transistor are both electrically connected to the selection unit; Alternatively, when the polarity of the seventh transistor is the same as that of the eighth transistor, the gate of the seventh transistor is electrically connected to the selection unit; the gate of the eighth transistor is used to input the first signal or to be electrically connected to the first node, and the level change trend of the first node is the same as the level change trend of the first signal.

10. The display circuit according to any one of claims 8 or 9, characterized in that: The seventh field effect unit and the eighth field effect unit do not include an oxide thin film transistor.

11. The display circuit according to any one of claims 8 to 10, characterized in that: The first node is located in the first GOA circuit.

12. The display circuit according to claim 11, wherein: The first GOA circuit includes: a ninth field effect unit and a tenth field effect unit; the ninth field effect unit, the tenth field effect unit and the eighth field effect unit have the same polarity; The first end of the ninth field effect unit is electrically connected to the third voltage source, the second end of the ninth field effect unit is electrically connected to the first end of the tenth field effect unit, the second end of the tenth field effect unit is electrically connected to the fourth voltage source, and the gate of the eighth field effect unit is electrically connected to the control end of the tenth field effect unit; the first end of the tenth field effect unit is used to output the first signal.

13. The display circuit according to claim 12, wherein: The ninth field effect unit includes a ninth transistor, and the tenth field effect unit includes a tenth transistor; the ninth transistor, the tenth transistor, and the eighth transistor have the same polarity; a first electrode of the ninth transistor being electrically connected to the third voltage source, a second electrode of the ninth transistor being electrically connected to the first electrode of the tenth transistor, a second electrode of the tenth transistor being electrically connected to the fourth voltage source, and a gate of the eighth transistor being electrically connected to a control terminal of the tenth transistor; The first electrode of the tenth transistor is configured to output the first signal.

14. The display circuit according to any one of claims 1 to 13, characterized in that: The selection circuit is also used to control the first scanning signal according to the reset signal; wherein, when the reset signal is at the eleventh level, the first scanning signal is at the sixth level so that the first element is reset; when the reset signal is at the twelfth level, the first element is not reset.

15. The display circuit according to claim 14, wherein: The gating circuit further includes: a reset unit; The control end of the reset unit is controlled by the reset signal, the first end of the reset unit is electrically connected to the fifth voltage source, and the second end of the reset unit is electrically connected to the input end of the selection unit; The reset unit is configured to connect the fifth voltage source and the input terminal of the selection unit when the reset signal is at the eleventh level, so that the selection unit outputs a ninth level and the first scanning signal is at the fifth level.

16. The display circuit according to claim 15, wherein: The reset unit includes: an eleventh transistor; a first electrode of the eleventh transistor being electrically connected to a second voltage source, a second electrode of the eleventh transistor being electrically connected to a selection unit of the gating circuit, and a gate of the eleventh transistor being used for inputting the reset signal; Wherein, when the reset signal is at the eleventh level, the eleventh transistor is turned on to connect the fifth voltage source and the input terminal of the selection unit; When the reset signal is at the twelfth level, the eleventh transistor is turned off.

17. A gating circuit, characterized in that: include: A gating circuit in a display circuit according to any one of claims 1 to 16.

18. A display panel, characterized in that: include: A display circuit as claimed in any one of claims 1 to 16.

19. A display screen, characterized in that: include: A display circuit as claimed in any one of claims 1 to 16.

20. An electronic device, characterized in that: The electronic device comprises: a display circuit according to any one of claims 1 to 16.

Images