Display panel and display device

Abstract

The invention discloses a display panel and a display device, and the display panel comprises a pixel circuit and a light-emitting element. The pixel circuit comprises a driving module, a data writing module and a light emitting control module. The driving module is used for providing driving current for the light-emitting element and comprises a driving transistor; the data write-in module is used for selectively providing a data signal for the driving transistor; the light-emitting control module is used for selectively allowing the light-emitting element to enter a light-emitting stage, and one end of the light-emitting control module is connected to a first power signal end and used for receiving a first power signal; wherein the pixel circuit further comprises a latch module and a first scanning signal line, and the first scanning signal line is used for receiving a first scanning signal; the latch module is connected between the grid electrode of the driving transistor and the first scanning signal line. According to the invention, regulation and control of the gate potential of the driving transistor can be realized.

Description

[0001] This application is a divisional application with the application date of October 23, 2020, application number 202011149636.4, and invention name “Display panel and display device”. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display panel and a display device including the display panel. Background Art

[0003] In a display panel, the pixel circuit provides the driving current required for display to the light-emitting elements of the display panel and controls whether the light-emitting elements enter the light-emitting stage. It is an indispensable component in most self-luminous display panels.

[0004] However, in existing display panels, the internal characteristics of the driver transistor in the pixel circuit slowly change over time, causing the threshold voltage of the driver transistor to drift. Alternatively, the gate potential of the driver transistor in the pixel circuit may be affected by the operation of the pixel circuit and become unstable. These issues can affect the overall characteristics of the driver transistor and, in turn, affect display uniformity. Summary of the Invention

[0005] In view of this, the present invention provides a display panel and a display device, which can help alleviate the problem of threshold voltage shift of a driving transistor, or improve the stability of the gate potential of the driving transistor.

[0006] An aspect of an embodiment of the present application provides a display panel, comprising

[0007] Pixel circuits and light-emitting elements;

[0008] The pixel circuit includes a driving module, a data writing module, and a light emitting control module;

[0009] The driving module is used to provide a driving current for the light emitting element, and the driving module includes a driving transistor;

[0010] The data writing module is used to selectively provide a data signal to the driving transistor;

[0011] The light emitting control module is used to selectively allow the light emitting element to enter the light emitting stage, and one end of the light emitting control module is connected to the first power signal end for receiving the first power signal; wherein,

[0012] The pixel circuit further includes a latch module and a first scanning signal line, wherein the first scanning signal line is used to receive a first scanning signal;

[0013] The latch module is connected between the gate of the driving transistor and the first scanning signal line.

[0014] Another aspect of the present invention provides another display panel, which includes:

[0015] Pixel circuits and light-emitting elements;

[0016] The pixel circuit includes a driving module, a data writing module, a light emitting control module, a compensation module, and a reset module;

[0017] The driving module is used to provide a driving current for the light emitting element, and the driving module includes a driving transistor;

[0018] The data writing module is used to selectively provide a data signal to the driving transistor;

[0019] The light emitting control module is used to selectively allow the light emitting element to enter the light emitting stage, and one end of the light emitting control module is connected to the first power signal end for receiving the first power signal;

[0020] The compensation module is connected between the gate and the drain of the driving transistor, and is used to compensate for the threshold voltage of the driving transistor;

[0021] The reset module is connected between the drain of the driving transistor and the reset signal terminal, and is used to provide a reset signal to the gate of the driving transistor; wherein,

[0022] The reset module is multiplexed as a bias module;

[0023] The working process of the pixel circuit includes a reset phase and a bias phase. In the reset phase, the compensation module and the reset module are turned on, and the reset signal terminal provides the reset signal to the gate of the driving transistor;

[0024] In the bias phase, the compensation module is turned off, the reset module is turned on, and the reset signal terminal provides a bias signal to the drain of the driving transistor;

[0025] The pixel circuit further includes a latch module and a reset signal line, wherein the reset signal line is used to provide the reset signal or the bias signal to the reset signal terminal, and the latch module is connected between the gate of the driving transistor and the reset signal line.

[0026] The present invention further provides a display device, comprising the display panel in any one of the above embodiments.

[0027] In an embodiment of the present invention, a latch module is provided, and the latch module is connected between the gate of the driving transistor and the first scan line or the reset signal line, so that the gate potential of the driving transistor can be regulated by the signal on the first scan signal or the reset signal line. Since the gate potential of the driving transistor plays a very important role in the normal operation of the pixel circuit, and the gate potential of the driving transistor is prone to change in different stages, the present invention can effectively maintain and regulate the gate potential of the driving transistor through the signal on the first scan signal or the reset signal line and the action of the latch module. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of a pixel circuit of a display panel provided by an embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of a pixel circuit of another display panel provided by an embodiment of the present invention;

[0030] Figure 3 yes Figure 1 One of the working timing diagrams of the pixel circuit shown;

[0031] Figure 4 yes Figure 1 The second working timing diagram of the pixel circuit shown;

[0032] Figure 5 yes Figure 1 The third working timing diagram of the pixel circuit shown;

[0033] Figure 6 is a schematic diagram of a pixel circuit of a display panel provided by another embodiment of the present invention;

[0034] Figure 7 yes Figure 6 One of the working timing diagrams of the pixel circuit shown;

[0035] Figure 8 yes Figure 6 The second working timing diagram of the pixel circuit shown;

[0036] Figure 9 yes Figure 6 The third working timing diagram of the pixel circuit shown;

[0037] Figure 10 It is a partial cross-sectional schematic diagram of a pixel circuit;

[0038] Figure 11 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0040] It should be noted that the following description sets forth specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways than those described herein, and those skilled in the art may make similar generalizations without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0041] refer to Figure 1 , Figure 1 This is a schematic diagram of a pixel circuit of a display panel provided by an embodiment of the present invention, wherein the display panel includes a pixel circuit 10 and a light-emitting element 20, and the pixel circuit 10 includes a driving module 11, a data writing module 12, and a light-emitting control module 13; the driving module 11 is used to provide a driving current for the light-emitting element 20, and the driving module 11 includes a driving transistor T0; the data writing module 12 is used to selectively provide a data signal Vdata to the driving transistor T0; the light-emitting control module 13 is used to selectively allow the light-emitting element to enter the light-emitting stage, and one end of the light-emitting control module 13 is connected to the first power signal end for receiving the first power signal PVDD; wherein the pixel circuit 10 also includes a latch module 16 and a first scan signal line, and the first scan signal line is used to receive a first scan signal S1; the latch module 16 is connected between the gate of the driving transistor T0 and the first scan signal line, and is used to regulate the gate potential of the driving transistor T0 according to the first scan signal S1.

[0042] Optionally, in this embodiment, the input end of the driving module 11 is connected to the source of the driving transistor T0, and the output end of the driving module 11 is connected to the drain of the driving transistor T0. Figure 1 In the pixel circuit shown in , the driving transistor T0 is a PMOS transistor; further, the driving transistor T0 may be a low-temperature polysilicon transistor.

[0043] Optionally, in this embodiment, the control end of the data writing module 12 is connected to the second scanning signal line for receiving the second scanning signal S2, and the second scanning signal S2 controls the opening and closing of the data writing module 12; the first end of the data writing module 12 is connected to the data signal input end for receiving the data signal Vdata, and the second end of the data writing module 12 is connected to the input end of the driving module 11; optionally, the data writing module 12 includes a fifth transistor T5, the source of the fifth transistor T5 is connected to the first end of the data writing module 12, and the drain of the fifth transistor T5 is connected to the second end of the data writing module 12.

[0044] Optionally, in this embodiment, the light control module 13 includes a first light control module 13a and a second light control module 13b. The first end of the first light control module 13a is connected to the first power signal end for receiving the first power signal PVDD, and the second end of the first light control module 13a is connected to the input end of the driving module 11; the first end of the second light control module 13b is connected to the output end of the driving module 11, and the second end is connected to the light emitting element 20. The control ends of the first light control module 13a and the second light control module 13b can be connected to the same light control signal line for receiving the light control signal EM, such as Figure 1 As shown; in other optional embodiments, the control ends of the first light control module 13a and the second light control module 13b can also be connected to different light control signal lines for receiving different light control signals. Optionally, the first light control module 13a includes a second transistor T2, the source of which is connected to the first end of the first light control module 13a and the drain of which is connected to the second end of the first light control module 13a; the second light control module 13a includes a third transistor T3, the source of which is connected to the first end of the second light control module 13b and the drain of which is connected to the second end of the second light control module 13b.

[0045] refer to Figure 2 , Figure 2 This is a schematic diagram of a pixel circuit of another display panel provided by an embodiment of the present invention, wherein the display panel includes a pixel circuit 10 and a light-emitting element 20, and the pixel circuit 10 includes a driving module 11, a data writing module 12, and a light-emitting control module 13; the driving module 11 is used to provide a driving current for the light-emitting element 20, and the driving module 11 includes a driving transistor T0; the data writing module 12 is used to selectively provide a data signal Vdata to the driving transistor T0; the light-emitting control module 13 is used to selectively allow the light-emitting element to enter the light-emitting stage, and one end of the light-emitting control module 13 is connected to the first power signal end for receiving the first power signal PVDD; wherein the pixel circuit 10 also includes a latch module 16 and a first scanning signal line, and the first scanning signal line is used to receive a first scanning signal S1; the latch module 16 is connected between the gate of the driving transistor T0 and the first scanning signal line, and is used to regulate the gate potential of the driving transistor T0 according to the first scanning signal S1.

[0046] Optionally, in this embodiment, the input end of the driving module 11 is connected to the source of the driving transistor T0, and the output end of the driving module 11 is connected to the drain of the driving transistor T0. Figure 1 In the pixel circuit shown in , the driving transistor T0 is an NMOS transistor; further, the driving transistor T0 may be an oxide semiconductor transistor.

[0047] Optionally, in this embodiment, the control end of the data writing module 12 is connected to the second scanning signal line for receiving the second scanning signal S2, and the second scanning signal S2 controls the opening and closing of the data writing module 12; the first end of the data writing module 12 is connected to the data signal input end for receiving the data signal Vdata, and the second end of the data writing module 12 is connected to the input end of the driving module 11; optionally, the data writing module 12 includes a fifth transistor T5, the source of the fifth transistor T5 is connected to the first end of the data writing module 12, and the drain of the fifth transistor T5 is connected to the second end of the data writing module 12.

[0048] Optionally, in this embodiment, the light control module 13 includes a first light control module 13a and a second light control module 13b. The first end of the first light control module 13a is connected to the first power signal end for receiving the first power signal PVDD, and the second end of the first light control module 13a is connected to the output end of the driving module 11; the first end of the second light control module 13b is connected to the input end of the driving module 11, and the second end is connected to the light emitting element 20. The control ends of the first light control module 13a and the second light control module 13b can be connected to the same light control signal line for receiving the light control signal EM, such as Figure 2 As shown; in other optional embodiments, the control ends of the first light control module 13a and the second light control module 13b can also be connected to different light control signal lines for receiving different light control signals. Optionally, the first light control module 13a includes a second transistor T2, the source of which is connected to the first end of the first light control module 13a and the drain of which is connected to the second end of the first light control module 13a; the second light control module 13a includes a third transistor T3, the source of which is connected to the first end of the second light control module 13b and the drain of which is connected to the second end of the second light control module 13b.

[0049] In an embodiment of the present invention, a latch module is provided, and the latch module is connected between the gate of the driving transistor and the first scan line, so that the gate potential of the driving transistor can be regulated by the first scan signal. Since the gate potential of the driving transistor plays a very important role in the normal operation of the pixel circuit, and the gate potential of the driving transistor is prone to change in different stages, the present invention can effectively maintain and regulate the gate potential of the driving transistor through the action of the first scan signal and the latch module.

[0050] Optionally, in this embodiment, if Figure 1As shown, the pixel circuit 10 also includes a reset module 15 and a compensation module 14. The reset module 15 is connected between the reset signal terminal and the drain of the driving transistor T0, and is used to provide a reset signal for the gate of the driving transistor T0. The reset signal includes the first transistor T1; the compensation module 14 is connected between the gate and the drain of the driving transistor T0, and is used to compensate for the threshold voltage of the driving transistor T0; the initialization module 17 is connected between the initialization signal terminal and the light-emitting element 20, and is used to selectively provide the initialization signal Vini to the light-emitting element 20.

[0051] Optionally, the source of the first transistor T1 is connected to the reset signal terminal, and the drain is connected to the drain of the driving transistor T0.

[0052] Optionally, the control terminal of the compensation module 14 is connected to the third scan signal line for receiving the third scan signal S3, which controls the on and off of the compensation module 14. The compensation module 14 includes a fourth transistor T4, the source of which is connected to the drain of the driving transistor T0, and the drain of which is connected to the gate of the driving transistor T0. Optionally, the fourth transistor T4 can be a PMOS transistor or an NMOS transistor. When the fourth transistor T4 is a PMOS transistor, the fourth transistor T4 is turned on when the third scan signal S3 is a low-level signal. The fourth transistor T4 can be a low-temperature polysilicon transistor. When the fourth transistor T4 is an NMOS transistor, the fourth transistor T4 is turned on when the third scan signal S3 is a high-level signal. The fourth transistor T4 can be an oxide semiconductor transistor. The following description takes the fourth transistor T4 as an NMOS oxide semiconductor transistor as an example.

[0053] Optionally, the initialization module Vini includes a sixth transistor T6 , wherein the source of the sixth transistor T6 is connected to the initialization signal terminal, and the drain is connected to the light emitting element 20 .

[0054] Figure 2 In the embodiment, the connection mode of the reset module 15, the compensation module 14 and the initialization module 17 is the same as that described in the previous paragraph, and the same description will not be repeated here. Figure 1 and Figure 2 In the embodiment, the source and drain of the driving transistor T0 are interchanged, and the end of the driving transistor T0 connected to the data writing module 11 is the source of the driving transistor T0.

[0055] In this embodiment, in some implementations, the control terminal of the reset module 15 is connected to the first scan signal line. That is, when the first scan signal S1 controls the reset module 15 to turn on, the gate potential of the driving transistor T0 is regulated to a first state under the action of the first scan signal S1 and the latch module 16. When the first scan signal line S1 controls the reset module 15 to turn off, the gate potential of the driving transistor T0 is regulated to a second state under the action of the first scan signal S1 and the latch module 16. The first state and the second state can be a state of raising the potential or a state of lowering the potential. For example, when the first scan signal S1 is low and the reset module 15 is turned on, the first state is a state of lowering the potential; when the first scan signal S1 is high and the reset module 15 is turned off, the second state is a state of raising the potential. For another example, when the first scan signal S1 is high and the reset module 15 is turned on, the first state is a state of raising the potential; when the first scan signal S1 is low and the reset module 15 is turned off, the second state is a state of lowering the potential.

[0056] In this embodiment, in some other implementations, the control end of the initialization module 17 is connected to the first scan signal line. That is, when the first scan signal S1 controls the initialization module 17 to turn on, the gate potential of the driving transistor T0 is regulated to a third state under the action of the first scan signal S1 and the latch module 16. When the first scan signal line S1 controls the initialization module 17 to turn off, the gate potential of the driving transistor T0 is regulated to a fourth state under the action of the first scan signal S1 and the latch module 16. The third state and the fourth state can be a state of raising the potential or a state of lowering the potential. For example, when the first scan signal S1 is at a low level and the initialization module 17 is on, the third state is a state of lowering the potential; when the first scan signal S1 is at a high level and the initialization module 17 is off, the fourth state is a state of raising the potential. For another example, when the first scan signal S1 is at a high level and the initialization module 17 is on, the third state is a state of raising the potential; when the first scan signal S1 is at a low level and the initialization module 17 is off, the fourth state is a state of lowering the potential.

[0057] In this embodiment, in some other implementations, the control end of the reset module 15 and the control end of the initialization module 17 are both used to receive the first scan signal S1, and the latch module 16 is connected to either the first scan signal line connected to the control end of the reset module 15 or the first scan signal line connected to the control end of the initialization module 17. In this implementation, the reset module 15 and the initialization module 16 both receive the first scan signal S1. When the transistors in both are PMOS transistors or NMOS transistors, the reset module 15 and the initialization module 16 are simultaneously turned on or off. This is permitted in the panel because the reset phase and the initialization phase of the pixel circuit are independent of each other. Therefore, the two phases can be performed simultaneously or at different times. In this implementation, the two phases are performed simultaneously. In this case, the first scan signal S1 can be shared for control. Therefore, the panel only needs to be provided with a shift register circuit for generating the first scan signal S1 to meet the requirements, thereby simplifying the panel structure and process.

[0058] In this embodiment, optionally, the operation process of the pixel circuit includes a reset phase and a bias phase. In the reset phase, the reset module 15 and the compensation module 14 are turned on, and the reset signal terminal provides a reset signal Vref to the gate of the driving transistor T0; in the bias phase, the reset module 15 is turned on, the compensation module 14 is turned off, and the reset signal terminal provides a bias signal Vobs to the drain of the driving transistor T0; that is, the reset module 15 is multiplexed as a bias module, and plays the role of providing the bias signal Vobs in the bias phase.

[0059] Because the display panel is in a non-biased stage, such as a light-emitting stage, the source of the driving transistor T0 receives the first power signal PVDD, and the gate of the driving transistor T0 receives the signal written in the data writing stage. Therefore, in the case where the driving transistor is a PMOS transistor, in the light-emitting stage, there may be a situation where the gate potential of the driving transistor T0 is higher than the drain potential. At this time, the driving transistor is in an on state. If this situation persists for a long time, the Id-Vg curve of the driving transistor T0 will shift, thereby causing the threshold voltage of the driving transistor T0 to shift. In the case where the driving transistor is an NMOS transistor, in the light-emitting stage, because the drain of the driving transistor T0 receives the first power signal PVDD, and the first power signal PVDD is usually a high-level signal, there may be a situation where the gate potential of the driving transistor T0 is lower than the drain potential. At this time, the driving transistor is in an on state. If this situation persists for a long time, the Id-Vg curve of the driving transistor T0 will shift, thereby causing the threshold voltage of the driving transistor T0 to shift. Therefore, in order to improve this situation, it is necessary to add a bias stage. In the bias stage, the potential difference between the gate potential and the drain potential of the driving transistor T0 is adjusted to reduce the problem existing in the above-mentioned non-bias stage, which causes the threshold voltage offset of the driving transistor T0, and ensure display uniformity.

[0060] During the reset phase, the gate of the driver transistor T0 receives a reset signal, clearing the gate potential of the driver transistor T0 to the reset signal before the reset phase. This is to reset the gate potential of the driver transistor T0 before the next operation to prevent the residual gate potential from affecting the next operation. For example, before the data writing phase, the reset phase is required to ensure that the signal written during the data writing phase is not interfered with by other signals.

[0061] Optionally, in this embodiment, the driving transistor T0 and the first transistor T1 are both PMOS transistors, and in the bias stage, the voltage of the first scanning signal S1 is lower than the voltage of the bias signal Vobs; or, the driving transistor T0 and the first transistor T1 are both NMOS transistors, and in the bias stage, the voltage of the first scanning signal S1 is higher than the voltage of the bias signal Vobs.

[0062] Taking the case where the control terminal of the reset module 15 is connected to the first scanning signal line as an example, the specific principles of other cases are the same as this case and can be used as a reference. Figure 1When both the driving transistor T0 and the first transistor T1 are PMOS transistors, during the bias phase, the first scanning signal S1 is a low-level signal. Under the action of the first scanning signal S1, the reset module 15 is turned on, and the bias signal Vobs is written to the drain of the driving transistor T0. As previously described, the purpose of the bias phase is to adjust the potential difference between the gate potential and the drain potential of the driving transistor in the non-bias phase. For example, the potential difference can be reduced or even reversed. Therefore, the drain potential needs to be higher, while the gate potential needs to be lower, to achieve this purpose. Therefore, in this embodiment, the bias signal Vobs is a high-level signal and the first scanning signal S1 is a low-level signal. The bias signal Vobs raises the drain potential of the driving transistor T0. The first scanning signal S1, through the action of the latch module 16, pulls down the gate potential of the driving transistor T0, thereby achieving dual-aspect adjustment of the gate potential and the drain potential of the driving transistor T0, which is beneficial to improving the bias effect.

[0063] Taking the control terminal of the reset module 15 connected to the first scanning signal line as an example, the specific principles of other situations are the same as this situation, which can be used as reference. Figure 2 When both the driving transistor T0 and the first transistor T1 are NMOS transistors, during the bias phase, the first scanning signal S1 is a high-level signal. Under the action of the first scanning signal S1, the reset module 15 is turned on, and the bias signal Vobs is written to the drain of the driving transistor T0. As previously described, the purpose of the bias phase is to adjust the potential difference between the gate potential and the drain potential of the driving transistor in the non-bias phase. For example, the potential difference can be reduced or even reversed. Therefore, the drain potential needs to be at a lower potential, while the gate potential needs to be at a higher potential to achieve this purpose. Therefore, in this embodiment, the bias signal Vobs is a low-level signal and the first scanning signal S1 is a high-level signal. The bias signal Vobs lowers the drain potential of the driving transistor T0. The first scanning signal S1 raises the gate potential of the driving transistor T0 through the action of the latch module 16, thereby achieving dual-aspect adjustment of the gate potential and the drain potential of the driving transistor T0, which is beneficial to improving the bias effect.

[0064] Optionally, in this embodiment, the driving transistor is a PMOS transistor, and in the bias stage, the drain voltage of the driving transistor T0 is greater than the gate voltage of the driving transistor T0; or, the driving transistor is an NMOS transistor, and in the bias stage, the drain voltage of the driving transistor T0 is less than the gate voltage of the driving transistor T0.

[0065] As previously mentioned, when the driving transistor is a PMOS transistor, during a non-biased phase such as the light-emitting phase, when the driving transistor T0 is turned on, the gate potential of the driving transistor T0 may be greater than the drain potential, resulting in a shift in the threshold voltage of the driving transistor T0. Therefore, if the drain voltage of the driving transistor is set to be greater than the gate voltage during the bias phase, this problem in the non-biased phase can be effectively offset. Similarly, when the driving transistor is an NMOS transistor, during a non-biased phase such as the light-emitting phase, when the driving transistor T0 is turned on, the gate potential of the driving transistor T0 may be lower than the drain potential, resulting in a shift in the threshold voltage of the driving transistor T0. Therefore, if the drain voltage of the driving transistor is set to be lower than the gate voltage during the bias phase, this problem in the non-biased phase can be effectively offset.

[0066] The following examples are described by Figure 1 The working sequence of the pixel circuit is described by taking the case where the driving transistor shown in FIG is a PMOS transistor as an example. Figure 2 In the case where the driving transistor shown in the figure is an NMOS transistor, the relationship between the time of each stage in its pre-stage also meets the various situations in the example. The same content will not be repeated in this embodiment.

[0067] refer to Figure 3-Figure 5 , Figure 3 yes Figure 1 One of the working timing diagrams of the pixel circuit shown, Figure 4 yes Figure 1 The second working timing diagram of the pixel circuit shown is: Figure 5 yes Figure 1 The third operating timing diagram of the pixel circuit is shown. Within one frame of the display panel, the pixel circuit's operating process includes a pre-stage and a light-emitting stage. Within at least one frame, the pre-stage of the pixel circuit includes a bias stage. For ease of description, in this embodiment, the signal received by the reset signal terminal is collectively referred to as V0.

[0068] like Figure 3As shown, the pre-stage also includes a reset stage; after the reset stage, the pixel circuit enters the bias stage. At the beginning of the bias stage, the gate potential of the driving transistor T0 is the reset signal Vref. In this case, at the beginning of the bias stage, the gate potential of the driving transistor T0 has been reset. If the driving transistor T0 is a PMOS transistor, the gate potential is reset to a low-level signal. Then, during the bias stage, the drain of the driving transistor T0 receives a high-level bias signal Vobs, achieving dual-aspect adjustment of the gate potential and the drain potential. If the driving transistor T0 is an NMOS transistor, the gate potential is reset to a high-level signal. Then, during the bias stage, the drain of the driving transistor T0 receives a low-level bias signal Vobs, achieving dual-aspect adjustment of the gate potential and the drain potential.

[0069] In some other embodiments, before the bias phase begins, the gate potential of the driving transistor T0 is not equal to the reset signal Vref.

[0070] like Figure 4 As shown, after the pixel circuit ends the light-emitting phase and enters the pre-phase, the reset module 15 is turned on, the compensation module 14 remains off, and the bias phase is entered. At this time, after the light-emitting phase ends and the pre-phase enters, the bias phase is entered without going through the reset phase. The gate potential of the driving transistor T0 is not equal to the reset signal Vref. Generally speaking, for PMOS transistors, the reset signal is a low-level signal. When the gate potential of the driving transistor T0 is not equal to the reset signal, the gate potential is higher than the reset signal. Then, after entering the bias phase, the gate potential will be high, making it difficult to reduce the potential difference between the gate and the drain, or reverse the potential difference between the gate and the drain. At this time, after the latch module 16 is set, because the first transistor T1 is also a PMOS transistor, the first transistor T1 is turned on during the bias phase, and the first scanning signal S1 is a low-level signal. Under the action of the first scanning signal S1 and the latch module 16, the potential of the gate of the driving transistor is lowered, so that while adjusting the drain voltage of the driving transistor during the bias phase, the gate voltage is also adjusted, achieving the purpose of two-way regulation, which helps to improve the bias effect.

[0071] like Figure 4 and 5As shown, the pre-stage also includes a data writing stage. During the data writing stage, the data writing module 12, the driving module 11, and the compensation module 14 are all turned on, and the data signal Vdata is written to the gate of the driving transistor T0. At least one biasing stage of the pre-stage is performed after the data writing stage. During the data writing stage, the data signal Vdata is written to the gate of the driving transistor T0, resulting in a relatively high gate potential of the driving transistor T0. Afterwards, the biasing stage is performed. Because the gate potential is high, it is also difficult to reduce the potential difference between the gate and the drain, or to reverse the potential difference between the gate and the drain. At this time, after the latch module 16 is set, since the first transistor T1 is also a PMOS transistor, the first transistor T1 is turned on during the biasing stage, and the first scanning signal S1 is a low-level signal. Under the action of the first scanning signal S1 and the latch module 16, the potential of the gate of the driving transistor is lowered, so that while adjusting the drain voltage of the driving transistor during the biasing stage, the gate voltage is also adjusted, achieving the purpose of two-way adjustment, which helps to improve the biasing effect.

[0072] like Figure 4 As shown, the pre-stage may include N bias stages, where N ≥ 1; Figure 4 Two bias stages are shown in FIG. , but the number may be one, three, or more than three. Figure 4 In the embodiment, the pre-stage includes a first bias stage and a second bias stage; the first bias stage is performed before the data writing stage, and the second bias stage is performed after the data writing stage; wherein the duration of the first bias stage is longer than the duration of the second bias stage. The first pre-stage can serve as a main bias stage, and the second bias stage can serve as an auxiliary bias stage. The first pre-stage mainly plays a biasing role, mainly responsible for offsetting the threshold voltage deviation in the non-bias stage. However, in order to prevent the bias effect of the first bias stage from being incomplete, other supplementary bias stages can be set to fully supplement the bias effect.

[0073] Optionally, in this embodiment, if Figure 1 As shown, the latch module 16 includes a first capacitor C1, the first plate of which is connected to the gate of the driving transistor T0, and the second plate of which is connected to the first scanning signal line. Because the capacitor has the function of charging and discharging, it can be used as a latch module to regulate the potential of one node relative to another node. Moreover, the capacitor no longer needs to have a separate control terminal for control, which simplifies the structure and process of the pixel circuit.

[0074] Optionally, the pixel circuit further includes a second capacitor C2; one plate of the second capacitor C2 is connected to the gate of the driving transistor T0, and is used to store the data signal transmitted to the gate of the driving transistor T0. Figure 1As shown, one plate of the second capacitor C2 is connected to the gate of the driving transistor T0, and the other plate is connected to the first power signal terminal for storing the data signal Vdata. Figure 2 As shown, one plate of the second capacitor C2 is connected to the gate of the driving transistor T0 , and the other plate is connected to the light emitting element 20 , for storing data signals.

[0075] In this embodiment, the capacitance value of the first capacitor C1 is optionally smaller than the capacitance value of the second capacitor C2. Since the function of the second capacitor C2 is to store the data signal Vdata written to the gate of the driving transistor T0, and the data signal Vdata written to the gate of the driving transistor T0 is one of the determining factors for the driving current generated by the driving transistor T0 during the light-emitting phase, it is necessary to use a capacitor with a strong storage capacity to fully store the signal of the driving transistor T0 during the data writing phase; and the bias phase is currently to adjust the potential difference between the gate potential and the drain potential of the driving transistor T0. Therefore, from the perspective of accurately storing data, the storage capacity of the second capacitor is required to be greater than the storage capacity of the first capacitor. Therefore, in this embodiment, the capacitance value of the first capacitor C1 is set to be smaller than the capacitance value of the second capacitor C2.

[0076] Furthermore, optionally, the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 satisfy the following relationship: C2×1 / 8≤C1≤C2×1 / 4. The inventors of the present application have discovered that when C2×1 / 8≤C1≤C2×1 / 4, the capacitance value of the first capacitor C1 can meet the requirements of the bias phase and can avoid the problem of an excessively large capacitance value of the first capacitor C1 causing an increased load on the pixel circuit and affecting signal transmission on the first scan signal line.

[0077] refer to Figure 6 , Figure 61 is a schematic diagram of a pixel circuit of a display panel provided by another embodiment of the present invention, wherein the display panel includes a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a driving module 11, a data writing module 12, a light-emitting control module 13, a compensation module 14, and a reset module 15; the driving module 11 is used to provide a driving current to the light-emitting element 20, and the driving module 11 includes a driving transistor T0; the data writing module 12 is used to selectively provide a data signal Vdata to the driving transistor T0; the light-emitting control module 13 is used to selectively allow the light-emitting element 20 to enter a light-emitting stage, and one end of the light-emitting control module 13 is connected to a first power signal end for receiving a first power signal PVDD; the compensation module 14 is connected between the gate and drain of the driving transistor T0 for compensating the driving transistor T0 threshold voltage; the reset module 15 is connected between the drain of the driving transistor T0 and the reset signal terminal, and is used to provide a reset signal for the gate of the driving transistor; wherein the reset module 15 is multiplexed as a bias module; the working process of the pixel circuit includes a reset phase and a bias phase, in which, in the reset phase, the compensation module 14 and the reset module 15 are turned on, and the reset signal terminal provides a reset signal Vref for the gate of the driving transistor T0; in the bias phase, the compensation module 14 is turned off, the reset module 15 is turned on, and the reset signal terminal provides a bias signal Vobs for the drain of the driving transistor T0; the pixel circuit also includes a latch module 16 and a reset signal line, the reset signal line is used to provide a reset signal Vref or a bias signal Vobs to the reset signal terminal, and the latch module 16 is connected between the gate of the driving transistor T0 and the reset signal line.

[0078] Optionally, in this embodiment, the input end of the driving module 11 is connected to the source of the driving transistor T0, and the output end of the driving module 11 is connected to the drain of the driving transistor T0. Figure 1 In the pixel circuit shown in , the driving transistor T0 is a PMOS transistor; further, the driving transistor T0 may be a low-temperature polysilicon transistor.

[0079] Optionally, in this embodiment, the control end of the data writing module 12 is connected to the second scanning signal line for receiving the second scanning signal S2, and the second scanning signal S2 controls the opening and closing of the data writing module 12; the first end of the data writing module 12 is connected to the data signal input end for receiving the data signal Vdata, and the second end of the data writing module 12 is connected to the input end of the driving module 11; optionally, the data writing module 12 includes a fifth transistor T5, the source of the fifth transistor T5 is connected to the first end of the data writing module 12, and the drain of the fifth transistor T5 is connected to the second end of the data writing module 12.

[0080] Optionally, in this embodiment, the light control module 13 includes a first light control module 13a and a second light control module 13b. The first end of the first light control module 13a is connected to the first power signal end for receiving the first power signal PVDD, and the second end of the first light control module 13a is connected to the input end of the driving module 11; the first end of the second light control module 13b is connected to the output end of the driving module 11, and the second end is connected to the light emitting element 20. The control ends of the first light control module 13a and the second light control module 13b can be connected to the same light control signal line for receiving the light control signal EM, such as Figure 1 As shown; in other optional embodiments, the control ends of the first light control module 13a and the second light control module 13b can also be connected to different light control signal lines for receiving different light control signals. Optionally, the first light control module 13a includes a second transistor T2, the source of which is connected to the first end of the first light control module 13a, and the drain of which is connected to the second end of the first light control module 13a; the second light control module 13a includes a third transistor T3, the source of which is connected to the first end of the second light control module 13b, and the drain of which is connected to the second end of the second light control module 13b;

[0081] Optionally, in this embodiment, the pixel circuit 10 also includes a reset module 15 and a compensation module 14, the reset module 15 is connected between the reset signal terminal and the drain of the driving transistor T0, and is used to provide a reset signal for the gate of the driving transistor T0, and the reset signal includes the first transistor T1; the compensation module 14 is connected between the gate and the drain of the driving transistor T0, and is used to compensate for the threshold voltage of the driving transistor T0; the initialization module 17, the initialization module 17 is connected between the initialization signal terminal and the light-emitting element 20, and is used to selectively provide the initialization signal Vini to the light-emitting element 20.

[0082] Optionally, the source of the first transistor T1 is connected to the reset signal terminal, and the drain is connected to the drain of the driving transistor T0.

[0083] Optionally, the control terminal of the compensation module 14 is connected to the third scan signal line for receiving the third scan signal S3, which controls the on and off of the compensation module 14. The compensation module 14 includes a fourth transistor T4, the source of which is connected to the drain of the driving transistor T0, and the drain of which is connected to the gate of the driving transistor T0. Optionally, the fourth transistor T4 can be a PMOS transistor or an NMOS transistor. When the fourth transistor T4 is a PMOS transistor, the fourth transistor T4 is turned on when the third scan signal S3 is a low-level signal. The fourth transistor T4 can be a low-temperature polysilicon transistor. When the fourth transistor T4 is an NMOS transistor, the fourth transistor T4 is turned on when the third scan signal S3 is a high-level signal. The fourth transistor T4 can be an oxide semiconductor transistor. The following description takes the fourth transistor T4 as an NMOS oxide semiconductor transistor as an example.

[0084] Optionally, the initialization module Vini includes a sixth transistor T6 , wherein the source of the sixth transistor T6 is connected to the initialization signal terminal, and the drain is connected to the light emitting element 20 .

[0085] In this embodiment, the gate of the driving transistor is connected to the reset signal line through a latch module. Since the reset signal line is responsible for providing a reset signal or a bias signal to the reset signal end, and due to differences in function and effect, the voltages of the reset signal and the bias signal are different, resulting in a voltage jump when the signal at the reset signal end is converted between the reset signal and the bias signal. In this embodiment, this voltage jump is used to maintain the gate potential of the driving transistor when the gate voltage of the driving transistor changes.

[0086] Optionally, in this embodiment, the driving transistor T0 is a PMOS transistor, and the voltage of the bias signal Vobs is higher than the voltage of the reset signal Vref; alternatively, the driving transistor T0 is an NMOS transistor, and the voltage of the bias signal Vobs is lower than the voltage of the reset signal Vref. Because the display panel is in a non-biased phase, such as a light-emitting phase, the source of the driving transistor T0 receives the first power supply signal PVDD, and the gate of the driving transistor T0 receives the signal written in the data writing phase. Therefore, when the driving transistor is a PMOS transistor, during the light-emitting phase, the gate potential of the driving transistor T0 may be higher than the drain potential. At this time, the driving transistor is in the on state. If this situation persists for a long time, it may cause the Id-Vg curve of the driving transistor T0 to shift, thereby causing the threshold voltage of the driving transistor T0 to shift. Therefore, to improve this situation, a bias phase is added. During the bias phase, the potential difference between the gate potential and the drain potential of the driving transistor T0 is adjusted to reduce the problem existing in the non-biased phase, which causes the threshold voltage shift of the driving transistor T0, thereby ensuring display uniformity. To mitigate the above problem, for PMOS transistors, the drain potential of the driving transistor T0 needs to be appropriately increased during the bias phase. Therefore, the bias signal Vobs is at a relatively high level, while the reset signal Vref is set to reset the gate of the driving transistor T0. Generally speaking, for PMOS transistors, the reset signal Vref is at a relatively low level. For NMOS transistors, the drain potential of the driving transistor T0 needs to be appropriately reduced during the bias phase. Therefore, the bias signal Vobs is at a relatively low level, while the reset signal Vref is set to reset the gate of the driving transistor T0. Generally speaking, for NMOS transistors, the reset signal Vref is at a relatively high level.

[0087] refer to Figure 7 and Figure 8 , Figure 7 yes Figure 6 One of the working timing diagrams of the pixel circuit shown in FIG. Figure 8 yes Figure 6 The second working sequence diagram of the pixel circuit is shown in FIG. Figure 7 As shown, the working process of the pixel circuit 10 includes a data writing phase. In the data writing phase, the data writing module 12, the driving module 11, and the compensation module 14 are all turned on, and the data signal Vdata is written into the gate of the driving transistor T0. At the end of the data writing phase, the compensation module 14 is turned off, and the signal V0 at the reset signal end is converted from the reset signal Vref to the bias signal Vobs. Or, as shown in FIG. Figure 8 As shown, at the end of the data writing phase, the compensation module 14 is turned off, and after the first interval phase, the signal V0 at the reset signal terminal is transformed from the reset signal Vref to the bias signal Vobs.

[0088] During the data writing phase, the data signal Vdata is written to the gate of the driving transistor T0. At the end of the data writing phase, the compensation module 14 is turned off, which means that the third scanning signal S3 has a falling edge. This process may cause the gate potential of the driving transistor T0, to which the data signal has just been written, to be unstable, and may cause the potential to be pulled down. Therefore, in this embodiment, a latch module 16 is provided between the gate of the driving transistor T0 and the reset signal line. By causing the signal V0 at the reset signal end to have a rising edge at the same time as the falling edge of the third scanning signal S3 or after a first interval, the gate potential of the driving transistor T0 is raised, offsetting the problem caused by the falling edge of the third scanning signal S3, thereby maintaining the gate potential of the driving transistor T0 after the data signal Vdata is written, and ensuring the stability of the driving current in the subsequent light-emitting phase.

[0089] Optionally, the duration of the first interval phase is shorter than the duration of the data writing phase. As previously described, the transition of the signal V0 at the reset signal terminal is intended to offset the instability of the gate potential of the driving transistor T0 caused by the falling edge of the third scanning signal S3. Therefore, if the duration of the first interval phase is too long, the transition of V0 may not effectively achieve this purpose. The data writing phase requires continuous writing of the data signal Vdata to the gate of the driving transistor T0, which requires a certain amount of time. Therefore, the above design is adopted in this embodiment.

[0090] Optionally, in this embodiment, if Figure 8 As shown, when the signal V0 at the reset signal end changes from the reset signal Vref to the bias signal Vobs, the first scanning signal S1 has a falling edge, the reset module 15 is turned on, and the pixel circuit 10 enters the bias stage; or Figure 7 As shown, after the signal V0 at the reset signal end is converted from the reset signal Vref to the bias signal Vobs, after the second interval stage, the first scanning signal S1 has a falling edge, and the reset module 15 is turned on. The simultaneous signal jumps can shorten the time of the front stage of the pixel circuit working process, which is conducive to achieving high-frequency display, and the second interval stage is spaced between the signal jumps, which can provide a certain buffer time for the driving transistor and help improve the stability of the driving transistor. How to set it specifically depends on the specific situation. Optionally, the time length of the second interval stage is less than the time length of the bias stage, because the second interval stage is only used for transition, so it does not need a long time, and the bias stage requires a certain time to achieve the bias effect.

[0091] like Figure 7 and Figure 8As shown, within one frame of the display panel, the working process of the pixel circuit includes a pre-stage and a light-emitting stage; wherein, within at least one frame of the display panel, the pre-stage of the pixel circuit includes a bias stage.

[0092] At least one bias stage of the pre-stage is performed after the data writing stage. As mentioned above, since the jump of the signal V0 at the reset signal end is mainly to offset the change of the falling edge of the third scanning signal S3 after the data is written, and after the signal V0 at the reset signal end jumps from the low-level reset signal Vref to the high-level bias signal Vobs, the first scanning signal S1 controls the reset module 15 to turn on, and the pixel circuit enters a bias stage.

[0093] refer to Figure 9 , Figure 9 yes Figure 6 The third working timing diagram of the pixel circuit in FIG. 1 , wherein the pre-stage may include N bias stages, where N ≥ 1; Figure 9 Two bias stages are shown in FIG. , but the number may be one, three, or more than three. Figure 9 In the embodiment, the pre-stage includes a first bias stage and a second bias stage; the first bias stage is performed before the data writing stage, and the second bias stage is performed after the data writing stage; wherein the duration of the first bias stage is longer than the duration of the second bias stage. The first pre-stage can serve as a main bias stage, and the second bias stage can serve as an auxiliary bias stage. The first pre-stage mainly plays a biasing role, mainly responsible for offsetting the threshold voltage deviation in the non-bias stage. However, in order to prevent the bias effect of the first bias stage from being incomplete, other supplementary bias stages can be set to fully supplement the bias effect.

[0094] Optionally, in this embodiment, the latch module 16 includes a first capacitor C1, wherein the first plate of the first capacitor C1 is connected to the gate of the drive transistor T0, and the second plate is connected to the reset signal line. Because the capacitor has the function of charging and discharging, it can be used as a latch module to regulate the potential of one node relative to another node. Moreover, the capacitor no longer needs to be set up with a separate control terminal for control, which simplifies the structure and process of the pixel circuit.

[0095] Optionally, the pixel circuit further includes a second capacitor C2; one plate of the second capacitor C2 is connected to the gate of the driving transistor T0, and is used to store the data signal transmitted to the gate of the driving transistor T0. Figure 6 As shown, one plate of the second capacitor C2 is connected to the gate of the driving transistor T0, and the other plate is connected to the first power signal terminal for storing data signals.

[0096] In this embodiment, the capacitance value of the first capacitor C1 is optionally smaller than the capacitance value of the second capacitor C2. Since the function of the second capacitor C2 is to store the data signal Vdata written to the gate of the driving transistor T0, and the data signal Vdata written to the gate of the driving transistor T0 is one of the determining factors for the driving current generated by the driving transistor T0 during the light-emitting phase, it is necessary to use a capacitor with a strong storage capacity to fully store the signal of the driving transistor T0 during the data writing phase; and the first capacitor C1 is mainly used to stabilize the gate potential of the driving transistor T0. Therefore, from the perspective of accurately storing data, the storage capacity of the second capacitor C2 is required to be greater than the storage capacity of the first capacitor C1. Therefore, in this embodiment, the capacitance value of the first capacitor C1 is set to be smaller than the capacitance value of the second capacitor C2.

[0097] Furthermore, optionally, the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 satisfy the following relationship: C2×1 / 8≤C1≤C2×1 / 4. The inventors of the present application have discovered that when C2×1 / 8≤C1≤C2×1 / 4, the capacitance value of the first capacitor C1 can meet the requirements of the bias phase and can avoid the problem of an increased load on the pixel circuit and affected signal transmission of the reset signal line due to an excessively large capacitance value of the first capacitor C1.

[0098] In the aforementioned embodiments of the present application, a latch module is mainly added to the pixel circuit to enhance the effect of the bias stage or stabilize the gate potential of the driving transistor. The working process related to the bias stage and the pixel circuit is described in detail in the following section.

[0099] refer to Figures 1-9 In this embodiment, optionally, in this embodiment, the working process of the pixel circuit 10 also includes at least one non-bias stage; in the bias stage, the gate voltage of the driving transistor T0 is Vg1, the source voltage is Vs1, and the drain voltage is Vd1; in the non-bias stage, the gate voltage of the driving transistor is Vg2, the source voltage is Vs2, and the drain voltage is Vd2.

[0100] In some embodiments, |Vg1-Vd1|<|Vg2-Vd2|. By setting |Vg1-Vd1|<|Vg2-Vd2|, the difference between the gate voltage and the drain voltage of the driving transistor T0 during the bias phase is smaller than the difference between the gate voltage and the drain voltage of the driving transistor T0 during the non-bias phase, thereby alleviating the threshold voltage shift phenomenon of the driving transistor T0.

[0101] In other embodiments, (Vg1-Vd1)×(Vg2-Vd2)<0. Here, by setting (Vg1-Vd1)×(Vg2-Vd2)<0, the potential difference between the gate potential and the drain potential of the driving transistor T0 in the non-biased phase is reversed in the biased phase, thereby effectively balancing the threshold voltage shift of the driving transistor T0 caused in the non-biased phase.

[0102] Further optionally, Vd1-Vg1>Vg2-Vd2>0. Here, by setting Vd1-Vg1>Vg2-Vd2>0, by setting a larger difference (Vd1-Vg1), the potential difference between the gate potential and the drain potential of the driving transistor T0 in the non-bias phase can be balanced by another larger reverse potential difference in the bias phase, thereby facilitating shortening the bias phase time.

[0103] In addition, optionally, if the time length of the bias phase is t1 and the time length of the non-bias phase is t2, then (|Vg1-Vd1||-|Vg2-Vd2||)×(t1-t2)<0. Here, when |Vg1-Vd1|| is greater than |Vg2-Vd2||, that is, the reversal potential difference used for biasing is larger, therefore, the time of the bias phase can be set shorter than the non-bias phase; conversely, if |Vg1-Vd1|| is less than |Vg2-Vd2||, that is, the reversal potential difference used for biasing is smaller, then the time of the bias phase can be set longer than the non-bias phase. The purpose of the above design is to fully offset the problem of the threshold voltage offset of the driving transistor generated in the non-bias phase during the bias phase, while avoiding other problems caused by excessive bias phase.

[0104] In the aforementioned embodiment, the non-bias phase is optionally the light emitting phase of the display panel, because in the light emitting phase, the driving transistor T0 provides a driving current to the light emitting element 20, such as Figure 2 In the pixel circuit shown, before the light-emitting element 20 enters the light-emitting phase, a data signal Vdata is first written to the gate of the driving transistor T0 until the gate potential of the driving transistor T0 is (Vdata-Vth). After that, the light-emitting phase begins. Therefore, during the light-emitting phase, the gate potential of the driving transistor T0 is a relatively high potential. In some cases, during the light-emitting phase, for example, the source potential of the driving transistor T0 is 4.6V, the gate potential is 3V, and the drain potential is 1V. Therefore, during the light-emitting phase, the driving transistor T0 is turned on, but the gate potential is higher than the drain potential, which causes the Id-Vg curve to shift, resulting in a shift in the threshold voltage Vth of the driving transistor T0. Therefore, in this embodiment, the light-emitting phase is set as a non-bias phase to solve the above-mentioned technical problems caused by the light-emitting phase.

[0105] refer to Figure 3-Figure 5 , where, optional, such as Figure 3 As shown, within one frame of picture time, it includes a pre-stage and a light-emitting stage, and the pre-stage includes a reset stage and a bias stage in sequence. In the reset stage, the first scanning signal S1 controls the reset module 15 to turn on. Here, the first transistor T1 in the reset module 15 can be a PMOS transistor or an NMOS transistor, and the NMOS transistor can be an oxide semiconductor transistor. The figure takes the PMOS transistor as an example; the third scanning signal S3 controls the compensation module 14 to turn on. Here, the fourth transistor T4 in the compensation module 14 can be a PMOS transistor or an NMOS transistor, and the NMOS transistor can be an oxide semiconductor transistor. The figure takes the NMOS transistor as an example; at this time, the reset signal end provides a reset signal Vref to the gate of the driving transistor T0 through the turned-on reset module 15 and the compensation module 14. V0 is Vref at this time, which is a relatively low low-level signal.

[0106] At the end of the reset phase, the compensation module 14 is turned off. Optionally, at the same time as the compensation module 14 is turned off, i.e., at the falling edge of the third scanning signal S3, the V0 signal at the reset signal terminal rises from the low level Vref to a relatively high high level signal Vobs. At this point, the reset module 15 remains on, and the pixel circuit enters the bias phase. The reset signal terminal provides the bias signal Vobs to the drain of the driving transistor T0. By arranging the bias phase to occur at the end of the reset phase, the duration of the pre-phase can be shortened.

[0107] In addition, optional, such as Figure 3 As shown, at the end of the reset phase, the compensation module 14 is first turned off. After a time interval, the V0 signal at the reset signal end rises from the low level Vref to a relatively high high level signal Vobs. The reset module 15 remains on, and the pixel circuit 10 enters the bias phase. Here, a time interval is set between the reset phase and the bias phase to avoid the simultaneous conversion of multiple signals, which may cause instability in the drive transistor. By stabilizing the drive transistor during the time interval before proceeding to the next step, the stability of the pixel circuit can be improved. Optionally, the length of this time interval is shorter than the length of the reset phase, or the length of this time interval is shorter than the length of the bias phase. Because this time interval is only set to stabilize the drive transistor, it does not need to be too long.

[0108] Optional, such as Figure 4As shown, after the reset phase ends, reset module 15 turns off, while compensation module 14 remains on for a period of time. After this period of time, compensation module 14 turns off, and simultaneously, or thereafter, reset module 15 turns on again. Simultaneously, or before this, the V0 signal at the reset signal terminal rises from a low-level Vref to a relatively high-level signal Vobs, and the pixel circuit enters the bias phase. During this process, if all signals transition simultaneously, this helps shorten the pre-phase duration. However, if there is a time interval between the transitions of each signal, this helps stabilize the drive transistor. The specific design can be flexibly set according to the specific situation.

[0109] Optional, such as Figure 4 As shown, after the reset phase ends, the time period between the reset module 15 being turned off and the compensation module 14 being turned off also includes a data writing phase. After the reset phase ends, the second scanning signal S2 controls the data writing module 12 to turn on, and the data signal Vdata is written into the gate of the driving transistor T0 through the turned-on data writing module 12, the driving module 11 and the compensation module 14. After the data writing phase ends, the compensation module 14 is turned off, and the reset module 15 is turned on again to perform the bias phase.

[0110] Optionally, in this embodiment, the length of the reset phase is shorter than the length of the bias phase, because the purpose of the reset phase is to write the reset signal into the gate of the driving transistor, so it does not need to be too long, while the bias phase is used to offset the threshold voltage offset in the non-bias phase, so a certain length of time is required to achieve the effect, so this setting is made. In addition, if Figure 4 In the situation shown, the duration of the data writing phase is also shorter than that of the biasing phase. This is because the purpose of the data writing phase is to write the data signal into the gate of the driving transistor, which does not require too much time. The biasing phase is used to offset the threshold voltage offset in the non-biasing phase. Therefore, a certain length of time is required to achieve the effect, hence this setting.

[0111] In the aforementioned embodiment, a reset phase is provided before the bias phase, and the gate potential of the driving transistor T0 is first reset to a relatively low-level signal by the reset signal Vref, and then the drain potential of the driving transistor T0 is raised to a relatively high-level signal by the bias signal Vobs. This achieves the purpose of lowering the gate potential of the driving transistor T0 and raising the drain potential of the driving transistor T0 during the bias phase. Adjustments are made from two aspects, which is more conducive to improving the potential difference between the gate and drain of the driving transistor T0, enhancing the effect of the bias phase, and fully offsetting the threshold voltage offset of the driving transistor T0 during the non-bias phase.

[0112] refer to Figure 5Optionally, the pre-stage of this embodiment includes N bias stages, where N ≥ 1; an intermediate stage is included between any two adjacent bias stages in the N bias stages. The reset stage in the aforementioned embodiment can be located before the first bias stage at the beginning of the bias stage, that is, the gate of the driving transistor T0 is reset before the bias stage begins. Alternatively, the reset stage can also be located in the intermediate stage between any two adjacent bias stages, such as the intermediate stage between the first bias stage and the second bias stage, or the intermediate stage between the second bias stage and the third bias stage, etc.; that is, at the beginning of the pre-stage, at least one bias stage is performed before the reset stage. Alternatively, the reset stage can also be located after the last bias stage of the pre-stage, that is, before the light-emitting stage. In this case, it should be noted that the data writing stage must be performed after the reset stage before entering the light-emitting stage. In other aforementioned embodiments, the data writing stage can be performed after the reset stage, or the bias stage can be directly entered without the data writing stage, depending on the specific circumstances.

[0113] For example, Figure 5 Two bias stages are shown in FIG, but the actual situation is not limited to two. Figure 5 As shown, optionally, in the pre-stage, the time lengths of any two bias stages may be unequal. For example, the time length of the first bias stage is greater than the time lengths of the other bias stages. This can be understood as follows: the first bias stage is the main bias stage, which is mainly responsible for offsetting the threshold voltage deviation in the non-bias stage. However, in order to prevent the bias effect of the first bias stage from being incomplete, other supplementary bias stages can be set to fully supplement the bias effect. On this basis, it can be set that the time lengths of the bias stages in the pre-stage are sequentially reduced, so that the bias effect of the previous bias stage can be supplemented by the subsequent bias stages. Based on the same concept, the opposite setting can also be made, such as the time length of the last bias stage is greater than the time lengths of the other bias stages. In particular, in the pre-stage, the time lengths of the bias stages increase sequentially, and the bias effect can be gradually achieved through the bias stages with gradually increasing time lengths. In addition, based on the above ideas, the time length of a certain bias stage in the middle can be set to be longer than the time length of the first bias stage and also longer than the time length of the second bias stage, that is, the final bias stage is used as a supplement, and the middle bias stage is the main bias stage.

[0114] Optionally, in this embodiment, a data writing cycle of the display panel includes a total of S frame refresh images, including a data writing frame and a holding frame, S>0; the data writing frame includes a data writing stage, in which the data writing module writes a data signal to the gate of the driving transistor; the holding frame does not include a data writing stage.

[0115] In one implementation of this embodiment, the pre-stage of at least one data writing frame includes a bias stage. In this case, reference may be made to Figure 4 As shown, the data writing phase can be performed before the biasing phase, after the biasing phase, or between two adjacent biasing phases. When the data writing phase is performed before the biasing phase, it is sufficient to ensure that the compensation module 14 is turned off during the biasing phase and the data signal Vdata is latched at the gate of the driving transistor T0.

[0116] Optionally, in this embodiment, if the time length of the pre-stage is T11, the sum of the time of all bias stages in the pre-stage is T22. After verification by the inventor, it is found that when T22≤2 / 3×T11, it can avoid the bias stage occupying the pre-stage for too long, which leads to an increase in the pre-stage time, resulting in a decrease in the refresh frequency of the display panel and affecting the display effect.

[0117] In another implementation of this embodiment, the pre-stage of at least one holding frame includes a bias stage. In this case, the pre-stage may include a bias stage and does not include a data writing stage. Optionally, the pre-stage may also include a reset stage, such as Figure 3 As shown, the reset phase may be omitted and the bias phase may be performed directly. In this case, if the duration of the pre-phase is T11, the sum of the durations of all the bias phases in the pre-phase is T22. According to the inventors' verification, T22 can be made equal to T11, that is, the entire pre-phase is the bias phase, or T22 ≥ 2 / 3 × T11. This allows the pre-phase time to be fully utilized for the bias phase, thereby avoiding an excessively long pre-phase and achieving a better biasing effect.

[0118] It should be noted that in this embodiment, only the pre-stage of the data write frame may include the bias stage, while the pre-stage of the hold frame may not include the bias stage. In this case, if the bias problem can be solved by only utilizing the data write frame, then the bias stage can be omitted from the hold frame. Alternatively, only the pre-stage of the hold frame may include the bias stage, while the pre-stage of the data write frame may not include the bias stage. Because the data write frame also performs the tasks of the reset stage and the data write stage, if the hold frame can fully perform the tasks of the bias stage, then the bias stage can be omitted from the data write frame, thereby simplifying the timing of the data write frame.

[0119] In another embodiment of the present embodiment, it is also possible to select the pre-stage of at least one holding frame and the pre-stage of at least one data writing frame to both include a bias stage. By so setting, the work of the bias stage can be jointly undertaken by the holding frame and the data writing frame to ensure the effect of the bias stage. Optionally, the time length of the bias stage in the holding frame can be longer than the time length of at least one bias stage in the data writing frame. As mentioned above, the pre-stage of the holding frame does not include the data writing stage, so its timing is relatively simple, which can make the bias stage time in the holding frame longer and the at least one bias stage time in the data writing frame shorter, thereby avoiding the pre-stage time of the data writing frame to be too long. On this basis, it is also possible to set the sum of the time lengths of the bias stages in the holding frame to be greater than or equal to the sum of the time lengths of the bias stages in the data writing frame. Further, optionally, the time length of the bias stage in the holding frame is longer than the time length of any one bias stage in the data writing frame to fully avoid the pre-stage time of the data writing frame to be too long.

[0120] In addition, in this embodiment, Figure 3 As shown in the above description, the start-up time of the initialization module 17, that is, the initialization phase of the pixel circuit, may not overlap with the bias phase, or may partially overlap with the bias phase. The initialization phase may end at the same time as the bias phase, or the initialization phase may end before or after the bias phase, depending on the specific situation.

[0121] In addition, in this embodiment, the display panel may further include an integrated chip, which is used to provide the pixel circuit with required drive signals, such as the data signal Vdata, the reset signal Vref, the bias signal Vobs, etc. Based on the same inventive concept, the integrated chip provided in this embodiment provides the reset signal Vref to the reset signal terminal during the reset phase of the pixel circuit, and provides the bias signal Vobs to the reset signal terminal during the bias phase of the pixel circuit, thereby ensuring the operation of the pixel circuit in this embodiment. For specific information about the reset signal Vref and the bias signal Vobs, please refer to the description of the aforementioned embodiment.

[0122] In the present application, some of T0, T1, T2, T3, T4, T5 and T6 can be PMOS using polysilicon as the active layer, and some can be NMOS using oxide semiconductor as the active layer. For example, T4 is an NMOS transistor, and the other transistors are PMOS transistors; or, T0 and T1 are transistors of the same type, such as a PMOS transistor or an NMOS transistor, and at least one of the remaining transistors is a transistor of another type, such as an NMOS transistor or a PMOS transistor. It can be understood that the effective pulse of the scanning signal of the NMOS transistor is a high level, and the effective pulse of the scanning signal of the PMOS transistor is a low level. It should be noted that Figures 1 to 9 The pixel circuit shown is only an example, and the structure of the pixel circuit in the embodiment of the present invention is not limited thereto.

[0123] Optionally, the width-to-length ratio of the channel region of the NMOS transistor is greater than the width-to-length ratio of the channel region of the PMOS transistor. In this application, if the NMOS transistor mainly plays the role of a switching transistor, it requires a rapid response capability, and the transistor with a large width-to-length ratio has a shorter channel region length, which is beneficial to improving the response capability of the transistor.

[0124] In addition, in the present application, the four scanning signals S1, S2, S3, and S4 can be different signals. In certain specific cases, such as when the timing meets certain conditions, at least two of the four signals S1, S2, S3, and S4 can also be the same signal. For example, when T5 and T6 are the same type of transistors, such as both PMOS or both NMOS, then S1 and S4 can be the same signal. For another example, when T4 and T6 are the same type of transistors, such as both PMOS or both NMOS, then S3 and S4 can be the same signal. The specific situation depends on the specific circuit structure and timing, and this embodiment does not specifically limit this.

[0125] refer to Figure 10 , Figure 10 This is a partial cross-sectional schematic diagram of a pixel circuit, in which the pixel circuit includes two types of transistors: a transistor Tm and a transistor Tn. The gate of transistor Tm is located in the first metal layer M1, and the source and drain are both located in the fourth metal layer M4. Transistor Tm includes a first active layer w1 located between the first metal layer M1 and the substrate. Transistor Tn includes a first gate and a second gate. The first gate is located in the second metal layer M2, and the second gate is located in the third metal layer M3. Transistor Tn includes a second active layer w2 located between the second metal layer M2 and the third metal layer M3, and the source and drain of transistor Tn are located in the fourth metal layer M4. Transistor Tm may be a low-temperature polysilicon transistor, and transistor Tn may be an oxide semiconductor transistor.

[0126] The pixel circuit includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 includes a first plate C11 and a second plate C12, the second capacitor C2 includes a third plate C23 and a fourth plate C24, the first plate and the second plate are located in any two of the six film layers: the first active layer w1, the first metal layer M1, the second metal layer M2, the second active layer w2, the third metal layer M3, and the fourth metal layer; the third plate and the fourth plate are located in any two of the six film layers: the first active layer w1, the first metal layer M1, the second metal layer M2, the second active layer w2, the third metal layer M3, and the fourth metal layer M4.

[0127] In some cases, the first electrode plate and the third electrode plate are located on the same layer, and the second electrode plate and the fourth electrode plate are located on the same layer. In this case, the area of ​​the first electrode plate is smaller than that of the third electrode plate, and the area of ​​the second electrode plate is smaller than that of the fourth electrode plate, so that the capacitance value of the first capacitor C1 is smaller than the capacitance value of the second capacitor C2.

[0128] In some cases, the first electrode plate and the third electrode plate are located in the same layer, and the second electrode plate and the fourth electrode plate are located in different layers. Optionally, the distance between the first electrode plate and the second electrode plate is greater than the distance between the third electrode plate and the fourth electrode plate, so that the capacitance value of the first capacitor C1 can be smaller than the capacitance value of the second capacitor C2; in this case, optionally, the first electrode plate and the third electrode plate are located in the first metal layer M1, the fourth electrode plate is located in the second metal layer M2, and the second metal layer is located in the second active layer, or the third metal layer M3, or the fourth metal layer M4.

[0129] In some cases, the first electrode plate, the second electrode plate, the third electrode plate, and the fourth electrode plate are all located in different film layers, and their specific positions can be located in any one of the six film layers: the first active layer w1, the first metal layer M1, the second metal layer M2, the second active layer w2, the third metal layer M3, and the fourth metal layer M4, all of which are within the protection scope of this situation.

[0130] Optionally, a first insulating layer is included between the first plate and the second plate, and a second insulating layer is included between the third plate and the fourth plate, wherein the dielectric constant of the first insulating layer is less than the dielectric constant of the second insulating layer, thereby making the capacitance value of the first capacitor C1 less than the capacitance value of the second capacitor C2. In addition, optionally, when the driving transistor is a PMOS transistor, the transistor Tm can be the driving transistor. In this case, the hydrogen content of the second insulating layer is greater than the hydrogen content in the first insulating layer. Because, in this embodiment, the second capacitor C2 is a storage capacitor in the pixel circuit, and in the direction perpendicular to the surface of the display panel, the second capacitor C2 generally overlaps with the driving transistor, and the driving transistor has a top-gate structure. Therefore, the second capacitor C2 is generally located on the side of the first active layer w1 away from the substrate. In particular, the third plate C23 of the second capacitor C2 can be reused with the gate of the transistor Tm, and the fourth plate can be located on the second metal layer M2 and overlap with the gate of the transistor Tm. At this time, the driving transistor is a PMOS transistor, which can be optionally a low-temperature polysilicon transistor. The active layer of the low-temperature polysilicon transistor needs to be hydrogenated, which results in a higher hydrogen content in the surrounding film layer. Therefore, in this embodiment, the hydrogen content of the second insulating layer is greater than the hydrogen content in the first insulating layer.

[0131] Optionally, the oxygen content in the first insulating layer is greater than the oxygen content in the second insulating layer. Because the first capacitor C1 is smaller than the second capacitor C2, in some cases, the thickness of the first insulating layer is greater than the thickness of the second insulating layer. Therefore, among the first plate and the second plate of the first capacitor C2, at least one plate is closer to the active layer of the transistor Tn, that is, the active layer of the oxide semiconductor transistor, than the third plate and the fourth plate. In order to ensure the normal function of the oxide semiconductor transistor, the hydrogen content in the film layer around the oxide semiconductor active layer is relatively small, and the oxygen content is relatively high. Therefore, in this case, the oxygen content in the first insulating layer is greater than the oxygen content in the second insulating layer.

[0132] Based on the same inventive concept, an embodiment of the present invention further provides a method for driving a display panel, wherein the display panel includes a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a data writing module 12, a driving module 11, a compensation module 14, and a reset module 15; the data writing module 12 is connected between a data signal input terminal and a source of a driving transistor T0, and is used to provide a data signal Vdata to the driving module 11; the driving module is used to provide a driving current to the light-emitting element 20, and the driving module 11 includes a driving transistor T0; the compensation module 14 is connected between a gate of the driving transistor T0 and a drain of the driving transistor T0, and is used to compensate for a threshold voltage of the driving transistor T0; the reset module 15 is connected between a reset signal terminal and the drain of the driving transistor T0, and is used to provide a reset signal Vref to the gate of the driving transistor T0; wherein the reset module 15 is also multiplexed as a bias module;

[0133] The driving method of the display panel includes:

[0134] Reset stage: In the reset stage, the reset module 15 and the compensation module 14 are turned on, and the reset signal terminal provides a reset signal to the gate of the driving transistor T0 to reset the gate of the driving transistor T0;

[0135] Bias stage: In the bias stage, the reset module 15 is turned on and the compensation module 14 is turned off. The reset signal terminal provides a bias signal Vobs to the drain of the driving transistor T0 to adjust the bias state of the driving transistor T0.

[0136] In other implementations of this embodiment, the driving method may include the driving method adopted in the working process of the pixel circuit in any of the aforementioned implementations. This embodiment will not repeat the same content, but it should be considered that all are within the protection scope of the driving method provided in this embodiment.

[0137] Based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising a display panel as described in any of the above embodiments. Optionally, the display panel may be an organic light-emitting display panel or a micro LED display panel.

[0138] refer to Figure 11 , Figure 11 is a schematic diagram of a display device provided by an embodiment of the present invention, such as Figure 11 As shown, the display device can be optionally applied to electronic devices 100 such as smart phones and tablet computers. It can be understood that the above embodiments only provide some examples of pixel circuit structures and pixel circuit driving methods. The display panel also includes other structures, which will not be described in detail here.

[0139] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module, a data writing module, a compensation module and a reset module; The driving module includes a driving transistor; The data writing module is connected to the source of the driving transistor and is used to selectively provide a data signal to the driving transistor; The compensation module is connected between the gate and the drain of the driving transistor; The reset module is connected between the drain of the driving transistor and the reset signal terminal, and is used to provide a reset signal to the gate of the driving transistor; wherein, The reset module is multiplexed as a bias module, and the working process of the pixel circuit includes a reset phase and a bias phase: In the reset phase, the compensation module and the reset module are turned on, and the reset signal terminal provides the reset signal to the gate of the driving transistor; In the bias phase, the compensation module is turned off, the reset module is turned on, and the reset signal terminal provides a bias signal to the drain of the driving transistor; The pixel circuit further includes a latch module and a reset signal line, wherein the reset signal line is used to provide the reset signal or the bias signal to the reset signal terminal, and the latch module is connected between the gate of the driving transistor and the reset signal line.

2. The display panel according to claim 1, wherein: The pixel circuit further includes a light emitting control module; The light-emitting control module is used to selectively allow the light-emitting element to enter the light-emitting stage. One end of the light-emitting control module is connected to the first power signal end for receiving a first power signal.

3. The display panel according to claim 1, wherein: The driving transistor is a PMOS transistor, and the voltage of the bias signal is higher than the voltage of the reset signal; The driving transistor is an NMOS transistor, and the voltage of the bias signal is lower than the voltage of the reset signal.

4. The display panel according to claim 1, wherein: The working process of the pixel circuit includes a data writing phase, in which the data writing module, the driving module, and the compensation module are all turned on, and the data signal is written into the gate of the driving transistor; wherein, At the end of the data writing phase, the compensation module is turned off and the signal at the reset signal end is converted from the reset signal to the bias signal; or At the end of the data writing phase, the compensation module is turned off, and after a first interval phase, the signal at the reset signal end is converted from the reset signal to the bias signal.

5. The display panel according to claim 4, wherein: The duration of the first interval phase is shorter than the duration of the data writing phase.

6. The display panel according to claim 4, wherein: When the data writing phase ends, the compensation module is turned off, and when the signal at the reset signal end changes from the reset signal to the bias signal, the signal at the reset signal end maintains the gate potential of the driving transistor through the latch module.

7. The display panel according to claim 4, wherein: When the signal at the reset signal end changes from the reset signal to the bias signal, the reset module is turned on, and the pixel circuit enters the bias stage; or, After the signal at the reset signal end is transformed from the reset signal to the bias signal, the reset module is turned on after a second interval period.

8. The display panel according to claim 4, wherein: During one frame of the display panel, the operation process of the pixel circuit includes a pre-stage and a light-emitting stage; wherein, During at least one frame of picture time, the pre-stage of the pixel circuit includes the bias stage.

9. The display panel according to claim 8, wherein: At least one of the bias phases of the pre-phase is performed after the data writing phase.

10. The display panel according to claim 8, wherein The pre-stage includes a first bias stage and a second bias stage; The first bias phase is performed before the data writing phase, and the second bias phase is performed after the data writing phase; wherein, The time length of the first bias stage is longer than the time length of the second bias stage.

11. The display panel according to claim 1, wherein The latch module includes a first capacitor, a first plate of the first capacitor is connected to the gate of the driving transistor, and a second plate of the first capacitor is connected to the reset signal line.

12. The display panel according to claim 10, wherein: The pixel circuit further includes a second capacitor; The pixel circuit further includes a light emitting control module, the light emitting control module is used to selectively allow the light emitting element to enter the light emitting stage, and one end of the light emitting control module is connected to the first power signal end for receiving the first power signal; The second capacitor is connected between the first power signal terminal and the gate of the driving transistor, and is used to store the data signal transmitted to the gate of the driving transistor; The capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor.

13. The display panel according to claim 10, wherein: The capacitance value of the first capacitor is C1, and the capacitance value of the second capacitor is C2, wherein C2×1 / 8≤C1≤C2×1 / 4.

14. A display device, characterized in that: A display panel comprising any one of claims 1-13.

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