GOA aging burn-in hidden danger optimization method based on chamfering technology

Abstract

The invention belongs to the technical field of liquid crystal screens, and provides a GOA aging and burn-in hidden danger optimization method based on a chamfering technology, and the method comprises the steps: receiving a first control signal and a second control signal through a level translator, controlling to generate a gate drive signal, determining the starting time of the rising edge of the gate drive signal according to the rising edge of the first control signal, and outputting the starting time of the rising edge of the gate drive signal; determining the ending moment of the rising edge of the gate drive signal according to the falling edge of the first control signal, determining the starting moment of the falling edge of the gate drive signal according to the rising edge of the second control signal, and determining the ending moment of the falling edge of the gate drive signal according to the falling edge of the second control signal; the pulse width of the first control signal and the pulse width of the second control signal are adjusted to prolong or shorten the duration of the rising edge and the falling edge of the gate drive signal, and a chamfer waveform with slowed rising and falling slopes is formed; the aging risk of the display screen can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of liquid crystal display driving technology, and in particular to a method for optimizing the hidden dangers of GOA aging and screen burn-in based on angle chamfering technology. Background Art

[0002] In the current LCD GOA drive circuit, the function of Levelshift is to convert the low voltage control signal into a high voltage drive signal, so that the GOA circuit can control the high voltage gate line (GATE) switching. Levelshift generates the CLK signal required for the screen GOA drive through the rising or falling edge of the two signals CPV1 and CPV2 (the definition may vary in different chips), such as Figure 1-2 As shown, the rising and falling edges of the output CLK waveform are steep, and the screen GOA drive circuit is a capacitive load. The peak current at the rising and falling edges of the CLK waveform is very large due to the capacitor charging and discharging effect. The equivalent capacitance varies greatly due to the LCD production process or design or the discrete parameters of TFT devices. When the equivalent capacitance is large enough, the peak current is very large and long-term operation can easily damage the glass circuit, causing aging of the display screen.

[0003] Existing technology implements protection by setting channel OCP protection parameters for the Levelshift output: the OCP protection current threshold, the OCP current detection time threshold, and the number of continuous overcurrent detection times. This solution is designed to shut off the output (without causing a safety incident) when a short circuit occurs within the display or a spike current lasting longer than 2µs. However, some displays with large equivalent capacitance due to production processes, designs, or discrete TFT device parameters experience particularly high spike currents, sometimes exceeding 500mA. However, if the duration does not reach the minimum detection threshold, protection will not be provided. Prolonged high-temperature aging and current shocks can cause the display to burn out.

[0004] Currently, common OCP protection mechanisms include Figure 3 As shown in the figure, the first type is without I2C control, and the OCP protection value parameters are fixed and cannot be adjusted; the second type is with I2C control, and the OCP protection value parameters are adjustable. The details of these two types are as follows: 1. Detecttime is the OCP detection time setting. To avoid false triggering caused by LCD load consistency and CLK rising and falling edge pulse current, the current minimum setting in the chip industry is 2us; 2. Detectlevel is the OCP detection current setting; 3. In actual applications, the pulse currents at the rising and falling edges of the CLK of different screens are tested to have large peak currents (ranging from 200mA to 700mA), and the duration of the current exceeding the Detectlevel is short (often tens to hundreds of ns), which does not meet the chip protection conditions. Summary of the Invention

[0005] In view of the above technical problems, the present invention provides a GOA aging and burn-in risk optimization method based on corner chamfering technology to reduce the aging risk of display screens.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] The present invention discloses a method for optimizing the potential risk of GOA aging and screen burn-in based on a chamfering technology. The method is applied to a GOA drive control circuit, wherein the GOA drive control circuit includes a level converter, and the level converter is controlled to output a gate drive signal. The method includes: Receiving a first control signal and a second control signal through the level converter, and controlling the generation of the gate drive signal, wherein the starting time of the rising edge of the gate drive signal is determined according to the rising edge of the first control signal, the ending time of the rising edge of the gate drive signal is determined according to the falling edge of the first control signal, the starting time of the falling edge of the gate drive signal is determined according to the rising edge of the second control signal, and the ending time of the falling edge of the gate drive signal is determined according to the falling edge of the second control signal; By adjusting the pulse width of the first control signal and the second control signal, the duration of the rising edge and the falling edge of the gate drive signal is extended or shortened, and a chamfered waveform with slowed rising and falling slopes is formed, so as to reduce the instantaneous peak current generated by the gate drive signal when charging and discharging the capacitive load.

[0008] Furthermore, a resistor is connected in series between the output end of the GOA drive control circuit and the corresponding gate line to limit the instantaneous peak current when the gate drive signal is output to the gate line.

[0009] Furthermore, the gate driving signal is equal to or not equal to a high level or a low level in a normal state outside the chamfering phase.

[0010] The technical solution disclosed in this disclosure has the following beneficial effects: This disclosure flexibly adjusts the rising and falling slopes of the gate drive signal output by the level converter, effectively and significantly reducing capacitor charge and discharge spike currents without affecting the normal operation of the LCD screen. This avoids the risk of screen burn-in caused by long-term high-temperature aging, thereby improving the utilization rate of relatively low-quality LCD screens without incurring additional costs. It is applicable to all current GOA-type LCD screens. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1This is a schematic diagram of the CLK waveform output by Levelshift in the background technology of this specification; Figure 2 This is a schematic diagram of the CLK signal charging and discharging a load in the background technology of this specification; Figure 3 Schematic diagram of a general OCP protection mechanism in the background technology of this specification; Figure 4 This is a principle flow chart of a method for optimizing the potential risk of GOA aging and screen burn-in based on corner cutting technology in an embodiment of this specification; Figure 5 This is a circuit diagram of the liquid crystal GOA control unit of the 4T1C unit in the embodiment of this specification; Figure 6 is a waveform diagram of the gate driving signal in the embodiment of this specification. DETAILED DESCRIPTION

[0012] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or that other methods, components, devices, steps, etc. may be employed. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0013] like Figure 4 As shown, the embodiment of this specification provides a method for applying to a GOA drive control circuit, wherein the GOA drive control circuit includes a level converter, wherein the level converter is controlled to output a gate drive signal, and the level converter is an existing Levelshift IC chip. The method includes steps S101-102: In step S101, a first control signal and a second control signal are received by the level converter, and the gate drive signal is controlled to be generated, wherein the starting time of the rising edge of the gate drive signal is determined according to the rising edge of the first control signal, the ending time of the rising edge of the gate drive signal is determined according to the falling edge of the first control signal, the starting time of the falling edge of the gate drive signal is determined according to the rising edge of the second control signal, and the ending time of the falling edge of the gate drive signal is determined according to the falling edge of the second control signal; In step S102, the pulse widths of the first control signal and the second control signal are adjusted to extend or shorten the duration of the rising edge and the falling edge of the gate drive signal, and to form a chamfered waveform with slowed rising and falling slopes, so as to reduce the instantaneous peak current generated by the gate drive signal when charging and discharging the capacitive load.

[0014] Among them, such as Figure 5 As shown in Figure 2, the control principle of GOA is: Step 1: STV is the gate start signal at the beginning of a frame. When the STV high level pulse is H, transistor Q8 is turned on, and the gate of transistor Q9 is high, making transistor Q9 in the pre-on state; Step 2: Then when CK1 becomes H, the signal G(n-1) is high, turning on transistor Q26 to send DATA from Source, and the grayscale level is sent to the liquid crystal electrode, causing the liquid crystal to deflect and control the corresponding primary color light passing through; Step 3: Signal G(n-1) is simultaneously sent to transistor Q12 of the next-stage GOA unit as a turn-on signal, putting transistor Q13 in a pre-turn-on state. When signal CK5 is high, transistor Q13 turns on and G(n) is high, turning on transistor Q27. G(n) is also sent to the previous-stage reset unit to turn on transistors Q10 and Q11, pulling the gates of transistors Q9 and Q26 down to VSS to cut off.

[0015] Take a 3840*2160 RGB color screen as an example: there are a total of 3840*2160*3=2.83392 million pixels. When using the CLK GOA architecture, a single CLK requires 360 pulses for each frame. The GOA circuit is subjected to the impact of this capacitive load spike current for a long time. Due to the LCD screen production process or design or the discrete TFT device parameters, the equivalent capacitance varies greatly. When the equivalent capacitance is large enough, long-term operation can easily damage the glass circuit.

[0016] In the present invention, as described in the above steps S101-102, based on the existing Leveshift IC chip using the corner cutting technology, combined with Figure 6 The first and second control signals are CLK1_IN and CLK2_IN, respectively, and the gate drive signal is CLK_OUT. The rising edge of CLK1_IN determines the starting position of the rising edge of CLK_OUT, and the falling edge of CLK1_IN determines the ending position of the rising edge of CLK_OUT. The rising edge of CLK2_IN determines the starting position of the falling edge of CLK_OUT, and the falling edge of CLK2_IN determines the ending position of the falling edge of CLK_OUT. By adjusting the pulse width of CLK1_IN and CLK2_IN, and thus the rising and falling slopes of CLK_OUT, the instantaneous peak current of the capacitor charging can be effectively reduced.

[0017] Figure 6 In this scheme, CKI1_IN serves as the enable source and CKI2_IN as the disable source. By controlling the phase difference between CKI1_IN and CKI2_IN, the CLK_OUT pulse width required by the LCD panel can be created. Specifically, by adjusting the pulse widths of the first control signal CLK1_IN and the second control signal CLK2_IN, the rising and falling slopes of the gate drive signal CLK_OUT can be flexibly controlled, achieving controllable "chamfering" of the output waveform edge slope. In other words, the timing coordination of these two control signals eliminates the abrupt transitions of the rising and falling segments of CLK_OUT, resulting in a gradual transition with a defined slope, referred to in the industry as "chamfering," which avoids the vertical jumps of traditional rectangular waveforms.

[0018] During the rising edge of CLK1_IN, the internal logic circuit of the chip controls the first-stage AVDD voltage high-side transistor to turn on and supply CLK_OUT. The internal circuit of the chip controls the gate drive current of the first-stage AVDD high-side transistor to be small and controllably gradual within the duration of the CLK1_IN pulse width. Therefore, the rising edge of CLK_OUT in this stage has a gradual change process with a certain slope. During the falling edge of CLK1_IN, the internal logic circuit of the chip controls the second-stage VGH voltage high-side transistor to turn on and supply CLK_OUT.

[0019] During the rising edge of CLK2_IN, the internal logic circuit of the chip controls the first-stage AVDD voltage down-pipe to turn on and supply CLK_OUT. During the duration of the CLK2_IN pulse width, the internal circuit of the chip controls the gate drive current of the first-stage AVDD down-pipe to be small and controllably gradual. Therefore, the falling edge of CLK_OUT in this stage has a gradual change process with a certain slope. During the falling edge of CLK2_IN, the internal logic circuit of the chip controls the second-stage VGL voltage down-pipe to turn on and supply CLK_OUT.

[0020] In addition, except for the time when the chamfer is not applied, CLK high is still equal to VGH, and CLK low is still equal to VGL, which does not affect the opening and closing of the TFT gate, and therefore does not affect the liquid crystal charging time. In addition, the falling edge chamfer can also play a multi-level gate drive role, reducing the impact of TFT junction capacitance on the pixel liquid crystal voltage when closed.

[0021] As can be seen, by flexibly adjusting the rising and falling slopes of the gate drive signal output by the level converter, the peak current of capacitor charging and discharging can be effectively and significantly reduced without affecting the normal operation of the LCD screen, thus avoiding the risk of screen burn-in caused by long-term high-temperature aging, thereby improving the utilization rate of relatively low-quality LCD screens without adding additional costs. This is applicable to all current GOA-type LCD screens.

[0022] In another optional embodiment, a resistor is connected in series between the output end of the GOA drive control circuit and the corresponding gate line to limit the instantaneous peak current when the gate drive signal is output to the gate line.

[0023] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and embodiments are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A method for optimizing the potential risk of GOA aging and screen burn-in based on corner cutting technology, characterized in that: The method is applied to a GOA drive control circuit, wherein the GOA drive control circuit includes a level converter, and the level converter is controlled to output a gate drive signal. The method includes: Receiving a first control signal and a second control signal through the level converter, and controlling the generation of the gate drive signal, wherein the starting time of the rising edge of the gate drive signal is determined according to the rising edge of the first control signal, the ending time of the rising edge of the gate drive signal is determined according to the falling edge of the first control signal, the starting time of the falling edge of the gate drive signal is determined according to the rising edge of the second control signal, and the ending time of the falling edge of the gate drive signal is determined according to the falling edge of the second control signal; By adjusting the pulse width of the first control signal and the second control signal, the duration of the rising edge and the falling edge of the gate drive signal is extended or shortened, and a chamfered waveform with slowed rising and falling slopes is formed, so as to reduce the instantaneous peak current generated by the gate drive signal when charging and discharging the capacitive load.

2. The method for optimizing the GOA aging and screen burn-in risk based on the angle cutting technology according to claim 1, characterized in that: A resistor is connected in series between the output end of the level converter and the corresponding gate line to limit the instantaneous peak current when the gate driving signal is output to the gate line.

3. The method for optimizing GOA aging and screen burn-in hazards based on angle cutting technology according to claim 1, characterized in that: The gate driving signal is equal to or not equal to a high level or a low level in a normal state outside the chamfering phase.

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