Signal development caching in memory device

Abstract

The application is directed to developing a cache for signals in a memory device. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache memory configured to store a signal to a logic state that may be stored at the memory array (e.g., in accordance with various read or write operations). For example, a signal (e.g., a cache memory signal, a signal state) associated with a memory state (e.g., a memory state). In various examples, accessing the memory device may include developing cache memory or the memory array, or both, access information from the signal based on various mappings or operations of the memory device.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 201980084212.3, application date December 20, 2019, and invention name “Signal Development Cache Storage in Memory Device”.

[0003] Cross Reference

[0004] This patent application claims priority to PCT Application No. PCT / US2019 / 067829 filed on December 20, 2019, by Yudanov et al., entitled “SIGNAL DEVELOPMENT CACHING IN A MEMORY DEVICE,” which claims priority to U.S. Provisional Patent Application No. 62 / 783,388 filed on December 21, 2018, by Yudanov et al., entitled “MULTIPLEXED SIGNAL DEVELOPMENT IN AMEMORY DEVICE,” each of which is assigned to the assignee of the present invention and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field of the present invention relates to signal exploitation caching in memory devices. Background Art

[0006] The following relates generally to memory systems, and more particularly to signal development caching in memory devices.

[0007] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states in the memory device. For example, a binary memory device has two logical states, typically represented by a logical "1" or a logical "0." Other memory devices can store more than two logical states. To access stored information, components of the electronic device can read or sense the stored logical states in the memory device. To store information, components of the electronic device can write or program the logical states in the memory device.

[0008] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selected memory, chalcogenide memory technology, and others. Memory cells can be volatile or nonvolatile. Summary of the Invention

[0009] An apparatus is described. The apparatus may include: a memory array having a plurality of memory cells, each of the plurality of memory cells being associated with one of a plurality of access lines of the memory array; a signal development cache having a plurality of storage elements different from the plurality of memory cells of the memory array; a sense amplifier array having a plurality of sense amplifiers, each of the plurality of sense amplifiers configured to output a logic state based at least in part on sensing signaling from the signal development cache; a first selection component operable to selectively couple the plurality of access lines of the memory array with the signal development cache; and a second selection component operable to selectively couple the signal development cache with the plurality of sense amplifiers of the sense amplifier array.

[0010] A method is described. The method may include coupling a plurality of access lines of a memory array to a signal development cache, wherein each of the plurality of access lines corresponds to a respective one of a group of memory cells of the memory array. The method may involve, at each of a plurality of cache elements of the signal development cache and based on coupling the plurality of access lines to the signal development cache, storing a cache signal state corresponding to a logic state stored by a respective one of the group of memory cells. The method may include coupling the plurality of cache elements of the signal development cache to a sense amplifier array based on the storing. The method may involve, at each of a plurality of sense amplifiers of the sense amplifier array, sensing a respective logic signal based at least in part on the stored respective signal state and the coupling of the plurality of cache elements to the sense amplifier array.

[0011] A method is described. The method may include receiving a write command at a memory device including a memory array, the write command including a plurality of logic states for writing to a plurality of memory cells of the memory array. The method may involve determining, based at least in part on the write command, that a corresponding cache signal for each of the plurality of logic states is to be stored at a corresponding storage element among a plurality of storage elements of a signal development cache. The method may include, based on the determination, coupling a plurality of sense amplifiers of a sense amplifier array to the plurality of storage elements of the signal development cache to store the corresponding cache signal for each of the plurality of logic states in the corresponding storage element. The method may involve, after storing the corresponding cache signal for each of the plurality of logic states in the corresponding storage element, coupling the plurality of storage elements to the plurality of memory cells. The method may include writing the plurality of logic states to the plurality of memory cells of the memory array based on coupling the plurality of storage elements to the plurality of memory cells.

[0012] An apparatus is described. The apparatus may include: a memory array comprising a plurality of memory cells; a signal development cache comprising a plurality of cache elements distinct from a group of memory cells; a sense amplifier comprising a plurality of sense amplifiers; and a controller operable to: couple a plurality of access lines of the memory array to the signal development cache, wherein each of the plurality of access lines corresponds to a respective one of the plurality of memory cells; store, at each of the plurality of cache elements and based at least in part on coupling the plurality of access lines to the signal development cache, a signal state corresponding to a logic state stored by the respective one of the plurality of memory cells; couple the plurality of cache elements to a sense amplifier array based on the storing; and sense, at each of the plurality of sense amplifiers, a respective logic signal based on the respective signal state and coupling the plurality of cache elements to the sense amplifier array.

[0013] An apparatus is described. The apparatus may include: a memory array comprising a plurality of memory cells; a signal development cache comprising a plurality of cache elements distinct from a group of memory cells; a sense amplifier comprising a plurality of sense amplifiers; and a controller operable to: receive a write command comprising a plurality of logic states for writing to the plurality of memory cells; determine, based at least in part on the write command, to store a corresponding cache signal for each of the plurality of logic states at a corresponding one of the plurality of cache elements; couple the plurality of sense amplifiers to the plurality of cache elements to store the corresponding cache signal for each of the plurality of logic states to the corresponding cache element based on the determination; after storing the corresponding cache signal for each of the plurality of logic states to the corresponding cache element, couple the plurality of cache elements to the plurality of memory cells; and write the plurality of logic states to the plurality of memory cells based on coupling the plurality of cache elements to the plurality of memory cells.

[0014] An apparatus is described. The apparatus may include: a memory array having a plurality of memory cells, each of the plurality of memory cells being associated with one of a plurality of access lines of the memory array; a signal development cache having a plurality of cache elements distinct from the plurality of memory cells of the memory array; a sense amplifier array having a plurality of sense amplifiers, each of the plurality of sense amplifiers configured to output a logic state based on latching signaling from the signal development cache; and selection circuitry operable to: selectively couple the plurality of access lines of the memory array with the signal development cache; selectively couple the signal development cache with the plurality of sense amplifiers of the sense amplifier array; selectively couple the plurality of access lines of the memory array with the plurality of sense amplifiers of the sense amplifier array; or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Illustrated is an example memory device that develops caching according to support signals as examples disclosed herein.

[0016] Figure 2 Illustrated are example circuits that support signal development caching in a memory device according to examples as disclosed herein.

[0017] Figure 3Illustrated are example circuits that support signal development caching in a memory device according to examples as disclosed herein.

[0018] Figure 4A and 4B Illustrated is an example of a read operation of a signal development cache in a supporting memory device according to examples as disclosed herein.

[0019] Figure 5A and 5B Illustrated is an example of a write operation that supports signal development cache in a memory device according to examples as disclosed herein.

[0020] Figure 6 Illustrated are examples of signal development components supporting signal development caching in a memory device according to examples as disclosed herein.

[0021] Figure 7 Illustrated are examples of sense amplifiers supporting signal development caching in a memory device according to examples as disclosed herein.

[0022] Figure 8A 、 8B 8C shows a block diagram of a system that supports signal development caching in a memory device according to examples as disclosed herein.

[0023] Figure 9 A system diagram is shown that supports signal development caching in a memory device according to examples as disclosed herein.

[0024] Figure 10 A block diagram of a memory device is shown that supports signal development caching in the memory device according to examples as disclosed herein.

[0025] Figure 11 and 12 A flow chart is shown illustrating a method of developing cache storage according to signals in a supporting memory device as examples disclosed herein. DETAILED DESCRIPTION

[0026] Different latencies associated with different components used in a memory access operation, or otherwise associated with portions of a memory access operation, can result in delays when performing the memory access operation. For example, when the duration of the latency associated with developing a signal based on accessing a memory cell (e.g., an operation including coupling the memory cell with a signal development component) is longer than the latency associated with generating an output signal at a sense amplifier (e.g., a sensing or latching operation at the sense amplifier), the memory device may be able to generate the output signal more quickly than if the memory device could perform the underlying signal development operation, the output signal being based on the underlying signal development operation. For a memory device having a single signal development component for each sense amplifier (e.g., a 1:1 mapping of the signal development component to the sense amplifier), the throughput of the memory device may therefore be limited by the latency or cycle duration associated with the signal development component or signal development operation, which may affect latency-sensitive applications.

[0027] According to examples disclosed herein, a memory device may include a signal development cache having a set of cache elements (e.g., signal storage elements) that can be selectively coupled and decoupled from sense amplifiers of the memory device. For example, the sense amplifier array may be coupled to a selection component (e.g., a multiplexer (MUX), a transistor network, a transistor array, a switch network, a switch array), and the selection component may be coupled to a set of signal development cache elements that can each be associated with one or more memory cells of the memory device. In some examples, a cell access signal (e.g., a cell read signal, a cell write signal) may be developed at each of the signal development cache elements independently of the other signal development cache elements (e.g., based at least in part on coupling to or other access to the corresponding memory cell). As used herein, a "set" may include one or more elements (e.g., one element, two elements, three elements, etc.).

[0028] In some examples (e.g., during a read operation), the signal development cache elements may each be coupled to a respective memory cell or access line during overlapping time intervals, such that multiple cell access signals (e.g., multiple cell read signals associated with the respective memory cell or access line of each of the respective signal development components) may be generated during the overlapping time intervals. The signal development cache elements may then be coupled to a sense amplifier via a selection component to generate a sense or latch signal (e.g., an output signal of the sense amplifier based on the respective cell access signal), the sense or latch signal being associated with a particular logic state stored by the respective memory cell (e.g., associated with the respective cell access signal). In examples where the cell access signal has been developed at multiple signal development cache elements, the multiple signal development cache elements may be coupled to the sense amplifier in a sequential manner to generate the sense or latch signal in a sequential manner.

[0029] According to examples disclosed herein, a signal exploitation cache can utilize storage elements (e.g., cache elements) that are different from the storage elements (e.g., memory elements) of a memory array to support various pipelining of information, including pipelining associated with read operations, write operations, transfer operations, and others. In some examples, the storage elements in a signal exploitation cache can utilize a different storage technology than the memory cells of the memory array or can store signal states (e.g., cache states) in a manner that is different from how the associated memory array stores logical states.

[0030] refer to Figures 1 to 3 Features of the disclosure introduced above are further described in the context of memory arrays and memory circuits that support signal development caching in memory devices. Figures 4A to 5B Describe a specific instance, Figures 4A to 5B The diagram illustrates specific read and write operations that support signal development cache storage in a memory device. Figures 6 to 9 Other examples of circuits, components, and arrangements that can support the described operations are described. Figures 10 to 12 Describing these and other features of the present disclosure, Figures 10 to 12 Illustrated are a block diagram and flow chart supporting signal development caching in a memory device.

[0031] Figure 1An example memory device 100 is illustrated that develops cache storage based on support signals as described herein. Memory device 100 may also be referred to as an electronic memory device. Memory device 100 may include a memory cell 105 that is programmable to store different states (e.g., memory states, which may be referred to herein as logical states). In some cases, memory cell 105 may be programmable to store two logical states, represented as logic 0 and logic 1. In some cases, memory cell 105 may be programmable to store more than two logical states. Additionally or alternatively, memory cell 105 may be programmable to store memory states based on analog or random operations (e.g., associated with neural networks), where the memory states correspond to information other than logic 0 or logic 1. In some examples, memory cell 105 may include a capacitive memory element, a ferroelectric memory element, a material memory element, a resistive element, a self-selected memory element, a thresholded memory element, or any combination thereof.

[0032] The group of memory cells 105 may be part of a memory segment 110 (e.g., including an array of memory cells 105) of the memory device 100, where, in some examples, a memory segment 110 may refer to a contiguous brick of memory cells 105 (e.g., a group of contiguous elements of a semiconductor chip). In some examples, a memory segment 110 may refer to the smallest group of memory cells 105 that can be biased during an access operation, or the smallest group of memory cells 105 that share a common node (e.g., a common plate line, a group of plate lines biased to a common voltage). Although a single memory segment 110 of the memory device 100 is shown, various examples of memory devices according to examples as disclosed herein may have a group of memory segments 110. In one illustrative example, the memory device 100 or a sub-segment thereof (e.g., a core of a multi-core memory device 100, a chip of a multi-chip memory device) may include 32 "banks," and each bank may include 32 segments. Thus, according to an illustrative example, memory device 100 , or a subsection thereof, may include 1,024 memory segments 110 .

[0033] In some examples, the memory cell 105 can store charge representing a programmable logic state (e.g., by storing charge in a capacitor, a capacitive memory element, or a capacitive storage element). In one example, a charged and an uncharged capacitor can each represent two logic states. In another example, a positively charged and a negatively charged capacitor can each represent two logic states. DRAM or FeRAM architectures can use such designs, and the capacitors employed can include a dielectric material with linear or parasitic polarization properties as an insulator. In some examples, such as FeRAM architectures, the memory cell 105 can include a ferroelectric capacitor having a ferroelectric material as an insulating (e.g., non-conductive) layer between the terminals of the capacitor. Different polarization levels of the ferroelectric capacitor can represent different logic states (e.g., supporting two or more logic states in the corresponding memory cell 105). In some examples, the ferroelectric material has nonlinear polarization properties.

[0034] In some examples, memory cell 105 may include a material portion, which may be referred to as a memory element, a memory storage element, a memory element of your choice, or a memory storage element of your choice. The material portion may have a variable and configurable resistance or other property representing different logical states. For example, a material that may take the form of a crystalline atomic configuration or an amorphous atomic configuration (e.g., capable of maintaining a crystalline state or an amorphous state within the ambient operating temperature range of memory device 100) may have different resistances depending on the atomic configuration. A more crystalline state of the material (e.g., a single crystal, a collection of relatively large grains that may be substantially crystalline) may have a relatively low resistance and may alternatively be referred to as a "set" logical state. A more amorphous state of the material (e.g., a completely amorphous state, a distribution of relatively small grains that may be substantially amorphous) may have a relatively high resistance and may alternatively be referred to as a "reset" logical state. Thus, a voltage applied to a memory cell 105 may induce different currents depending on whether the material portion of the memory cell 105 is in a more crystalline state or a more amorphous state. Thus, the magnitude of the current resulting from application of the read voltage to the memory cell 105 can be used to determine the logic state stored by the memory cell 105 .

[0035] In some examples, a memory element can be configured with various ratios of crystalline and amorphous regions (e.g., varying degrees of atomic order and disorder) that can result in an intermediate resistance that can represent different logical states (e.g., supporting two or more logical states in the corresponding memory cell 105). Furthermore, in some examples, a material or memory element can have more than two atomic configurations, such as an amorphous configuration and two different crystalline configurations. Although described herein with reference to the resistance of different atomic configurations, a memory device can use some other characteristic of the memory element to determine the stored logical state corresponding to an atomic configuration or combination of atomic configurations.

[0036] In some cases, a memory element in a more amorphous state may be associated with a threshold voltage. In some instances, when a voltage greater than the threshold voltage is applied across the memory element in the more amorphous state, current may flow through the memory element. In some instances, when a voltage less than the threshold voltage is applied across the memory element in the more amorphous state, current may not flow through the memory element. In some instances, a memory element in a more crystalline state may not be associated with a threshold voltage (e.g., may be associated with a zero threshold voltage). In some instances, current may flow through the memory element in response to a non-zero voltage across the memory element in the more crystalline state.

[0037] In some cases, the material in both the more amorphous state and the more crystalline state can be associated with a threshold voltage. For example, self-selected or thresholded memory can be based on the difference in the threshold voltage of the memory cell between different programmed states (e.g., through different composition distributions). The logic state of a memory cell 105 having such a memory element can be set by biasing or heating the memory element over time to a temperature profile that supports the formation of a specific atomic configuration or combination of atomic configurations.

[0038] The memory device 100 may include a three-dimensional (3D) memory array in which multiple two-dimensional (2D) memory arrays (e.g., layers, tiers) are formed one above the other. In various examples, such an array may be divided into a set of memory segments 110, where each memory segment 110 may be arranged within a layer or tier, distributed across multiple layers or tiers, or any combination thereof. Compared to a 2D array, such an arrangement may increase the number of memory cells 105 that can be placed or formed on a single die or substrate, which in turn may reduce the production cost of the memory device 100 or improve the performance of the memory device 100, or both. The layers or tiers may be separated by electrically insulating material. Each layer or tier may be aligned or positioned so that the memory cells 105 are substantially aligned with each other across each layer, thereby forming a stack of memory cells 105.

[0039] In the example of memory device 100, each row of memory cells 105 of memory segment 110 may be associated with one of a set of first access lines 120 (eg, word lines (WL), such as WL1 through WL2). M ), and each column of memory cells 105 may be coupled to one of a set of second access lines 130 (eg, digit lines (DL), such as DL1 to DL N In some examples, rows of memory cells 105 of different memory segments 110 (not shown) may be coupled to one of different pluralities of first access lines 120 (e.g., different from WL1 to WL2). M 1 to DL1, and the columns of memory cells 105 of different memory segments 110 may be coupled to one of different pluralities of second access lines 130 (eg, different from DL1 to DL N In some cases, the first access line 120 and the second access line 130 may be substantially perpendicular to each other in the memory device 100 (eg, when viewing the plane of the layer of the memory device 100, such as Figure 1 ). References to word lines and bit lines or the like are interchangeable without detracting from understanding or operation.

[0040] In general, one memory cell 105 may be located at (e.g., coupled to, coupled between, or in a manner similar to) the intersection of a first access line 120 and a second access line 130. This intersection, or an indication of this intersection, may be referred to as the address of the memory cell 105. A target or selected memory cell 105 may be the memory cell 105 located at the intersection of a powered or otherwise selected first access line 120 and a powered or otherwise selected second access line 130. In other words, the first access line 120 and the second access line 130 may be powered or otherwise selected to access (e.g., read, write, rewrite, refresh) the memory cell 105 at their intersection. Other memory cells 105 that are in electronic communication with (eg, connected to) the same first access line 120 or second access line 130 may be referred to as non-target or non-selected memory cells 105 .

[0041] In some architectures, the logical storage components of memory cell 105 (e.g., capacitive memory elements, ferroelectric memory elements, resistive memory elements, or other memory elements) can be electrically isolated from second access line 130 by a cell select component (which, in some instances, can be referred to as a switch component or selector device). First access line 120 can be coupled to the cell select component (e.g., via a control node or terminal of the cell select component) and can control the cell select component of or associated with memory cell 105. For example, the cell select component can be a transistor and first access line 120 can be coupled to the gate of the transistor (e.g., where the gate node of the transistor can be the control node of the transistor). Activating first access line 120 of memory cell 105 can result in an electrical connection or closed circuit between the logical storage components of memory cell 105 and its corresponding second access line 130. Second access line 130 can then be accessed to read from or write to memory cell 105.

[0042] In some examples, the memory cells 105 of the memory segment 110 may also be connected to one of a plurality of third access lines 140 (eg, plate lines (PL), such as PL1 to PL2). N 1 ). Although illustrated as separate lines, in some examples, the plurality of third access lines 140 may represent or be otherwise functionally equivalent to a common plate line, a common plate, or other common node of the memory segment 110 (e.g., a node common to each of the memory cells 105 in the memory segment 110), or other common node of the memory device 100. In some examples, the plurality of third access lines 140 may couple the memory cells 105 to one or more voltage sources for various sensing and / or writing operations, including those described herein. For example, when the memory cell 105 employs a capacitor to store a logic state, the second access line 130 may provide access to a first terminal or plate of the capacitor, and the third access line 140 may provide access to a second terminal or plate of the capacitor (e.g., a terminal associated with an opposite plate of the capacitor opposite the first terminal of the capacitor, or a terminal otherwise located on a side of the capacitor opposite the first terminal of the capacitor). In some examples, memory cells 105 of different memory segments 110 (not shown) may be associated with one of a different plurality of third access lines 140 (eg, different from PL1 through PL2). N A set of plate lines, different common plate lines, different common plates, different common nodes) are coupled, different pluralities of third access lines 140 may be coupled to the illustrated third access lines 140 (eg, plate lines PL1 to PL N ) electrical isolation.

[0043] The plurality of third access lines 140 can be coupled to a plate assembly 145, which can control various operations, such as activating one or more of the plurality of third access lines 140 or selectively coupling one or more of the plurality of third access lines 140 to a voltage source or other circuit element. Although the plurality of third access lines 140 of the memory device 100 are shown as being substantially parallel to the plurality of second access lines 130, in other examples, the plurality of third access lines 140 can be substantially parallel to the plurality of first access lines 120, or in any other configuration.

[0044] Although the reference Figure 1 The access lines described are shown as straight lines between the memory cell 105 and the coupled components, but the access lines may be associated with other circuit elements, such as capacitors, resistors, transistors, amplifiers, voltage sources, switching elements, selection elements, and other elements, which may be used to support access operations, including those described herein. In some examples, an electrode may be coupled to the memory cell 105 and the first access line 120 (e.g., coupled between the memory cell 105 and the first access line 120), or to the memory cell 105 and the second access line 130 (e.g., coupled between the memory cell 105 and the second access line 130). The term electrode may refer to an electrical conductor or other electrical interface between components, and in some cases, may be employed as an electrical contact to the memory cell 105. An electrode may include a trace, a wire, a conductive line, a conductive layer, a conductive pad, and the like, that provides a conductive path between elements or components of the memory device 100.

[0045] Access operations such as reading, writing, rewriting, and refreshing can be performed on memory cell 105 by activating or selecting first access line 120, second access line 130, and / or third access line 140 coupled to memory cell 105 (which may include applying a voltage, charge, or current to the respective access lines). First access line 120, second access line 130, and third access line 140 can be made of a conductive material such as a metal (e.g., copper (Cu), silver (Ag), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), a metal alloy, carbon, or other conductive or semiconductive materials, alloys, or compounds. Upon selecting memory cell 105, the generated signal (e.g., a cell access signal, a cell read signal) can be used to determine the logic state stored by memory cell 105. For example, a memory cell 105 having a capacitive memory element storing a logic state may be selected, and the resulting charge flow through an access line and / or the resulting voltage of the access line may be detected, converted, or amplified to determine the programmed logic state stored by the memory cell 105 .

[0046] Access to memory cells 105 may be controlled by row component 125 (e.g., a row decoder), column component 135 (e.g., a column decoder), or plane component 145 (e.g., a plane driver), or a combination thereof. For example, row component 125 may receive a row address from memory controller 170 and, based on the received row address, select or activate the appropriate first access line 120. Similarly, column component 135 may receive a column address from memory controller 170 and select or activate the appropriate second access line 130. Thus, in some examples, memory cells 105 may be accessed by selecting or activating first access line 120 and second access line 130. In some examples, such access operations may be accompanied by the plate component 145 biasing one or more of the third access lines 140 (e.g., biasing one of the third access lines 140 of a memory segment 110, biasing all of the third access lines 140 of a memory segment, biasing a common plate line of a memory segment 110 or memory device 100, biasing a common node of a memory segment 110 or memory device 100), which may be referred to as “moving the plate” of the memory cell 105, memory segment 110, or memory device 100. In various examples, any one or more of the row component 125, column component 135, or plate component 145 may be referred to as or otherwise include an access line driver or access line decoder.

[0047] In some examples, memory controller 170 can control operations (e.g., read operations, write operations, rewrite operations, refresh operations, discharge operations, dissipation operations, and equalization operations) of memory cell 105 through various components (e.g., row components 125, column components 135, plate components 145, and sense components 150). In some cases, one or more of row components 125, column components 135, plate components 145, and sense components 150 can be co-located with memory controller 170 or otherwise included together. In some examples, any one or more of row components 125, column components 135, or plate components 145 can also be referred to as a memory controller or circuitry for performing access operations of memory device 100. In some examples, any one or more of row components 125, column components 135, or plate components 145 can be described as controlling or performing operations for accessing memory device 100, or controlling or performing operations for accessing memory segments 110 of memory device 100.

[0048] The memory controller 170 may generate row and column address signals to activate the desired first access line 120 and second access line 130. The memory controller 170 may also generate or control various voltages or currents used during operation of the memory device 100. Although a single memory controller 170 is shown, the memory device 100 may have more than one memory controller 170 (e.g., a memory controller 170 for each of a set of memory banks 110 of the memory device 100, a memory controller 170 for each of a number of subsets of memory banks 110 of the memory device 100, a memory controller 170 for each of a set of chips of a multi-chip memory device 100, a memory controller 170 for each of a set of banks of a multi-bank memory device 100, a memory controller 170 for each core of a multi-core memory device 100, or any combination thereof), where the different memory controllers 170 may perform the same functions and / or different functions.

[0049] Although the memory device 100 is illustrated as including a single row component 125, a single column component 135, and a single board component 145, other examples of the memory device 100 may include different configurations to accommodate a memory bank 110 or a group of memory banks 110. For example, in various memory devices 100, a row component 125 may be shared among a group of memory banks 110 (e.g., having subcomponents common to all memory banks in the group of memory banks 110, having subcomponents dedicated to respective memory banks in the group of memory banks 110), or a row component 125 may be dedicated to one memory bank 110 in a group of memory banks 110. Likewise, in various memory devices 100, a rank component 135 may be shared among a group of memory banks 110 (e.g., having subcomponents common to all memory banks in the group of memory banks 110, having subcomponents specific to respective memory banks in the group of memory banks 110), or a rank component 135 may be specific to one memory bank 110 in a group of memory banks 110. Additionally, in various memory devices 100, a plane component 145 may be shared among a group of memory banks 110 (e.g., having subcomponents common to all memory banks in the group of memory banks 110, having subcomponents specific to respective memory banks in the group of memory banks 110), or a plane component 145 may be specific to one memory bank 110 in a group of memory banks 110.

[0050] In general, the amplitude, shape, or duration of the applied voltage, current, or charge may be adjusted or varied and may be different for the various operations discussed in operating the memory device 100. Furthermore, one, multiple, or all memory cells 105 within the memory device 100 may be accessed simultaneously. For example, during a reset operation in which all memory cells 105 or a group of memory cells 105 (e.g., the memory cells 105 of a memory segment 110) are set to a single logic state, multiple or all memory cells 105 of the memory device 100 may be accessed simultaneously.

[0051] Sense component 150, when accessing (e.g., in cooperation with memory controller 170) memory cell 105, can read (e.g., sense) memory cell 105 to determine the logic state stored by memory cell 105. For example, sense component 150 can be configured to sense, in response to a read operation, a current or charge passing through memory cell 105, or a voltage resulting from coupling memory cell 105 with sense component 150 or other intervening components (e.g., a signal development component between memory cell 105 and sense component 150). Sense component 150 can provide an output signal indicative of (e.g., based at least in part on) the logic state stored by memory cell 105 to one or more components (e.g., column component 135, input / output component 160, memory controller 170). In various memory devices 100, the sensing component 150 may be shared among a group or bank of memory segments 110 (e.g., having subcomponents common to all memory segments in a group or bank of memory segments 110, having subcomponents dedicated to corresponding memory segments in a group or bank of memory segments 110), or the sensing component 150 may be dedicated to one memory segment 110 in a group or bank of memory segments 110.

[0052] In some examples, during or after accessing memory cell 105, the logical storage portion of memory cell 105 can discharge or otherwise permit charge or current to flow through its corresponding first access line 120, second access line 130, or third access line 140. This charge or current can result from biasing memory cell 105 or applying a voltage to memory cell 105 from one or more voltage sources or supplies (not shown) of memory device 100, where such voltage sources or supplies can be part of row component 125, column component 135, plate component 145, sensing component 150, memory controller 170, or some other component (e.g., a biasing component). In some examples, the discharge of memory cell 105 can result in a change in the voltage of second access line 130, which sensing component 150 can compare to a reference voltage to determine the stored state of memory cell 105. In some examples, a voltage may be applied to memory cell 105 (e.g., using corresponding first access line 120 and second access line 130) and the presence or magnitude of the resulting current may depend on the applied voltage and the resistance state of the memory element of memory cell 105, which sensing component 150 may use to determine the stored state of memory cell 105.

[0053] In some examples, when a read signal (e.g., a read pulse, a read current, a read voltage) is applied across a memory cell 105 having a material memory element storing a first logic state (e.g., a set state associated with a more crystalline atomic configuration), the memory cell 105 conducts current due to the read pulse exceeding the threshold voltage of the memory cell 105. In response to, or at least partially based on, this, the sensing component 150 may detect the current through the memory cell 105 as part of determining the logic state stored by the memory cell 105. When a read pulse is applied to a memory cell 105 having a memory element storing a second logic state (e.g., a reset state associated with a more amorphous atomic configuration) (this may occur before or after the read pulse is applied across the memory cell 105 having the memory element storing the first logic state), the memory cell 105 may not conduct current due to the read pulse not exceeding the threshold voltage of the memory cell 105. As part of determining the stored logic state, the sensing component 150 may detect little or no current through the memory cell 105.

[0054] In some examples, a threshold current can be defined for sensing the logic state stored by memory cell 105. The threshold current can be set to be higher than the current that can pass through memory cell 105 when memory cell 105 does not reach the threshold in response to a read pulse, but equal to or lower than the expected current through memory cell 105 when memory cell 105 reaches the threshold in response to a read pulse. For example, the threshold current can be higher than the leakage current of the associated first access line 120, second access line 130, or third access line 140. In some examples, the logic state stored by memory cell 105 can be determined at least in part based on a voltage generated (e.g., across a shunt resistor) due to the current driven by the read pulse. For example, the generated voltage can be compared relative to a reference voltage, where a generated voltage less than the reference voltage corresponds to a first logic state and a generated voltage greater than the reference voltage corresponds to a second logic state.

[0055] In some examples, more than one voltage may be applied when reading memory cell 105 (e.g., multiple voltages may be applied during part of a read operation). For example, if the applied read voltage does not induce current flow, one or more other read voltages may be applied (e.g., until current flow is detected by sensing component 150). Based at least in part on the read voltage that induces current flow, the stored logic state of memory cell 105 may be determined. In some cases, the read voltage may be ramped (e.g., smoothly increased to a higher magnitude) until current flow or other conditions are detected by sensing component 150. In other cases, predetermined read voltages (e.g., a predetermined sequence of read voltages that increase in steps to higher magnitudes) may be applied until current flow is detected. Similarly, a read current may be applied to memory cell 105, and the magnitude of the voltage used to form the read current may depend on the resistance or overall threshold voltage of memory cell 105.

[0056] The sensing component 150 may include various switching components, selection components, multiplexers, transistors, amplifiers, capacitors, resistors, voltage sources, or other components to detect, convert, or amplify a difference in a sense signal (e.g., a difference between a read voltage and a reference voltage, a difference between a read current and a reference current, a difference between a read charge and a reference charge) (in some examples, this may be referred to as sensing or latching, or generating a sense or latch signal). In some examples, the sensing component 150 may include a set of components (e.g., circuit elements, circuitry) that is repeated for each of a set of second access lines 130 connected to the sensing component 150. For example, the sensing component 150 may include a separate sensing circuit or circuitry (e.g., a separate sense amplifier, a separate signal development component) for each of a set of second access lines 130 coupled to the sensing component 150, so that the logic state can be separately detected for a respective memory cell 105 coupled to a respective access line in the set of second access lines 130. In some examples, a reference signal source (e.g., a reference component) or a generated reference signal may be shared among components of the memory device 100 (e.g., shared among one or more sensing components 150, shared among separate sensing circuits of a sensing component 150, shared among the first access line 120, the second access line 130, or the third access line 140 of the memory segment 110).

[0057] Sense component 150 may be included in a device that includes memory device 100. For example, sense component 150 may be included with other read and write circuitry, decode circuitry, or register circuitry of a memory (which may be coupled with or to memory device 100). In some examples, the detected logic state of memory cell 105 may be output as an output via column component 135 or input / output component 160. In some examples, sense component 150 may be part of column component 135, row component 125, or memory controller 170. In some examples, sense component 150 may be connected to or otherwise be in electronic communication with column component 135, row component 125, or memory controller 170.

[0058] Although a single sensing component 150 is shown, the memory device 100 (e.g., the memory segment 110 of the memory device 100) may include more than one sensing component 150. For example, a first sensing component 150 may be coupled to a first subset of the second access lines 130 and a second sensing component 150 may be coupled to a second subset of the second access lines 130 (e.g., different from the first subset of the second access lines 130). In some examples, this partitioning of the sensing components 150 may support parallel (e.g., simultaneous) operation of the multiple sensing components 150. In some examples, this partitioning of the sensing components 150 may support matching sensing components 150 having different configurations or characteristics to specific subsets of the memory cells 105 of the memory device (e.g., to support different types of memory cells 105, to support different characteristics of a subset of the memory cells 105, to support different characteristics of a subset of the second access lines 130).

[0059] Additionally or alternatively, two or more sensing components 150 may be coupled (e.g., selectively coupled) to the same set of second access lines 130 (e.g., to achieve component redundancy). In some examples, this configuration may support maintaining functionality that overcomes a failure or otherwise poor or degraded operation of one of the redundant sensing components 150. In some examples, this configuration may support the ability to select one of the redundant sensing components 150 for a particular operating characteristic (e.g., related to power consumption characteristics, related to access speed characteristics of a particular sensing operation, related to operating the memory cell 105 in a volatile mode or a non-volatile mode).

[0060] In some memory architectures, accessing a memory cell 105 can degrade or destroy the logic state stored by one or more memory cells 105 in a memory segment 110, and a rewrite or refresh operation can be performed to return the original logic state to the memory cell 105. In DRAM or FeRAM, for example, the capacitor of a memory cell 105 can be partially or completely discharged or depolarized during a sensing operation, thereby destroying the logic state stored in the memory cell 105. In PCM, for example, a sensing operation can result in a change in the atomic configuration of the memory cell 105, thereby changing the resistance state of the memory cell 105. Thus, in some examples, the logic state stored in the memory cell 105 can be rewritten after an access operation. Furthermore, activating a single first access line 120, second access line 130, or third access line 140 can cause all memory cells 105 coupled to the activated first access line 120, second access line 130, or third access line 140 to discharge. Thus, several or all memory cells 105 coupled to first access line 120, second access line 130, or third access line 140 associated with the access operation (e.g., all cells of an accessed row, all cells of an accessed column) may be rewritten after an access operation.

[0061] In some examples, reading memory cell 105 may be non-destructive. That is, the logic state of memory cell 105 may not need to be rewritten after reading memory cell 105. For example, in a non-volatile memory such as PCM, accessing memory cell 105 may not destroy the logic state, and therefore, memory cell 105 may not need to be rewritten after access. However, in some examples, refreshing the logic state of memory cell 105 may or may not be necessary in the absence or presence of other access operations. For example, the logic state stored by memory cell 105 may be refreshed at periodic intervals by applying appropriate write, refresh, or equalization pulses or biases to maintain the stored logic state. Refreshing memory cell 105 can reduce or eliminate read disturb errors or logic state corruption (due to charge leakage or changes in the atomic configuration of the memory element over time).

[0062] Memory cell 105 can be set, written, or refreshed by activating associated first access line 120, second access line 130, and / or third access line 140 (e.g., via memory controller 170). In other words, a logic state can be stored in memory cell 105 (e.g., via a cell access signal, via a cell write signal). Row component 125, column component 135, or plate component 145 can receive data to be written to memory cell 105, for example, via input / output component 160. In some examples, a write operation can be performed at least in part by sense component 150, or the write operation can be configured to bypass sense component 150.

[0063] In the case of a capacitive memory element, memory cell 105 can be written to by applying a voltage to the capacitor and then isolating the capacitor (e.g., isolating the capacitor from the voltage source used to write to memory cell 105, thereby floating the capacitor) to store a charge associated with the desired logical state in the capacitor. In the case of ferroelectric memory, the ferroelectric memory element (e.g., a ferroelectric capacitor) of memory cell 105 can be written to by applying a voltage of sufficiently high magnitude to polarize the ferroelectric memory element (e.g., a ferroelectric capacitor) with the polarization associated with the desired logical state (e.g., applying a saturation voltage). The ferroelectric memory element can be isolated (e.g., floating), or a zero net voltage or bias can be applied across the ferroelectric memory element (e.g., ground, virtual ground, or equalizing the voltage across the ferroelectric memory element). In the case of PCM, the memory element can be written to by applying a current having a profile that causes the memory element to form an atomic configuration associated with the desired logical state (e.g., by heating and cooling).

[0064] The sensing component 150 may include a plurality of signal development components that can be selectively coupled and decoupled with respective ones of a set of sense amplifiers. For example, the sense amplifiers of the sensing component 150 may be coupled to a selection component of the sensing component 150, and the selection component may be coupled to a set of signal development components of the sensing component 150 (which may be associated with one or more memory cells 105 or one or more access lines (e.g., one or more second access lines 130) of the memory device 100). In some examples, a cell access signal may be developed at each of the signal development components independently of the other signal development components.

[0065] In some examples, the signal development components of the sensing component 150 can each be coupled to a respective memory cell during overlapping time intervals, such that multiple cell access signals (e.g., a cell read signal, a cell write signal, each associated with a respective memory cell of each of the respective signal development components) can be generated during the overlapping time intervals. In examples where the cell access signals are developed at multiple signal development components (e.g., in a read operation of multiple memory cells 105, in a multi-cell read operation), the multiple signal development components can be coupled to a sense amplifier (e.g., in a sequential manner, in a step-by-step manner) to generate a sense or latch signal for the sense amplifier (e.g., in a sequential manner, in a step-by-step manner) based at least in part on the cell access signals. In instances where a sense or latch signal sequence is associated with writing or rewriting a group of memory cells 105 (e.g., in a write or refresh operation of multiple memory cells 105, in a multi-cell write or refresh operation), multiple signal development components can be coupled to the sense amplifiers (e.g., sequentially, in a step-by-step manner) to generate multiple cell access signals (e.g., sequentially, in a step-by-step manner) based at least in part on the sense or latch signals of the sense amplifiers. In some instances, multiplexing the signal development components of the sense component 150 can compensate for portions of the signal development components or portions of the access operation associated with different latencies, which can reduce the effects of access serialization.

[0066] Figure 2 An example circuit 200 is illustrated that supports signal development caching in a memory device according to examples as disclosed herein. The circuit 200 may include a memory cell 105-a and a sensing element 150-a, which may be a reference Figure 1 1 and 2. The circuit 200 may also include a word line 205, a digit line 210, and a plate line 215, which may correspond to reference lines 105, 106, and 107, respectively, in some examples. Figure 1 1. First access line 120, second access line 130, and third access line 140 are depicted (e.g., of memory segment 110). In some examples, plate line 215 may illustrate a common plate line, common plate, or another common node for memory cell 105-a and another memory cell 105 (not shown) of the same memory segment 110. Circuit 200 illustrates circuitry that can support the described techniques for signal development caching in a memory device.

[0067] The sensing component 150-a may include a sense amplifier 290 (e.g., an amplifier component, an input / output amplifier, a "latch") that may include a first node 291 and a second node 292. In various examples, the first node 291 and the second node 292 may be coupled to different access lines of a circuit (e.g., the signal line 285 and the reference line 275 of the circuit 200, respectively), or may be coupled to a common access line of a different circuit (not shown). In some examples, the first node 291 may be referred to as a signal node, and the second node 292 may be referred to as a reference node. The sense amplifier 290 may be associated with (e.g., coupled with, coupled to) one or more input / output (I / O) lines (e.g., I / O line 295), which may include a first node 291 and a second node 292 connected to a reference line. Figure 1 The depicted input / output component 160 is coupled to access lines of the column component 135. Although the sense amplifier 290 is illustrated as having a single I / O line 295, a sense amplifier according to examples as disclosed herein may have more than one I / O line 295 (e.g., two I / O lines 295). In various examples, other configurations and nomenclature for access lines and / or reference lines are possible according to examples as disclosed herein.

[0068] The memory cell 105-a may include a logical storage component (e.g., a memory element, a storage element, a memory storage element), such as a capacitor 220 having a first plate (cell plate) 221 and a second plate (cell bottom) 222. The cell plate 221 and the cell bottom 222 may be capacitively coupled via a dielectric material positioned therebetween (e.g., in DRAM applications), or capacitively coupled via a ferroelectric material positioned therebetween (e.g., in FeRAM applications). The cell plate 221 may be coupled to a voltage V plate is associated with the voltage V bottom 2. As described herein, various logic states can be stored by charging, discharging, or polarizing capacitor 220.

[0069] Capacitor 220 may be in electronic communication with digit line 210, and the stored logic state of capacitor 220 may be read or sensed by operating the various elements represented in circuit 200. For example, memory cell 105-a may also include a cell select component 225, which in some examples may be referred to as a switch component or selector device that couples with or between an access line (e.g., digit line 210) and capacitor 220. In some examples, cell select component 225 may be considered outside the illustrative boundaries of memory cell 105-a, and cell select component 225 may be referred to as a switch component or selector device that couples with or between an access line (e.g., digit line 210) and memory cell 105-a.

[0070] When the cell select component 225 is activated (e.g., by activating a logic signal or voltage), the capacitor 220 can be selectively coupled to the digit line 210, and when the cell select component 225 is deactivated (e.g., by deactivating a logic signal or voltage), the capacitor 220 can be selectively isolated or decoupled from the digit line 210. A logic signal or other selection signal or voltage can be applied to a control node 226 (e.g., a control node, a control terminal, a select node, a select terminal) of the cell select component 225 (e.g., via the word line 205). In other words, the cell select component 225 can be configured to selectively couple or decouple the capacitor 220 (e.g., a logic storage component) from the digit line 210 based on the logic signal or voltage applied to the control node 226 via the word line 205.

[0071] Activating cell select component 225 may be referred to as selecting memory cell 105-a in some examples, and deactivating cell select component 225 may be referred to as deselecting memory cell 105-a in some examples. In some examples, cell select component 225 is a transistor (e.g., an n-type transistor) and its operation can be controlled by applying an activation or selection voltage to the transistor gate (e.g., a control or select node or terminal). The voltage used to activate the transistor (e.g., the voltage between the transistor gate terminal and the transistor source terminal) may be a voltage greater than the threshold voltage of the transistor (e.g., a positive activation or selection voltage). The voltage used to deactivate the transistor may be a voltage less than the threshold voltage of the transistor (e.g., ground or a negative deactivation or deselection voltage).

[0072] 210 ). A cell select component 225 may be activated or deactivated using word line 205 (e.g., by row component 125). For example, a select voltage (e.g., a word line logic signal or a word line voltage) applied to word line 205 may be applied to the gate of a transistor of cell select component 225, which may selectively connect or couple capacitor 220 to digit line 210 (e.g., provide a conductive path between capacitor 220 and digit line 210). A deselect or deactivation voltage applied to word line 205 may be applied to the gate of a transistor of cell select component 225, which may selectively disconnect, decouple, or isolate capacitor 220 from digit line 210. In some examples, activating cell select component 225 may be referred to as selectively coupling memory cell 105-a to digit line 210, and deactivating cell select component 225 may be referred to as selectively decoupling or isolating memory cell 105-a from digit line 210.

[0073] In other examples, the positions of cell select component 225 and capacitor 220 in memory cell 105-a may be swapped such that cell select component 225 may be coupled to or between plate line 215 and cell plate 221, and capacitor 220 may be coupled to or between digit line 210 and the other terminal of cell select component 225. In this example, cell select component 225 may remain connected (e.g., in electronic communication) with digit line 210 through capacitor 220. This configuration may be associated with alternative timing and biasing for access operations.

[0074] In examples employing ferroelectric capacitors, capacitor 220 may or may not be fully discharged immediately after being connected to or coupled with digit line 210. In various schemes, to sense the logic state stored by the ferroelectric capacitor, a voltage may be applied to plate line 215 and / or digit line 210, and word line 205 may be biased (e.g., by activating word line 205) to select memory cell 105-a. In some cases, plate line 215 and / or digit line 210 may be brought to virtual ground and then isolated from virtual ground before activating word line 205, which may be referred to as a floating condition, an idle condition, or a standby condition.

[0075] Operating the memory cell 105-a by varying the voltage of the cell plate 221 (e.g., via the plate line 215) may be referred to as "moving the cell plate." Biasing the plate line 215 and / or the digit line 210 may result in a voltage difference across the capacitor 220 (e.g., the voltage of the digit line 210 minus the voltage of the plate line 215). The voltage difference may be accompanied by a change in the stored charge on the capacitor 220, where the magnitude of the change in the stored charge may depend on the initial state of the capacitor 220 (e.g., whether the initial logic state stores a logic 1 or a logic 0). In some aspects, the change in the stored charge of the capacitor 220, or some portion of this charge, may be used by the sensing component 150-a to determine the logic state stored by the memory cell 105-a (e.g., in a charge transfer sensing scheme). In some aspects, the change in the stored charge of the capacitor 220 may result in a change in the voltage of the digit line 210, which may be used by the sensing component 150-a to determine the logic state stored by the memory cell 105-a. The cell access signal may refer to a signal generated when the memory cell 105-a is selected or activated (e.g., when coupled with a signal development component), and may include a cell read signal in a read operation of the memory cell 105-a, or a cell write signal in a write operation, a rewrite operation, or a refresh operation of the memory cell 105-a. In various examples, the cell access signal may be referred to as a cell coupling signal or a cell charge sharing signal.

[0076] In some examples, the digit line 210 can be coupled to additional memory cells 105 (not shown), each of which can be coupled to a different word line 205 (not shown). In other words, in some examples, a different memory cell 105 coupled to the digit line 210 can be selected or activated based at least in part on a different word line logic signal.

[0077] The digit line 210 may have a property that causes an intrinsic capacitance 230 (e.g., on the order of several pico-farads (pF), which may be non-negligible in some cases) that couples the digit line 210 to a voltage source 240-a having a voltage V0. The voltage source 240-a may represent a common ground or virtual ground voltage, or the voltage of an adjacent access line (not shown) of the circuit 200. Although in Figure 2 2 is illustrated as a separate element, but intrinsic capacitance 230 may be associated with a property distributed throughout digit line 210 or another portion of circuit 200 .

[0078] In some examples, intrinsic capacitance 230 may depend on the physical characteristics of digit line 210, including the conductor dimensions (e.g., length, width, thickness) of digit line 210. Intrinsic capacitance 230 may also depend on the characteristics of adjacent access lines or circuit components, the proximity to such adjacent access lines or circuit components, or the insulation characteristics between digit line 210 and such access lines or circuit components. Thus, the change in voltage of digit line 210 after selecting or activating memory cell 105-a may depend on the net capacitance of digit line 210 (e.g., the net capacitance associated with digit line 210). In other words, when charge flows along digit line 210 (e.g., to or from digit line 210), a finite amount of charge may be stored along digit line 210 (e.g., in intrinsic capacitance 230, in another capacitance coupled to digit line 210), and the resulting voltage of digit line 210 may depend on the net capacitance of digit line 210.

[0079] Circuit 200 (e.g., sensing component 150-a) can include a signal development component 250, which can be an example of a signal development component or signal development circuit coupled to or between memory cell 105-a and sense amplifier 290. In some examples, access lines associated with signal development component 250 (e.g., access lines coupled to inputs / outputs of signal development component 250, access lines coupled to or between signal development component 250 and sense amplifier 290) can be referred to as signal development lines (SDLs) (e.g., signal development line 255, "cache line" (CL)). Signal development component 250 can amplify or otherwise convert signals (e.g., cell access signals) on digit line 210 and signal development line 255. For example, for a read operation, the signal development component 250 can generate a cell read signal based at least in part on coupling with the capacitor 220 (e.g., prior to a sensing operation by the sense amplifier 290) or otherwise be associated with generating the cell read signal based at least in part on coupling with the capacitor 220, which can include charge sharing between the signal development component 250 and the capacitor 220. In another example, for a write operation, a rewrite operation, or a refresh operation, the signal development component 250 can generate a cell write signal for the capacitor 220 (e.g., based at least in part on coupling with the sense amplifier 290, in response to a write command, a refresh command, a rewrite command, or a read command) or otherwise be associated with generating the cell write signal for the capacitor 220, which can include charge sharing between the signal development component 250 and the capacitor 220.

[0080] In some examples, signal development component 250 may include a signal storage element, such as a capacitor (e.g., a signal development cache element, an integrating capacitor, an amplifier capacitor (AMPCap), which may in some cases be referred to alternatively as a "flying capacitor"), or another type of charge storage element configured to store a signal or signal state that is different from the logic state stored at memory cell 105 (e.g., different from the logic state stored at memory cell 105-a). Additionally or alternatively, signal development component 250 may include a transistor, an amplifier, a gate-to-cathode amplifier, or any other charge or voltage conversion or amplification component. For example, signal development component 250 may include a charge transfer sense amplifier (CTSA), which in some examples may include a transistor having a gate terminal coupled to a voltage source.

[0081] Although the sensing component 150-a is illustrated as having a single signal development component 250, according to examples disclosed herein, the sensing component 150-a may include one or more additional signal development components 250 (not shown) to form a set of signal development components 250 (e.g., a signal development cache). Each signal development component in the set of signal development components 250 of the sensing component 150-a may be associated with (e.g., configured to selectively couple or decouple from, or to develop cell access signals for) one or more memory cells 105 or one or more digit lines 210, which may or may not include the memory cell 105-a or digit line 210. For example, each signal development component 250 in the set of signal development components 250 can selectively couple or decouple with one or more digit lines 210 of a memory segment 110 of a memory array. In examples where a respective one of the signal development components 250 is coupled with more than one memory cell 105 or more than one digit line 210, any of the memory cells 105 or digit lines 210 can be selectively coupled or decoupled with the respective signal development component 250 by a selection component (e.g., a digit line selection component, a multiplexer, a transistor network, a transistor array, a switch network, a switch array, not shown) between the respective signal development component 250 and the associated memory cell 105 or digit line 210.

[0082] The sensing component 150-a may also include a selection component 280 (e.g., a signal development component selection component, a multiplexer, a transistor network, a transistor array, a switch network, a switch array) coupled to or between a set of signal development components 250 (e.g., a set of signal development lines 255) and a sense amplifier 290. The selection component 280 may be configured to selectively couple or decouple any signal development component or signal development line in the set of signal development components 250 or signal development lines 255 to the sense amplifier 290. The selection component 280 may be associated with an access line (e.g., a signal line 285) for carrying a signal (e.g., a voltage, a charge, a current) between the selection component 280 and the sense amplifier 290. For example, the output of selection component 280 (e.g., in a read operation) can be an output signal (e.g., a signal carried via signal line 285) based at least in part on an input signal (e.g., a signal carried from signal development component 250 selected by selection component 280, a signal carried by signal development line 255 selected by selection component 280). In some examples, the output signal of selection component 280 can be equal to or substantially equal to the input signal of selection component 280 (e.g., where V sig =V SDL Although described in the context of input signals via signal line 255 and output signals via signal line 285, the interpretation of the inputs and outputs may be reversed in certain access operations employing circuit 200 (e.g., in a write operation, a rewrite operation, a refresh operation).

[0083] In a read operation, the voltage of signal line 285 after selecting memory cell 105-a (e.g., a cell read signal after coupling memory cell 105-a or digit line 210 to signal development component 250, after selecting signal development component 250 at selection component 280) can be compared by sense component 150-b to a reference (e.g., the voltage of reference line 275) to determine the logic state stored in memory cell 105-a (e.g., to generate a sense or latch signal). In some examples, the voltage of reference line 275 can be provided by reference component 270. In other examples, reference component 270 can be omitted and the reference voltage can be provided, for example, by accessing memory cell 105-a or digit line 210 to generate the reference voltage (e.g., in a self-referenced access operation). Other operations can be used to support selecting and / or sensing memory cell 105-a.

[0084] In some examples, circuit 200 may include a bypass line 260 that may permit bypassing (e.g., selectively bypassing) of signal development component 250 or some other portion of the circuitry between memory cell 105-a and sense amplifier 290. In some examples, bypass line 260 may be selectively enabled or disabled by switch component 265. In other words, when switch component 265 is activated, digit line 210 may be coupled to signal development line 255 or select component 280 (e.g., coupling memory cell 105-a and select component 280 or some other portion of the circuitry between the memory cell and sense amplifier 290) via bypass line 260.

[0085] In some examples, when switch component 265 is activated, signal development component 250 can be selectively isolated or decoupled from one or both of digit line 210 or signal development line 255 (e.g., by another switch component or a selection component, not shown). When switch component 265 is deactivated, digit line 210 can be selectively coupled to signal development line 255 or selection component 280 via signal development component 250. In other examples, one or more additional selection components (not shown) can be used to selectively couple memory cell 105-a (e.g., digit line 210) to one of signal development component 250 (e.g., via signal development line 255) or bypass line 260.

[0086] Additionally or alternatively, in some examples, a switch or selection component can be used to selectively couple the selection component 280 to one of the signal development component 250 (e.g., via the signal development line 255) or the bypass line 260. In some examples, the selectable bypass line 260 can support generating a cell access signal (e.g., a cell read signal) for detecting a logic state of the memory cell 105-a using the signal development component 250, and generating a cell access signal (e.g., a cell write signal) to write a logic state to the memory cell 105-a by bypassing the signal development component 250.

[0087] Some examples of memory devices that support multiplexed signal development may share a common access line (not shown) between the memory cell 105 and the sense amplifier 290 to support generation of a sense signal and a reference signal from the same memory cell 105. In one example, the common access line between the signal development component 250 and the sense amplifier 290 may be referred to as a “common line,” and the common access line may replace the signal line 285 and the reference line 275 illustrated in the circuit 200.

[0088] In such examples, the common access line can be connected to the sense amplifier 290 at two different nodes (e.g., a first node 291 and a second node 292, as described herein). In some examples, the common access line can permit a self-referenced read operation to share components that may be present between the sense amplifier 290 and the memory cell 105 being accessed in both signal generation and reference generation operations. This configuration can reduce the sensitivity of the sense amplifier 290 to operational variations of various components in the memory device, such as the memory cell 105, access lines (e.g., word line 205, digit line 210, plate line 215), signal development circuitry (e.g., signal development component 250), transistors, voltage sources 293 and 294, and others.

[0089] Although digit line 210, signal development line 255, and signal line 285 are identified as separate lines, according to examples as disclosed herein, digit line 210, signal development line 255, signal line 285, and any other lines connecting memory cell 105 and sense amplifier 290 may be referred to as a single access line. The constituent parts of this access line may be identified separately in various example configurations for purposes of illustrating intervening components and intervening signals.

[0090] The sense amplifier 290 may include various transistors or amplifiers to detect, convert, or amplify the difference in signals, which may include or otherwise be referred to as generating a sense signal or a latch signal. For example, the sense amplifier 290 may include a circuit that receives a sense signal voltage at a first node 291 (e.g., a cell read signal, V sig ) and the reference signal voltage at the second node 292 (eg, V ref ) and compares the sense signal voltage to the reference signal voltage. The output of sense amplifier 290 (e.g., a sense or latch signal) can be driven to a higher voltage (e.g., a positive voltage) or a lower voltage (e.g., a negative voltage, ground) based on the comparison at sense amplifier 290.

[0091] For example, if the first node 291 has a lower voltage than the second node 292, the output of the sense amplifier 290 can be driven to the relatively lower voltage of the low voltage source 293 (eg, V L , which may be a ground voltage or a negative voltage substantially equal to V0). Sense component 150 including sense amplifier 290 or I / O component 160 coupled to such sense component 150 may latch the output of sense amplifier 290 to determine the logic state stored in memory cell 105-a (e.g., when first node 291 has a voltage lower than second node 292, a logic 0 is detected).

[0092] If the first node 291 has a higher voltage than the second node 292, the output of the sense amplifier 290 may be driven to the voltage of the high voltage source 294 (eg, V H 1. The sense component 150 including the sense amplifier 290 or the I / O component 160 coupled to the sense component 150 may latch the output of the sense amplifier 290 to determine the logic state stored in the memory cell 105-a (e.g., when the first node 291 has a higher voltage than the second node 292, a logic 1 is detected). The latched output of the sense amplifier 290 corresponding to the detected logic state of the memory cell 105-a may then be output via one or more input / output (I / O) lines (e.g., I / O line 295).

[0093] To perform a write operation, a rewrite operation, or a refresh operation on memory cell 105-a, a voltage (e.g., a cell write signal) may be applied across capacitor 220. Various methods may be used. In one example, cell select component 225 may be selected or activated by word line 205 (e.g., by selecting or activating word line 205) to electrically connect capacitor 220 to digit line 210. A voltage may be applied across capacitor 220 by controlling the voltage of cell plate 221 (e.g., through plate line 215) and cell bottom 222 (e.g., through digit line 210). In some examples, a write operation, a rewrite operation, or a refresh operation may be based at least in part on a sense or latch signal at sense amplifier 290, which may be based on a signal received via I / O line 295 (e.g., a write signal, a refresh signal) or based on a signal generated at sense amplifier 290 (e.g., a rewrite signal).

[0094] For example, to write a logic 0, cell plate 221 can be taken high (e.g., a positive voltage is applied to plate line 215) and cell bottom 222 can be taken low (e.g., digit line 210 is grounded, digit line 210 is virtually grounded, a negative voltage is applied to digit line 210). The reverse process can be performed to write a logic 1, with cell plate 221 taken low and cell bottom 222 taken high. In some cases, the voltage applied across capacitor 220 during a write operation can have a magnitude equal to or greater than the saturation voltage of the ferroelectric material in capacitor 220, such that capacitor 220 is polarized and thus maintains a charge even when the magnitude of the applied voltage is reduced or when zero net voltage is applied across capacitor 220. In some examples, sense amplifier 290 or signal development component 250 can be used to perform the write operation, which can include coupling low voltage source 293 or high voltage source 294 to the digit line. When the sense amplifier 290 is used to perform a write operation, the signal development component 250 may or may not be bypassed (eg, by applying a write signal via the bypass line 260 ).

[0095] The circuit 200, including the sensing component 150-a, the cell selection component 225, the signal development component 250, the switch component 265, the reference component 270, the selection component 280, or the sense amplifier 290, can include various types of transistors. For example, the circuit 200 can include an n-type transistor, where applying a relatively positive voltage above a threshold voltage of the n-type transistor (e.g., an applied voltage having a positive magnitude relative to the source terminal that is greater than the threshold voltage) to the gate of the n-type transistor enables a conductive path between other terminals of the n-type transistor (e.g., the source terminal and the drain terminal).

[0096] In some examples, an n-type transistor can function as a switching component, wherein the applied voltage is a logic signal for selectively enabling conductivity through the transistor by applying a relatively high logic signal voltage (e.g., a voltage corresponding to a logic 1 state, which may be associated with a positive logic signal voltage supply), or selectively disabling conductivity through the transistor by applying a relatively low logic signal voltage (e.g., a voltage corresponding to a logic 0 state, which may be associated with a ground or virtual ground voltage, or a negative voltage). In some examples in which an n-type transistor is employed as a switching component, the voltage of the logic signal applied to the gate terminal can be selected to operate the transistor at a particular operating point (e.g., in a saturation region or in an active region).

[0097] In some examples, n-type transistors may behave differently from (e.g., more complex than) logic switches, and the selective conductivity across the transistor may also vary with varying source and drain voltages. For example, the applied voltage at the gate terminal may have a specific voltage level (e.g., a clamping voltage, a control voltage) that is used to achieve conductivity between the source and drain terminals when the source terminal voltage is below a specific level (e.g., below the gate terminal voltage minus a threshold voltage). When the source terminal voltage or the drain terminal voltage rises above the specific level, the n-type transistor may be deactivated, breaking the conductive path between the source and drain terminals.

[0098] Additionally or alternatively, circuit 200 may include a p-type transistor, wherein applying a relatively negative voltage above a threshold voltage of the p-type transistor (e.g., an applied voltage having a negative magnitude relative to the source terminal that is greater than the threshold voltage) to the gate of the p-type transistor enables a conductive path between other terminals (e.g., the source and drain terminals) of the p-type transistor.

[0099] In some examples, a p-type transistor can function as a switching component, wherein the applied voltage is a logic signal for selectively enabling conductivity by applying a relatively low logic signal voltage (e.g., a voltage corresponding to a logic "1" state, which may be associated with a negative logic signal voltage supply), or selectively disabling conductivity by applying a relatively high logic signal voltage (e.g., a voltage corresponding to a logic "0" state, which may be associated with a ground or virtual ground voltage, or a positive voltage). In some examples in which a p-type transistor is employed as a switching component, the voltage of the logic signal applied to the gate terminal can be selected to operate the transistor at a particular operating point (e.g., in a saturation region or in an active region).

[0100] In some examples, the behavior of a p-type transistor may be different from (e.g., more complex than) a logical switch performed by a gate voltage, and the selective conductivity across the transistor may also vary with varying source and drain voltages. For example, the applied voltage at the gate terminal may have a specific voltage level for achieving conductivity between the source and drain terminals as long as the source terminal voltage is above a specific level (e.g., above the gate terminal voltage plus a threshold voltage). When the source terminal voltage drops below the specific level, the p-type transistor may be deactivated, breaking the conductive path between the source and drain terminals.

[0101] The transistors of circuit 200 may be field-effect transistors (FETs), including metal oxide semiconductor FETs, which may be referred to as MOSFETs. These and other types of transistors may be formed from regions of doped material on a substrate. In some examples, the transistors may be formed on a substrate dedicated to a particular component of circuit 200 (e.g., a substrate for sense amplifier 290, a substrate for signal development component 250, a substrate for memory cell 105-a), or the transistors may be formed on a substrate common to a particular component of circuit 200 (e.g., a substrate common to sense amplifier 290, signal development component 250, and memory cell 105-a). Some FETs may have a metal portion comprising aluminum or other metal, but some FETs may implement other non-metallic materials such as polysilicon, including those that may be referred to as MOSFETs. Furthermore, while an oxide portion may be used as the dielectric portion of a FET, other non-oxide materials may be used in the dielectric material in FETs (including those that may be referred to as MOSFETs).

[0102] In some examples, different portions of circuit 200, or different operations using portions of circuit 200, can be associated with different latencies. For example, in one portion of an access operation (e.g., a first sub-operation, a first group of sub-operations), a cell access signal can be developed by coupling memory cell 105-a with signal development component 250 (e.g., based at least in part on activating or selecting cell selection component 225, based at least in part on activating another switch component, isolation component, or selection component between memory cell 105-a and signal development component 250). In some examples, the cell access signal can be developed based at least in part on charge sharing between memory cell 105-a (e.g., capacitor 220) and signal development component 250 (e.g., charge flowing from capacitor 220 to signal development component 250, charge flowing from signal development component 250 to capacitor 220), or can be otherwise associated with such charge sharing. In some examples (e.g., in a read operation), the developed cell access signal (e.g., a cell read signal) or charge sharing can be based at least in part on the logic state stored by the memory cell 105-a. In some examples (e.g., in a write operation, a rewrite operation, a refresh operation), the developed cell access signal (e.g., a cell write signal) or charge sharing can be based at least in part on the developed sense or latch signal (e.g., at the sense amplifier 290, at the signal line 285). As disclosed herein, charge sharing between the memory cell 105-a and the signal development component 250 can be associated with a voltage change on the digit line 210, a voltage change on the signal development line 255, or both.

[0103] The development of a cell access signal for an access operation can be associated with a latency, which can refer to the amount of time (e.g., duration) for developing the cell access signal, the delay between initiating a cell access signal development operation and the cell access signal reaching a threshold level suitable for a subsequent portion of the access operation (e.g., in a read operation), or the delay between initiating a cell access signal development operation and writing a logic value to the memory cell 105 (e.g., in a write operation, a rewrite operation, or a refresh operation). In some instances (e.g., in a read operation), the duration or latency can be referred to as a "row-to-column address delay," and in some instances (e.g., in a write operation), the duration or latency can be referred to as a "row precharge delay," which can be longer or shorter than the row-to-column address delay.

[0104] In some examples, charge sharing between memory cell 105-a, digit line 210 (eg, intrinsic capacitance 230), and signal development component 250 may be coupled with time constant behavior (eg, voltage V DL The time constant behavior of the change of voltage V SDLThe duration or latency for developing a cell access signal may refer to the duration between a coupling or activation operation (e.g., selection or activation of cell select component 225, selection or activation of another component configured to selectively couple memory cell 105-a with signal development component 250) and the time when digit line 210 or signal development line 255 reaches a steady-state voltage or when digit line 210 or signal development line 255 reaches a threshold proportion of the steady-state voltage (e.g., 95% of the steady-state voltage, 99% of the steady-state voltage).

[0105] In some examples, the duration or wait time for developing a cell access signal can be expressed as a time constant (e.g., the duration for reaching 63% of the change between the initial voltage and the steady-state voltage), or as a multiple of time constants. For example, the duration or wait time for developing a cell access signal can be expressed as a duration of three time constants, or a duration otherwise associated with the cell access signal being within 5% of its steady-state value. In another example, the duration or wait time for developing a cell access signal can be expressed as a duration of five time constants, or a duration otherwise associated with the cell access signal being within 1% of its steady-state value.

[0106] In some examples, the charge sharing behavior and associated time constant or other latency may be based at least in part on the capacitance of memory cell 105-a, the capacitance of signal development component 250, or other capacitance between memory cell 105-a and signal development component 250 (e.g., intrinsic capacitance, such as intrinsic capacitance 230). For example, a relatively high capacitance of digit line 210 (e.g., relatively high intrinsic capacitance 230) may be associated with relatively high latency (e.g., a relatively long duration of the development cell read signal), and a relatively low capacitance of digit line 210 may be associated with relatively low latency (e.g., a relatively short duration of the development cell read signal). In another example, a relatively high capacitance of memory cell 105-a (e.g., capacitor 220) may be associated with relatively low latency (e.g., a relatively short duration of the development cell read signal), and a relatively low capacitance of memory cell 105-a may be associated with relatively high latency (e.g., a relatively long duration of the development cell read signal).

[0107] Although described with reference to time constant behavior, the duration or latency associated with exploiting the cell access signal may additionally or alternatively include other behaviors, such as ramping, stepping, or oscillating (e.g., underdamped) behavior. In some examples, exploiting the cell access signal may include a set of operations, such as a set of coupling, isolation, activation, deactivation, selection, or deselection operations, and the duration or latency associated with exploiting the cell access signal may include associated circuit behavior for each of the set of operations. For example, exploiting the cell access signal may include activating a switch or selection component along digit line 210 or signal development line 255, activating a switch or selection component between a digit line or signal development line and another component (e.g., selectively coupling a voltage source (not shown) to digit line 210 or signal development line 255), or other operations or combinations of operations.

[0108] In another portion of the access operation (e.g., a second sub-operation, a second group of sub-operations), a sense signal (e.g., a latched signal, an output signal, an input / output signal) can be developed by activating the sense amplifier 290 (e.g., based at least in part on selectively coupling the signal development component 250 with the sense amplifier 290, based at least in part on selectively coupling the sense amplifier with one or both of the low voltage source 293 or the high voltage source 294). In some examples, the sense signal can be developed based at least in part on charge sharing between the signal development component 250 and the sense amplifier 290, or the sense signal can be otherwise associated with charge sharing. In some examples (e.g., in a read operation), the sense signal or charge sharing can be based at least in part on a developed cell access signal (e.g., at the signal development component 250, at the signal development line 255). As described herein, the charge sharing between the signal development component 250 and the sense amplifier 290 can be associated with a voltage change on the I / O line 295, which can be based at least in part on the voltage V sig With voltage V ref Comparison between. (For example, when V sig Less than V ref When V L output, when V sig Greater than V ref When V H output).

[0109] Developing a sense or latch signal for an access operation can also be associated with a latency, which can refer to the amount of time it takes to develop the sense or latch signal, or the delay between initiating the sense or latch signal generation operation and the sense or latch signal reaching a threshold level suitable for the subsequent portion of the access operation (e.g., an output indicating the logic state stored by memory cell 105-a). For example, charge sharing between signal development component 250 and sense amplifier 290 can also be associated with a time constant behavior (e.g., a time constant behavior of the voltage change of I / O line 295) or other logarithmic or exponential behavior. The duration or wait time for developing a sense or latch signal may refer to the duration between a coupling or activation operation (e.g., selection or activation of a switch component such as selection component 280 or a selection component configured to selectively couple the signal development component 250 with the sense amplifier 290, coupling of the sense amplifier 290 with one or both of the low voltage source 293 or the high voltage source 294) and the I / O line 295 reaching a steady-state voltage or the I / O line 295 reaching a threshold proportion of the steady-state voltage (e.g., 90% of the steady-state voltage, 95% of the steady-state voltage).

[0110] The duration or latency for developing a sense or latch signal can also be expressed as a time constant, or as multiple time constants. Although described with reference to time constant behavior, the duration or latency associated with developing a sense or latch signal can additionally or alternatively include other behaviors, such as ramping, stepping, or oscillating (e.g., underdamped) behavior. In some examples, developing a sense or latch signal can include a set of operations, such as a set of coupling, isolation, activation, deactivation, selection, or deselection operations, and the duration or latency associated with developing the sense or latch signal can include associated circuit behavior for each of the set of operations.

[0111] In some examples of circuit 200, the latency associated with developing a cell access signal can be longer in duration than the latency associated with generating a sense or latch signal. For example, charge sharing between signal development component 250 and memory cell 105-a can be associated with a different amount of charge than, or a slower charge transfer than, charge sharing between signal development component 250 and sense amplifier 290. In other words, signal development component 250 or memory cell 105-a can be associated with, or otherwise considered to be, a relatively high-latency portion of circuit 200, and sense amplifier 290 can be associated with, or otherwise considered to be, a relatively low-latency portion of circuit 200. In such examples, circuit 200 can support executing input or output operations more quickly than executing signal development operations.

[0112] According to an example disclosed herein, a memory device 100 including circuit 200 can couple each of a set of signal development components 250 with a respective memory cell 105 during overlapping time intervals so that a plurality of cell access signals (e.g., associated with the respective memory cell 105 of each of the respective signal development components 250) can be generated during the overlapping time intervals. Each signal development component in the set of signal development components 250 can be selectively coupled (e.g., in sequential order) with a sense amplifier 290 via a selection component 280 to generate a sequence of sense or latch signals at the sense amplifier 290, or vice versa. For example, in a read operation or a set of read operations, the sequence of sense or latch signals generated at the sense amplifier 290 can be based on the respective cell access signals (e.g., cell read signals) developed at the set of signal development components 250 during the overlapping time intervals, which cell access signals can be associated with a particular logic state stored by the respective memory cell 105. Thus, as disclosed herein, a memory device 100 including circuit 200 can include signal development components 250 multiplexed via selection components 280, which in some examples can compensate for portions of access operations associated with different latencies.

[0113] Figure 3 An example circuit 300 is illustrated for developing cache storage based on signals in a supporting memory device as disclosed herein. It should be understood that circuit 300 is merely one illustrative example and that many implementations, including other specific circuits and topologies, are possible following the principles and techniques disclosed herein, as will be appreciated by those of ordinary skill in the art.

[0114] Circuit 300 includes a set of memory cells 105-b (e.g., memory cells 105-b-111 through 105-b-srm) and a sensing element 150-b. Although memory cells 105-b are illustrated as including capacitors and cell select components, memory cells 105-b according to examples as disclosed herein may include various configurations (e.g., with or without cell select components) and various types of logic storage elements (e.g., capacitive memory elements, ferroelectric memory elements, material memory elements, resistive memory elements, thresholded memory elements, other memory elements) to support various types of memory devices (e.g., DRAM memory devices, FeRAM memory devices, PCM devices, chalcogenide memory devices). Circuit 300 illustrates circuitry that can support the described techniques for signal development caching in memory devices.

[0115] The sensing component 150-b may include a set of signal development components 250-a (e.g., signal development components 250-a-1 to 250-as) each associated with one or more of the memory cells 105-b. The sensing component 150-b may also include a selection component 280-a (e.g., a signal development component selection component, a MUX, a transistor network, a transistor array, a switch network, a switch array) coupled to the set of signal development components 250-a (e.g., via signal development lines 255-a-1 to 255-as). The selection component 280-a may be configured to selectively couple a selected one of the signal development components 250-a (e.g., a selected one of the signal development lines 255-a) to a sense amplifier 290-a of the sensing component 150-b (e.g., via signal line 285-a, in response to a logic or selection signal, such as a signal development component multiplexing (SDCM) signal). Sense amplifier 290 - a may exchange (eg, communicate, receive, transmit) input or output signals with other components of the memory device (eg, input / output component 160 ) via I / O line 295 - a .

[0116] In the example of circuit 300, memory cells 105-b may be arranged according to a set of domains 310-a (e.g., domains 310-a-1 through 310-as). In other words, circuit 300 may illustrate an example of a set of memory cells 105-b divided across or otherwise associated with s domains. In the example of circuit 300, each of domains 310-a may be associated with (e.g., coupled to) one of signal development components 250-a (e.g., domain 310-a-1 is associated with signal development component 250-a-1). However, in various examples of circuitry supporting the described techniques, a domain 310 may be associated with more than one signal development component 250, or a signal development component 250 may be associated with more than one domain 310, or both.

[0117] Although the example domain 310-a of the circuit 300 is described with reference to specific characteristics, alternative domain definitions or organizations may also be utilized to support the described techniques. As one such example, the memory cells 105 or access lines (e.g., word lines 205, digit lines 210, plate lines 215) of a domain may be organized or subdivided differently than the domain 310-a illustrated in the circuit 300, or the domain may be defined differently than the domain 310-a illustrated in the circuit 300 (e.g., the components are contained within the illustrative boundaries of the domain), or the domain may be coupled to the signal development component 250 or the sense amplifier 290 differently than the domain 310-a illustrated in the circuit 300 (e.g., utilizing a different multiplexing organization or scheme, a different selection component).

[0118] In the example of circuit 300, each of domains 310-a can include memory cells 105-b coupled to or between one of a set of digit lines 210-a and one of a set of plate lines 215-a. For example, for domain 310-a-1, each memory cell in the set of memory cells 105-b (e.g., each of memory cells 105-b-111 through 105-b-1rm) can be coupled to one of digit lines 210-a-11 through 210-a-1r and can be coupled to one of plate lines 215-a-11 through 215-a-1r. In other words, domain 310-a can illustrate an arrangement of memory cells 105-b divided across or otherwise associated with r digit lines 210-a, or "columns." Although the example circuit 300 is illustrated as having individual plate lines 215-a, in some examples, a group of plate lines 215-a (e.g., a group of two or more of plate lines 215-a-11 through 215-a-1r) may represent or otherwise be functionally equivalent to common plate lines of a domain 310-a (e.g., domain 310-a-1), or may represent or otherwise be functionally equivalent to common plate lines of a portion of domain 310-a (e.g., a “sub-domain”), or a different group of plate lines 215-a (e.g., a group of two or more of plate lines 215-a-11 through 215-a-sr) may represent or otherwise be functionally equivalent to common plate lines of a group of domains 310-a (e.g., a group of domains 310-a-1 through 310-as).

[0119] The domain 310-a may also illustrate an arrangement of memory cells 105-b divided across or otherwise associated with m word lines 205-a or “rows.” For example, the domain 310-a-1 may include a respective group of m memory cells 105-b coupled to or between each of the digit lines 210-a of the domain 310-a and each of the plate lines 215-a of the domain (e.g., a group of memory cells 105-b-111 through 105-b-11m coupled to or between digit line 210-a-11 and plate line 215-a-11). For a group of memory cells 105-b coupled to the same digit line 210-a and the same plate line 215-a, the memory cells 105-b may be configured to be coupled to the same digit line 210-a and the same plate line 215-a based at least in part on the associated logic signal WL (e.g., for domain 310-a, the logic signal WL 11 To WL 1mAlthough illustrated as sharing a common set of word lines 205-a in domain 310-a (e.g., word lines 205-a-11 through 205-a-1m shared across each of the columns of domain 310-a-1), other examples of memory devices may have different arrangements of word lines 205 in domain 310.

[0120] In the example of circuit 300, each of domains 310-a may also include or otherwise be associated with a selection component 320-a (e.g., a digit line selection component, a MUX, a transistor network, a transistor array, a switch network, a switch array) coupled to each digit line in the set of digit lines 210-a of domain 310-a. For example, domain 310-a-1 may include a selection component 320-a-1 coupled to each of digit lines 210-a-11 through 210-a-1r. For example, selection component 320-a-1 may be configured to selectively couple a selected one of digit lines 210-a-11 through 210-a-1r or one of memory cells 105-b-111 through 105-b-11m with signal development component 250-a-1 (e.g., in response to a logic or selection signal, such as digit line multiplexing (DLM) signal DLM1). Thus, each of the selection components 320-a-1 through 320-as can be associated with a respective one of the signal development components 250-a-1 through 250-as.

[0121] In the example of circuit 300, each of the signal development components 250-a can be associated with a respective group of memory cells 105-b or a respective group of digit lines 210-a. In some examples, the selection components 320-a-1 through 320-as can be instances of a plurality of second selection components, wherein each second selection component of the plurality of second selection components is associated with a respective signal development component 250 and is configured to selectively couple any one of the memory cells 105-b or digit lines 210-a in the group to the respective signal development component 250.

[0122] In the illustrative example, each of the domains 310-a may include 1,048,576 memory cells 105-b arranged into 1,024 uniquely addressed rows and 1,024 columns (e.g., where m=1024 and r=1024). According to the illustrative example of the circuit 300, one signal development component 250-a may be mapped to a particular domain 310-a, but in other examples, a group of more than one signal development components 250-a may be mapped to a particular domain 310-a (e.g., mapped to a respective set of digital lines 210-a of the domain 310-a). In some examples, this mapping may be fixed (e.g., where a respective set of digital lines 210-a is mapped to a respective signal development component 250-a within each domain 310-a), which may reduce multiplexing or selection circuit complexity in some examples. In various other examples (not shown), the signal development component 250 can be mapped to more than one domain 310, more than one set of digital lines 210 (e.g., of a domain), or other configurations. Additionally or alternatively, a domain 310 or a set of digital lines 210 can be mapped to more than one signal development component 250. In other words, a memory device can include various configurations of the signal development component 250 to support the examples of multiplexed signal development described herein.

[0123] In the example of circuit 300, each of digit lines 210-a is associated with (e.g., configured to selectively couple with) a single one of the signal development components (e.g., via a corresponding one of select components 320-a-1). For example, digit line 210-a-11 may be associated with signal development component 250-a-1 instead of signal development component 250-as. However, in various examples of circuitry supporting the described techniques for signal development caching in a memory device, a particular digit line 210-a may be associated with (e.g., configured to selectively couple with) more than one signal development component 250-a, which may include select components different from the set of select components 320-a-1 through 320-as illustrated in circuit 300. For example, digital line 210-a-11 may be associated with signal development component 250-a-1 or signal development component 250-as or any other signal development component 250-a of circuit 300 (e.g., configured to selectively couple with signal development component 250-a-1 or signal development component 250-as or any other signal development component 250-a of circuit 300).

[0124] In another illustrative example of supporting the described techniques for multiplexed signal development, another circuit may include several domains, each having 1,048,576 memory cells 105 arranged into 1,024 uniquely addressed rows and 1,024 columns, which may refer to a different component organization than circuit 300. Each of the domains of the other circuit may be arranged such that m=1024 and r=1024, and the digit lines 210 of the respective domains of this other circuit may be collectively mapped to an array of 64 signal development components 250 (e.g., according to a many-to-one mapping, according to a many-to-many mapping). In one example of the other circuit, each of the signal development components 250 may be mapped to a respective subset of the domain's digit lines 210 (e.g., one signal development component 250 may be mapped to 1024 / 64=16 digit lines 210 within each domain). In some examples, this mapping may be fixed (eg, where groups or subsets of 16 digital lines 210 map to corresponding signal development components 250 within each domain), which may reduce multiplexing or selection circuit complexity in some examples.

[0125] In this other example, a row of 1,024 memory cells 105 (e.g., spanning one domain of the other circuit) can be selected by a single word line 205 in each domain. In other words, with 64 signal development components 250 per domain and r=1,024, activation of a word line in one domain and activation of another word line in another domain (e.g., including other independent word lines in other domains) can select the memory cells 105 associated with the respective row. With 64 signal development components 250 per domain of this circuit, 64 memory cells in a group of 1,024 memory cells 105 can be accessed at a time in each domain (e.g., by selectively coupling a respective digit line 210 to each of the 64 signal development components 250 via a respective selection component). During this access, other digit lines 210 can be selectively isolated from the respective signal development component 250 and other signal development components 250 interfacing the same domain. Furthermore, other digit lines 210 can be shunted or shielded from other digit lines 210, as described herein.

[0126] Thus, examples according to the techniques disclosed herein may include instances in which word lines 205 within a domain or word lines 205 across multiple domains, or some combination thereof, are independent (e.g., selectively independent of each other). Examples according to the techniques disclosed herein may also include instances in which word lines 205 within a domain or word lines 205 across multiple domains, or some combination thereof, are locked (e.g., hardwired) to be selected together (jointly). It should be understood that in instances in which word lines 205 are independently selectable, such word lines 205 may still be operated simultaneously (e.g., even if locked) at least at certain times or under certain conditions. Furthermore, examples according to the techniques disclosed herein may include instances in which many digital lines 210 are mapped to many signal development components 250 within a domain, as well as instances in which many digital lines 210 are mapped to one signal development component 250 within a domain (e.g., the selection component 280 may have many-to-one or many-to-multifunctionality). Throughout this disclosure (including references to Figure 8A 、 8B and 8C) describe aspects of these and other example variations.

[0127] In some examples, operations associated with word line selection may be time-limited to prevent data loss or corruption, which may involve waiting for completion of ongoing operations with respect to accessed cells. For example, when switching from a first word line 205-a of a domain 310-a to a second word line 205-a of the same domain 310-a, such a switch may require waiting for completion of cell access signal development (e.g., by signal development component 250-a) for domain 310-a before the switch occurs. In an instance where a word line 205-a is shared across several domains (e.g., word line 205-a shared between domains 310-a-1 and 310-as, word line 205-a-11 being functionally equivalent to word line 205-a-s1), when switching from a first shared word line 205-a to a second shared word line 205-a, such a switch may require waiting for completion of cell access signal development in each of domains 310-a-1 and 310-as (e.g., each of signal development components 250-a-1 and 250-as) before the switch occurs.

[0128] In the example of circuit 300, each of domains 310-a may also include or otherwise be associated with a set of shunts 330-a (e.g., digit line shunts, digital to board shunts). For example, domain 310-a-1 may include a set of shunts 330-a-11 through 330-a-1r. Each of shunts 330-a may be coupled to or between digit line 210-a and board line 215-a. For example, for domain 310-a-1, shunt 330-a-11 may be coupled to or between digit line 210-a-11 and board line 215-a. For example, the shunt 330-a-11 may be configured to selectively couple the digit line 210-a-11 with the plate line 215-a-11 (eg, in response to a logic or switch signal DLS). 11 In some examples, shunt 330-a can be configured to selectively equalize the bias between digit line 210-a and plate line 215-a, or to equalize one or more memory cells 105-b coupled to or between digit line 210-a and plate line 215-a. In some examples, shunt 330-a can be configured to selectively discharge one or more memory cells 105-b coupled to or between digit line 210-a and plate line 215-a.

[0129] In some examples, circuit 300 can be operated according to shunt shielding. For example, when multiplexing is performed on domain 310-a (e.g., using selection component 320-2), shunt 330-a of a shielded digit line 210-a (e.g., a digit line 210-a not associated with an access operation being performed) can support selective coupling with plate line 215-a to prevent or reduce data loss (e.g., charge leakage) of memory cell 105-b associated with the shielded digit line 210-a. In other words, shunt 330-a can shut off bit transfer on the shielded digit line 210-a not associated with the access operation being performed.

[0130] The selection components 280-a and 320-a can include various component configurations and can each be referred to as a multiplexer, a transistor network, a transistor array, a switch network, or a switch array. In one example, the selection component 280-a can include a set of transistors that are each coupled to a sense amplifier 290-a (e.g., each coupled to a signal line 285-a). Each transistor in the set of transistors can also be coupled to a corresponding one of the signal development components 250-a (e.g., a corresponding one of the signal development lines 255-a-1 through 255-as). Each transistor in the set of transistors can be configured to selectively couple a corresponding one of the signal development components 250-a to the sense amplifier 290-a in response to one of a set of switch or logic signals provided to the gate of the transistor.

[0131] In some examples, the selection component 280-a or the selection component 320-a may include a decoder or other logic or selection signal conversion component. For example, the decoder of the selection component 280-a may receive a logic or selection signal (e.g., signal SDCM), which may be a digital signal (e.g., a signal having or otherwise representing a plurality of bits) received via a signal bus. In some examples, the decoder may receive the digital signal as input to generate a set of binary signals (e.g., switch or logic signals) that may be applied to the gates of a group of transistors configured in a switch arrangement. For example, the decoder of the selection component 280-a may receive the selection signal SDCM as a 4-bit digital input signal and generate 16 binary (e.g., on / off) switch signals, each of which is applied to the gate of one of the group of 16 transistors configured in the switch arrangement.

[0132] In various examples, selection component 280-a can be configured such that one of signal development components 250-a-1 through 250-as is coupled (e.g., selectively coupled) to sense amplifier 290-a at a time, and the other of signal development components 250-a-1 through 250-as can be decoupled (e.g., selectively decoupled) from sense amplifier 290-a at that time (e.g., a time when the one of signal development components 250-a-1 through 250-as is selectively coupled to sense amplifier 290-a). In some examples, selection component 280-a can also be configured to support operation in which none of signal development components 250-a-1 through 250-as is coupled to sense amplifier 290-a at a particular time (e.g., in which each of signal development components 250-a-1 through 250-as is selectively isolated from sense amplifier 290-a). In various examples of circuit 300, selection component 320-a may include similar features or sets of features as selection component 280-a, or selection component 320-a may include different features or sets of features than selection component 280-a.

[0133] In some examples of circuit 300, signal development component 250-a or memory cell 105-b can be associated with or otherwise considered to be a relatively high-latency portion of circuit 300, and sense amplifier 290-a can be associated with or otherwise considered to be a relatively low-latency portion of circuit 300. According to examples as disclosed herein, sensing component 150-b can illustrate an example of dividing memory cell access circuitry into a high-latency portion (e.g., signal development component 250-a) and a low-latency portion (e.g., sense amplifier 290-a) and coupling one set of the high-latency portions with one set of the low-latency portions through a multiplexer (e.g., selection component 280-a).

[0134] In the example of circuit 300, selection component 280-a can provide a first degree of data pipelining, which can reduce the effects of data access serialization (due to row buffer conflicts). For example, selection component 280-a can support overlapping data transfers on different sets of digit lines 210-a (e.g., different domains 310-a). As a result, sense amplifier 290-a can be free to support read, write, rewrite, or refresh operations (e.g., while coupled to one of signal development components 250-a) while other signal development components 250-a are involved in data transfers (e.g., while other signal development components 250-a are coupled to digit lines 210-a or memory cells 105-b).

[0135] The group of signal development components 250-a can be viewed as a small, fast local cache (e.g., a signal development cache), wherein respective signal development components 250-a can be configured to store signal states that differ from the logic states stored at memory cells 105-b. This configuration can be used to support reduced row buffer conflict rates, increase internal bandwidth, or achieve other benefits. In some examples, selection components 320-a can provide additional gains by providing a second degree of data pipelining via multiplexing digital lines 210-a. Thus, according to examples as disclosed herein, a memory device 100 including circuit 300 can include signal development components 250-a multiplexed via selection components 280-a or digital lines 210-a multiplexed via one or more selection components 320-a, which can compensate for portions of access operations or portions of access circuitry associated with different latencies.

[0136] Various memory devices (e.g., memory device 100) may include various arrangements of circuit 300. For example, memory device 100 may include a set of sensing components 150-b, or sensing components 150 may otherwise include a set of sense amplifiers 290-a and a corresponding set of multiplexed signal development components 250-a. In one example, memory device 100, or a portion thereof, may include 16 sense amplifiers 290-a multiplexed with 1024 digit lines 210-a (this may or may not include multiplexing via selection components 320-a). In some examples, a set of sense amplifiers 290-a may be included in a composite array, where the set of sense amplifiers 290-a is accessed as a single sense amplifier "row" of the composite array. In various examples, the multiplexed digit lines 210-a may be in the same domain 310-a or in different domains 310. In some examples, each of the domains 310 - a may be independently controllable and accessible via the same row component 125 or different row components 125 .

[0137] Figure 4A Illustrated is an example of a read operation 400 that supports signal development caching in a memory device according to examples as disclosed herein. The read operation 400 may illustrate portions (e.g., time intervals) of an access operation associated with generating cell access signals (e.g., cell read signals, cell write signals) and latch signals when accessing a memory cell 105. For example, the read operation 400 may be divided into a read signal development portion 410 (e.g., a cell read portion), a latch signal generation portion 420, and a rewrite signal development portion 430 (e.g., a cell rewrite portion). The read operation 400 may employ circuitry that supports multiplexed signal development, such as with reference to FIG. Figure 3As an illustrative example, read operation 400 is described with reference to reading the logic state stored by memory cell 105-b-111 of circuit 300, but read operation 400 may illustrate operations that may be performed on any one or more of memory cells 105-b of circuit 300.

[0138] The read signal development portion 410 can be associated with charge sharing between the memory cell 105-b-111 (e.g., a capacitive storage element, a linear capacitor, or a ferroelectric capacitor of the memory cell 105-b-111), the digit line 210-a-11 (e.g., intrinsic capacitance 230), and the signal development component 250-a-1. The read signal development portion 410 can be an example of developing a signal (e.g., a signal state, a cache signal) at the signal development component 250-a-1 based at least in part on selectively coupling the signal development component 250-a-1 with the memory cell 105-b-111. In some examples, developing the read signal at the signal development component 250-a-1 is associated with a first latency (e.g., a relatively high latency or long duration). During the read signal development portion 410, the signal development component 250-a-1 can be selectively decoupled from the sense amplifier 290-a.

[0139] In some examples of reading the signal development portion 410, an access line (e.g., signal development line 255-a-1) of the signal development component 250-a-1 can be biased at a relatively high voltage, which can be associated with storing a relatively high voltage charge at the signal development component 250-a-1 (e.g., in a signal storage component (e.g., an integrating capacitor) of the signal development component 250-a-1). In some examples, this biasing can be associated with a "plate low" read operation, wherein during the read signal development portion 410, the plate line 215-a-11 associated with the memory cell 105-b-111 is biased at a lower voltage (e.g., a ground voltage) than the digit line 210-a-1 associated with the memory cell 105-b-111 being accessed.

[0140] The read signal development portion 410 may also include selectively coupling the memory cell 105-b-111 with the signal development component 250-a-1. In some examples, the read signal development portion 410 may include activating the word line 205-a-11 associated with the memory cell 105-b-111 being read (e.g., activating logic signal WL1), which may selectively couple the memory storage element (e.g., capacitor 220) with the corresponding digit line 210-a-11 (e.g., via the cell select component 225 of the memory cell 105-b-111). In some examples, the read signal development portion 410 may include selectively coupling the corresponding digit line 210-a-11 with the signal development component 250-a-1 (e.g., via the select component 320-a-1, based on the select signal DLM1, or some other switching component). Charge can thus be shared between the memory cell 105-b-111 and the signal development component 250-a-1 and can stabilize after a certain time (e.g., according to a time constant behavior), where the voltage changes of the digital line 210-a-11 and the signal development line 255-a-1 are based at least in part on the logic state stored by the memory cell 105-b-111.

[0141] In some examples, the read signal development portion 410 may include a delay (e.g., a delay portion, a delay duration) between developing the read signal (e.g., the read signal at the signal development component 250 reaches a steady state, the read signal reaches a maximum value at the signal development component 250) and providing the developed read signal (e.g., maintained by the signal development component 250) to the sense amplifier 290. In other words, there may be a delay or inactivity period during the read signal development portion 410 before initiating the latch signal generation portion 420, which, in some examples, may include a decay of the developed read signal (e.g., a decay of the maintained read signal). In some examples, the circuit 300 may be configured such that the duration of this delay or inactivity period, or the amount of delay in the developed read signal, can be tolerated while still reliably detecting the logic state stored by the memory cell 105. In some examples, this functionality of the circuit 300 may be supported by a refresh operation of the signal development component 250 (e.g., maintaining a cache signal at the signal development component 250) that mitigates the delay of the developed read signal. These and other configurations may enable signal development component 250 to perform cache functions in circuit 300 (eg, caching of developed read signals or cache signals for a certain amount of time).

[0142] In some examples, charge sharing of the read signal development portion 410 can be associated with a destructive read operation (e.g., where the originally stored logic state of the memory cell 105-b-111 is lost or otherwise degraded at the memory cell 105-b-111), and thus can be subsequently followed by a rewrite operation (e.g., rewrite signal development portion 430). In some examples, the rewrite operation may not immediately follow the read signal development portion 410, such as when the stored data is transferred to the signal development component 250, where it can be stored and further read, written, or modified. In various examples, the data can be transferred back to the same memory cell 105 or a different memory cell 105, which can be associated with an operation that makes the signal development component 250 available for other operations. In some instances, charge sharing of the read signal development portion 410 may be associated with a non-destructive read operation (e.g., where the initially stored logic state of memory cell 105-b-111 is maintained at memory cell 105-b-111) and, therefore, may not be followed by a rewrite operation (e.g., the rewrite signal development portion 430 may be omitted).

[0143] Charge sharing in the read signal development portion 410 may be associated with a delay or latency known as row-to-column address delay. In DRAM applications, data may be stored at the memory cell 105 as electrode charge and may respond relatively quickly (e.g., with relatively low latency). In FeRAM applications, data may be stored at the memory cell 105 as a cell state in the form of a dipole orientation or polarization. The dynamics of these dipoles may be relatively slow (e.g., with relatively high latency), which may result in longer sensing times for FeRAM applications (e.g., longer than for DRAM applications). Therefore, in some examples (e.g., in FeRAM applications), the read signal development portion 410 may be associated with a relatively high latency or long duration (e.g., compared to the latch signal generation portion 420). In some FeRAM applications, for example, the latency associated with the operation of the read signal development portion 410 may be approximately 50 nanoseconds.

[0144] In some examples of the read signal development portion 410, shunts 330-a associated with other memory cells 105-b of the domain 310-a-1, such as shunt 330-a-12 (not shown, which may be associated with digit line 210-a-12 or plate line 215-a-12) to 330-a-1r, may be selected or activated. This may equalize biases across the unaccessed memory cells 105-b (e.g., equalize biases between digit line 210-a-12 and plate line 215-a-12, equalize biases between digit line 210-a-1r and plate line 215-a-1r, etc.). In FeRAM applications, for example, such bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cell 105-b-111 being accessed during the read signal development portion 410.

[0145] Latch signal generation portion 420 may be associated with charge sharing between signal development component 250-a-1 and sense amplifier 290-a. Latch signal generation portion 420 may be an example of generating an output signal of sense amplifier 290-a (e.g., an amplifier component) based at least in part on a developed signal (e.g., a cell read signal) at signal development component 250-a-1. In some examples, generating the latch signal at sense amplifier 290-a is associated with a second latency (e.g., a relatively low latency or short duration). Transitioning from read signal development portion 410 to latch signal generation portion 420 may include selectively coupling signal development component 250-a-1 to sense amplifier 290-a.

[0146] In some examples, selectively coupling the signal development component 250-a-1 with the sense amplifier 290-a may include selection via the selection component 280-a based on the logic select signal SDCM. In some examples, selectively coupling the signal development component 250-a-1 with the sense amplifier 290-a may include selective coupling via some other switching component (e.g., an isolation switching component) between the signal development component 250-a-1 and the sense amplifier 290-a. In some examples, charge sharing by the latch signal generation portion 420 may be relatively rapid and may take a fraction of the amount of time involved in charge sharing between the memory cell 105-b-11 and the signal development component 250-a-1. In other words, the duration of the latch signal generation portion 420 may be shorter than that of the read signal development portion 410. In some FeRAM applications, for example, the latency associated with the operation of the latch signal generation portion 420 may be approximately 5 to 10 nanoseconds.

[0147] In some examples, latch signal generation portion 420 may include "energizing" sense amplifier 290-a, which may include selectively coupling one or more voltage sources (e.g., low voltage source 293, high voltage source 294) to sense amplifier 290-a. Thus, an output signal based at least in part on the cell read signal (e.g., based at least in part on the logic state stored by memory cell 105-b-111) may be generated at sense amplifier 290-a. The output signal may be communicated from sense amplifier 290-a to another component of the memory device (e.g., input / output component 160) via I / O line 295 to provide an indication of the data stored by memory cell 105-b-111. In some examples, the output signal or some other signal associated with the generated latch signal may also be communicated back to or otherwise shared with signal development component 250-a-1, which in some examples may support a rewrite operation (e.g., after a destructive read operation). For example, as part of latch signal generation portion 420, based on the generated latch signal or output signal (e.g., based on whether memory cell 105-b-111 stores a logic 0 or a logic 1), a rewrite signal can be communicated or otherwise shared or generated using signal development component 250-a-1 (e.g., via signal development line 255-a-1). In some examples, the generated latch signal or output signal can be communicated back to signal development component 250-a-1 to enhance the charge or other signal maintained at signal development component 250-a-1, which can support a rewrite operation on memory cell 105-b-111.

[0148] In some examples of the latch signal generation portion 420, shunts 330-a associated with other memory cells 105-b of the domain 310-a-1, such as shunts 330-a-12 (not shown, which may be associated with digit line 210-a-12 or plate line 215-a-12) to 330-a-1r, may be selected or activated. This may equalize bias across the unaccessed memory cells 105-b (e.g., equalize the bias between digit line 210-a-12 and plate line 215-a-12, equalize the bias between digit line 210-a-1r and plate line 215-a-1r, etc.). In FeRAM applications, for example, such bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cell 105-b-111 being accessed during the latch signal generation portion 420.

[0149] The rewrite signal development portion 430 can be associated with charge sharing between the memory cell 105-b-111, the digit line 210-a-11, and the signal development component 250-a-1. The rewrite signal development portion 430 can be an example of developing a cell access signal (e.g., a cell write signal, a cell rewrite signal) at or using the signal development component 250-a-1. In some cases, the development of the cell access signal (e.g., a cell write signal, a cell rewrite signal) at or using the signal development component 250-a-1 can be based at least in part on a latch signal of the sense amplifier 290-a (e.g., generated during the latch signal generation portion 420). In some examples, a cell access signal (e.g., a cell write signal, a cell rewrite signal) at or using the signal development component 250-a-1 can be based on a charge or voltage maintained at the signal development component 250-a-1 (e.g., based at least in part on the read signal development portion 410), where the charge or voltage maintained at the signal development component 250-a-1 can be indicative of a logic state initially stored by the memory cell 105-b-111. In some examples, the charge or voltage maintained at the signal development component 250-a-1 can be independent of the latch signal at the sense amplifier 290-a, or can be enhanced by the latch signal at the sense amplifier 290-a (e.g., enhanced during the latch signal generation portion 420).

[0150] In some examples, developing the rewrite signal at signal development component 250-a-1 is associated with a third latency (e.g., a relatively high latency or long duration) that may or may not be equal to the first latency. Transitioning from latch signal generation portion 420 to rewrite signal development portion 430 may include selectively decoupling or isolating signal development component 250-a-1 from sense amplifier 290-a (e.g., via selection component 280-a or an isolation switch component). Although rewrite signal development portion 430 may support rewriting the logic state of memory cell 105 that has been discharged, depolarized, or otherwise damaged or degraded in a read operation, in examples of non-destructive read operations (e.g., when 105-b-111 maintains the stored logic state after reading signal development portion 410), rewrite signal development portion 430 may be omitted, and latch signal generation portion 420 may be subsequently followed by another access operation (e.g., a read operation, a write operation, a refresh operation).

[0151] In various examples, rewriting of the memory cell 105-b-111 during the rewrite signal development portion 430 may be performed or modified based on whether the rewrite signal is generated or otherwise provided by the sense amplifier 290-a or based on whether the rewrite signal is generated or otherwise provided by the signal development component 250-a. For example, the rewrite operation of the rewrite signal development portion 430 may be performed without relying on the rewrite signal of the sense amplifier 290-a, such as when the signal development component 250-a is configured to locally maintain the charge or other state (e.g., cache state, signal state) associated with the originally stored logic state of the memory cell 105-b-111 until it is transferred back to the memory cell 105-b-111 (e.g., to provide a local cache function as associated with the rewrite operation). In other words, depending on whether the signal development component 250-a relies on the latch signal of the sense amplifier 290-a to rewrite the memory cell 105-b-111, the read signal development portion 410 or the latch signal generation portion 420 may or may not be "destructive" from the perspective of the signal development component 250-a. In some examples (e.g., when the signal development component 250-a is configured to maintain a charge or other state indicative of the originally stored logic state of the memory cell 105-b-111), the rewriting of the memory cell 105-b-111 may occur after a certain delay period (e.g., of the rewrite signal development portion 430) depending on the duration that the signal development component 250-a is configured to maintain such a charge or other state or the type of control logic that implements the write-back (e.g., first-in, first-out (FIFO), least recently used (LRU), or other).

[0152] In some examples of rewrite operations, the circuit 300 can be configured to couple the memory cell 105-b-111 to a high voltage source (e.g., a high voltage rail via the signal development component 250-a-1), which can be a direct coupling via pull-up or pull-down circuitry (e.g., a transistor or other switching component of the signal development component 250-a-1). In some examples, the signal development component 250-a-1 can be configured with a capacitor or other charge storage component, and the latch signal generation portion 420 or the rewrite signal development portion 430 can include charging or refreshing the capacitor or other charge storage component with a charge sufficient to rewrite the memory cell 105-b-111 (e.g., during the rewrite signal development portion 430). Thus, in various instances, the signal development component 250-a-1 may rewrite the logic state to the memory cell 105-b-111, which may be performed when the signal development component 250-a-1 is selectively decoupled from the sense amplifier 290-a so that the sense amplifier 290-a is free to support operations with respect to the other signal development component 250-a.

[0153] Overwriting the charge sharing of signal development portion 430 may be associated with a delay or latency referred to as row precharge delay, which may include fully or partially overwriting the logic state initially stored at memory cell 105-b-111. For example, to overwrite a logic 0, digit line 210-a-11 may be biased to a positive voltage (e.g., 1.5V) and plate line 215-a-11 may be biased to ground or a negative voltage (e.g., 0V). To overwrite a logic 1, digit line 210-a-11 may be biased to ground or a negative voltage (e.g., 0V) and plate line 215-a-11 may be biased to a positive voltage (e.g., 1.5V). In some cases, the biasing of digit line 210-a-11 and plate line 215-a-11 may be based at least in part on the generated latch signal (e.g., before sense amplifier 290-a and signal development component 250-a-1 are selectively isolated). For example, signal development component 250-a-1 or sense amplifier 290-a can bias digit line 210-a-11 to a positive voltage or ground based at least in part on the latch signal during rewriting of signal development portion 430. In some cases, this bias can be based on a charge or other state maintained at signal development component 250-a-1, which can be independent of the generated latch signal (e.g., generated using sense amplifier 290-a).

[0154] In DRAM applications, data may be written to the memory cell 105 as electrode charges and may respond relatively quickly (e.g., relatively low latency). In FeRAM applications, data may be written to the memory cell 105 as cell states in the form of dipole orientations or polarizations. The dynamics of these dipoles may be relatively slow (e.g., relatively high latency), which may result in longer write times for FeRAM applications (e.g., longer than for DRAM applications). Therefore, in some examples (e.g., in FeRAM applications), the rewrite signal development portion 430 may be associated with a relatively high latency or long duration (e.g., compared to the latch signal generation portion 420). At the end of the rewrite signal development portion 430, all digit lines 210-a-11 and all plate lines 215-a of the domain 310-a-1 may be biased to ground voltage, effectively equalizing the bias of each of the memory cells 105-b across the domain 310-a-11, which may support maintaining the logic state stored by the memory cell 105-b over time.

[0155] In some examples, shunts 330-a associated with other memory cells 105-b of domain 310-a-1, such as shunt 330-a-12 (not shown, which may be associated with digit line 210-a-12 or plate line 215-a-12) to 330-a-1r, may be selected or activated during the rewrite signal development portion 430. This may equalize biases across unaccessed memory cells 105-b (e.g., equalize biases between digit line 210-a-12 and plate line 215-a-12, equalize biases between digit line 210-a-1r and plate line 215-a-1r, etc.). This bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than memory cell 105-b-111 being rewritten during the rewrite signal development portion 430.

[0156] The read operation 400 may be performed with a total duration t A1 -t A0 105-b-11, includes a read signal development portion 410, a latch signal generation portion 420, and a rewrite signal development portion 430 for reading the single memory cell 105-b-111. In an example where the read operation 400 does not employ multiplexed signal development techniques (e.g., a sequence of read operations 400 using the same signal development component 250), a subsequent read operation employing the sense amplifier 290-a may be followed by the rewrite signal development portion 430. Thus, performing multiple read operations 400 (e.g., reading multiple memory cells 105-b) using the same signal development component 250 may involve a duration t A1 -t A0 An integer multiple of (e.g., at least 2*(t A1 -t A0 ) to read two memory cells 105-b). However, multiplexing the signal development component 250-a (eg, via the selection component 280-a) may reduce the amount of time involved for the sense amplifier 290-a to read multiple memory cells 105-b.

[0157] Figure 4BIllustrated is an example of a read operation 450 supporting signal development caching in a memory device according to examples as disclosed herein. The read operation 450 may illustrate portions (e.g., time intervals) of an access operation (e.g., a multi-cell access operation) associated with generating cell access signals (e.g., cell read signals, cell write signals) and latch signals when accessing four memory cells 105 (e.g., via four signal development components 250). For example, the read operation 450 may be divided into a read signal development portion 410-a, a latch signal generation portion 420-a, and a rewrite signal development portion 430-a for each of a group of memory cells 105-b, which may be referenced to FIG. Figure 4A The read operation 450 may employ circuitry that supports multiplexing signal development, such as that described in the accompanying drawings. Figure 3 Described circuit 300. Read operation 450 illustrates an example of separating signal development operations from input / output operations, which can increase data throughput in a memory device.

[0158] As an illustrative example, a read operation 450 is described with reference to reading logic states stored by four memory cells 105-b of four different domains 310-a, each of which is associated with a respective signal development component 250-a that is multiplexed with a sense amplifier 290-a. For example, a read signal development portion 410-a-1, a latch signal generation portion 420-a-1, and a rewrite signal development portion 430-a-1 can refer to a read operation of memory cell 105-b-111 (e.g., of domain 310-a-1 associated with signal development component 250-a-1). For example, a read signal development portion 410-a-2, a latch signal generation portion 420-a-2, and a rewrite signal development portion 430-a-2 can refer to a read operation of memory cell 105-b-211 (e.g., of domain 310-a-2 (not shown) that can be associated with signal development component 250-a-2). For example, the read signal development portion 410-a-3, the latch signal generation portion 420-a-3, and the rewrite signal development portion 430-a-3 can refer to a read operation of the memory cell 105-b-311 (e.g., of the domain 310-a-3 (not shown) that can be associated with the signal development component 250-a-3). For example, the read signal development portion 410-a-4, the latch signal generation portion 420-a-4, and the rewrite signal development portion 430-a-4 can refer to a read operation of the memory cell 105-b-411 (e.g., of the domain 310-a-4 (not shown) that can be associated with the signal development component 250-a-4). Each of the signal development components 250-a-1, 250-a-2, 250-a-3, and 250-a-4 can be selectively coupled with the same sense amplifier 290-a via a selection component 280-a (eg, based on a logic select signal SDCM).

[0159] Each of the read signal development portions 410-a may be associated with charge sharing between a corresponding memory cell 105-b, a corresponding digit line 210-a, and a corresponding signal development component 250-a (which may occur during overlapping time intervals). The read signal development portion 410-a may be an example of developing a signal (e.g., a cell read signal, a cache signal, a signal state) at a signal development component 250-a based at least in part on selectively coupling a signal development component 250-a from a plurality of signal development components 250-a with a memory cell 105-b from a plurality of memory cells 105-b. The read signal development portion 410-a-1 may be an instance of coupling (e.g., via selection component 280-a, via selection component 320-a-1) memory cell 105-b-111 (e.g., first memory cell) with signal development component 250-a-1 (e.g., first signal development component) during a first time interval (e.g., and based at least in part on a determination that memory cell 105-b-111 is to be accessed), and the read signal development portion 410-a-2 may be an instance of coupling (e.g., via selection component 280-a, via selection component 320-a-2) memory cell 105-b-211 (e.g., second memory cell) with signal development component 250-a-2 (e.g., second signal development component) during a second time interval overlapping with the first time interval (e.g., and based at least in part on a determination that memory cell 105-b-211 is to be accessed).

[0160] Thus, charge can be shared between memory cell 105-b-1 11 and signal development component 250-a-1, between memory cell 105-b-2 11 and signal development component 250-a-2, between memory cell 105-b-3 11 and signal development component 250-a-3, and between memory cell 105-b-4 11 and signal development component 250-a-4. In other words, charge can be shared via signal development components 250-a-1 through 250-a-4 during overlapping time intervals. In some examples, developing cell reads of signals at signal development components 250-a-1 through 250-a-4 are associated with a first latency (e.g., a relatively high latency or long duration).

[0161] In some instances of the read signal development portion 410-a, shunts 330-a associated with other memory cells 105-b of the corresponding domain 310-a may be selected or activated, which may equalize the bias across the memory cells 105-b that are not being accessed. For example, for domain 310-a-1, during the read signal development portion 410-a-1, the bias between digit line 210-a-12 and plate line 215-a-12 may be equalized via shunt 330-a-12, the bias between digit line 210-a-13 and plate line 215-a-13 may be equalized via shunt 330-a-13, and so on. In FeRAM applications, for example, such bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cell 105-b being accessed during the corresponding read signal development portion 410.

[0162] Latch signal generation portion 420-a may be associated with charge sharing between respective ones of signal development component 250-a-1 and sense amplifier 290-a (which may occur during non-overlapping time intervals). Latch signal generation portion 420-a may each be an example of generating an output signal of sense amplifier 290-a based at least in part on a developed signal at the respective signal development component 250-a (e.g., based on a cell read signal, a cache signal, or a signal state). In some examples, generating the latch signal at sense amplifier 290-a is associated with a second latency (e.g., a relatively low latency or short duration). Transitioning from read signal development portion 410 to corresponding latch signal generation portion 420-a may include selectively coupling the respective signal development component 250-a with sense amplifier 290-a.

[0163] Latch signal generation portion 420-a-1 may be an example of coupling signal development component 250-a-1 (e.g., first signal development component) to sense amplifier 290-a (e.g., via selection component 280-a) during a third time interval following the first time interval. In some examples, the third time interval may at least partially overlap with the second time interval, or the third time interval may be within the second time interval. Latch signal generation portion 420-a-2 may be an example of coupling signal development component 250-a-2 (e.g., second signal development component) to sense amplifier 290-a (e.g., via selection component 280-a) during a fourth time interval following the second time interval (e.g., and following the third time interval).

[0164] Latch signal generation portions 420-a-1 through 420-a-4 may be executed according to a sequence that may be based, at least in part, on a sequence of signal development components selected or otherwise indicated by logic select signal SDCM. In some examples, each of latch signal generation portions 420-a may be separated by a gap or delay period (e.g., the period between latch signal generation portion 420-a-1 and latch signal generation portion 420-a-2), which may be associated with a gap or delay in selecting component 280-a, a gap or delay associated with changing the value of logic select signal SDCM, or a period during which no signal development component 250-a is coupled to sense amplifier 290-a. In other words, an access operation may include a gap or delay period between when one signal development component 250-a is selectively decoupled from sense amplifier 290-a and when another signal development component 250-a is selectively coupled to sense amplifier 290-a. In other examples, this decoupling and coupling may be configured to occur simultaneously.

[0165] In some examples, the latch signal generation portion 420-a may include "activating" the sense amplifier 290-a, which may include selectively coupling one or more voltage sources (e.g., a low voltage source 293, a high voltage source 294) to the sense amplifier 290-a. Thus, according to the sequence of latch signal generation portions 420-a-1 through 420-a-4, a sequence of output signals may be generated at the sense amplifier 290-a that is based at least in part on a corresponding cell read signal sequence (e.g., based at least in part on the logic states stored by the accessed memory cells 105-b-111 through 105-b-411 according to the sequence or read signal generation portions 410-a-1 through 410-a-4).

[0166] The output signal can be passed from the sense amplifier 290-a to another component of the memory device (e.g., the input / output component 160) via the I / O line 295 to provide an indication of the data stored by the memory cell 105-b. In some examples, the output signal or some other signal associated with the generated latch signal can also be passed back to the signal development components 250-a-1 through 250-a-4 or otherwise shared with the signal development components 250-a-1 through 250-a-4, which in some examples can support an overwrite operation (e.g., after a destructive read operation). For example, as part of the latch signal generation portion 420, based on the generated latch signal or output signal (e.g., based on whether the memory cell 105-b stores a logic 0 or a logic 1), an overwrite signal can be passed or otherwise shared with a corresponding one of the signal development components 250-a-1 through 250-a-4.

[0167] In some instances of the latch signal generation portion 420-a, shunts 330-a associated with other memory cells 105-b of the corresponding domain 310-a may be selected or activated, which may equalize the bias across the memory cells 105-b that are not being accessed. For example, for domain 310-a-1, during the latch signal generation portion 420-a-1, the bias between digit line 210-a-12 and plate line 215-a-12 may be equalized via shunt 330-a-12, the bias between digit line 210-a-13 and plate line 215-a-13 may be equalized via shunt 330-a-13, and so on. In FeRAM applications, for example, such bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cell 105-b being accessed during the corresponding latch signal generation portion 420.

[0168] The rewrite signal development portion 430-a can be associated with charge sharing between a corresponding one of the memory cells 105-b, a corresponding one of the digit lines 210-a, and a corresponding one of the signal development components 250-a. The rewrite signal development portions 430-a can each be an example of developing a cell access signal (e.g., a cell write signal, a cell rewrite signal) at the signal development component 250-a based at least in part on a latched signal of the sense amplifier 290-a, or can be independent of the latched signal of the sense amplifier 290-a. In some examples, developing the rewrite signal at the signal development component 250-a-1 is associated with a third latency (e.g., a relatively high latency or a long duration), which may or may not be equal to the first latency. Transitioning from the latched signal generation portion 420-a to the corresponding rewrite signal development portion 430-a can include selectively isolating the corresponding signal development component 250-a from the sense amplifier 290-a (e.g., via the selection component 280-a or another isolation switch component). Although the rewrite signal development portion 430-a can support rewriting a logic state to a memory cell 105 that has been discharged, depolarized, or otherwise damaged or degraded during a read operation, in instances of non-destructive read operations, the rewrite signal development portion 430-a can be omitted (e.g., associated with charge sharing between the signal development component and the memory cell).

[0169] In some instances of the rewrite signal development portion 430-a, shunts 330-a associated with other memory cells 105-b of the corresponding domain 310-a may be selected or activated, which may equalize biases across memory cells 105-b that are not being accessed. For example, for domain 310-a-1, during the rewrite signal development portion 430-a-1, the bias between digit line 210-a-12 and plate line 215-a-12 may be equalized via shunt 330-a-12, the bias between digit line 210-a-13 and plate line 215-a-13 may be equalized via shunt 330-a-13, and so on. This bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cell 105-b being accessed during the rewrite signal development portion 430-a.

[0170] Like the read operation 400, the read operation 450 may also be performed with a total duration t A1 -t A0 1. The read operation of a single memory cell 105 of FIG. 10 may include a read signal development portion 410-a-1, a latch signal generation portion 420-a-1, and a rewrite signal development portion 430-a-1 for reading a single memory cell 105-b-111. However, by employing multiplexed signal development as disclosed herein, performing multiple read operations via the same sense amplifier 290-a may not take the duration t. A1 -t A0 An integer multiple of t (e.g., where the integer multiple may correspond to the number of memory cells 105-b accessed in parallel). Specifically, by generating cell access signals (e.g., cache signals, signal states) in overlapping time intervals (e.g., time intervals of the read signal development portion 410-a or the rewrite signal development portion 430-a of the signal development component 250-a-1 that overlap with time intervals of the read signal development portion 410-a or the rewrite signal development portion 430-a of the signal development component 250-a-2, etc.), multiple memory cells 105-b can be read in a time shorter than this integer multiple. In other words, according to the described techniques for multiplexed signal development, the sense amplifier 290-a can support reading at t A3 -t A2 Four memory cells 105-b are read within a duration of t, which may be shorter than 4*(t A1 -t A0 ) (e.g., shorter than a corresponding integer multiple of the duration used to read a single memory cell 105-b).

[0171] In one example, the rewrite signal development portions 430-a-1, 430-a-2, 430-a-3, and 430-a-4 of a first set of reads may be followed by the read signal development portions 410-a-5, 410-a-6, 410-a-7, and 410-a-8 of a second set of reads, respectively. The first set of reads may be associated with a first digit line index (e.g., a value of "1," as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4), and the second set of reads may be associated with a second digit line index (e.g., a value of "2," as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4). Alternatively, more generally, the first and second sets of reads may differ based, at least in part, on the selected digit line 210-a for the read operation.

[0172] In some examples (e.g., where selection components 320-a across domains 310-a are independently controllable, where logic select signals DLM across domains 310-a are independently controllable), as soon as rewriting signal development portion 430 is completed for signal development component 250, a new digit line 210-a can be selected (e.g., via selection component 320-a) for the same signal development component 250. In other words, as illustrated in the example of read operation 450, for signal development components 250-a multiplexed with the same sense amplifier 290-a, the rewrite signal development portion 430-a for a first set of reads can overlap in time with the read signal development portion 410-a for a second set of reads (e.g., read signal development portion 410-a-5 overlaps with rewrite signal development portion 430-a-4). Thus, in the example of a read operation 450 where domains 310-a-1 through 310-a-4 are independently controllable, the periodicity for reading four memory cells 105 may be determined by the time t A3 -t A2 Graphical description, time t A3 -t A2 In some instances, it may be equal to or nearly equal to time t A1 -t A0 , or t A1 -t A0 plus some delay or gap period (e.g., associated with selecting the new digit line 210-a via the selection component 320-a), or some other duration based on the overall duration associated with the read operation (e.g., t A1 -t A0 ), the corresponding waiting times of the sub-operations (for example, the relative durations of the read signal development part 410, the latch signal generation part 420, and the rewrite signal development part 430) and the degree of multiplexing (for example, the number of signal development components 250-a multiplexed with the sense amplifier 290-a).

[0173] In some examples, a subsequent read may be performed on a memory cell 105-b that is coupled to a different digit line 210-a than the previous read operation but to the same activated word line 205-a (which may reduce latency). For example, maintaining the selected word line 205-a may eliminate a word line deselection operation and a subsequent word line selection operation. Such an example may be accompanied by shunting the digit line 210-a associated with the earlier read operation (e.g., the digit line 210-a that was not previously shunted) and not shunting the digit line 210-a associated with the later read operation (e.g., the digit line 210-a that was shunted during the earlier write operation).

[0174] In another example not shown, a set of reads may be associated with a first common word line (eg, where logical word lines WL 11 、WL 21 、WL 31 and WL 41 ), and the second set of reads may be associated with a second common word line (eg, where the logical word lines WL are simultaneously activated). 12 、WL 22 、WL 32 and WL 42 ). Alternatively, more generally, the first set of reads and the second set of reads may differ based at least in part on the selected common word line 205-a for the read operations. In some instances (e.g., where word lines 205-a across domains 310-a are not independently controllable), a new word line 205-a may be selected upon completion of the latch signal generation portion 420 or upon completion of the rewrite signal development portion 430 for all multiplexed signal development components 250-a (e.g., associated with sense amplifiers 290-a or other groups of domains 310-a that are not independently controllable). In other words, in some instances, for signal development components multiplexed with the same sense amplifier 290-a, the latch signal generation portion 420 or the rewrite signal development portion 430 of the first set of reads may not overlap in time with the read signal development portion 410 of the second set of reads.

[0175] For example, when the word line 205-a spanning domains 310-a-1 through 310-a-4 is not independently controllable, the read signal development portion 410-a-5 may follow or otherwise follow the rewrite signal development portion 430-a-4. Thus, in instances where the domains 310-a are not independently controllable, the periodicity for reading four memory cells 105 may be equal to or nearly equal to the combined time of one read signal development portion 410-a, each of the latch signal generation portions 420-a-1 through 420-a-4 of the multiplexing signal development components 250-a-1 through 250-a-4, and one rewrite signal development portion 430-a, plus any associated delay or gap period (e.g., associated with selecting a new word line 205-a via the selection component 280-a or selecting the new signal development component 250-a). Thus, in some examples where domains 310-a are not independently controllable, this periodicity can be compared to the time t A2 -t A0 The periodicity of the illustrations is long.

[0176] Thus, according to various examples as disclosed herein, the advantages provided by the described signal development multiplexing (e.g., reduced latency when accessing multiple memory cells 105-b in parallel) can scale with the relative latency differences (e.g., durations) of the read signal development portion 410, the latch signal generation portion 420, and the rewrite signal development portion 430. The advantages provided by the described signal development multiplexing can also depend on whether the domains 310-a are configured to be independently controllable or to be controlled via a common access line or common logic signal.

[0177] Although the techniques of read operation 450 are described with reference to a single sense amplifier 290-a, the techniques of read operation 450 may be repeated for each sense amplifier 290 of the sense amplifier array, including various operations being performed concurrently (e.g., in parallel with simultaneous or offset initiation or triggering) to support further pipelining of read operations in memory device 100. For example, read operation 450 or another read operation performed concurrently or offset with read operation 450 may include a signal development operation including read signal development portions 410-b-1, 410-b-2, 410-b-3, and 410-b-4 (not shown) associated with different sense amplifiers 290 (e.g., of the same sense amplifier array). In some examples, read signal development portion 410-b-1 may be initiated simultaneously with read signal development portion 410-a-1 or otherwise performed concurrently or offset (e.g., according to simultaneous access of multiple memory cells of a row, field, or sub-field, according to concurrent signal exchanges with a cache line). Likewise, read signal development portion 410 - b - 2 may be initiated simultaneously with or otherwise performed concurrently or offset from read signal development portion 410 - a - 2 , and so on.

[0178] Furthermore, read operation 450, or another read operation performed concurrently with read operation 450, may include input / output operations including latch signal generation portions 420-b-1, 420-b-2, 420-b-3, and 420-b-4 (not shown) associated with different sense amplifiers 290 (e.g., of the same sense amplifier array). In some examples, latch signal generation portion 420-b-1 may be initiated simultaneously with latch signal generation portion 420-a-1 or otherwise performed concurrently or offset (e.g., based on simultaneous sensing at the sense amplifier array, based on simultaneous latching at a set of latches of a sense component or I / O component, based on concurrent signal exchanges with a cache line). Similarly, latch signal generation portion 420-b-2 may be initiated simultaneously with latch signal generation portion 420-a-2 or otherwise performed concurrently or offset, and so on. Although described in the context of two parallel reads associated with two different sense amplifiers 290, the described techniques can be applied to any number of parallel reads. For example, to support a 64-bit information transfer scheme, 64 parallel reads can be performed using 64 sense amplifiers 290 according to the examples disclosed herein.

[0179] Figure 5AAn example of a write operation 500 supporting signal development caching in a memory device according to an example as disclosed herein is illustrated. The write operation 500 may illustrate portions (e.g., time intervals) of an access operation associated with generating a latch signal and a cell access signal (e.g., a cell write signal) when accessing a memory cell 105. For example, the write operation 500 may be divided into a latch signal generation portion 510 and a write signal development portion 520 (e.g., a cell write portion). The write operation 500 may employ circuitry supporting multiplexed signal development, such as with reference to FIG. Figure 3 As an illustrative example, write operation 500 is described with reference to writing a logic state to memory cell 105-b-111 of circuit 300, but write operation 500 may illustrate operations that may be performed on any one or more of memory cells 105-b of circuit 300.

[0180] The latch signal generation portion 510 can be associated with charge sharing between the signal development component 250-a-1 and the sense amplifier 290-a. The latch signal generation portion 510 can be an example of generating a latch signal (e.g., a cache signal, a signal state) at the sense amplifier 290-a or the signal development component 250-a-1 based at least in part on a write command or write signal received via the I / O line 295-a (e.g., from the input / output component 160 or the memory controller 170). In some examples, generating the latch signal at the sense amplifier 290-a or the signal development component 250-a-1 is associated with a fourth latency (e.g., a relatively low latency or short duration), which can be the same as or different from the second latency of the latch signal generation portion 420 described with reference to the read operations 400 and 450.

[0181] The latch signal generating portion 510 may include selectively coupling the signal development component 250-a-1 with the sense amplifier 290-a (e.g., at the beginning of the latch signal generating portion 510, or at another time after other operations of the latch signal generating portion 510 (e.g., after receiving a write command or write signal via the I / O line 295-a)). In some examples, selectively coupling the signal development component 250-a-1 with the sense amplifier 290-a may include selection based on a logic select signal SDCM via the selection component 280-a. In some examples, selectively coupling the signal development component 250-a-1 with the sense amplifier 290-a may include selective coupling via some other switching component (e.g., an isolation switching component) between the signal development component 250-a-1 and the sense amplifier 290-a.

[0182] In some examples, the latch signal generation portion 510 may include "activating" the sense amplifier 290-a, which may include selectively coupling one or more voltage sources (e.g., a low voltage source 293, a high voltage source 294) to the sense amplifier 290-a. Thus, a latch signal based at least in part on a write command or write signal (e.g., received via I / O line 295-a) may be generated at the sense amplifier 290-a. The generated latch signal, or some other signal associated with the generated latch signal, may be passed to the signal development component 250-a-1 or otherwise shared with the signal development component 250-a-1 (e.g., storing a cache signal or signal state at a cache element of the signal development component 250-a-1) to support writing of the memory cell 105-b-111. For example, as part of the latch signal generating portion 510, based on the latch signal generated (e.g., based on whether the memory cell 105-b-111 will store logic 0 or logic 1), the signal development component 250-a-1 can be used to pass or otherwise share or generate a write signal (e.g., via the signal development line 255-a-1).

[0183] The write signal development portion 520 can be associated with charge sharing between the memory cell 105-b-111, the digit line 210-a-11, and the signal development component 250-a-1. The write signal development portion 520 can be an example of developing a cell access signal (e.g., a cell write signal) at or using the signal development component 250-a-1 based at least in part on a latch signal from the sense amplifier 290-a. In some examples, developing the write signal at the signal development component 250-a-1 is associated with a fifth latency (e.g., a relatively high latency or long duration), which may or may not be equal to the third latency of the rewrite signal development portion 430 described with reference to the read operations 400 and 450. Transitioning from the latch signal generation portion 510 to the write signal development portion 520 can include selectively decoupling or isolating the signal development component 250-a-1 from the sense amplifier 290-a (e.g., via the selection component 280-a or an isolation switch component).

[0184] In some examples of write operations, the circuit 300 can be configured to couple the memory cell 105-b-111 to a high voltage source (e.g., a high voltage rail, via the signal development component 250-a-1), which can be a direct coupling via pull-up or pull-down circuitry (e.g., a transistor or other switching component of the signal development component 250-a-1). In some examples, the signal development component 250-a-1 can be configured with a capacitor or other charge storage component, and the latch signal generation portion 510 or the write signal development portion 520 can include charging or refreshing the capacitor or other charge storage component with a charge sufficient to rewrite the memory cell 105-b-111 (e.g., during the write signal development portion 520). Thus, in various instances, the signal development component 250-a-1 may write a logic state to the memory cell 105-b-111, which may be performed when the signal development component 250-a-1 is selectively decoupled from the sense amplifier 290-a so that the sense amplifier 290-a is free to support operations with respect to the other signal development component 250-a.

[0185] Charge sharing for writing the signal development portion 520 may also be associated with a delay or latency, referred to as a row precharge delay, that may be involved in writing the logic state to the memory cell 105-b-111 based on the write command. For example, to write a logic 0, the digit line 210-a-11 may be biased to a positive voltage (e.g., 1.5V) and the plate line 215-a-11 may be biased to ground or a negative voltage (e.g., 0V). To write a logic 1, the digit line 210-a-11 may be biased to ground or a negative voltage (e.g., 0V) and the plate line 215-a-11 may be biased to a positive voltage (e.g., 1.5V). The biasing of the digit line 210-a-11 and the plate line 215-a-11 may be based at least in part on the generated latch signal (e.g., before the sense amplifier 290-a and the signal development component 250-a-1 are selectively isolated). For example, during the write signal development portion 520, the signal development component 250-a-1 can bias the digit line 210-a-11 to a positive voltage or a ground voltage based at least in part on a latch signal (e.g., based at least in part on a write command). At the end of the write signal development portion 520, all digit lines 210-a-11 and all plate lines 215-a of the domain 310-a-1 can be biased at a ground voltage, effectively equalizing the bias of each of the memory cells 105-b across the domain 310-a-11, which can support maintaining the logic state stored by the memory cells 105-b over time.

[0186] In some examples, shunts 330-a associated with other memory cells 105-b of domain 310-a-1, such as shunts 330-a-12 through 330-a-1r, may be selected or activated during the write signal development portion 520. This may equalize bias across unaccessed memory cells 105-b (e.g., equalize bias between digit line 210-a-12 and plate line 215-a-12, equalize bias between digit line 210-a-1r and plate line 215-a-1r, etc.). This bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than memory cell 105-b-111 being written during the write signal development portion 520.

[0187] The write operation 500 may have a total duration t B1 -t B0 105-b-111, includes a latch signal generating portion 510 and a write signal developing portion 520 for writing to a single memory cell 105-b-111. In an example where the write operation 500 does not employ multiplexed signal development techniques (e.g., a sequence of write operations 500 using the same signal development component 250), a subsequent write operation employing the sense amplifier 290-a may follow the write signal developing portion 520. Thus, performing multiple write operations 500 (e.g., writing to multiple memory cells 105-b) using the same signal development component 250 may involve a duration t B1 -t B0 An integer multiple of (e.g., at least 2*(t B1 –t B0 ) to read two memory cells 105-b). However, multiplexing the signal development component 250-a (e.g., via the selection component 280-a) can reduce the amount of time involved in writing to multiple memory cells 105-b by the sense amplifier 290-a.

[0188] Figure 5B Illustrated is an example of a write operation 550 supporting signal development caching in a memory device according to examples as disclosed herein. The write operation 550 may illustrate portions (e.g., time intervals) of an access operation (e.g., a multi-cell access operation) associated with generating latch signals and cell access signals (e.g., cell write signals) when accessing four memory cells 105 (e.g., via four signal development components 250). For example, the write operation 550 may be divided into a latch signal generation portion 510-a and a write signal development portion 520-a for each of a group of memory cells 105-b, which may be referenced to FIG. Figure 5AThe write operation 550 may employ a circuit system that supports multiplexing signal development, such as that described in reference Figure 3 Described circuit 300. Write operation 550 illustrates an example of separating signal development operations from input / output operations, which can increase data throughput in a memory device.

[0189] As an illustrative example, a write operation 550 is described with reference to writing logic states to four memory cells 105-b of four different domains 310-a, wherein each of the different domains is associated with a respective signal development component 250-a that is multiplexed with a sense amplifier 290-a. For example, the latch signal generation portion 510-a-1 and the write signal development portion 520-a-1 can refer to a write operation to the memory cell 105-b-111 (e.g., of the domain 310-a-1 associated with the signal development component 250-a-1). For example, the latch signal generation portion 510-a-2 and the write signal development portion 520-a-2 can refer to a write operation to the memory cell 105-b-211 (e.g., of the domain 310-a-2 (not shown) associated with the signal development component 250-a-2). For example, the latch signal generation portion 510-a-3 and the write signal development portion 520-a-3 can refer to a write operation of the memory cell 105-b-311 (e.g., of the domain 310-a-3 (not shown) associated with the signal development component 250-a-3). For example, the latch signal generation portion 510-a-4 and the write signal development portion 520-a-4 can refer to a write operation of the memory cell 105-b-411 (e.g., of the domain 310-a-4 (not shown) associated with the signal development component 250-a-4). Each of the signal development components 250-a-1, 250-a-2, 250-a-3, and 250-a-4 can be selectively coupled to the same sense amplifier 290-a via the selection component 280-a (e.g., based on the logic select signal SDCM).

[0190] Each of the latch signal generating portions 510-a can be associated with charge sharing between the signal development component 250-a-1 and the corresponding sense amplifier 290-a (which can occur during non-overlapping time intervals). The latch signal generating portions 510-a can each be an example of generating a signal (e.g., a cache signal, a signal state) at the signal development component 250-a based at least in part on selectively coupling the signal development component 250-a with the sense amplifier 290-a (e.g., an amplifier component). In some examples, such a signal can be generated based at least in part on a write command or a write signal. In some examples, generating the latch signal, cache signal, or signal state is associated with a fourth latency (e.g., a relatively low latency or short duration).

[0191] The latch signal generating portion 510-a-1 can be an example of coupling the signal development component 250-a-1 (e.g., a first signal development component) with the sense amplifier 290-a (e.g., an amplifier component) (e.g., via the selection component 280-a) during a first time interval and based at least in part on determining that the memory cell 105-b-111 (e.g., the first memory cell) is to be accessed. The latch signal generating portion 510-a-2 can be an example of coupling the signal development component 250-a-2 (e.g., a second signal development component) with the sense amplifier 290-a (e.g., via the selection component 280-a) during a second time interval subsequent to the first time interval and based at least in part on determining that the memory cell 105-b-211 (e.g., the second memory cell) is to be accessed.

[0192] The latch signal generating portions 510-a-1 through 510-a-4 can be executed according to a sequence that can be based, at least in part, on a memory cell write command or signal sequence (e.g., received via I / O line 295-a). This sequence can also correspond to a sequence selected or otherwise indicated by logic select signal SDCM for signal development component 250-a. In some examples, each of the latch signal generating portions 510-a can be separated by a gap or delay period (e.g., a period between latch signal generating portion 510-a-1 and latch signal generating portion 510-a-2), which can be associated with a gap or delay for selecting component 280-a, a gap or delay associated with changing the value of logic select signal SDCM, or a period during which no signal development component 250-a is coupled to sense amplifier 290-a. In other words, an access operation may include a gap or delay period between when one signal development component 250-a is selectively decoupled from a sense amplifier 290-a and when another signal development component 250-a is selectively coupled to a sense amplifier 290-a. In other examples, this decoupling and coupling may be configured to occur simultaneously.

[0193] In some examples, the latch signal generation portion 510-a may include "activating" the sense amplifier 290-a, which may include selectively coupling one or more voltage sources (e.g., a low voltage source 293, a high voltage source 294) to the sense amplifier 290-a. Thus, according to the sequence of latch signal generation portions 510-a-1 through 510-a-4, a signal sequence based at least in part on the corresponding write command or signal sequence may be generated at the sense amplifier 290-a or the signal development component 250-a.

[0194] As part of or in conjunction with a write operation, one or more signals may be communicated between the sense amplifier 290 and the signal development component 250. For example, the generated latch signal may also be communicated back to or otherwise shared with the signal development components 250-a-1 through 250-a-4 to support the corresponding write operation. For example, as part of the latch signal generation portion 510-a, based on the generated latch signal (e.g., based on whether the memory cell 105-b is to store a logic 0 or a logic 1), the write signal may be communicated or otherwise shared with a respective one of the signal development components 250-a-1 through 250-a-4.

[0195] The write signal development portion 520-a may be associated with charge sharing between a corresponding one of the memory cells 105-b, a corresponding one of the digit lines 210-a, and a corresponding one of the signal development components 250-a. The write signal development portions 520-a may each be an example of developing a cell access signal (e.g., a cell write signal) at the signal development component 250-a based at least in part on a latch signal of the sense amplifier 290-a. Transitioning from the latch signal generation portion 510 to the corresponding write signal development portion 520-a may include selectively isolating the corresponding signal development component 250-a from the sense amplifier 290-a (e.g., via the selection component 280-a or another isolation switch component). The write signal development portion 520-a-1 may be an example of coupling the signal development component 250-a-1 (e.g., the first signal development component) with the memory cell 105-b-111 (e.g., the first memory cell) during a third time interval subsequent to the first time interval. In some examples, the second time interval is within, or at least partially overlaps, the third time interval. Writing the signal development portion 520-a-2 can be an example of coupling the signal development component 250-a-2 (e.g., a second signal development component) with the memory unit 105-b-211 (e.g., a second memory unit) during a fourth time interval following the second time interval that overlaps with the third time interval.

[0196] In some instances of writing a signal development portion 520-a, shunts 330-a associated with other memory cells 105-b of the corresponding domain 310-a may be selected or activated, which may equalize biases across memory cells 105-b that are not being accessed. For example, for domain 310-a-1, during writing a signal development portion 520-a-1, the bias between digit line 210-a-12 and plate line 215-a-12 may be equalized via shunt 330-a-12, the bias between digit line 210-a-13 and plate line 215-a-13 may be equalized via shunt 330-a-13, and so on. This bias equalization may prevent or reduce data loss (e.g., due to charge leakage) in memory cells 105-b other than the memory cell 105-b being accessed during writing a signal development portion 520-a.

[0197] Like the write operation 500, the write operation 550 may also be performed with a total duration t B1 -t B0 105-b- 111. However, by employing multiplexed signal development according to examples disclosed herein, performing multiple write operations via the same sense amplifier 290-a may not take the duration t B1 -t B0 In other words, the sense amplifier 290-a can support multiple access signals at t B2 -t B0 The four memory cells 105-b are written within a duration of t, which may be shorter than 4*(t B1– t B0 ) (e.g., shorter than a corresponding integer multiple of the duration for writing to a single memory cell 105-b).

[0198] In one example, the write signal development portions 520-a-1, 520-a-2, 520-a-3, and 520-a-4 of a first set of writes can be followed by the latch signal generation portions 510-a-5, 510-a-6, 510-a-7, and 510-a-8 of a second set of writes, respectively. The first set of writes can be associated with a first digit line index (e.g., a value of "1," as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4), and the second set of writes can be associated with a second digit line index (e.g., a value of "2," as indicated by logic select signals DLM1, DLM2, DLM3, and DLM4). Alternatively, more generally, the first and second sets of writes can differ based, at least in part, on the selected digit line 210-a for the write operation. In some examples (e.g., where selection components 320-a across domains 310-a are independently controllable, where logic select signals DLM across domains 310-a are independently controllable), as soon as writing the signal development portion 520-a is completed for the signal development component 250, a new digit line 210-a can be selected (e.g., via the selection component 320-a) for the same signal development component 250. In other words, as illustrated in the example of operation 550, for a signal development component 250-a multiplexed with the same sense amplifier 290-a, a first set of written write signal development portions 520-a can overlap in time with a second set of written latch signal generation portions 510-a (e.g., latch signal generation portion 510-a-5 overlaps with write signal development portion 520-a-4). Thus, in the example of operation 550 where domains 310-a-1 through 310-a-4 are independently controllable, the periodicity for writing to the four memory cells 105 may be determined by the time t B2 -t B0 Graphical description, time t B2 -t B0 The total duration associated with the write operation (e.g., t B1 -t B0 ), the corresponding wait times of the sub-operations (e.g., the relative durations of the latch signal generating portion 510-a and the write signal developing portion 520-a), and the degree of multiplexing (e.g., the number of signal developing components 250-a multiplexed with the sense amplifier 290-a).

[0199] In some examples, a subsequent write may be performed on a memory cell 105-b that is coupled to a different digit line 210-a than the previous write operation, but to the same activated word line 205-a (which may reduce latency). For example, maintaining the selected word line 205-a may eliminate a word line deselection operation and a subsequent word line selection operation. Such an example may be achieved by shunting the digit line 210-a associated with the earlier write operation (e.g., the digit line 210-a that was not previously shunted) and not shunting the digit line 210-a associated with the later write operation (e.g., the digit line 210-a that was shunted during the earlier write operation).

[0200] In another example not shown, a set of writes may be associated with a first common word line (eg, where logical word lines WL of different domains are activated simultaneously). 11 、WL 21 、WL 31 and WL 41 ), and the second set of writes may be associated with a second common word line (eg, where logical word lines WL of different domains are activated simultaneously). 12 、WL 22 、WL 32 and WL 42 ). Alternatively, more generally, the first set of writes and the second set of writes may differ based at least in part on the selected common word line 205-a for the write operations. In some examples (e.g., where word lines 205-a across domains 310-a are not independently controllable), a new word line 205-a may be selected as soon as the write signal development portion 520 is completed for all multiplexed signal development components 250-a (e.g., associated with sense amplifiers 290-a or other groups of domains 310-a that are not independently controllable). In other words, in some examples, for signal development components 250 multiplexed with the same sense amplifier 290-a, the write signal development portion 520 of the first set of writes may not overlap in time with the latch signal generation portion 510 of the second set of writes.

[0201] For example, when the word line 205-a spanning domains 310-a-1 through 310-a-4 is not independently controllable, the latch signal generating portion 510-a-5 may follow or otherwise be followed by the write signal developing portion 520-a-4. Thus, in instances where domains 310-a are not independently controllable, the periodicity for writing to the four memory cells 105 may be equal to or nearly equal to the combined time for each of the latch signal generating portions 510-a-1 through 510-a-4 and one of the write signal developing portions 520-a of the multiplexing signal developing components 250-a-1 through 250-a-4. Thus, in some instances where domains 310-a are not independently controllable, this periodicity may be comparable to that indicated by time t B2 -t B0 The periodicity of the illustrations is long.

[0202] Thus, according to various examples as disclosed herein, the advantages provided by the described signal development multiplexing (e.g., reduced latency when accessing multiple memory cells 105-b in parallel) can scale with the relative latency difference (e.g., duration) of the latch signal generating portion 510 and the write signal developing portion 520. The advantages of the described signal development multiplexing can also depend on whether the domains 310-a are configured to be independently controllable or to be controlled via a common access line or common logic signal.

[0203] Although the techniques of write operation 550 are described with reference to a single sense amplifier 290-a, the techniques of write operation 550 may be repeated for each sense amplifier 290 of a sense amplifier array, including various operations being performed concurrently (e.g., in parallel with simultaneous or offset initiation or triggering) to support further pipelining of write operations in memory device 100. For example, write operation 550, or another write operation performed concurrently with write operation 550, may include input / output operations including latch signal generating portions 510-b-1, 510-b-2, 510-b-3, and 510-b-4 (not shown) associated with different sense amplifiers (e.g., of the same sense amplifier array). In some examples, latch signal generation portion 510-b-1 may be initiated simultaneously with latch signal generation portion 510-a-1 or otherwise executed concurrently or offset (e.g., based on simultaneous sensing at a sense amplifier array, based on simultaneous latching at a set of latches of a sensing component or I / O component, based on concurrent signal exchanges with a cache line). Similarly, latch signal generation portion 510-b-2 may be initiated simultaneously with latch signal generation portion 510-a-2 or otherwise executed concurrently or offset, and so on.

[0204] Furthermore, write operation 550, or another write operation performed concurrently or offset with write operation 550, may include a signal development operation including write signal development portions 520-b-1, 520-b-2, 520-b-3, and 520-b-4 (not shown) associated with different sense amplifiers (e.g., of the same sense amplifier array). In some examples, write signal development portion 520-b-1 may be initiated simultaneously with write signal development portion 520-a-1 or otherwise performed concurrently or offset (e.g., based on simultaneous access of multiple memory cells of a row, field, or sub-field, based on concurrent signal exchanges with a cache line). Similarly, write signal development portion 520-b-2 may be initiated simultaneously with write signal development portion 520-a-2 or otherwise performed concurrently or offset, and so on. Although described in the context of two parallel writes associated with two different sense amplifiers 290, the described techniques are applicable to any number of parallel writes. For example, to support a 64-bit information transfer scheme, 64 parallel writes may be performed using 64 sense amplifiers 290 according to examples as disclosed herein.

[0205] Figure 6 Illustrated is an example of a signal development component 250-b supporting signal development caching in a memory device according to examples as disclosed herein. The signal development component 250-b may be a reference Figure 1 5. Signal development component 250-b may be coupled to or between digit line 210-b and signal development line 255-b. Signal development component 250-b may include capacitor 610 (e.g., an integrating capacitor, a storage element, a cache element, a cache storage element) and transistor 620, which may be configured in an amplifier configuration (e.g., as a charge transfer sense amplifier, as a gate-to-cathode amplifier).

[0206] Capacitor 610 may be an example of a signal storage component or charge storage component of signal development component 250-b. In the example of signal development component 250-b, capacitor 610 may be coupled to or between a line of signal development component 250-b (e.g., signal development line 255-b) and a voltage source 615 (e.g., a ground voltage source, a voltage source having a reference voltage for capacitor 610) of signal development component 250-b. Although illustrated as including capacitor 610, according to examples disclosed herein, signal development component 250 may additionally or alternatively include or otherwise employ transistors, diodes, or other components in a particular state that may provide the functionality of a signal storage component or charge storage component in signal development component 250. In some examples, a group of signal development components 250-b may include a group of capacitors 610, which may provide a fast local memory cache (e.g., a signal development cache) in a device that includes a group of signal development components 250-b.

[0207] In some examples, a memory device including a signal development component 250 - b may include a memory cell 105 that employs a logic storage element that includes a capacitive element (e.g., a linear capacitor in a DRAM application, a ferroelectric capacitor in a FeRAM application). In various examples, the capacitor 610 may include the same capacitive element or technology as the logic storage element (e.g., the capacitor 610 may be a linear capacitor in a DRAM application, the capacitor 610 may be a ferroelectric capacitor in a FeRAM application), or a different capacitive element or technology than the logic storage element (e.g., the capacitor 610 may be a linear capacitor in a FeRAM application, a PCM application, or a chalcogenide memory application).

[0208] Transistor 620 may be an example of an amplifier or voltage regulator of signal development component 250-b and may be configured to transfer charge between signal development line 255-b and digit line 210-b based at least in part on one or both of a voltage of signal development line 255-b (e.g., a first access line) and a voltage of digit line 210-b (e.g., a second access line). For example, a gate node of transistor 620 may be coupled to a voltage source 625, and charge may be transferred across the transistor based at least in part on a relationship between a voltage of voltage source 625 (e.g., V2) and the voltage of digit line 210-b. In various examples, transistor 620 may be associated with one or more digit lines 210 (e.g., multiplexed digit lines 210) and may be located outside the illustrative boundaries of signal development component 250-b (e.g., in an example of a memory device that includes transistor 620 for each of a set of multiplexed digit lines 210).

[0209] Transistor 620 can provide signal conversion between digit line 210-b and signal development line 255-b. For example, transistor 620 can permit charge flow (e.g., current) from signal development line 255-b (e.g., from capacitor 610) to digit line 210-b immediately after the voltage of digit line 210-b decreases (e.g., after selecting memory cell 105 via selection component 320, selecting digit line 210), as fed or enabled by voltage source 625. A relatively small charge flow to digit line 210-b can be associated with a relatively small voltage change of signal development line 255-b, whereas a relatively large charge flow to digit line 210-b can be associated with a relatively large voltage change of signal development line 255-b. Depending on the net capacitance of signal development line 255-b (e.g., including capacitor 610), for example, signal development line 255-b can experience a relatively small voltage change or a relatively large voltage change depending on the charge flow across transistor 620 after selecting memory cell 105. In some examples, transistor 620 or signal development component 250-b can be isolated from digit line 210-b by a switch component or a selection component, such as selection component 320. Transistor 620 can also be referred to as a "voltage regulator" or "biasing component" depending on how transistor 620 regulates charge flow in response to the voltage of digit line 210-b.

[0210] In some examples, signal development component 250-b can include circuitry configured to support selective coupling (e.g., of signal development line 255-b) to a relatively high voltage (e.g., voltage source 635). For example, signal development component 250-b can include switch component 630 operable based on logic signal SW1. In some examples, voltage source 645 can be coupled to a relatively high voltage rail or supply, which can support charging capacitor 610 (e.g., for development cell access signals).

[0211] In some examples, signal development component 250-b may include circuitry configured to support selective coupling (e.g., of digital line 210-b) to a reference voltage (e.g., voltage source 645). For example, signal development component 250-b may include switch component 640 operable based on logic signal SW2. In some examples, voltage source 645 may be coupled to a ground or virtual ground rail or supply. In some examples, voltage source 645 may be coupled to the same rail or supply as voltage source 615 (e.g., V1 may be equal to V4).

[0212] In some examples, signal development component 250-b may include circuitry configured to support selective coupling (e.g., signal development line 255-b, signal development component 250-b) with another component (e.g., selection component 280, sense amplifier 290). For example, signal development component 250-b may include switch component 650, which may be referred to as an isolation switch component and may be operable based on logic signal ISO. Additionally or alternatively, according to examples disclosed herein, the isolation switch component may be included in sense amplifier 290.

[0213] Figure 7 Illustrated is an example of a sense amplifier 290-b supporting signal development caching in a memory device according to examples as disclosed herein. The sense amplifier 290-b may be a reference Figure 1 5. Sense amplifier 290-b may be coupled to or between signal line 285-b and reference line 275-b. Sense amplifier 290-b may also be associated with (e.g., coupled to) I / O lines 295-b and 295-c. In some examples, sense amplifier 290-b may be referred to as an amplifier component of a memory device.

[0214] Sense amplifier 290-b may include a pair of opposing amplifiers 710-a and 710-b. Although illustrated as amplifiers, sense amplifier 290-b may alternatively or equivalently include pairs of cross-coupled transistors (e.g., a pair of cross-coupled p-type transistors and a pair of cross-coupled n-type transistors).

[0215] In some examples, sense amplifier 290-b can include circuitry configured to support selective coupling (e.g., of opposing amplifiers 710-a and 710-b) with sense amplifier low and high voltage sources (e.g., voltage sources 293-b and 294-b). For example, sense amplifier 290-b can include switching components 730-a and 730-b that are operable based on logic signals SW3 and SW4, respectively. In some examples, activating or selecting logic signals SW3 and SW4 can be referred to as activating or latching sense amplifier 290-b.

[0216] In some examples, sense amplifier 290-b can include circuitry configured to support selective coupling or decoupling with another component, such as signal development component 250, selection component 280, or reference component 270. For example, sense amplifier 290-b can include switch components 720-a and 720-b, which can be referred to as isolation switch components and can be operable based on logic signals ISO1 and ISO2. Additionally or alternatively, according to examples disclosed herein, the isolation switch components can be included in signal development component 250 or selection component 280.

[0217] In some instances (e.g., supporting a read operation), sense amplifier 290-b may generate an output signal based at least in part on a cell read signal. For example, signal development component 250 (e.g., a selected one of a set of signal development components 250) may pass a cell access signal via signal line 285-b or otherwise share a charge based at least in part on the cell access signal with sense amplifier 290-b. Reference component 270 may pass a reference signal via reference line 275-b or otherwise share a charge based at least in part on the reference signal with sense amplifier 290-b. When signal line 285-b has a higher voltage than reference line 275-b, a signal amplifier having a relatively higher voltage (e.g., V H ) and an I / O line 295-b having a relatively low voltage (e.g., V L ) generates an output signal through the I / O line 295-c. When the reference line 275-b has a higher voltage than the signal line 285-b, a signal having a relatively higher voltage (e.g., V H ) and an I / O line 295-c having a relatively low voltage (eg, V L ) generates an output signal on I / O line 295-b. In some examples, switch components 720-a and 720-b can be closed to receive a cell read signal or a cell reference signal, and then opened when sense amplifier 290-b is activated (e.g., "latched").

[0218] In some examples, the generated sense or latch signal or otherwise generated output signal can be shared or otherwise associated with a write signal or rewrite signal passed to the selected signal development component 250 via signal line 285-b (e.g., after closing switch component 720-a). In some examples, a write command or write signal can be received at sense amplifier 290-b (e.g., from input / output component 160 via I / O lines 295-b and 295-c), and the received write command or write signal can be latched, shared (e.g., via signal line 285-b), or otherwise associated with the cell write signal generated by the selected signal development component 250. In some examples, the write command or write signal associated with sense amplifier 290-b can bypass signal development component 250 (e.g., via bypass line 260).

[0219] Figure 8A A block diagram of a system 800 supporting signal development caching according to examples disclosed herein is shown. System 800 may include a memory array 805, a selection component 815, an array of signal development components 825, a selection component 835, and a sense amplifier array 845. In some examples, these and other components may be included in a data path 860 of system 800.

[0220] The memory array 805 may include a set of memory cells 105 that may be associated with, for example, a reference Figures 1 to 3 205, digit lines 210, plate lines 215). Memory array 805 may be associated with access lines such as those described (e.g., word lines 205, digit lines 210, plate lines 215). In some examples, a memory array may be associated with A rows (e.g., A independently accessible word lines 205) and B columns (e.g., B independently accessible digit lines 210). In one example, memory array 805 may be associated with 1,048,576 memory cells 105 arranged according to 1,024 word lines 205 and 1,024 digit lines 210. Each of memory cells 105 may be configured to store a respective logic state, which may alternatively be referred to as a memory state.

[0221] In some examples, the memory array 805 can be arranged in a set of domains (which can be similar to the reference Figure 3 310). In one example, the memory array 805 can be split among four domains, and each of the four domains can have four independent zones with plate control (e.g., each domain of the memory array 805 can have four zones with common or individually biased plate lines 215, which can be examples of sub-domains). In such an example, the memory array 805 can be arranged according to 16 control zones, which can be associated with selecting 64 bits of data.

[0222] The signal development component array 825 may include a set of signal development components 250, which may include reference Figures 2 to 7 Aspects of the signal development component 250 described herein. The signal development component array 825 or its components (e.g., cache elements of the signal development component array 825) can be an example of a signal development cache according to examples as disclosed herein. In some examples, the signal development components 250 or cache elements of the signal development component array 825 can be arranged in a grid having C columns and D rows. In some examples, each of the D rows can be associated with a cache block, and each of the C columns can be associated with a location in a respective cache block. In one example, the signal development component array 825 can be associated with eight cache blocks, each having 64 locations. Each of the locations in each of the cache blocks can correspond to a single signal development component 250 or a cache element of the signal development component 250.

[0223] The selection component 815 may include various components that support mapping the memory cells 105 of the memory array 805 with the signal development components 250 of the signal development component array 825. For example, the selection component 815 may provide for selective coupling and decoupling of individual digit lines 210 of the memory array 805 with individual signal development components 250 of the signal development component array 825 to support the various examples of multiplexed signal development described herein.

[0224] The selection component 815 can be coupled to the memory array 805 via a bus 810 having N signal paths, and the selection component 815 can be coupled to the signal development component array 825 via a bus 820 having M signal paths. In some examples, the selection component 815 can be coupled to each of the digit lines 210 of the memory array 805 (e.g., where N=B). In some examples, the bus 820 can have fewer signal paths than the bus 810, where M is associated with the size of the cache block of the signal development component array (e.g., the number of storage elements per cache line of the cache block). For example, the bus 810 can have N=1,024 signal paths, and the bus 820 can have M=64 signal paths, or some other number of signal paths.

[0225] In various examples, each digit line 210 of the memory array 805 can be configured for selective coupling with a specific one of the signal development components 250 of the signal development component array 825, a specific set of signal development components 250 of the signal development component array 825, or can be configured for selective coupling with any one of the signal development components 250 of the signal development component array. Additionally or alternatively, the signal development components 250 of the signal development component array 825 can be configured for selective coupling with a specific one of the digit lines 210 of the memory array 805, a specific set of digit lines 210 of the memory array, or can be configured for selective coupling with any one of the digit lines 210 of the memory array 805. In other words, the mapping between digit lines 210 and signal development components 250 in accordance with the described techniques can include a one-to-many mapping, a many-to-one mapping, or a many-to-many mapping.

[0226] The sense amplifier array 845 may include a set of sense amplifiers 290, which may include reference Figures 2 to 7 8. Aspects of the sense amplifiers 290 are described. In some examples, the sense amplifiers of the sense amplifier array 845 can be arranged in stripes or other grouped arrangements. A selection component 835 can be coupled between the signal development component array 825 (e.g., via bus 830) and the sense amplifier array 845 (e.g., via bus 840) to support various mappings between the signal development components 250 and the sense amplifiers 290. In various examples, the sense amplifiers 290 (e.g., of the sense amplifier array 845) can be integrated between cache blocks (e.g., of the signal development component array 825) or can be external to the signal development component cache area (e.g., external to the signal development component array 825). In some examples, the sense amplifier array 845 can be coupled to a bus 850, which can support information transfer using I / O components (not shown) that can be considered to be within or outside the illustrative boundaries of the data path 860.

[0227] In some examples, signal development component array 825 may be coupled to a stripe or other grouping of sense amplifiers 290 (e.g., of sense amplifier array 845), each of which may also be independently accessible. For example, each sense amplifier in a stripe of sense amplifiers 290 may be configured for selective coupling with a particular one of signal development components 250 of signal development component array 825, a particular group of signal development components 250 of signal development component array 825, or may be configured for selective coupling with any one of signal development components 250 of the signal development component array. Additionally or alternatively, signal development components 250 of signal development component array 825 may be configured for selective coupling with a particular one of sense amplifiers 290 of a stripe of sense amplifiers, a particular group of sense amplifiers of a stripe of sense amplifiers, or may be configured for selective coupling with any one of sense amplifiers 290 of a stripe of sense amplifiers. In other words, the mapping between signal development components 250 of signal development component array 825 and sense amplifiers 290 of sense amplifier array 845 (eg, via selection component 835 ) in accordance with the described techniques may include a one-to-many mapping, a many-to-one mapping, or a many-to-many mapping.

[0228] In an illustrative example in which the memory array 805 is associated with 1,024 digit lines 210, each of the 1,024 digit lines 210 can be coupled to a multiplexer (e.g., of the selection component 815), where the digit lines can be reduced to 64×4=256 digit lines. This can support signal transfers of four groups of 64 digit lines that overlap in time (e.g., participating in simultaneous transfers between the memory cells 105 and the signal development component 250). In some examples, each of these four groups can be routed to any of eight cache blocks (e.g., of the signal development component array 825), where each cache block can include 8 lines times 64 bits. In other words, the total cache size associated with this signal development component array 825 can be 64×64 bits. According to this example of array routing, any 64-bit sub-row from the memory array can be routed to any of the 64-bit signal development component cache lines.

[0229] In another illustrative example, system 800 may include several domains (e.g., of memory array 805), each of which has 1,048,576 memory cells 105 arranged into 1,024 uniquely addressable rows and 1,024 columns. Each of the domains of system 800 can be mapped (e.g., via selection component 815) with 64 signal development components (e.g., of signal development component array 825). In other words, 64 signal development components can be mapped to 1,024 digital lines 210 within each domain. In some examples, a particular signal development component 250 can be mapped to 16 digital lines 210 within each domain (e.g., 1,024 digital lines 210 divided by 64 signal development components 250). In some examples, this mapping can be fixed (e.g., where a group of 16 digital lines 210 is mapped to a respective signal development component 250 within each domain), which can reduce multiplexing or selection circuit complexity in some examples. In various other examples, the signal development component 250 can be mapped to more than one domain, more than one group of digital lines 210 (e.g., of a domain), or other configurations. Additionally or alternatively, a domain or group of digital lines 210 can be mapped to more than one signal development component 250. In other words, a memory device can include various configurations of the signal development component 250 to support the examples of multiplexed signal development described herein.

[0230] In this illustrative example, a row of 1,024 memory cells 105 (e.g., spanning one domain 310) can be selected by a single word line 205 in each domain. With 64 signal development components 250 per domain, 64 memory cells in a group of 1,024 memory cells 105 can be accessed at a time in each domain (e.g., by selectively coupling a respective digit line 210 with each of the 64 signal development components 250-a via a selection component 815). During this access, other digit lines 210 can be selectively isolated from the signal development components 250 interfacing the same domain. Furthermore, other digit lines 210 can be shunted or shielded from other digit lines 210, as described herein.

[0231] In some examples, the operation of one or more components of system 800 may be controlled by a memory controller, such as memory controller 870. Memory controller 870 may be a memory controller such as a memory controller 870. Figure 1170 are described or otherwise associated with performing operations of the memory controller 170. The memory controller 870 may illustrate a controller or other circuitry configured to control various components or operations of the system 800. For example, the system 800 may include various components or circuitry of the data path 860, which may include the memory array 805, the selection component 815, the signal development component array 825, the selection component 835, and the sense amplifier array 845, as well as other components along the information transmission path in the system 800 (e.g., the row components 125, the column components 135, the board components 145, the I / O components 160, and other components). In various examples, the memory controller 870 may communicate with any one or more of the components of the data path 860 to control the associated components or operations.

[0232] The memory controller 870 can be configured (e.g., by one or more commands received from a host device) to perform one or more write operations, read operations, eviction operations, or bypass operations, among other examples of memory operations for the system 800. In various examples of such operations, the memory controller 870 can be configured to transfer data between one or more portions of the memory array 805, one or more portions of the signal development component array 825 (e.g., cache blocks of the signal development component array 825), or one or more portions of the sense amplifier array 845 in accordance with the one or more memory operations.

[0233] In some examples, the memory controller 870 can be configured to perform a read operation, which can include transferring data from the signal development component array 825 to the sense amplifier array 845 (e.g., when the requested data is stored in the signal development component array 825). In some examples, the memory controller 870 can be configured to transfer data from the memory array 805 to the signal development component array 825 (e.g., when the requested data is not present in the signal development component array 825). Additionally or alternatively, the memory controller 870 can be configured to perform an eviction operation. An eviction operation can include transferring data stored in the signal development component array 825 to the memory array 805 before transferring other data (e.g., data associated with the read operation) from the memory array 805 to the signal development component array 825. In some examples, the memory controller 870 can be configured to perform cache bypass operations, which can include transferring data from the memory array 805 directly to the sense amplifier array 845, which can facilitate streaming read operations (e.g., performing multiple read operations in parallel), as an example.

[0234] In some examples, the memory controller may be configured to perform a write-back operation, which may include transferring data from the sense amplifier array 845 to the signal development component array 825 (e.g., after performing a read operation). Additionally or alternatively, the memory controller 870 may be configured to perform a write-through operation. A write-through operation may include transferring data from the sense amplifier array 845 directly to the memory array 805 in accordance with a write command based on a determination that the data is stored at the signal development component array 825. In some examples, the memory controller 870 may be configured to perform a bypass operation. For example, a bypass operation may include transferring data from the sense amplifier array 845 directly to the memory array 805 in accordance with a write command based on a determination that the data is not stored in the signal development cache. Such examples of bypass operations may facilitate streaming write operations (e.g., performing multiple write operations in parallel). In some cases, one or more of the write operations described herein may include an eviction operation. For example, the memory controller 870 may transfer data stored in the signal development component array 825 to the memory array 805 based on determining that data corresponding to a write command (eg, a write back command) is not currently stored in the signal development component array 825 .

[0235] Although Figure 8A The system 800 in the example of FIG is illustrated as a selection component 815 operable to selectively couple the memory array 805 with the signal development component array 825 and a selection component 835 operable to selectively couple the signal development component array 825 with the sense amplifier array 845, but other configurations for supporting the described techniques for memory access are possible. For example, in some cases, the memory array 805 can be selectively coupled to the sense amplifier array 845 in a manner that bypasses the signal development component array 825 or its components. In some examples, the coupling between the memory array 805 and the sense amplifier array 845 can be provided by one or more bypass lines (e.g., reference lines). Figure 2 The bypass line 260) described supports.

[0236] Figure 8B A block diagram of a system 800-a supporting signal development caching according to an example disclosed herein is shown. The system 800-a may include a memory array 805-a, a bus 810-a, a bus 820-a, a signal development component array 825-a, a bus 840-a, a sense amplifier array 845-a, a bus 850-a, and a memory controller 870-a, each of which may be referenced. Figure 8AMemory array 805-a, bus 810-a, bus 820-a, signal development component array 825-a, bus 840-a, and sense amplifier array 845-a may be part of data path 860-a, and memory controller 870-a may be coupled with any one or more of these and other components of data path 860-a to support the techniques disclosed herein.

[0237] In some examples, a system such as system 800-a may include a selection component 875 that is operable to selectively couple the memory array 805-a with the sense amplifier array 845-a (e.g., bypassing the signal development component array 825-a or its components), selectively couple the memory array 805-a with the signal development component array 825-a, or selectively couple the signal development component array 825-a with the sense amplifier array 845-a. In some cases, the selection component 875 may be operable to selectively couple the memory array 805-a, the sense amplifier array 845-a, and the signal development component array 825-a concurrently with each other. The selection component 875 may thus include or otherwise support the various methods described elsewhere herein and attributed to reference Figure 2 The switch assembly 265 described in reference Figure 2 and 3 The selection component 280 described, reference Figure 3 The selection component 320 described, reference Figure 8A The selection component 815 described or referenced Figure 8A The functionality of one or more of the selection components 835 and other features or functions are described.

[0238] The example of system 800-a may in some cases be referred to as a "T" configuration, in which each of the memory array 805, the signal development component array 825, and the sense amplifier array 845 may be coupled with a common selection component 875 (e.g., a center switch network). In this example, each of the memory array 805-a, the signal development component array 825-a, and the sense amplifier array 845-a may be coupled with the selection component 875 according to the number of signal paths in the respective system components, and the common selection component 875 may be configured or operable to perform the described techniques for signal development caching according to various multiplexing levels or other arrangements with the respective system components.

[0239] More generally, the selection component 875 can include various switching components, selection components, or other circuitry operable to selectively couple any of the memory array 805-a or its components (e.g., a plurality of access lines of the memory array 805-a), the signal development component array 825-a or its components (e.g., cache elements of a signal development cache), or the sense amplifier array 845-a or its components (e.g., a plurality of sense amplifiers 290 of the sense amplifier array 845-a) concurrently with any or both of the other arrays (e.g., all three arrays or their components can be coupled concurrently). The selection component 875 can thereby support various access techniques according to examples as disclosed herein. For example, in some cases, each of the memory array 805-a or its components, the signal development component array 825-a or its components, and the sense amplifier array 845-a or its components may be coupled to each other, and the sense amplifier array 845-a may enhance signals transmitted in either direction between the signal development component array 825-a and the memory array 805-a (for example, to support the writing of logic states from the signal development component array 825-a to the memory array 805-a or to support the writing of logic states from the memory array 805-a to the signal development component array 825-a).

[0240] In some examples, bus 850-a can support information transfer using I / O components (not shown) that can be considered to be within or outside the illustrative boundaries of data path 860. In some cases, bus 850-a can be coupled with selection component 875, as illustrated in the example of system 800-a. In other cases, bus 850-a can be coupled with sense amplifier array 845-a, as illustrated in the example of system 800. In various examples, the operation of selection component 875 can be coordinated (e.g., by memory controller 870-a) to avoid signaling conflicts in data path 860-a, including coordination to avoid or mitigate conflicts that could inadvertently corrupt or degrade information (e.g., logic states, signal states) intended to be maintained at components of data path 860-a.

[0241] In some cases, a system according to the described techniques for signal development caching may be arranged in a "T" configuration, where each of the memory array 805, the signal development component array 825, and the sense amplifier array 845 may be coupled with a common center node (e.g., a common bus node, a center node of each signal path in a set of signal paths of a common bus). Figure 8CA block diagram of a system 800-b supporting signal development caching according to this example is shown. The system 800-b may include a memory array 805-b, a bus 810-b, a bus 820-b, a signal development component array 825-b, a bus 840-b, a sense amplifier array 845-b, a bus 850-b, and a memory controller 870-b, each of which may be referenced. Figure 8A and 8B Memory array 805-b, bus 810-b, bus 820-b, signal development component array 825-b, bus 840-b, and sense amplifier array 845-b may be part of data path 860-b, and memory controller 870-b may be coupled with any one or more of these and other components of data path 860-b to support the techniques disclosed herein.

[0242] Furthermore, system 800-b may include a central node 880. Each of the memory array 805, the signal development component array 825, and the sense amplifier array 845 may be selectively coupled to the central node 880 via a respective selection component 885-a, 885-b, or 885-c. Each respective selection component 885-a, 885-b, 885-c may have a first coupling to the common central node based on the number of signal paths of the common bus and a second coupling to the respective system component (e.g., the memory array 805, the signal development component array 825, or the sense amplifier array 845), a degree of multiplexing with the respective system component, or other arrangements. Thus, although central node 880 is illustrated as a single point, central node 880 may illustrate a common bus connection having a respective common node for each signal path in a set of signal paths coupled to central node 880. In some cases, the central node 880 and the corresponding selection component 885-a, 885-b, or 885-c may include the components of the present invention as referred to in the reference Figure 8B Aspects of the selection component 875 are described together or otherwise support its functionality. In various examples, the operations of the selection components 885-a, 885-b, and 885-c can be coordinated (e.g., by the memory controller 870-b) to avoid conflicts at the central node 880, including coordination to avoid or mitigate conflicts that could inadvertently corrupt or degrade information (e.g., logic states, signal states) intended to be maintained at the components of the data path 860-b.

[0243] Figure 9A block diagram of a system 900 supporting signal development caching according to an example as disclosed herein is shown. The system 900 may include a memory array 805-c, a bus 810-c, a selection component 815-c, a bus 820-c, a signal development component array 825-c, a bus 830-c, a selection component 835-c, a bus 840-c, a sense amplifier array 845-c, and a controller 870-c, each of which may be referenced. Figure 8A 、 8B and examples of corresponding components described in 8C.

[0244] The memory array 805-c can be arranged according to various numbers of memory cells 105, word lines 205, digit lines 210, and plate lines 215 or other plate nodes. In one example, the memory array 805-c can be arranged according to 1,024 word lines (e.g., A=1,024) and 1,024 digit lines (e.g., B=N=1,024), or some other organization of a 1,024×1,024 array of memory cells 105.

[0245] In some examples, the memory array 805-c can be arranged according to the number of domains 310-b, which can each include an equal number of digit lines 210 or columns. For example, the system 900 illustrates an example of a memory array 805-c that includes four domains 310-b (e.g., domains 310-b-1, 310-b-2, 310-b-3, and 310-b-4). In one example, each of the domains 310-b can include 256 digit lines 210. Each of the domains 310-b can have independently controllable word lines 205, and each word line 205 can select or stripe a defined number of sub-rows 908 that may or may not be aligned across the memory array 805-c. For example, in the example of the system 900, one word line 205 can select or stripe four sub-rows 908 (e.g., one sub-row per domain 310-b). In some cases, one or more of the sub-rows 908 of a given word line 205 may be activated while the remaining sub-rows 908 of that word line 205 may not be activated. For example, the sub-rows of domains 310-b-1 and 310-b-3 associated with a given word line 205 may be activated, but the sub-rows of domains 310-b-2 and 310-b-4 may not be activated. In some examples, sub-rows 908 associated with different word lines 205 may be activated concurrently in different domains 310-b. For example, in the example of system 900, sub-rows 908-a and 908-b may be associated with different word lines 205 but may be activated concurrently.

[0246] In some examples, each domain 310-b can be arranged according to a defined number of control zones 907. In the example of system 900, each domain 310-b can include four control zones 907, so that the memory array 805-c can include a total of sixteen control zones 907. It should be understood that all specific numbers included herein are non-limiting examples used merely for clarity in explaining the concepts herein, and the claims are not limited in any way thereby. In an example where a domain 310-b includes 256 digit lines 210, each of the control zones 907 can include (e.g., span) 64 digit lines 210. In some examples, each of the control zones 907 can support independent board control. Independent plate control can refer to the ability of a plate line 215 within a control zone 907 to be activated simultaneously with other plate lines within the control zone 907 (e.g., with the same bias, through the same independently controllable plate node), but independently of the plate lines 215 in other control zones 907. In various examples, each of the control zones 907 can be associated with a common plate or plate node (e.g., common to all memory cells 105 of the control zone), or each of the control zones 907 can be associated with a plate line 215 that can be biased or activated independently of each other.

[0247] In some examples, the word lines 205 can be further striped within the plateline region of the domain 310-b (e.g., each control zone 907) to provide additional access granularity within the domain 310-b. In one example, for two sub-rows 908 within the domain 310-b, a first row of memory cells 105 can be activated for a first set of control zones 907 within the domain 310-b and a second row of memory cells 105 can be activated for a second set of control zones 907 within the domain 310-b. More generally, for a domain 310-b having a set of sub-rows 908 or control zones 907, a row of memory cells 105 can be activated for some or each of a set of sub-rows or control zones 907 in the domain 310-b.

[0248] In some examples, a group of digit lines 210, a group of memory cells 105, or both spanned by a sub-row 908 or control zone 907 can be referred to as a sub-domain. In some examples, partitioning access to domain 310-b into sub-domains can be supported by including multiple contacts from a common driver (e.g., a word line driver) at the top of the word line transistor gates (e.g., relative to the substrate). These contacts can be gated by additional transistors, enabling word line charge to be deposited on the word line transistor gates. In this manner, sub-domains can be created using striped word lines 205 and charge-locked pull-up gate transistors. Sub-domains can provide the functionality of forming bit rows from multiple word lines 205 accessed simultaneously on the same domain 310-b, which can expand access patterns or reduce row buffer contention, among other benefits.

[0249] The memory controller 870-c can support various biasing or activation of word lines in the memory array 805-c. In some examples, the memory controller 870-c can be configured or operable to concurrently couple a word line driver to a first segment of a first word line 205 (e.g., a first sub-row 908) within a given domain 310-b and to a second segment of a second word line 205 (e.g., a second sub-row 908) within a given domain 310-b. In some examples, the memory controller 870-c can be configured or operable to concurrently couple another word line driver to a second segment of a first word line 205 (e.g., a third sub-row 908) within a given domain 310-b and to a first segment of a second word line 205 (e.g., a fourth sub-row 908) within a given domain 310-b.

[0250] In an example of system 900, each digital line 210 of memory array 805-c can be coupled to a selection component 815-c via bus 810-c (e.g., into multiplexer (MUX) 917). In some examples, the digital lines 210 of domain 310-b can be grouped according to corresponding sub-buses 912 of bus 810-c, where each sub-bus 912-a can be associated with a certain number of signal paths. For example, the digital lines of domain 310-b-1 can be coupled via sub-bus 912-a, the digital lines of domain 310-b-2 can be coupled via sub-bus 912-b, the digital lines of domain 310-b-3 can be coupled via sub-bus 912-c, and the digital lines of domain 310-b-4 can be coupled via sub-bus 912-d. An example of system 900 can include four sub-buses 912, and each sub-bus 912 can include 256 signal paths. As such, bus 810 - c may include or otherwise be associated with a total of 1024 digital lines 210 .

[0251] In some examples, each sub-bus 912 can be mapped via MUX 917 to an intermediate sub-bus 919 that can include a different number of signal paths (e.g., where the signal paths of a sub-bus 912 are an integer multiple of the signal paths of the intermediate sub-bus 919). For example, for a 4:1 multiplexing ratio, each sub-bus 912 can include 256 signal paths, and each intermediate sub-bus 919 can include 64 signal paths. In some examples, this multiplexing can include mapping the signal paths of the intermediate sub-bus 919 to the activated or otherwise selected digit lines 210 of a given domain 310-b, and these digitally activated or selected digit lines 210 can be un-shunted (e.g., associated with deactivated shunts 330). In some examples, the remaining digit lines 210 that are not activated or selected can be shunted (e.g., associated with activated shunts 330), which can mitigate charge leakage or other degradation of the logic state stored by non-target memory cells 105. In some cases, the logic state may alternatively be referred to as a memory state. In the example of the system 900 supported by a 4:1 multiplexing ratio (e.g., at MUX 917), four groups of 64 bits may be transmitted simultaneously or concurrently (e.g., overlapping in time) via the bus 810-c and the selection component 815-c, with each group corresponding to a different domain 310-b.

[0252] In the example of system 900, each intermediate sub-bus 919 can be coupled to a MUX 918 (e.g., a routing MUX), which can be part of the selection component 815-c. The MUX 918 can be operable to couple a selected set of digital lines 210 to a corresponding set of storage elements or cache elements in a corresponding cache block 926 of the signal development component array 825-c (e.g., via a corresponding sub-bus 922 of bus 820-c). The example of system 900 can include four sub-buses 922 (e.g., sub-buses 922-a, 922-b, 922-c, and 922-d) between the MUX 918 and the signal development component array 825-c, and each sub-bus 922 can include 64 signal paths. In the example of system 900, any of the illustrated or logical locations of sub-bus 922 can be mapped to any of the illustrated or logical locations of intermediate sub-bus 919. For example, intermediate sub-bus 919-a can be mapped to any of sub-buses 922-a, 922-b, 922-c, or 922-d, etc. Thus, any of the intermediate sub-buses 919 can be mapped to any of the cache blocks 926. In another example, bus 820-c can include a separate sub-bus 922 (not shown) for each of the cache blocks 926, which can be another configuration that supports mapping of any of the intermediate sub-buses 919 to any of the cache blocks 926 (e.g., via MUX 918).

[0253] The signal development component array 825-c can be arranged according to cache blocks 926, each of which can be associated with a number of cache lines that are each coupled to a respective set of storage elements (e.g., cache elements). Each of the storage elements can be configured to maintain a signal state (e.g., a cache signal, a cache state) corresponding to a logic state when the respective storage element is isolated from one or both of the memory array 805-c or the sense amplifier array 845-c. In the example of the system 900, the signal development component array 825-c can include eight cache blocks 926, each of which includes eight cache lines, and each cache line includes 64 cache elements. Thus, the total cache size of the signal development component array 825-c can be 64×64 bits (e.g., 4,096 bits). In some instances, the signal development component array 825-c (e.g., cache memory block 926) may include another selection component, not shown, that is operable to select or activate a target cache memory line of the corresponding cache memory block 926 (e.g., coupling the target cache memory line with the sub-bus 922).

[0254] In some examples, the number of signal paths of a corresponding sub-bus 922 can be equal to the number of storage elements in a cache line or row of signal development component array 825-c. Thus, the number of storage elements coupled to a cache line can be proportional to (e.g., equal to, an integer multiple of) the number of digit lines 210 in a control zone 907 or sub-domain. For example, if a control zone 907 is associated with 64 digit lines 210, then a cache line can be associated with 64n (where n=1, 2, 3, ...) storage elements. In some examples, the number of signal paths of a sub-bus 922 or the number of signal paths of an intermediate sub-bus 919 or the number of storage elements in a cache line can be equal to the number of data bits for a read command or the number of data bits for a write command (e.g., where 64 storage elements in a given cache line or 64 signal paths of a given sub-bus 922 or intermediate sub-bus 919 can correspond to a 64-bit data transfer scheme).

[0255] In various examples, the selection component 815-c can be operable to couple more than one memory cell 105 to a given storage element of the cache block 926, to couple a memory cell 105 to more than one storage element of the cache block 926, or both. For example, where the memory cells 105 of the memory array 805-c are operable to store one of a set of more than two logic states, the selection component 815-c can be operable to selectively couple one of the digit lines 210 of the sub-bus 912 to two or more of the set of storage elements of the cache block 926. In another example, where the storage elements of the cache block 926 are operable to store one of a set of more than two signal states, the selection component 815-c can be operable to selectively couple one of the storage elements of the cache block to two or more digit lines 210 or memory cells 105 of the memory array 805-c.

[0256] In some cases, data may be provided to the requesting device from the signal development component array 825-c. Retrieving data may include outputting data (e.g., information stored as signal states, cache states) from the cache block 926 to the corresponding MUX 932 via a corresponding sub-bus 929 of the bus 830-c. An example of the system 900 may include four sub-buses 929 (e.g., sub-buses 929-a, 929-b, 929-c, and 929-d), each of which may include one information transfer signal path bit (e.g., 64 signal paths for a 64-bit information transfer scheme). The MUX 932 may be operable to select a set of bits or signal states from the cache block 926. In one example, if the cache block is configured to output 64 bits, the MUX 932 may be operable to select eight of the 64 bits for transfer to the sense amplifier sub-array 937. In another example, if the cache block is configured to output 64 bits, then the MUX 932 can be operable to select 64 bits from a specific location of the signal development component array 825-c (e.g., a specific cache block 926 or a cache line thereof). In the example of the system 900, various selection operations can be supported by the selection component 835-c including four MUXs 932 (e.g., MUXs 932-a, 932-b, 932-c, and 932-d). In some examples, the system 900 can multiplex multiple sense amplifier sub-arrays 937 with the signal development component array 825-c to increase device bandwidth.

[0257] In some examples, the MUX 932 can output the selected bits to a corresponding sense amplifier subarray 937 via a corresponding sub-bus 934 of the bus 840-c. An example of the system 900 can include four sub-buses 934 (e.g., sub-buses 934-a, 934-b, 934-c, and 934-d), and each sub-bus 934 can have one signal path per bit (e.g., 8 signal paths for 8 bits, 64 signal paths for 64 bits) that passes between a corresponding MUX 932 and a corresponding sense amplifier subarray 937. The sense amplifier subarrays 937 can each include a set of sense amplifiers 290 operable to compare signaling to one or more reference voltages and provide an indication of an associated logic state. In an example of the system 900, the sense amplifier array can include four sense amplifier subarrays 937-a (e.g., sense amplifier subarrays 937-a-1, 937-a-2, 937-a-3, and 937-a-4). Although the sense amplifier sub-array 937-a of system 900 is depicted as being external to the signal development component array 825-c, in some systems the sense amplifier sub-array 937-a may be integrated between cache memory blocks 926. For example, each of the cache memory blocks 926 may include 64 integrated sense amplifiers to support a 64-bit information transfer scheme.

[0258] In various examples, the selection component 815-c and the selection component 835-c can be configured for or otherwise operate according to different latencies or bandwidths. For example, the selection component 835-c can be configured for signal exchanges between a group of storage elements of the signal development component array 825-c and the sense amplifier array 845-c having a first latency, and the selection component 815-c can be configured for signal exchanges between a group of memory cells and the group of storage elements of the signal development component array 825-c having a second latency that is greater than the first latency (e.g., to account for relatively slower signal development in the memory array 805-c than in the sense amplifier array 845-c).

[0259] One or more of the memory array 805-c, the selection component 815-c, the signal development component array 825-c, the selection component 835-c, and the sense amplifier array 845-c can be coupled to a memory controller 870-c to support various operations of the system 900. In some cases, the memory controller 870-c can include a content addressable memory (CAM) that supports mapping between addresses of the memory array 805-c and the signal development component array 825-c, and this mapping can be used to perform various selective couplings via the selection component 815-c or the selection component 835-c. In some examples, a separate CAM can be coupled to each cache block 926 of the signal development component array 825-c or each MUX 932-d of the selection component 835-c. In some examples, the system 900 can support various associative techniques in which addresses in the signal development component array 825-c can be associated with or mapped to addresses in the memory array 805-c. In some cases, the memory controller 870-c may be configured to manage a refresh procedure to maintain the cache signals stored by the set of storage elements of the signal development component array 825-c.

[0260] In some examples, system 900 can be operated to provide requested data (e.g., in response to a read command). For example, a memory device including system 900 can receive one or more commands (e.g., from a requesting device) to perform a read on a plurality of memory locations of memory array 805-c. In the illustrative example, the memory device can activate subrow 908-a of domain 310-b-1, subrow 908-b of domain 310-b-2, subrow 908-c of domain 310-b-3, and subrow 908-d of domain 310-b-4, which can activate wordline terminals for a first memory location, a second memory location, a third memory location, and a fourth memory location, respectively. The memory device can also activate control zones 907 within each domain 310-b corresponding to the first memory location, the second memory location, the third memory location, and the fourth memory location, which can include activating plateline terminals for these locations. In the example where each control zone 907 is associated with 64 digit lines, 64 digit lines 210 of the 256 total digit lines 210 associated with each sub-bus 912 may be activated. It should be noted that there may be instances where different portions of the word lines, different sub-domains, or various other patterning techniques may be used to activate the digit lines 210.

[0261] Continuing with the illustrative example, MUX 917 may select 64 signal paths for each sub-bus 912 that are activated to reduce the total number of coupled signal paths from 1024 signal paths going to MUX 917 to 256 signal paths output from MUX 917 (e.g., 64 signal paths via intermediate sub-bus 919-a, 64 signal paths via intermediate sub-bus 919-b, 64 signal paths via intermediate sub-bus 919-c, and 64 signal paths via intermediate sub-bus 919-d). The 256 total signal paths may be input to MUX 918, which may route a first group of 64 signal paths to a first sub-bus 922-a, a second group of 64 signal paths to a second sub-bus 922-b, a third group of 64 signal paths to a third sub-bus 922-c, and a fourth group of 64 signal paths to a fourth sub-bus 922-d. It should be noted that the ordering may be different without departing from the scope of the present disclosure.

[0262] Continuing with the illustrative example, the 64 signal paths carried by each of the sub-buses 922-a, 922-b, 922-c, and 922-d may be coupled to a respective cache block 926 (e.g., a respective cache line), wherein the respective cache block may support the signal development described with reference to FIG4 (e.g., according to the read signal development portion 410). Based on this signal development, the storage elements of the respective cache block may store a signal state (e.g., a cache state) associated with the logic state stored by the coupled memory cells 105 of the memory array 805-c.

[0263] After developing or storing the corresponding signals or signal states at the signal development component array 825-c, the corresponding cache memory block 926 can each output 64 signals to sub-buses 929-a, 929-b, 929-c, and 929-d. The 64 signals of each of the sub-buses 929-a, 929-b, 929-c, and 929-d can then be coupled to the sense amplifier array 845-c via the selection component 835-c according to various multiplexing techniques, where the corresponding sense amplifier 290 can sense the logic state based at least in part on the signal provided by the cache memory block 926. The logic state can be latched by the sense amplifier 290 or other latching components. For example, the sense amplifier sub-array 937-a can output the logic state and the data can be read out to the requesting device. If the sense amplifier sub-array 937-a is not integrated with latches, then latches or SRAM cache may be implemented so that the sense amplifiers 290 may be between the signal development component array 825-c and the latches or SRAM cache.

[0264] In some cases, information data may be read directly from signal development component array 825-c. For example, memory array 805-c may not be accessed and select component 815-c may not be operated, but the remaining steps described herein may occur (e.g., if the relevant signal states are stored at signal development component array 825-c before receiving the access command). Additionally or alternatively, MUX 917 may support various operations on the information passed to MUX 917. For example, MUX 917 may shuffle bits according to a pattern or flip bits (e.g., from 0 to 1, from 1 to 0). To enable MUX 917 to perform such operations, MUX 917 may integrate additional signal development components with reactive components (e.g., transistors) or may have capacitive or inductive features that enable charge sharing or charge transfer to maintain its integrity. In such cases, the selection component 815 - c in conjunction with the signal development component array 825 - c may be referred to as a hierarchical signal development component apparatus (eg, partially in MUX 917 or 918 and partially in the signal development component array 825 - c ).

[0265] In some examples, the system 900 can be operated to store data (e.g., in response to a write command). For example, a memory device including the system 900 can receive one or more commands (e.g., from a requesting device) to perform a write to a plurality of memory locations of the memory array 805-c. In an illustrative example, the data can be provided to the sense amplifier subarray 937, where each sense amplifier 290 of the sense amplifier subarray 937 can be configured to receive a target logic state of the write command and generate a write signal based on the target logic state. For example, the sense amplifier subarrays 937-a, 937-b, 937-c, and 937-d can receive different sets of data and can each output 8 bits or 64 bits (e.g., 8 write signals or 64 write signals) to the MUXs 932-a, 932-b, 932-c, and 932-d, respectively, via subbuses 934-a, 934-b, 934-c, and 934-d. MUXes 932-a, 932-b, 932-c, and 932-d may select eight of the 64 signal paths of sub-buses 929-a, 929-b, 929-c, and 929-d, respectively, and may output corresponding signals to the signal paths of each sub-bus 929. Signals provided via the coupled signal paths may be stored in corresponding cache memory blocks 926 (e.g., according to latch signal generation portion 510), and the process may be repeated until a bit has been output from MUXes 932-a, 932-b, 932-c, and 932-d for each of the 64 lines of each sub-bus 929.

[0266] Continuing with the illustrative example, once 64 bits have been stored in a cache block 926 (e.g., a cache line) coupled to one of the sub-buses 929, the respective cache block 926 may output 64 write signals to the respective sub-bus 922. For example, a cache block 926 coupled to sub-bus 929-a may provide 64 write signals via sub-bus 922-a, a cache block 926 coupled to sub-bus 929-b may provide 64 write signals via sub-bus 922-b, a cache block 926 coupled to sub-bus 929-c may provide 64 write signals via sub-bus 922-c, and a cache block 926 coupled to sub-bus 929-d may provide 64 write signals via sub-bus 922-d. Each sub-bus 922 may be routed via MUX 918 to a corresponding intermediate sub-bus 919 and MUX 917, which may couple the signal paths of the intermediate sub-bus 919 with a selected subset of the signal paths of sub-bus 912 (e.g., with a subset of the digital lines 210 of the corresponding domain 310-b).

[0267] In some examples, the 64 digital lines 210 along which each sub-bus 912 outputs 64 bits (e.g., selected by MUX 917) can be associated with corresponding control zones 907 of different domains 310-b. To store the 64 bits in a particular memory location, the sub-row 908 containing the memory cells in which the 64 bits are to be stored can be activated. For example, sub-row 908-a may be activated to store the 64-bit output on sub-bus 912-a in a first memory location (e.g., in a memory cell coupled to sub-row 908-a); sub-row 908-b may be activated to store the 64-bit output on sub-bus 912-b in a second memory location (e.g., in a memory cell coupled to sub-row 908-b); sub-row 908-c may be activated to store the 64-bit output on sub-bus 912-c in a third memory location (e.g., in a memory cell coupled to sub-row 908-c); and sub-row 908-d may be activated to store the 64-bit output on sub-bus 912-d in a fourth memory location (e.g., in a memory cell coupled to sub-row 908-d). In some examples, such operations may be included in write signal generation portion 520.

[0268] In various examples, routing or multiplexing supported by system 900 (e.g., selection component 815-c) may be capable of routing between a 64-bit sub-row from memory array 805-c and one of each potential 64-bit cache line of signal development component array 825-c. Thus, system 900 may be configured (e.g., via CAM, via cache associativity) to provide signal caching with various set associativity depending on the application in which system 900 is used. A cache controller (e.g., memory controller 870-c) that configures system 900 to operate according to this configuration may be microcode driven. Thus, a memory device including system 900 may be capable of performing dynamic changes in associativity when microcode is sent from an operating system (OS) to the controller via control signals.

[0269] The described techniques for signal development caching and multiplexing can support clusters of signal development components 250 (e.g., of signal development component array 825-c) intermixed with a memory array (e.g., memory array 805-c) and can act as an in-memory cache with various associativity settings. For example, row address or tag matching can be used to monitor which rows of memory array 805-c may have information stored (e.g., as signal states, as cache states) in signal development component array 825-c. In some examples, a local CAM can be used to make signal development component array 825-c fully associative. Write-back and write-through strategies or operations (e.g., with or without combining) can be supported and can include one or more reconfigurable options to change them.

[0270] In some instances, the system 900 may support rank-level and chip-level parallelization. For example, multiple chips may have the same timing specifications or operations and may be clocked simultaneously to scale the bandwidth for one or more devices (e.g., DIMMs, attached PCIe). In some cases, simultaneous writes and reads may be performed on the same domain 310 or in a subdomain by activating one set of multiplexed digital lines 210 from a row while precharging another set of digital lines 210 from the same row. In some cases, the two transmitted data paths may be isolated (e.g., due to not toggling the corresponding boards). The latency of the read data path, the write data path, or both may be balanced, which may achieve higher efficiency than if the latency of the read data path, the write data path, or both were not balanced.

[0271] In order to configure the memory device with an optional signal development cache configuration enabled via the BIOS, dynamic bandwidth amplification can be performed via the OS or memory controller (e.g., memory controller 870). For example, dynamic adjustment of the multiplexing rate can occur. In some cases, the signal development component array 825-c can be integrated with the OS page map. For example, the physical page can be at the granularity of a row, which can support integration with the OS page table or distributed hardware-accelerated in-memory page table walks or other operations.

[0272] In some examples, system 900 can support computational operations at signal development component array 825. For example, if values ​​are stored so that they fit within a multiplexed structure, their bit accesses can overlap in time, which can be referred to as pipelined-multiplexed in-memory computation. Subdomain computation using staggered charge-sharing waves can also be supported. Furthermore, using subdomains can provide functionality for staggered activation. For example, activation waves can be directed toward signal development component array 825 so that multiple memory cells 105 can share charge on the same digit line 210, thereby providing analog computation based on charge sharing. This computational wave can be used to perform mathematical operations or other divisions in a wavelike or synchronous manner on digit lines 210 that are encoded by access patterns configured by one or more hierarchical components of system 900 to activate domains 310, subdomains, board lines, or zones. In this computational wave, proximity to sensing logic along the wave can provide a latency gradient for the wave and can help increase computational speed.

[0273] In some examples, a memory page migration system can be supported in which the page cache does not have a backing store but instead has a byte-addressable memory extension. This system can be associated with a value of persistent memory (e.g., persistent FeRAM). Additionally, the expanded capacity can improve the efficiency of relatively slow multi-level cell architectures (e.g., quad-level cell (QLC) architectures) by expanding the page cache size.

[0274] In some instances, the signal development component storage element may not maintain a signal strong enough to write to the memory cell 105, in which case strengthening may be supported. For example, charge pumping of the signal development component 250 may be performed, and the sense amplifier 290 may be used to amplify or generate a write signal to both the signal development component storage element and the memory cell 105.

[0275] In some examples, system 900 can implement a T-connection, wherein the bottom of the T-connection can be coupled to sense amplifier array 845 and the sides of the T-connection can be coupled to memory array 805 and signal development component array 825, respectively. Thus, a tri-state connector can exist, wherein each node of the T-connection is connected to at least one other node, which can support enhanced flexibility for signal enhancement. The T-connection can enable signal enhancement when charge coupling may be insufficient during write operations. The tri-state connection can connect memory array 805 to signal development component array 825, connect the signal development component array to sense amplifier array 845, connect the sense amplifier array 845 to memory array 805, or connect all three arrays together.

[0276] In some cases (e.g., when implementing a write-through cache policy), the signal development component array 825 and the main memory connection can operate on the same physical line by enabling a selection component (e.g., selection component 815, selection component 835), which can support concurrent writing of information to the signal development component array 825 and the memory array 805. In such cases, the information is available in the signal development component array 825 for subsequent reading. However, isolating the main memory connection from the signal development component array 825 can enable streaming writes. This isolation can depend on whether the information to be written to the memory address is also maintained in the signal development component array 825.

[0277] The techniques for signal development caching according to the examples disclosed herein can be supported by various physical configurations of memory devices or components thereof. In some examples, the signal development cache (e.g., cache element array, signal development element array 825) and the memory array 805 can be formed on the same die (e.g., the same or different levels of a memory die or chip, the same or different layers of a memory die or chip, at similar or overlapping distances from the substrate of the memory die or chip). In some examples, the signal development cache and the memory array 805 can utilize similar memory architectures (e.g., capacitive memory architectures), and modifications can be made during the manufacturing process to selectively form different memory architectures in the same component (e.g., in the same die, to form ferroelectric capacitors for the memory cells of the memory array 805 and linear capacitors for the cache elements of the signal development cache). In various examples, the sense amplifiers 290 (eg, or the sense amplifier array 245 ) can be formed on the same, different, or overlapping levels or layers as the cache elements or memory elements (eg, of the same memory die or chip with respect to a substrate).

[0278] In some examples, when the memory device includes multiple layers or levels, one layer or level may include the memory array 805 and another layer or level may include the signal development cache. In various examples, the sense amplifier array 845, the memory controller 870, or both may be included in a different (e.g., third) layer or level located above or below (e.g., relative to the substrate) the layer or level including the memory array 805 or the signal development cache.

[0279] In some examples, the memory array 805 and the signal development cache (e.g., the signal development component array 825) can be formed on different memory dies or chips, and such different dies or chips can be coupled to each other (e.g., using bonding techniques, using through-silicon vias). In various examples, the sense amplifier array 845 or the memory controller 870 can be included on the same or different memory dies or chips. Several memory dies or chips or stacks thereof can be included in the same memory device package. In any of the described examples, various physical or logical arrangements of the described components, or combinations thereof, can be used to support the described techniques for signal development caching, including but not limited to reference 100. Figure 1 、 2 , 3, 6, 7, 8A, 8B, 8C and the arrangements described in 9.

[0280] Figure 10 A block diagram 1000 is shown of a memory device 1005 that supports signal development caching in a memory device according to examples as disclosed herein. The memory device 1005 may be a memory device as described in reference Figures 1 to 9 Examples of aspects of the described memory device. Memory device 1005 can include a memory SDC coupling component 1010, a signal state storage component 1015, an SDC SA coupling component 1020, a sensing component 1025, a command receiver 1030, a word line activation component 1035, a plate node bias component 1040, a storage determination component 1045, and a logic state write component 1050. Each of these modules can communicate with each other directly or indirectly (e.g., via one or more buses).

[0281] The memory SDC coupling component 1010 can perform various coupling operations between a memory array and a signal development cache. In some examples, the memory SDC coupling component 1010 can couple a set of access lines of a memory array to the signal development cache, wherein each of the set of access lines can correspond to a respective one of a set of memory cells of the memory array. In some examples, the memory SDC coupling component 1010 can couple a first access line of the set of access lines to a first cache element of a set of cache elements during a first time interval. In some examples, the memory SDC coupling component 1010 can couple a second access line of the set of access lines to a second cache element of the set of cache elements during a second time interval that at least partially overlaps with the first time interval.

[0282] In some examples, the memory SDC coupling component 1010 may couple a group of storage elements to the group of memory cells after storing a corresponding cache signal for each of a group of logic states to the corresponding storage element. In some examples, the memory SDC coupling component 1010 may couple a first storage element in the group of storage elements to a first memory cell in the group of memory cells during a third time interval. In some examples, the memory SDC coupling component 1010 may couple a second storage element in the group of storage elements to a second memory cell in the group of memory cells during a fourth time interval that overlaps with the third time interval.

[0283] The signal state storage component 1015 may, at each of a set of cache memory elements of the signal development cache memory and based on coupling the set of access lines with the signal development cache memory, store a signal state (e.g., a cache memory signal) corresponding to a logic state stored by a corresponding one of the set of memory cells (e.g., corresponding to a signal developed based on the coupling).

[0284] The SDC sense amplifier (SA) coupling component 1020 may perform various coupling operations between a signal development cache and a sense amplifier array. In some examples, the SDC SA coupling component 1020 may couple the set of cache elements of the signal development cache to the sense amplifier array based on the storing (e.g., after or concurrently with the storing). In some examples, the SDC SA coupling component 1020 may couple the first cache element of the set of cache elements to the first sense amplifier of the sense amplifier array during a third time interval. In some examples, the SDC SA coupling component 1020 may couple the second cache element of the set of cache elements to the first sense amplifier of the sense amplifier array during a fourth time interval subsequent to the third time interval. In some examples, the SDC SA coupling component 1020 may couple the first cache element of the set of cache elements to the first sense amplifier of the sense amplifier array during the third time interval. In some examples, the SDC SA coupling component 1020 may couple the second cache element in the set of cache elements with a second sense amplifier of the sense amplifier array during a fourth time interval that at least partially overlaps the third time interval.

[0285] In some examples, the SDC SA coupling component 1020 may couple a group of sense amplifiers of a sense amplifier array to the group of storage elements of the signal development cache based on the determination to store the corresponding cache signals for each of the group of logic states in the corresponding storage elements. In some examples, the SDC SA coupling component 1020 may couple a first sense amplifier of the sense amplifier array to a first storage element in the group of storage elements during a first time interval. In some examples, the SDC SA coupling component 1020 may couple the first sense amplifier of the sense amplifier array to a second storage element in the group of storage elements during a second time interval subsequent to the first time interval.

[0286] The sensing component 1025 can sense (e.g., capture, latch, or enhance) a respective logic signal at each of a set of sense amplifiers of the sense amplifier array based on the stored respective signal states and the coupling of the set of cache memory elements to the sense amplifier array.

[0287] The command receiver 1030 may receive various commands from a requesting device. In some examples, the command receiver 1030 may receive a write command that includes a set of logic states for writing to a set of memory cells of the memory array. In some examples, the command receiver 1030 may receive a read command from a requesting device (e.g., a host device, a device other than the memory device), and coupling the set of access lines of the memory array with the signal development cache may be based on the read command. In some examples, the command receiver 1030 may receive a read command from a requesting device (e.g., a host device, a device other than the memory device) after or during storage of the corresponding cache signal or cache signal state at each of the set of cache elements of the signal development cache, and coupling the signal development cache with the sense amplifier array may be based on the read command.

[0288] In some examples, a memory array can include multiple domains, each associated with a respective subset of a plurality of word lines, and the word line activation component 1035 can activate word lines of a first domain in the set of domains to couple a first subset of the set of memory cells with a first subset of the set of access lines. In some examples, the word line activation component 1035 can activate word lines of a second domain in the set of domains to couple a second subset of the set of memory cells with a second subset of the set of access lines.

[0289] In some examples, each of a plurality of domains of a memory array can be associated with one or more of a plurality of plate nodes operable to be biased independently of other plate nodes of the plurality of plate nodes. In some examples, plate node biasing component 1040 can bias a plate node of a first domain, wherein storing the cache signal corresponding to the logic state stored by the first subset of memory cells is based on biasing the plate node of the first domain. In some examples, plate node biasing component 1040 can bias a plate node of a second domain, wherein storing the cache signal corresponding to the logic state stored by the second subset of memory cells is based on biasing the plate node of the second domain.

[0290] The storage determination component 1045 can determine, based on the write command, to store a respective cache signal (eg, signal state) for each of the set of logical states at a respective storage element in a set of storage elements of a signal development cache.

[0291] The logic state writing component 1050 can write the set of logic states to the set of memory cells of the memory array based on coupling the set of storage elements with the set of memory cells.

[0292] Figure 11 A flow chart is shown illustrating a method or methods 1100 of developing a cache according to a signal in a supporting memory device as disclosed herein. The operations of the method 1100 may be performed as described with reference to Figures 1 to 9 For example, the operations of method 1100 may be performed by a memory device or components thereof as described in reference Figure 10 The memory device described herein performs the functions described herein. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described herein. Additionally or alternatively, the memory device may use dedicated hardware to perform various aspects of the functions described herein.

[0293] At 1105, the memory device may couple a set of access lines of a memory array to a signal development cache, wherein each of the set of access lines corresponds to a respective one of a set of memory cells of the memory array. The operation of 1105 may be as described in reference to Figures 1 to 9 In some examples, aspects of the operation of 1105 may be performed as described in reference to Figure 10 The described memory SDC coupling component is implemented.

[0294] At 1110, the memory device may store, at each of a set of cache elements of the signal development cache and based on coupling the set of access lines with the signal development cache, a signal state (e.g., a cache signal) corresponding to a logic state stored by a corresponding one of the set of memory cells (e.g., corresponding to a signal developed based on the coupling). The operation of 1110 may be as described with reference to Figures 1 to 9 In some examples, aspects of the operation of 1110 may be performed as described in reference to Figure 10 The described signal state storage component performs

[0295] At 1115, the memory device may couple the set of cache elements of the signal development cache to a sense amplifier array based on the storing (eg, after the storing, concurrently with the storing). The operation of 1115 may be as described with reference to Figures 1 to 9 In some examples, aspects of the operation of 1115 may be performed as described in reference to Figure 10 The described SDC SA coupling components are implemented.

[0296] At 1120, the memory device may sense (e.g., capture, latch, or enhance) a respective logic signal at each of a set of sense amplifiers of the sense amplifier array based on the stored respective signal states and the coupling of the set of cache elements to the sense amplifier array. The operation of 1120 may be as described in reference to Figures 1 to 9 In some examples, aspects of the operation of 1120 may be performed as described in reference to Figure 10 The sensing components described perform.

[0297] In some examples, an apparatus as described herein may perform a method or methods, such as method 1100 . The apparatus may include features, circuitry, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for coupling a set of access lines of a memory array with a signal development cache, wherein each of the set of access lines corresponds to a respective one of a set of memory cells of the memory array; storing, at each of a set of cache elements of the signal development cache and based on coupling the set of access lines with the signal development cache, a signal state (e.g., a cache signal) corresponding to a logic state stored by a respective one of the set of memory cells (e.g., corresponding to a signal developed based on the coupling); coupling the set of cache elements of the signal development cache with a sense amplifier array based on the storing (e.g., subsequent to, concurrently with, the storing); and sensing (e.g., capturing, latching, or strengthening) a respective logic signal at each of a set of sense amplifiers of the sense amplifier array based on the stored respective signal state and the coupling of the set of cache elements to the sense amplifier array.

[0298] In some examples of method 1100 and the apparatus described herein, coupling the set of access lines of the memory array with the signal development cache may include operations, features, circuitry, means, or instructions for: coupling a first access line in the set of access lines with a first cache element in the set of cache elements during a first time interval; and coupling a second access line in the set of access lines with a second cache element in the set of cache elements during a second time interval that at least partially overlaps with the first time interval.

[0299] In some examples of method 1100 and the apparatus described herein, coupling the signal development cache with a sense amplifier array may include operations, features, circuitry, means, or instructions for coupling the first cache element of the set of cache elements with a first sense amplifier of the sense amplifier array during a third time interval; and coupling the second cache element of the set of cache elements with the first sense amplifier of the sense amplifier array during a fourth time interval subsequent to the third time interval.

[0300] In some examples of method 1100 and the apparatus described herein, coupling the signal development cache with a sense amplifier array may include operations, features, circuitry, means, or instructions for: coupling the first cache element in the set of cache elements with a first sense amplifier of the sense amplifier array during a third time interval; and coupling the second cache element in the set of cache elements with a second sense amplifier of the sense amplifier array during a fourth time interval that at least partially overlaps with the third time interval.

[0301] Method 1100 and some examples of the apparatus described herein may further include operations, features, circuitry, means, or instructions for receiving a read command from a requesting device (e.g., a host device, another device distinct from a memory device), wherein coupling the set of access lines of the memory array with the signal development cache may be based on the read command.

[0302] Method 1100 and some examples of the apparatus described herein may further include operations, features, circuit systems, means, or instructions for performing the following: after or during storing the corresponding cache signal or cache signal state at each of the set of cache elements of the signal development cache, receiving a read command at the memory device from a requesting device (e.g., a host device, another device different from the memory device), wherein coupling the signal development cache with the sense amplifier array may be based on the read command.

[0303] In some examples of method 1100 and the apparatus described herein, the memory array may include a set of domains each associated with a respective subset of the set of word lines, and method 1100 or the apparatus may include operations, features, circuitry, means, or instructions for activating word lines of a first domain in the set of domains to couple a first subset of the set of memory cells with a first subset of the set of access lines, and activating word lines of a second domain in the set of domains to couple a second subset of the set of memory cells with a second subset of the set of access lines.

[0304] In some instances of method 1100 and the apparatus described herein, each of the set of domains may be associated with one or more of a set of plate nodes, each of the one or more of the set of plate nodes being operable to be biased independently of other plate nodes in the set of plate nodes, and method 1100 or the apparatus may further include operations, features, circuit systems, components, or instructions for: biasing the plate nodes of the first domain, wherein storing the cache memory signals corresponding to the logical states stored by the first subset of memory cells may be based on biasing the plate nodes of the first domain; and biasing the plate nodes of the second domain, wherein storing the cache memory signals corresponding to the logical states stored by the second subset of memory cells may be based on biasing the plate nodes of the second domain.

[0305] Figure 12 Display diagrams according to reference Figures 1 to 9 The described example is a flow chart of a method or methods 1200 for supporting signal exploitation caching in a memory device. The operations of the method 1200 may be performed as described with reference to Figures 1 to 9 For example, the operations of method 1200 may be performed by a memory device or components thereof as described in reference Figure 10 The memory device described herein performs the functions described herein. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the functions described herein. Additionally or alternatively, the memory device may use dedicated hardware to perform various aspects of the functions described herein.

[0306] At 1205, the memory device may receive a write command including a set of logic states for writing to a set of memory cells of the memory array. The operation of 1205 may be as described in reference to Figures 1 to 9 In some examples, aspects of the operation of 1205 may be performed as described in reference to Figure 10 The described command receiver executes.

[0307] At 1210, the memory device may determine, based on the write command, that a corresponding cache signal (e.g., signal state) for each of the set of logic states is to be stored at a corresponding storage element in a set of storage elements of a signal development cache. The operation of 1210 may be as described in reference to Figures 1 to 9 In some examples, aspects of the operation of 1210 may be performed as described in reference to Figure 10 The described storage determination component performs.

[0308] At 1215, the memory device may couple a set of sense amplifiers of a sense amplifier array to the set of storage elements of the signal development cache based on the determination to store the corresponding cache signal for each of the set of logic states to the corresponding storage element. The operation of 1215 may be as described in reference to Figures 1 to 9 In some instances, aspects of the operation of 1215 may be performed as described in reference to Figure 10 The described SDC SA coupling components are implemented.

[0309] At 1220, the memory device may couple the set of storage elements to the set of memory cells after storing the corresponding cache signal for each of the set of logic states to the corresponding storage element. The operation of 1220 may be as described in reference to Figures 1 to 9 In some examples, aspects of the operation of 1220 may be performed as described in reference to Figure 10 The described memory SDC coupling component is implemented.

[0310] At 1225, the memory device may write the set of logic states to the set of memory cells based on coupling the set of storage elements to the set of memory cells of the memory array. The operation of 1225 may be as described in reference to Figures 1 to 9 In some examples, aspects of the operation of 1225 may be performed as described in reference to Figure 10 The described logic states are written to the component execution.

[0311] In some examples, an apparatus as described herein may perform one or several methods, such as method 1200 . The apparatus may include features, circuitry, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a write command at a memory device including a memory array, the write command including a set of logic states for writing to a set of memory cells of the memory array; determining, based on the write command, to store a corresponding cache signal (e.g., a signal state) for each of the set of logical states at a corresponding storage element in a set of storage elements of a signal development cache; coupling, based on the determination, a set of sense amplifiers of a sense amplifier array to the set of storage elements of the signal development cache to store the corresponding cache signal for each of the set of logical states to the corresponding storage element; coupling the set of storage elements with the set of memory cells after storing the corresponding cache signal for each of the set of logical states to the corresponding storage element; and writing the set of logical states to the set of memory cells based on coupling the set of storage elements with the set of memory cells of the memory array.

[0312] In some examples of method 1200 and the apparatus described herein, storing the respective cache memory signal for each of the set of logic states at the respective storage element of the signal development cache may include operations, features, circuit systems, means, or instructions for coupling a first sense amplifier of a sense amplifier array with a first storage element in the set of storage elements during a first time interval; and coupling the first sense amplifier of the sense amplifier array with a second storage element in the set of storage elements during a second time interval subsequent to the first time interval.

[0313] In some examples of method 1200 and the apparatus described herein, coupling the group of storage elements with the group of memory cells may include operations, features, circuit systems, components, or instructions for coupling the first storage element in the group of storage elements with a first memory cell in the group of memory cells during a third time interval; and coupling the second storage element in the group of storage elements with a second memory cell in the group of memory cells during a fourth time interval that overlaps with the third time interval.

[0314] It should be noted that the methods described herein are possible implementations, and that the operations and steps may be rearranged or otherwise modified and other implementations are possible. In addition, portions from two or more than two of the methods may be combined.

[0315] An apparatus is described. The apparatus may include: a memory array having a set of memory cells, each memory cell in the set of memory cells being associated with one of a set of access lines of the memory array; a signal development cache having a set of storage elements different from the set of memory cells of the memory array; a sense amplifier array having a set of sense amplifiers, each sense amplifier in the set of sense amplifiers being configured to output a logic state based on sensing, capturing, or latching signaling from the signal development cache; a first selection component operable to selectively couple the set of access lines of the memory array with the signal development cache; and a second selection component operable to selectively couple the signal development cache with the set of sense amplifiers of the sense amplifier array.

[0316] Some examples of the apparatus may include a third selection component operable to selectively couple the set of access lines of the memory array with the set of sense amplifiers of the sense amplifier array.

[0317] In some examples, the memory array includes a set of domains, each of the domains being associated with a respective subset of the set of access lines of the memory array, and each of the domains being associated with a respective set of second access lines to selectively couple memory cells of the memory array with the respective subset of the set of access lines.

[0318] In some examples, the apparatus may be operable to concurrently select one or more of the respective sets of second access lines of a first of the set of domains and one or more of the respective sets of second access lines of a second of the set of domains.

[0319] In some examples, each of the domains includes a respective set of sub-domains, each of the sub-domains being associated with a respective group within the subset of the set of access lines corresponding to the respective domain.

[0320] In some examples, each of the sub-domains may be associated with an independently controllable board node.

[0321] In some examples, each of the domains includes a respective segment of second access lines within a domain, each of the sub-domains being associated with a respective group within the subset of the set of access lines corresponding to the respective domain.

[0322] In some examples, the second access line may include a word line, and for a given domain, the apparatus may be operable to concurrently couple a first word line driver with a first segment of a first word line within the given domain and with a second segment of a second word line within the given domain, and to concurrently couple a second word line driver with the second segment of the first word line within the given domain and with the first segment of the second word line within the given domain.

[0323] In some examples, the signal development cache may be associated with a set of cache lines, each of which is coupled with a respective subset of the set of storage elements.

[0324] In some examples, the number of the respective subset of the set of storage elements for each of the cache memory lines may be proportional to (e.g., equal to, an integer multiple of) the number of the respective groups within the subset of the set of access lines corresponding to the respective domain.

[0325] In some examples, the integer multiple of the number of the respective subset of the set of storage elements for each of the cache lines may be equal to the number of data bits for a read command, the number of data bits for a write command, or both.

[0326] In some examples, the first selection component may be configured for signal exchange between the group of memory cells and the group of storage elements of the signal development cache memory having a first latency, and the second selection component may be configured for signal exchange between the group of storage elements of the signal development cache memory and the group of sense amplifiers having a second latency, the second latency being less than the first latency.

[0327] In some examples, the first selection component may be operable to concurrently couple each access line of the subset of the set of access lines of the memory array with a respective one of the subset of the set of storage elements of the signal development cache.

[0328] In some examples, the second selection component may be operable to couple each storage element of a subset of the set of storage elements of the signal development cache with a respective one of the set of sense amplifiers of the sense amplifier array.

[0329] In some examples, each storage element in the set of storage elements may be configured to maintain a signal state (e.g., a cache signal, a cache state) corresponding to a logic state when the respective storage element is isolated from one or both of the memory array or the sense amplifier array.

[0330] In some examples, each sense amplifier in the set of sense amplifiers may be configured to receive a target logic state of a write command and generate a write signal based on the target logic state.

[0331] In some examples, to write the target logic state to a target memory cell, the apparatus may be configured to convey the write signal from a corresponding one of the group of sense amplifiers to one of the group of storage elements of the signal development cache memory via the second selection component, and convey a second write signal from the one of the group of storage elements of the signal development cache memory to the target memory cell via the first selection component, the second write signal being based on conveying the write signal to the one of the group of storage elements of the signal development cache memory.

[0332] In some examples, to write the target logic state to a target memory cell, the apparatus may be configured to isolate the set of storage elements of the signal development cache from the write signal and convey the write signal to the target memory cell via the first selection component and the second selection component.

[0333] In some examples, each memory cell of the set of memory cells includes a respective storage element having an architecture different from the set of storage elements of the signal development cache.

[0334] In some examples, the respective storage element of each memory cell in the set of memory cells includes a ferroelectric cell (eg, a ferroelectric capacitor).

[0335] In some examples, the respective storage element of each memory cell in the set of memory cells includes a material memory element (e.g., a material operable to store a logic state with configurable material properties, configurable atomic arrangement, configurable resistance, configurable threshold voltage).

[0336] In some examples, each storage element in the set of storage elements of the signal development cache includes a linear capacitor.

[0337] Some examples of the apparatus may include a controller configured to manage a refresh procedure to maintain cache signals stored by the set of storage elements of the signal development cache.

[0338] In some examples, each memory cell in the set of memory cells may be operable to store one of a set of more than two logic states, and the first selection component may be operable to selectively couple one of the access lines of the memory array with two or more of the set of storage elements of the signal development cache.

[0339] In some examples, each storage element of the signal development cache may be operable to store one of a set of more than two cache signal states, and the first selection component may be operable to selectively couple one of the set of storage elements of the signal development cache with two or more of the access lines of the memory array.

[0340] In some examples, each storage element of the signal development cache may be operable to store one of a set of more than two cache signal states, and the first selection component may be operable to selectively couple one of the set of storage elements of the signal development cache with two or more of the set of memory cells.

[0341] An apparatus is described. The apparatus may include: a memory array including a set of memory cells; a signal development cache including a set of cache elements distinct from the set of memory cells; sense amplifiers including a set of sense amplifiers; and a controller. The controller may be operable to cause the apparatus to: couple a set of access lines of the memory array to the signal development cache, wherein each of the plurality of access lines corresponds to a respective one of the set of memory cells; store, at each of the set of cache elements and based on coupling the set of access lines to the signal development cache, a signal state (e.g., a cache signal) corresponding to a logic state stored by the respective one of the set of memory cells (e.g., corresponding to a signal developed based on the coupling); couple the set of cache elements to the sense amplifier array based on the storing (e.g., subsequent to, concurrently with, the storing); and sense (e.g., capture, latch, and strengthen) a respective logic signal at each of the set of sense amplifiers based on the respective signal state and by coupling the set of cache elements to the sense amplifier array.

[0342] Another apparatus is described. The apparatus may include: a memory array including a set of memory cells; a signal development cache including a set of cache elements different from the set of memory cells; a sense amplifier including a set of sense amplifiers; and a controller. The controller may be operable to: receive a write command including a set of logic states for writing to the set of memory cells; determine, based on the write command, to store a corresponding cache signal (e.g., a signal state) for each of the set of logic states at a corresponding one of the set of cache elements; couple the set of sense amplifiers to the set of cache elements to store the corresponding cache signal for each of the set of logic states to the corresponding cache element based on the determination; after storing the corresponding cache signal for each of the set of logic states to the corresponding cache element, couple the set of cache elements to the set of memory cells; and write the set of logical states to the set of memory cells based on coupling the set of cache elements to the set of memory cells.

[0343] Another apparatus is described. The apparatus may include: a memory array having a set of memory cells, each memory cell in the set of memory cells being associated with one of a set of access lines of the memory array; a signal development cache having a set of storage elements different from the set of memory cells of the memory array; a sense amplifier array having a set of sense amplifiers, each sense amplifier in the set of sense amplifiers being configured to output a logic state based on latching signaling from the signal development cache; and selection circuitry. The selection circuitry may be configured for or operable to: selectively couple the plurality of access lines of the memory array with the signal development cache; selectively couple the signal development cache with the plurality of sense amplifiers of the sense amplifier array; selectively couple the plurality of access lines of the memory array with the plurality of sense amplifiers of the sense amplifier array; or any combination thereof.

[0344] In some examples, the selection circuitry may be operable to support concurrent coupling of the set of access lines of the memory array, the signal development cache, and the set of sense amplifiers of the sense amplifier array.

[0345] In some examples, the selection circuitry may be operable to support concurrent coupling of one of the set of access lines of the memory array, one of the cache elements of the signal development cache, and one of the set of sense amplifiers of the sense amplifier array.

[0346] In some examples, the selection circuitry may be reconfigurable to support changing between strategies for writing information back to the memory array.

[0347] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have various bit widths.

[0348] The terms "electronic comm...

Claims

1. A device comprising: a first multiplexer coupled to a first digit line and a second digit line of the memory array; a signal development cache including a first node coupled to the first multiplexer and configured to selectively couple to the first digit line and the second digit line via the first multiplexer at different times; A second multiplexer is coupled to a second node of the signal development cache and is configured to selectively couple the signal development cache with a sense amplifier.

2. The apparatus according to claim 1, further comprising: a third multiplexer coupled to a third digit line and a fourth digit line of the memory array; as well as A second signal development cache includes a node coupled to the third multiplexer and is configured to be selectively coupled to the third digit line and the fourth digit line via the third multiplexer at different times.

3. The apparatus of claim 1 , wherein the memory array comprises domains, each of the domains being associated with a respective plurality of digit lines of the memory array, and each of the domains being associated with a respective plurality of word lines to selectively couple memory cells of the memory array with the respective plurality of digit lines. 4 . The apparatus of claim 3 , wherein each of the domains comprises a respective set of sub-domains, each of the sub-domains being associated with a respective group of a plurality of digit lines corresponding to the respective domain.

5. The apparatus of claim 4, wherein each sub-domain is associated with an independently controllable board node.

6. The apparatus of claim 4, wherein for a given domain, the apparatus is operable to: concurrently coupling a first word line driver to a first segment of a first word line within the given domain and to a second segment of a second word line within the given domain; and A second word line driver is concurrently coupled to the second segment of the first word line within the given domain and to the first segment of the second word line within the given domain.

7. The apparatus of claim 1 , wherein the signal development cache has a plurality of storage elements, and wherein the signal development cache is associated with cache lines, each of the cache lines being coupled to a respective subset of the plurality of storage elements.

8. The apparatus of claim 7, wherein the first multiplexer is operable to concurrently couple each digit line of a subset of a plurality of digit lines of the memory array with a corresponding one of a subset of the plurality of storage elements of the signal development cache.

9. The apparatus of claim 7 , wherein the sense amplifier is included in a sense amplifier array comprising a plurality of sense amplifiers, and wherein the second multiplexer is operable to couple each storage element of a subset of the plurality of storage elements of the signal development cache with a respective one of the plurality of sense amplifiers of the sense amplifier array.

10. The apparatus of claim 7, wherein the sense amplifier is included in a sense amplifier array, and wherein each storage element of the plurality of storage elements is configured to maintain a signal state corresponding to a logic state when the respective storage element is isolated from one or both of the memory array or the sense amplifier array.

11. The apparatus of claim 1 , wherein: The first multiplexer is configured for signal exchange between the memory array and the signal development cache having a first delay; and The second multiplexer is configured for signal exchange between the signal development cache and the sense amplifier with a second delay that is less than the first delay.

12. The apparatus of claim 1, wherein the sense amplifier is configured to receive a target logic state of a write command and generate a write signal based at least in part on the target logic state.

13. The apparatus according to claim 12, wherein To write the target logic state to a target memory cell, the apparatus is configured to: routing the write signal from the sense amplifier to the signal development cache via the second multiplexer; and A second write signal is conveyed from the signal development cache to the target memory cell via the first multiplexer, the second write signal being based at least in part on the write signal.

14. The apparatus of claim 1, wherein the memory array comprises memory cells having an architecture different from a plurality of storage elements of the signal development cache.

15. The apparatus of claim 14, wherein each memory cell of the memory array is operable to store one of a set of more than two logic states, and wherein the first multiplexer is operable to selectively couple the first digit line with two or more storage elements of the signal development cache.

16. The apparatus of claim 14 , wherein each storage element of the plurality of storage elements is operable to store one of a set of more than two cache signal states, and wherein the first multiplexer is operable to selectively couple one of the plurality of storage elements of the signal development cache with the first digit line and the second digit line.

17. A method comprising: coupling a first digital line of the memory array to a first cache element of the signal development cache through the multiplexer during a first time interval; storing a first cache signal state corresponding to a first logic state in the first cache element based at least in part on coupling the first digit line to the first cache element; coupling a second digit line of the memory array to a second cache element of the signal development cache through the multiplexer during a second time interval that at least partially overlaps the first time interval; storing a second cache signal state corresponding to a second logic state in the second cache element based at least in part on coupling the second digit line to the second cache element; as well as The first cache signal state and the second cache signal state are sensed from the signal development cache through the sense amplifier array based at least in part on coupling the signal development cache with the sense amplifier array.

18. The method of claim 17, wherein coupling the signal development cache with the sense amplifier array comprises: coupling the first cache element with a first sense amplifier of the sense amplifier array during a third time interval; and During a fourth time interval subsequent to the third time interval, the second cache element is coupled with the first sense amplifier of the sense amplifier array.

19. The method of claim 17, wherein coupling the signal development cache with the sense amplifier array comprises: coupling the first cache element with a first sense amplifier of the sense amplifier array during a third time interval; and During a fourth time interval that at least partially overlaps the third time interval, the second cache element is coupled to a second sense amplifier of the sense amplifier array.

20. The method of claim 17, further comprising: A read command is received, wherein coupling the first digit line with the first cache element and coupling the second digit line with the second cache element are each based at least in part on the read command.

21. The method of claim 17, further comprising: After storing the first cache signal state and the second cache signal state, a read command is received, wherein coupling the signal development cache with the sense amplifier array is based at least in part on the read command.

22. A method comprising: receiving a write command indicating a first logic state and a second logic state for writing to a memory array; coupling a sense amplifier array to a first storage element of a signal development cache via a multiplexer during a first time interval, wherein a first cache signal state representing the first logic state is stored in the first storage element based at least in part on coupling the sense amplifier array to the first storage element; coupling the sense amplifier array to a second storage element of the signal development cache via the multiplexer during a second time interval subsequent to the first time interval, wherein a second cache signal state representing the second logic state is stored in the second storage element based at least in part on coupling the sense amplifier array to the second storage element; as well as The first logic state and the second logic state are written to the memory array based at least in part on coupling the signal development cache with the memory array.

23. The method of claim 22, wherein coupling the signal development cache with the memory array comprises: coupling the first storage element to a first memory cell of the memory array during a third time interval; and During a fourth time interval that overlaps the third time interval, the second storage element is coupled to a second memory cell of the memory array. The method of claim 23 , wherein the third time interval overlaps with the second time interval.

25. The method of claim 23, wherein a second multiplexer couples the first storage element with the first memory cell, and wherein a third multiplexer couples the second storage element with the second memory cell.

26. The method of claim 22, further comprising: generating, by the sense amplifier array, a first latch signal based at least in part on the first logic state, wherein the first cache signal state is based at least in part on the first latch signal; and A second latch signal is generated by the sense amplifier array based at least in part on the second logic state, wherein the second cache signal state is based at least in part on the second latch signal.

27. The method of claim 22, further comprising: developing a cache memory by the signal to generate a first write signal based at least in part on the first cache signal state, wherein the first logic state is written to the memory array based at least in part on the first write signal; and Developing a cache memory via the signal generates a second write signal based at least in part on the second cache signal state, wherein the second logic state is written to the memory array based at least in part on the second write signal.

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