Laminated battery and method for manufacturing same

Abstract

The invention relates to the technical field of solar cells, and provides a laminated cell and a manufacturing method thereof, which are at least beneficial to improving the efficiency of the laminated cell. The laminated cell comprises a crystalline silicon bottom cell, a middle layer and a perovskite top cell which are sequentially laminated in a preset direction, the middle layer comprises a conductive composite layer, the conductive composite layer is located on the surface, facing the perovskite top cell, of the crystalline silicon bottom cell, and materials of the conductive composite layer comprise a conductive polymer and a metal dopant; the metal grid layer is embedded into one side, far away from the crystalline silicon bottom battery, of the conductive composite layer, and the conductive composite layer exposes the surface, far away from the conductive composite layer, of the metal grid layer; the barrier layer is located on the side, away from the composite layer, of the metal grid layer and covers the surfaces of the metal grid layer and the conductive composite layer.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a stacked cell and a method for manufacturing the same. Background Art

[0002] Currently, the power conversion efficiency (PCE) of single-junction perovskite solar cells (PSCs) has reached 25.7%, very close to the theoretical maximum energy conversion efficiency under ideal conditions, known as the Shockley-Queisser (SQ) limit. To break this SQ limit for single-junction solar cells, the construction of multi-junction tandem solar cells (TSCs) can more efficiently utilize solar energy and reduce hot carrier losses, potentially achieving a PCE greater than 40%.

[0003] Whether it is a single-cell solar cell or a multi-cell stacked solar cell, interface non-radiative recombination limits the further improvement of cell performance. Taking multi-cell stacked solar cells as an example, although good progress has been made, there is still a big gap compared with its theoretical efficiency. Specifically, it is mainly reflected in the fact that the intermediate connection layer causes a large loss in the performance of the stacked devices at both ends.

[0004] Therefore, in the current research on stacked batteries, the design and optimization of the intermediate connection structure is a key challenge. Summary of the Invention

[0005] The embodiments of the present application provide a stacked battery and a method for manufacturing the same, which are at least beneficial to improving the efficiency of the stacked battery.

[0006] According to some embodiments of the present application, on the one hand, the embodiments of the present application provide a stacked battery, including a crystalline silicon bottom battery, an intermediate layer and a perovskite top battery stacked in sequence along a preset direction, wherein the intermediate layer includes: a conductive composite layer, the conductive composite layer is located on the surface of the crystalline silicon bottom battery facing the perovskite top battery, and the material of the conductive composite layer includes a conductive polymer and a metal dopant; a metal grid layer, the metal grid layer is embedded in the side of the conductive composite layer away from the crystalline silicon bottom battery, and the conductive composite layer exposes the surface of the metal grid layer away from the conductive composite layer; a barrier layer, the barrier layer is located on the side of the metal grid layer away from the composite layer, covering the surface of the metal grid layer and the conductive composite layer.

[0007] In some embodiments, the perovskite top cell includes: a perovskite absorption layer and an electron transport layer and a hole transport layer located on opposite sides of the perovskite absorption layer, and the hole transport layer is located between the blocking layer and the perovskite absorption layer and contacts the blocking layer.

[0008] In some embodiments, an interface passivation layer is further included between the perovskite absorption layer and the hole transport layer.

[0009] In some embodiments, the material of the interface passivation layer includes tetrafluorophenethylamine, 2-phenethylamine, 3,5-difluorophenethylamine, benzamidine hydrochloride, or polyethyleneimine.

[0010] In some embodiments, the material of the barrier layer includes aluminum oxide, silicon oxide, or hafnium oxide.

[0011] In some embodiments, the barrier layer has a thickness of 3 nm to 8 nm.

[0012] In some embodiments, the orthographic projection of the metal grid layer on the surface of the crystalline silicon bottom cell has a hexagonal grid shape.

[0013] In some embodiments, the hexagonal pore size is 100 nm to 300 nm.

[0014] In some embodiments, the line width of the metal grid layer is 10 nm to 30 nm.

[0015] In some embodiments, the material of the conductive polymer includes at least one of PEDOT:PSS or PEDOT:Tos; and the material of the metal dopant includes at least one of FeCl 3 , MoO 3 , or HAuCl 4 .

[0016] According to some embodiments of the present application, on the other hand, the embodiments of the present application also provide a method for manufacturing a stacked battery, including: preparing a perovskite top battery; depositing a barrier layer on the surface of the perovskite top battery; spraying a metal grid layer on the surface of the barrier layer away from the perovskite top battery; spin-coating a conductive composite layer on the side of the metal grid layer away from the barrier layer, the conductive composite layer also filling the gaps in the metal grid layer, the material of the conductive composite layer including a conductive polymer and a metal dopant; placing a crystalline silicon bottom battery on the conductive composite layer and then performing packaging processing to form a stacked battery.

[0017] In some embodiments, preparing a perovskite top cell includes: preparing an electron transport layer; forming a perovskite absorption layer on the electron transport layer; spin-coating an interface passivation layer on the surface of the perovskite absorption layer away from the electron transport layer; performing ultraviolet ozone treatment on the side of the interface passivation layer away from the perovskite absorption layer; forming a hole transport layer on the interface passivation layer; depositing a blocking layer on the surface of the perovskite top cell includes: the blocking layer is located on the surface of the hole transport layer away from the interface passivation layer.

[0018] In some embodiments, the process parameters of the ultraviolet ozone treatment include: a wavelength of 150 nm to 200 nm; a power of 30 W to 60 W; and a time of 20 s to 40 s.

[0019] In some embodiments, in the conductive composite layer, the volume ratio of the conductive polymer to the metal dopant is 4:1 to 6:1.

[0020] In some embodiments, the process method for spraying the metal mesh layer is inkjet printing, and the process parameters of inkjet printing include: ink concentration of 0.2wt%~0.5wt%; temperature of 60℃~80℃; drying time of 20s~60s.

[0021] The technical solution provided by the embodiments of the present application has at least the following advantages: The stacked cell provided in the embodiment of the present application is composed of a crystalline silicon bottom cell and a perovskite top cell. The crystalline silicon bottom cell and the perovskite top cell are compositely connected by an intermediate layer. The intermediate layer includes a conductive composite layer, a metal grid layer and a barrier layer stacked in sequence from the crystalline silicon bottom cell to the perovskite top cell. The conductive composite layer includes a conductive polymer and a metal dopant. The conductive polymer can provide lateral conductivity and collect holes in the crystalline silicon bottom cell. The metal dopant can further enhance the conductivity of the conductive polymer and reduce the series resistance. The conductive polymer and the metal dopant work together to reduce surface defects of the crystalline silicon bottom cell, inhibit composite losses, and increase the open circuit voltage. The metal grid layer is used to solve the problem of insufficient lateral conductivity of the conductive composite layer, ensure uniform current distribution, and avoid local current congestion. At the same time, the mesh formed by the grid of the metal grid layer can help maintain a high light transmittance of the intermediate layer. The barrier layer is used to prevent metal ions in the metal grid layer from diffusing into the perovskite top cell, avoiding performance degradation of the perovskite top cell and improving the overall stability of the stacked cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A schematic diagram of the structure of a stacked battery provided in an embodiment of the present application; Figure 2 A schematic structural diagram of another laminated battery provided in an embodiment of the present application; Figure 3 A schematic structural diagram of another laminated battery provided in an embodiment of the present application; Figure 4 It is the orthographic projection of the metal grid layer on the surface of the barrier layer.

[0024] Description of reference numerals: 100, crystalline silicon bottom cell; 200, middle layer; 201, conductive composite layer; 202, metal grid layer; 203, barrier layer; 300, perovskite top cell; 301, perovskite absorption layer; 302, electron transport layer; 303, hole transport layer; 304, interface passivation layer. DETAILED DESCRIPTION

[0025] As can be seen from the background art, the design and optimization of the intermediate connection structure is the key to improving the performance loss of stacked batteries.

[0026] In the related art, indium tin oxide (ITO) is used as a transparent conductive oxide (TCO) and as the intermediate composite layer of tandem cells. Although ITO has advantages such as high conductivity and light transmittance, it has defects such as high brittleness, poor flexibility, and prone to cracking under bending or stretching conditions. It also absorbs light in the near-infrared or ultraviolet regions, which can easily reduce the light utilization of the bottom cell in the tandem cell, thereby reducing the efficiency of the tandem cell. In addition, ITO generally requires high-temperature annealing to achieve low resistance, but other layers in the tandem cell (such as the perovskite absorber layer) may not be able to withstand high temperatures.

[0027] The embodiments of the present application provide a stacked battery and a method for manufacturing the same, which are at least beneficial to improving the efficiency of the stacked battery.

[0028] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0029] In the description of the embodiments of the present application, technical terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limiting the embodiments of the present application.

[0030] In the accompanying drawings corresponding to the embodiments of the present application, the thickness and area of ​​the layers are exaggerated for better understanding and ease of description. When describing a component as being on another component or on the surface of another component, the component may be "directly" located on the surface of the other component, or a third component may be present between the two components. Conversely, when describing a component as being on the surface of another component or as being formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as being "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0031] In the description of the embodiments of the present application, when a component “includes” another component, unless otherwise stated, other components are not excluded, and other components may be further included.

[0032] The terms used in the description of the various embodiments described herein are for describing specific embodiments only and are not intended to be limiting. As used in the description of the various embodiments described, "component" is also intended to include plural forms unless the context clearly indicates otherwise.

[0033] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0034] Figure 1 A schematic diagram of the structure of a stacked battery provided in an embodiment of the present application; Figure 2 A schematic structural diagram of another laminated battery provided in an embodiment of the present application; Figure 3 A schematic structural diagram of another laminated battery provided in an embodiment of the present application; Figure 4 It is the orthographic projection of the metal grid layer on the surface of the barrier layer.

[0035] refer to Figures 1 to 4 The stacked cell provided in the embodiment of the present application includes a crystalline silicon bottom cell 100, an intermediate layer 200, and a perovskite top cell 300 stacked in sequence along a preset direction. The intermediate layer 200 includes: a conductive composite layer 201, a metal grid layer 202, and a barrier layer 203.

[0036] The conductive composite layer 201 is located on the surface of the crystalline silicon bottom cell 100 facing the perovskite top cell 300 . The material of the conductive composite layer 201 includes a conductive polymer and a metal dopant.

[0037] The metal grid layer 202 is embedded in a side of the conductive composite layer 201 away from the crystalline silicon bottom cell 100 , and the conductive composite layer 201 exposes a surface of the metal grid layer 202 away from the conductive composite layer 201 .

[0038] The barrier layer 203 is located on a side of the metal mesh layer 202 away from the conductive composite layer 201 , and covers the surfaces of the metal mesh layer 202 and the conductive composite layer 201 .

[0039] The tandem cell provided in the embodiments of the present application comprises a crystalline silicon bottom cell 100 and a perovskite top cell 300. The crystalline silicon bottom cell 100 and the perovskite top cell 300 are compositely connected by an intermediate layer 200. The intermediate layer 200 comprises a conductive composite layer 201, a metal grid layer 202, and a barrier layer 203, stacked sequentially from the crystalline silicon bottom cell 100 toward the perovskite top cell 300. The conductive composite layer 201 comprises a conductive polymer and a metal dopant. The conductive polymer provides lateral conductivity and collects holes in the crystalline silicon bottom cell 100. The metal dopant further enhances the conductivity of the conductive polymer and reduces series resistance. The conductive polymer and the metal dopant work together to reduce surface defects in the crystalline silicon bottom cell 100, suppress recombination losses, and increase the open circuit voltage. The metal grid layer 202 is used to address the problem of insufficient lateral conductivity of the conductive composite layer 201, ensuring uniform current distribution and avoiding local current congestion. At the same time, the mesh formed by the metal grid layer 202 can help maintain the high light transmittance of the intermediate layer 200. The barrier layer 203 is used to prevent the metal ions in the metal grid layer 202 from diffusing into the perovskite top cell 300 , thereby avoiding the performance degradation of the perovskite top cell 300 and improving the overall stability of the stacked cell.

[0040] The crystalline silicon bottom cell 100 may be any one of a PERC cell (Passivated Emitter and Rear Cell), a PERT cell (Passivated Emitter and Rear Totally-diffused cell), a TOPCon cell (Tunnel Oxide Passivated Contact), a HIT / HJT cell (Heterojunction Technology), or a BC cell (Back Contact). The BC cell may be an IBC cell (Interdigitated Back Contact), an HPBC cell (Hybrid Passivated Back Contact), a TBC cell that superimposes TOPCon technology and IBC technology, or an HBC cell that superimposes HIT / HJT technology and IBC technology. Of course, other types of back contact cells are also possible.

[0041] The crystalline silicon bottom cell 100 can also be a single crystal silicon solar cell, a polycrystalline silicon solar cell, an amorphous silicon solar cell or a multi-compound solar cell. The multi-compound solar cell can specifically be a cadmium sulfide solar cell, a gallium arsenide solar cell, a copper indium selenide solar cell or a perovskite solar cell.

[0042] refer to Figure 2 In some embodiments, the perovskite top cell 300 includes a perovskite absorber layer 301, and an electron transport layer 302 and a hole transport layer 303 located on opposite sides of the perovskite absorber layer 301. The hole transport layer 303 is located between the barrier layer 203 and the perovskite absorber layer 301 and is in contact with the barrier layer 203. In this way, the hole transport layer 303 matches the energy level of the crystalline silicon bottom cell 100 to ensure efficient hole collection in the intermediate layer 200 and reduce interfacial recombination. The barrier layer 203 can prevent metals or impurities from diffusing into the hole transport layer 303, maintaining the stability of the perovskite absorber layer 301.

[0043] The general chemical formula of the material of the perovskite absorption layer 301 is ABX3, where A can be CH3NH3 + 、NH(CH3)2 + 、Cs + or Rb + ; B can be Pb 2+ 、Sn 2+ Or Sr 2+ ; X can be 1 —Br — 、Cl — .

[0044] The materials of the electron transport layer 302 include tin oxide, titanium dioxide, C 60 , fullerenes and their derivatives and other materials.

[0045] The hole transport layer 303 is made of materials including molybdenum oxide, cuprous thiocyanate, poly(4-phenyl)(2,4,6-trimethylphenyl)amine), and poly(3,4-ethylenedioxythiophene):polystyrenesulfonate) (PEDOT:PSS).

[0046] refer to Figure 3 In some embodiments, an interface passivation layer 304 is further included between the perovskite absorption layer 301 and the hole transport layer 303. There are a large number of uncoordinated Pb 2+ Ion or halogen vacancies, these defects will become non-radiative recombination centers, resulting in a shortened carrier lifetime, a decrease in open circuit voltage and fill factor. The interface passivation layer 304 neutralizes the uncoordinated ions and passivates the surface defects of the perovskite absorption layer 301 through chemical bonding (such as Lewis acid / base interaction) or physical coverage.

[0047] In some embodiments, the material of the interface passivation layer 304 includes tetrafluorophenethylamine, 2-phenethylamine, 3,5-difluorophenethylamine, benzamidine hydrochloride, or polyethyleneimine.

[0048] The thickness of the interface passivation layer 304 is 1 nm to 3 nm, for example, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, 2.3 nm, 2.5 nm, 2.7 nm or 3 nm.

[0049] In the conductive composite layer 201, the conductive polymer material includes at least one of PEDOT:PSS (poly(3,4-ethylenedioxythiophene):polystyrenesulfonate) or PEDOT:Tos (poly(3,4-ethylenedioxythiophene):p-toluenesulfonate); the metal dopant material includes at least one of FeCl3, MoO3, or HAuCl4. These conductive polymers have high hole mobility, efficiently collecting holes from the crystalline silicon bottom cell 100 and transferring them to the perovskite top cell 300. FeCl3 and HAuCl4, as oxidizing dopants, extract electrons from the conductive polymer, increasing the carrier concentration. MoO3 can enhance hole injection efficiency by forming an interfacial dipole layer.

[0050] The thickness of the conductive composite layer 201 ranges from 100 nm to 300 nm, and can be, for example, 100 nm, 110 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 270 nm, or 300 nm. The thickness of the conductive composite layer 201 within an appropriate range facilitates a balance between high conductivity and high light transmittance.

[0051] In some embodiments, the orthographic projection of the metal grid layer on the surface of the crystalline silicon bottom cell may be in the shape of a triangle, a quadrilateral, a pentagon, a hexagon, or the like.

[0052] refer to Figure 4 In some embodiments, the orthographic projection of the metal grid layer 202 onto the surface of the crystalline silicon bottom cell 100 forms a hexagonal grid, optionally a regular hexagon. Compared to other polygons, hexagons are one of the most efficient densely packed structures in nature. Their high symmetry and uniform side lengths / angles ensure that the current transmission path from the surface of the crystalline silicon bottom cell 100 to the grid nodes is consistent, avoiding local current congestion. Furthermore, for the same grid area, the hexagonal grid has a higher aperture ratio (the ratio of the open area of ​​the mesh to the total grid area) than other polygonal or random grids, allowing more light to pass through the intermediate layer 200 to the crystalline silicon bottom cell 100, thereby improving the current matching of the tandem cell.

[0053] In some embodiments, the hexagonal pore diameter W is 100 nm to 300 nm, for example, 100 nm, 120 nm, 155 nm, 180 nm, 200 nm, 213 nm, 255 nm, 286 nm, or 300 nm. The pore diameter refers to the maximum distance between any two points on a single mesh opening in the nano-metal mesh layer 202.

[0054] In some embodiments, the line width H of the metal mesh layer 202 is 10 nm to 30 nm, for example, 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 23 nm, 26 nm, 29 nm, or 30 nm. The line width refers to the diameter of the nanowires forming a single mesh in the nanometal mesh layer 202.

[0055] The material of the metal grid layer 202 includes an alloy composed of one or more of silver, copper, gold or aluminum. For example, the alloy may be a silver-copper alloy, a silver-aluminum alloy, a gold-silver alloy, a copper-aluminum alloy, a copper-gold alloy or a gold-aluminum alloy.

[0056] The material of the barrier layer 203 includes aluminum oxide, silicon oxide, or hafnium oxide, and aluminum oxide or silicon oxide can be selected to balance performance and cost.

[0057] In some embodiments, the thickness of the barrier layer 203 is 3 nm to 8 nm, for example, 3 nm, 4 nm, 5 nm, 6.6 nm, 7 nm or 8 nm.

[0058] The tandem cell provided in the embodiments of the present application comprises a crystalline silicon bottom cell 100 and a perovskite top cell 300. The crystalline silicon bottom cell 100 and the perovskite top cell 300 are compositely connected by an intermediate layer 200. The intermediate layer 200 comprises a conductive composite layer 201, a metal grid layer 202, and a barrier layer 203, stacked sequentially from the crystalline silicon bottom cell 100 toward the perovskite top cell 300. The conductive composite layer 201 comprises a conductive polymer and a metal dopant. The conductive polymer provides lateral conductivity and collects holes in the crystalline silicon bottom cell 100. The metal dopant further enhances the conductivity of the conductive polymer and reduces series resistance. The conductive polymer and the metal dopant work together to reduce surface defects in the crystalline silicon bottom cell 100, suppress recombination losses, and increase the open circuit voltage. The metal grid layer 202 is used to address the problem of insufficient lateral conductivity of the conductive composite layer 201, ensuring uniform current distribution and avoiding local current congestion. At the same time, the mesh formed by the metal grid layer 202 can help maintain the high light transmittance of the intermediate layer 200. The barrier layer 203 is used to prevent the metal ions in the metal grid layer 202 from diffusing into the perovskite top cell 300 , thereby avoiding the performance degradation of the perovskite top cell 300 and improving the overall stability of the stacked cell.

[0059] Accordingly, another embodiment of the present application further provides a method for manufacturing a laminated battery, which can be used to manufacture the laminated battery provided in the above embodiment. For the same or corresponding parts as the previous embodiment, please refer to the corresponding description of the previous embodiment and will not be described in detail below.

[0060] The manufacturing method of the laminated battery provided in the embodiment of the present application includes: S11, preparing perovskite top cell; S12, depositing a barrier layer on the surface of the perovskite top cell; S13, spraying a metal grid layer on the surface of the barrier layer away from the perovskite top cell; S14, spin-coating a conductive composite layer on a side of the metal grid layer away from the barrier layer, wherein the conductive composite layer also fills the gaps in the metal grid layer, wherein the material of the conductive composite layer includes a conductive polymer and a metal dopant, and the barrier layer, the metal grid layer, and the conductive composite layer together constitute an intermediate layer; S15. Place a crystalline silicon bottom cell on the conductive composite layer and then perform packaging processing to form a stacked cell.

[0061] In the manufacturing method of the stacked cell provided in the embodiment of the present application, a perovskite top cell is first prepared, and then a barrier layer, a metal grid layer and a conductive composite layer are sequentially formed on the perovskite top cell to form an intermediate layer. Finally, a crystalline silicon bottom cell is placed on the intermediate layer and then packaged to obtain a stacked cell. Because the material of the perovskite absorption layer is sensitive to moisture, high temperature and solvents, if the crystalline silicon bottom cell or the metal grid layer is prepared first, the perovskite solution processing for the subsequent formation of the perovskite absorption layer may be affected by the underlying structure, resulting in a decrease in crystallization quality or interface contamination. Depositing the barrier layer immediately after the perovskite top cell is prepared can isolate physical or chemical damage during the subsequent preparation of the metal grid layer. First, the metal grid layer is sprayed to form a metal grid layer, and then a conductive composite layer composed of a liquid conductive polymer and a metal dopant is spin-coated. This allows the conductive composite layer to penetrate into the mesh formed by the grid of the metal grid layer. After solidification, a continuous lateral conductive network is formed, and at the same time, close electrical contact is formed with the grid to reduce the interface resistance. Finally, the crystalline silicon cell is placed and uniform pressure is applied through the packaging to ensure that the conductive composite layer forms an ohmic contact with the surface of the crystalline silicon bottom cell while avoiding delamination. If a crystalline silicon bottom cell is placed first and then a perovskite top cell is prepared on top, the solvent or annealing in the perovskite top cell preparation process may damage the crystalline silicon bottom cell.

[0062] In some embodiments, preparing a perovskite top cell includes: preparing an electron transport layer; forming a perovskite absorption layer on the electron transport layer; spin-coating an interface passivation layer on the surface of the perovskite absorption layer away from the electron transport layer; performing ultraviolet ozone treatment on the side of the interface passivation layer away from the perovskite absorption layer; forming a hole transport layer on the interface passivation layer; depositing a blocking layer on the surface of the perovskite top cell includes: the blocking layer is located on the surface of the hole transport layer away from the interface passivation layer.

[0063] After forming the electron transport layer and perovskite absorber layer, an interfacial passivation layer is formed on the surface of the perovskite absorber layer. Chemical bonding (such as Lewis acid / base interactions) or physical coverage within the interfacial passivation layer neutralizes uncoordinated ions and passivates surface defects in the perovskite absorber layer. UV-ozone treatment of the interfacial passivation layer removes residual organic matter (such as solvent molecules) on the surface of the interfacial passivation layer, enhancing the adhesion of the subsequent interfacial passivation layer. It also moderately oxidizes the perovskite absorber layer, reducing band bending and improving the fill factor.

[0064] In some embodiments, the UV ozone treatment process parameters include: a wavelength of 150 nm to 200 nm, a power of 30 W to 60 W, and a duration of 20 seconds to 40 seconds. The short wavelength ensures a localized reaction during the ozone treatment without damaging the perovskite absorber layer.

[0065] In some embodiments, spin coating the interface passivation layer includes: dissolving tetrafluorophenylethylamine in isopropyl alcohol to prepare a mixed solution and spin coating the mixed solution on the surface of the electron transport layer, and then purging and drying with an inert gas to volatilize the isopropyl alcohol.

[0066] In some embodiments, the concentration of tetrafluorophenethylamine in isopropanol is 0.3 mg / mL to 0.8 mg / mL; the spin coating speed is 3000 rpm to 5000 rpm; and the spin coating time is 20 s to 40 s.

[0067] Among them, tetrafluorophenethylamine can also be replaced by 2-phenethylamine, 3,5-difluorophenethylamine, benzamidine hydrochloride or polyethyleneimine.

[0068] The barrier layer formation process includes atomic layer deposition (ALD), chemical vapor deposition (CVD) or physical vapor deposition (PVD), and ALD can be selected. ALD deposits with atomic-level precision, which is beneficial to improving the density of the barrier layer.

[0069] In some embodiments, the metal mesh layer is sprayed using inkjet printing. Inkjet printing process parameters include: ink concentration of 0.2wt% to 0.5wt%, temperature of 60°C to 80°C, and drying time of 20s to 60s. Inkjet printing can produce a metal mesh layer of high precision and quality.

[0070] In some embodiments, in the conductive composite layer, the volume ratio of the conductive polymer to the metal dopant is 4:1 to 6:1, for example, 4:1, 5:1, or 6:1.

[0071] The spin coating process parameters of the conductive composite layer include: a rotation speed of 2500 rpm to 3500 rpm, a time of 20 s to 40 s, and annealing at 120° C. for 5 min after spin coating.

[0072] In some embodiments, the encapsulation process parameters include: a temperature of 100°C to 150°C, a pressure of 0.5 MPa to 1 MPa, and a duration of 8 to 15 minutes. Thermal compression bonding is used to ensure good ohmic contact between the conductive composite layer and the crystalline silicon bottom cell, preventing damage to the perovskite top cell caused by high-temperature processes (greater than 150°C).

[0073] The following is a specific embodiment provided by this application. The stacked cell includes a TOPCon bottom cell, an intermediate layer, and a perovskite top cell stacked in a predetermined direction. The intermediate layer includes a conductive composite layer, a metal grid layer, and a barrier layer. The conductive composite layer is made of PEDOT:PSS and FeCl₃ and is 200nm thick. The metal grid layer is made of silver nanowires with a line width of 20nm and a pore size of 200nm. The barrier layer is made of aluminum oxide with a thickness of 5nm.

[0074] Compared with conventional stacked cells using ITO as the intermediate layer, the stacked cell provided in the embodiment of the present application has an intermediate layer sheet resistance of 0.8Ω / sq, a light transmittance of 92% from 800nm ​​to 1200nm, and an interface recombination current (J0) of 0.9fA / cm 2 The sheet resistance of ITO as the intermediate layer is 12Ω / sq, the transmittance from 800nm ​​to 1200nm is 75%, and the interface recombination current (J0) is 5.2fA / cm 2 It can be seen that the intermediate layer of the stacked battery provided in the embodiment of the present application is beneficial to reducing the square resistance, improving the transmittance, and reducing the interface recombination current.

[0075] Compared to conventional tandem cells using ITO as the intermediate layer, the tandem cell provided in the embodiments of the present application has an open circuit voltage (Voc) increased from the conventional 1.82V to 1.94V, a fill factor (FF) increased from the conventional 78% to 83%, and a conversion efficiency (η) increased from the conventional 29.5% to 33.1% (AM1.G, 25°C), significantly improving the performance and efficiency of the tandem cell. The tandem cell provided in the embodiments of the present application has an efficiency retention rate of 98.5% (conventional: 90%) after 1000 hours at a temperature of 85°C and a humidity of 85% RH. After 1000 bend tests (with a curvature radius of 3mm), the resistance change was less than 2% (conventional: greater than 50%), significantly improving the stability of the tandem cell.

[0076] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application, and therefore the scope of protection of the present application shall be based on the scope of protection claimed.

Claims

1. A laminated battery, characterized in that: The invention comprises a crystalline silicon bottom cell, an intermediate layer and a perovskite top cell stacked in sequence along a preset direction, wherein the intermediate layer comprises: A conductive composite layer, the conductive composite layer is located on a surface of the crystalline silicon bottom cell facing the perovskite top cell, and the material of the conductive composite layer includes a conductive polymer and a metal dopant; a metal grid layer, wherein the metal grid layer is embedded in a side of the conductive composite layer away from the crystalline silicon bottom cell, and the conductive composite layer exposes a surface of the metal grid layer away from the conductive composite layer; The barrier layer is located on a side of the metal grid layer away from the composite layer and covers the surfaces of the metal grid layer and the conductive composite layer.

2. The stacked battery according to claim 1, characterized in that The perovskite top cell includes: a perovskite absorption layer and an electron transport layer and a hole transport layer located on opposite sides of the perovskite absorption layer, wherein the hole transport layer is located between the barrier layer and the perovskite absorption layer and contacts the barrier layer.

3. The laminated battery according to claim 2, characterized in that: An interface passivation layer is further included between the perovskite absorption layer and the hole transport layer.

4. The laminated battery according to claim 3, characterized in that: The material of the interface passivation layer includes tetrafluorophenethylamine, 2-phenethylamine, 3,5-difluorophenethylamine, benzamidine hydrochloride or polyethyleneimine.

5. The laminated battery according to claim 1, wherein: The material of the barrier layer includes aluminum oxide, silicon oxide or hafnium oxide.

6. The laminated battery according to claim 1 or 5, characterized in that: The thickness of the barrier layer is 3nm~8nm.

7. The stacked battery according to claim 1, characterized in that: The orthographic projection of the metal grid layer on the surface of the crystalline silicon bottom cell has a hexagonal grid shape.

8. The laminated battery according to claim 7, characterized in that: The hexagonal pore size is 100 nm to 300 nm.

9. The stacked battery according to claim 1, characterized in that: The line width of the metal grid layer is 10nm~30nm.

10. The stacked battery according to claim 1, characterized in that: The material of the conductive polymer includes at least one of PEDOT:PSS or PEDOT:Tos; the material of the metal dopant includes at least one of FeCl3, MoO3 or HAuCl4.

11. A method for manufacturing a stacked battery, characterized in that: include: Preparation of perovskite top cells; depositing a barrier layer on a surface of the perovskite top cell; Spraying a metal grid layer on the surface of the barrier layer away from the perovskite top cell; Spin-coating a conductive composite layer on a side of the metal grid layer away from the barrier layer, wherein the conductive composite layer also fills the gaps in the metal grid layer, wherein the material of the conductive composite layer includes a conductive polymer and a metal dopant, and the barrier layer, the metal grid layer and the conductive composite layer together constitute an intermediate layer; A crystalline silicon bottom cell is placed on the conductive composite layer and then packaged to form the stacked cell.

12. The method for manufacturing a stacked battery according to claim 11, wherein: The preparation of the perovskite top cell comprises: preparing an electron transport layer; forming a perovskite absorption layer on the electron transport layer; Spin-coating an interface passivation layer on a surface of the perovskite absorption layer away from the electron transport layer; Performing ultraviolet ozone treatment on a side of the interface passivation layer away from the perovskite absorption layer; forming a hole transport layer on the interface passivation layer; Depositing a barrier layer on the surface of the perovskite top cell includes: the barrier layer is located on a surface of the hole transport layer away from the interface passivation layer.

13. The method for manufacturing a stacked battery according to claim 12, wherein: The process parameters of the ultraviolet ozone treatment include: wavelength of 150nm~200nm; power of 30W~60W; time of 20s~40s.

14. The method for manufacturing a stacked battery according to claim 11, wherein: In the conductive composite layer, the volume ratio of the conductive polymer to the metal dopant is 4:1 to 6:

1.

15. The method for manufacturing a stacked battery according to claim 11, wherein: The process method for spraying the metal mesh layer is inkjet printing, and the process parameters of the inkjet printing include: ink concentration of 0.2wt%~0.5wt%; temperature of 60℃~80℃; drying time of 20s~60s.

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