Dynamic on-resistance test circuit and device of semiconductor device

Abstract

The invention discloses a dynamic on-resistance test circuit and device of a semiconductor device, which are used for testing the dynamic on-resistance of the semiconductor device. The test circuit comprises a power supply input control circuit, a first change-over switch, a second change-over switch, a half-bridge circuit, a driving switch, an inductor and a first resistor, and on-off states of the power supply input control circuit, the first change-over switch, the second change-over switch, the half-bridge circuit, the driving switch and a semiconductor device to be tested are controlled. The semiconductor device to be tested is enabled to be in different test modes, diversified combined test conditions are provided, accurate test of the dynamic on resistance of the semiconductor device to be tested under different influence factors can be realized, and test requirements of the dynamic on resistance of the semiconductor device to be tested when the semiconductor device to be tested is conducted in the first quadrant and the third quadrant are met.

Description

Technical Field

[0001] The present application relates to the field of detection technology, and in particular to a dynamic on-resistance test circuit and device for a semiconductor device. Background Art

[0002] With the development of power electronics technology, higher conversion efficiency and smaller device size have become the development direction of power electronic systems. The realization of this direction mainly relies on the continuous improvement and breakthroughs of power electronic devices. Therefore, the application field has put forward higher performance requirements for power electronic devices. Power electronic devices, also known as semiconductor devices, have the main function of achieving power conversion and circuit control by switching between on and off states. They are widely used in energy systems, computer systems, aerospace and other fields, and are closely related to people's lives. Currently, GaN semiconductor devices have higher voltage resistance, lower on-resistance, and faster switching speeds than Si-based semiconductor devices. They can further improve the power density and efficiency of power supply systems. They have replaced some Si-based semiconductor devices and are widely used in high-voltage, medium-to-high-power, and high-switching frequency applications.

[0003] For enhanced-mode (E-mode) GaN semiconductor devices, when they are turned on, their circuit impedance is divided into static on-resistance and dynamic on-resistance. The former is the resistance of the device under continuous and stable operating conditions, while the latter is mainly the dynamic on-resistance at the turn-on instant due to current collapse. An increase in dynamic on-resistance can cause abnormal heating, increased losses, reduced efficiency, and even failure due to heat accumulation in devices under high-frequency conditions of high voltage stress. Therefore, it is necessary to test the dynamic on-resistance of E-mode GaN semiconductor devices so that the circuit can be adjusted according to the dynamic on-resistance of the E-mode GaN semiconductor devices and improve the electrical performance of the E-mode GaN semiconductor devices. Summary of the Invention

[0004] The present application provides a dynamic on-resistance test circuit and device for a semiconductor device, which are used to test the dynamic on-resistance of the semiconductor device.

[0005] In a first aspect, an embodiment of the present application provides a dynamic on-resistance test circuit for a semiconductor device, the test circuit comprising: a power input control circuit, a first switching switch, a second switching switch, a half-bridge circuit, a drive switch, an inductor, and a first resistor, wherein the input end of the power input control circuit is used to couple a DC power supply, the first output end is coupled to the first end of the half-bridge circuit, and the second output end is respectively coupled to the second end of the half-bridge circuit, the first test end, and the second end of the first resistor, and the power input control circuit is used to control the conduction or disconnection between the DC power supply and the half-bridge circuit. In addition, the first end of the inductor is respectively coupled to the midpoint of the bridge arm of the half-bridge circuit, the first end of the first switching switch, and the first end of the second switching switch, the second end of the inductor is respectively coupled to the second end of the second switching switch and the first end of the drive switch, the second end of the first switching switch is coupled to the first end of the first resistor, the third end of the first switching switch is coupled to the second end of the drive switch, and the third end of the second switching switch is coupled to the second test end. The first test end is used to couple to the first end of the semiconductor device to be tested, and the second test end is used to couple to the second end of the semiconductor device to be tested. With this arrangement, by controlling the on / off states of the first and second switches, and controlling the on / off states of the power input control circuit, the half-bridge circuit, the drive switch, and the semiconductor device under test, the semiconductor device under test is placed in different test modes, providing a variety of combined test conditions. Therefore, through the mutual coordination of the power input control circuit, the first switch, the second switch, the half-bridge circuit, the drive switch, the inductor, and the first resistor, it is possible to accurately test the dynamic on-resistance of the semiconductor device under test under different influencing factors, and it is also possible to simultaneously meet the dynamic on-resistance test requirements of the semiconductor device under test when it is conducting in the first quadrant and the third quadrant.

[0006] If the semiconductor device to be tested is a GaN semiconductor device (eg, an enhancement-mode GaN semiconductor device), the first end of the semiconductor device to be tested may be the drain of the GaN semiconductor device, and the second end of the semiconductor device to be tested may be the source of the GaN semiconductor device.

[0007] In some embodiments, the power input control circuit includes a first control switch and a second control switch, wherein the first end of the first control switch is coupled to the positive terminal of the DC power supply, and the second end of the first control switch serves as a first output terminal. Furthermore, the first end of the second control switch is coupled to the negative terminal of the DC power supply, and the second end of the second control switch serves as a second output terminal. This arrangement can achieve a simple power input control circuit, making it relatively simple to use. Furthermore, it can not only control the connection and disconnection of the DC power supply, but also reduce production costs.

[0008] In some embodiments, the test circuit further includes: a first capacitor coupled between the first output terminal and the second output terminal, or a second capacitor coupled between the first terminal and the second terminal of the first resistor.

[0009] In some embodiments, a half-bridge circuit includes a first bridge arm switch and a second bridge arm switch, wherein a first end of the first bridge arm switch is coupled to a first output end, a first end of the second bridge arm switch is coupled to a second output end, and a second end of the first bridge arm switch and a second end of the second bridge arm switch are coupled to a bridge arm midpoint. This arrangement can realize a simple half-bridge circuit, thereby simplifying application and reducing production costs.

[0010] In some embodiments, the half-bridge circuit further includes: a second resistor; and the second end of the second bridge arm switch is coupled to the midpoint of the bridge arm through the second resistor, so as to limit the current through the second resistor.

[0011] In some embodiments, the test circuit further includes a clamp circuit coupled to the first detection terminal and the second detection terminal. Thus, the voltage display range of the oscilloscope is limited by the clamp circuit, thereby improving the vertical resolution of the oscilloscope.

[0012] In some embodiments, the clamping circuit includes: a diode, a voltage regulator, a clamping resistor, and a clamping voltage source, wherein the cathode of the diode is coupled to the second detection terminal, the anode of the diode is coupled to the first terminal of the clamping resistor and the cathode of the voltage regulator, the anode of the voltage regulator is coupled to the first detection terminal and the cathode of the clamping voltage source, and the second terminal of the clamping resistor is coupled to the anode of the clamping voltage source.

[0013] In a second aspect, an embodiment of the present application further provides a device for testing the dynamic on-resistance of a semiconductor device, the device comprising: a controller, a data collector, and a dynamic on-resistance test circuit for the semiconductor device. The controller is coupled to the test circuit, and the data collector is coupled to the test circuit. Furthermore, the controller is configured to provide a switching signal to the test circuit for controlling a power input control circuit, a first switching switch, a second switching switch, a half-bridge circuit, a drive switch, and a semiconductor device under test, so as to control the semiconductor device under test to be in different operating modes; wherein the operating modes include a forward conduction hard switching mode, a forward conduction soft switching mode, and a reverse conduction soft switching mode. The data collector is configured to collect the on-voltage and on-current of the semiconductor device under test when the semiconductor device under test is in different operating modes, and determine the dynamic on-resistance of the semiconductor device under test based on the on-voltage and on-current. With this arrangement, by controlling the operating state of the test circuit, the on-resistance of the semiconductor device under test in different operating modes can be measured.

[0014] In some embodiments, when the semiconductor device under test is in a forward conduction hard switching mode, the process includes: a first stage, a second stage, and a third stage;

[0015] In the first stage, the first terminal and the third terminal of the first switching switch are turned on, the second terminal and the third terminal of the second switching switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on;

[0016] In the second stage, the first terminal and the third terminal of the first switching switch are turned on, the second terminal and the third terminal of the second switching switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the drive switch are all turned on;

[0017] In the third stage, the first terminal and the third terminal of the first switch are turned on, the second terminal and the third terminal of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on;

[0018] The data collector is further used to collect the on-state voltage and on-state current of the semiconductor device under test in the third stage, so as to calculate the dynamic on-state resistance of the semiconductor device under test in the forward conduction hard switching mode based on the on-state voltage and on-state current.

[0019] In some embodiments, when the semiconductor device under test is in the forward conduction soft switching mode, it includes: a first stage, a second stage, a third stage, a fourth stage, a fifth stage, a sixth stage and a seventh stage;

[0020] In the first stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on;

[0021] In the second stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit and the first bridge arm switch in the half-bridge circuit are all turned on;

[0022] In the third stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the drive switch are all turned on;

[0023] In the fourth stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch, the second control switch, and the drive switch in the power input control circuit are all turned on;

[0024] In the fifth stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the second bridge arm switch in the half-bridge circuit, and the drive switch are all turned on;

[0025] In the sixth stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit and the second bridge arm switch in the half-bridge circuit are all turned on;

[0026] In the seventh stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the second bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on;

[0027] The data collector is further used to collect the on-state voltage and on-state current of the semiconductor device under test in the seventh stage, so that the dynamic on-state resistance of the semiconductor device under test in the forward conduction soft switching mode can be calculated based on the on-state voltage and on-state current, and the dynamic on-state resistance of the semiconductor device under test when it is turned on in the first quadrant under soft switching can be obtained.

[0028] In some embodiments, when the semiconductor device under test is in the reverse conducting soft switching mode, it includes: a first stage, a second stage, a third stage, a fourth stage, a fifth stage, a sixth stage and a seventh stage;

[0029] In the first stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on;

[0030] In the second stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit and the first bridge arm switch in the half-bridge circuit are all turned on;

[0031] In the third stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the drive switch are all turned on;

[0032] In the fourth stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch, the second control switch, and the drive switch in the power input control circuit are all turned on;

[0033] In the fifth stage, the second end and the third end of the first switch are turned on, the first end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the second bridge arm switch in the half-bridge circuit, and the drive switch are all turned on;

[0034] In the sixth stage, the second end and the third end of the first switch are turned on, the first end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit and the second bridge arm switch in the half-bridge circuit are all turned on;

[0035] In the seventh stage, the second end and the third end of the first switch are turned on, the first end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the second bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on;

[0036] The data collector is further used to collect the on-state voltage and on-state current of the semiconductor device under test in the seventh stage, so that the dynamic on-state resistance of the semiconductor device under test in the reverse conduction soft switching mode can be calculated based on the on-state voltage and on-state current, and the dynamic on-state resistance of the semiconductor device under test when it is turned on in the third quadrant under soft switching can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of the structure of an enhancement-mode GaN semiconductor device using a p-GaN cap layer structure in the related art;

[0038] Figure 2 A schematic structural diagram of a device for testing the dynamic on-resistance of a semiconductor device provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of a circuit structure of a dynamic on-resistance test circuit for a semiconductor device provided in an embodiment of the present application;

[0040] Figure 4 A schematic diagram of a specific circuit structure of a dynamic on-resistance test circuit for a semiconductor device provided in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of a circuit structure for coupling a test circuit provided in an embodiment of the present application with a semiconductor device to be tested;

[0042] Figure 6 A schematic diagram of another circuit structure for coupling a test circuit provided in an embodiment of the present application with a semiconductor device to be tested;

[0043] Figure 7 A schematic diagram of another circuit structure for coupling a test circuit provided in an embodiment of the present application with a semiconductor device to be tested;

[0044] Figure 8 A schematic diagram of another circuit structure of coupling the test circuit 110 provided in an embodiment of the present application with the semiconductor device to be tested;

[0045] Figure 9 A schematic diagram of a specific circuit structure of a dynamic on-resistance test circuit for a semiconductor device provided in an embodiment of the present application.

[0046] Reference numerals

[0047] 100-test device; 110-test circuit; 111-power input control circuit; 112-half-bridge circuit; 113-clamping circuit; 120-controller; 130-data acquisition device; SW1-first switching switch; SW2-second switching switch; Q1-first bridge arm switch; Q2-second bridge arm switch; Q3-drive switch; L-inductor; R1-first resistor; R2-second resistor; VDC-DC power supply; SD1-first test terminal; SD2-second test terminal; M0-bridge arm midpoint; SC1-first control switch; SC2-second control switch; DM-semiconductor device to be tested; C1-first capacitor; C2-second capacitor; VD-diode; ZD-voltage regulator; RD-clamping resistor; VCC-clamping voltage source. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "at least one" means one or more, where "multiple" means two or more. In view of this, in the embodiments of the present application, "multiple" can also be understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the previous and next associated objects are in an "or" relationship. In addition, words such as "first" and "second" are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, in the embodiments of the present application, "coupling" refers to electrical connection, and the coupling of two electrical components can be a direct or indirect connection between the two electrical components. For example, the coupling of A and B can be either a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components. For example, the coupling of A and B can also be a direct connection between A and C, and a direct connection between C and B, with A and B being connected through C.

[0049] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrative purposes and do not represent true proportions.

[0050] The switch in the embodiment of the present application may be one or more of various types of switching devices such as a relay, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a silicon carbide (SiC) MOSFET, a GaN semiconductor device, a Schottky diode, etc., which are not listed one by one in the embodiment of the present application. In addition, each switch may include a first end, a second end and a control end, wherein the control end is used to control the closing or opening of the switch. When the switch is closed, current can be transmitted between the first end and the second end of the switch. When the switch is open, current cannot be transmitted between the first end and the second end of the switch. Taking MOSFET as an example, the control end of the switch is the gate, the first end of the switch may be the source, the second end may be the drain, or the first end may be the drain and the second end may be the source.

[0051] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, its specific application scenario is first explained below.

[0052] Traditional silicon (Si)-based semiconductor devices not only suffer from low energy efficiency, but also, after years of development, their performance has approached the theoretical limits of silicon materials. The discovery and research of semiconductor devices that can replace Si-based semiconductor devices has become a key direction in the development of power electronics technology in recent years. Various semiconductor devices developed using the third-generation semiconductor material gallium nitride (GaN) have seen rapid development. Compared to traditional Si semiconductor devices, GaN semiconductor devices, due to their material properties, can operate at higher voltage stresses, faster switching frequencies, and have a wider temperature tolerance, making them more suitable for high-frequency, high-power density applications.

[0053] Unlike Si-based semiconductor devices that form a conductive channel through a PN junction, GaN semiconductor devices form a two-dimensional electron gas (2DEG) conductive channel through the extremely strong spontaneous polarization and piezoelectric polarization effect at the interface between GaN and AlGaN. The difference in the conductive channel results in a different conductive mechanism of the device. GaN semiconductor devices include depletion-mode GaN semiconductor devices and enhancement-mode (E-mode) GaN semiconductor devices. Since a negative voltage signal must be continuously applied to the depletion-mode GaN semiconductor device in the off state, this not only complicates the circuit design, but also increases the power consumption of the entire system. Therefore, the design and application of power electronic systems tend to use enhancement-mode GaN semiconductor devices, and the development and application of enhancement-mode GaN semiconductor devices have also become a current research hotspot. At present, enhancement-mode GaN semiconductor devices with a p-GaN cap layer structure are generally used to realize GaN high electron mobility transistors (HEMTs). Its basic structure refers to Figure 1 , Figure 1 FIG1 is a schematic diagram of the structure of an enhancement-mode GaN semiconductor device using a p-GaN capping layer structure in the related art. Of course, the structure of the enhancement-mode GaN semiconductor device can also be other structures, which are not limited here.

[0054] However, enhancement-mode GaN semiconductor devices also face a series of reliability issues and challenges in practical applications. Among them, the current collapse effect is the most significant and has the greatest impact. The current collapse effect manifests itself in the specific device parameters as dynamic on-resistance. Dynamic on-resistance refers to the temporary increase in on-resistance and decrease in maximum drain current of an enhancement-mode GaN semiconductor device when a high voltage is applied to the device in the off state and then switched to the on state. This dynamic on-resistance phenomenon not only makes it impossible to predict and calculate the specific conduction losses of enhancement-mode GaN semiconductor devices in practical applications, but also has a significant impact on the reliability and operating life of the entire system using enhancement-mode GaN semiconductor devices. Furthermore, device manufacturers do not specify the dynamic on-resistance parameter in their data sheets, and continue to use the traditional static on-resistance parameter as the on-resistance of enhancement-mode GaN semiconductor devices. This clearly does not reflect the actual characteristics of enhancement-mode GaN semiconductor device parameters. Therefore, understanding the mechanism and variation of the dynamic on-resistance of enhancement-mode GaN semiconductor devices and proposing optimization methods are of great guiding significance for the design and application of power electronics systems.

[0055] The dynamic on-resistance phenomenon in enhancement-mode GaN semiconductor devices is related to charge trapping and detrapping within the device channel and between different layers: when the device is off, electrons are trapped outside the channel; when the device is turned on, these trapped electrons are unable to fully return to the channel to participate in the conduction process. Charge trapping and detrapping occur through two mechanisms:

[0056] Mechanism 1: When the enhancement-mode GaN semiconductor device is in the off-state, a high voltage is applied between its drain, source, and gate, and a large number of electrons are injected into the buffer layer and captured by holes in the buffer layer. The greater the off-state voltage stress and the longer the off-state voltage stress lasts, the more electrons are trapped. However, after the device is turned on, it cannot provide more energy to capture the trapped electrons into the channel, thereby exacerbating the dynamic on-resistance phenomenon. At the same time, the drain current of the device in the on-state also affects the dynamic on-resistance. The larger the drain current, the more electrons need to participate in the conduction, and the less affected by the dynamic on-resistance phenomenon; conversely, the smaller the drain current, the more obvious the dynamic on-resistance phenomenon is on the device. Therefore, the off-state voltage stress, the off-state voltage stress duration, and the drain current (or load current) are three factors affecting the dynamic on-resistance.

[0057] Mechanism 2: During hard switching, the drain and source of enhancement-mode GaN semiconductor devices experience high voltage stress and high current simultaneously. A large number of hot electrons in the 2DEG (2DEG) move outward and are injected into the vicinity of the gate and drain surfaces and into the buffer layer, where they are captured by holes in these regions. Conversely, during soft switching, since the drain and source do not experience high voltage and high current simultaneously, they cannot provide sufficient electric field energy to accelerate the outward movement of a large number of hot electrons and capture them. The number of captured electrons is lower than in the hard switching state, and the decapture energy required to maintain electron balance in the channel is also reduced, making dynamic on-resistance less likely to occur. In addition to soft / hard switching conditions, when the device operates at high frequency in an actual converter, changes in switching frequency and duty cycle can be seen as changes in the on and off times within each cycle, which also affect the dynamic on-resistance.

[0058] Furthermore, in power electronics systems, due to the presence of inductive loads, parasitic line inductance, and transformer magnetizing inductance, forward-conducting semiconductor devices often require reverse-conducting diodes to provide a freewheeling circuit for the inductors. Due to the unique lateral symmetry of enhancement-mode GaN semiconductor devices, while they lack the PN body diode of metal oxide semiconductor field-effect transistors (MOSFETs), they can still conduct current in the reverse direction through their lateral conduction channel, offering the advantage of zero reverse recovery losses. Generally speaking, with the exception of a few current-controlled circuits, the vast majority are voltage-controlled. Circuits such as rectification, inversion, and bidirectional DC / DC circuits all require bidirectional conduction performance in switching transistors, making research on their third-quadrant (or reverse) freewheeling capability crucial. Because enhancement-mode GaN semiconductor devices have symmetrical lateral channels, they can achieve bidirectional current conduction in both the first and third quadrants through the same 2DEG conductive channel. Consequently, enhancement-mode GaN semiconductor devices can be used as switches in rectification, inversion, and bidirectional DC / DC circuits. However, when enhancement-mode GaN semiconductor devices achieve first-quadrant and third-quadrant conduction, there will be a dynamic on-resistance problem.

[0059] Based on the above analysis, the main factors affecting the dynamic on-resistance of GaN semiconductor devices include: off-state voltage stress, off-state voltage stress duration, load current, switching conditions (i.e., soft switching and hard switching), switching frequency, and duty cycle. Currently, traditional dynamic on-resistance test equipment for GaN semiconductor devices is difficult to test all of these factors, and the same test equipment cannot simultaneously meet the requirements for testing the dynamic on-resistance of GaN semiconductor devices when conducting in the first and third quadrants.

[0060] To solve the above problems, the embodiments of the present application provide a dynamic on-resistance test circuit and device for measuring the dynamic on-resistance of semiconductor devices, which can realize accurate testing of the dynamic on-resistance of semiconductor devices under different influencing factors in the same test circuit and test device, and can also simultaneously meet the test requirements of the dynamic on-resistance of semiconductor devices when they are turned on in the first quadrant and the third quadrant.

[0061] Figure 2 A schematic diagram of a structure of a dynamic on-resistance test device for a semiconductor device according to an embodiment of the present application, referring to Figure 2The test device 100 may include: a controller 120, a data collector 130, and a dynamic on-resistance test circuit 110 for a semiconductor device. The test circuit 110 is coupled to the semiconductor device to be tested, the controller 120 is coupled to the test circuit 110, and the data collector 130 is coupled to the test circuit 110. When the test device is working, the controller 120 is used to provide a switching signal to the test circuit 110 to control the semiconductor device to be tested to be in different working modes. The data collector 130 is used to collect the on-voltage and on-current of the semiconductor device to be tested when the semiconductor device to be tested is in different working modes, and determine the dynamic on-resistance of the semiconductor device to be tested based on the on-voltage and on-current. With this arrangement, by controlling the working state of the test circuit 110, the on-resistance of the semiconductor device to be tested in different working modes can be measured. Among them, the working mode includes forward conduction hard switching mode, forward conduction soft switching mode and reverse conduction soft switching mode, that is, the test device in the embodiment of the present application can measure the on-resistance of the semiconductor device to be tested in the forward conduction hard switching mode, the on-resistance in the forward conduction soft switching mode, and the on-resistance in the reverse conduction soft switching mode.

[0062] For example, the controller 120 may be a digital signal processing (DSP) chip. By controlling the operation of the test circuit 110 through the DSP chip, one-stop, fully dynamic parameter automated testing of the dynamic on-resistance of a semiconductor device can be achieved, as well as automatic control of the on and off of switches in the test circuit 110 and the operation of the protection modules of the test circuit 110.

[0063] It is understood that the structure shown in the embodiment of the present application does not constitute a specific limitation on the test device. In other embodiments of the present application, the test device may include Figure 2 More or fewer components than those shown in the figures may be used, some components may be combined, some components may be separated, or different component arrangements may be used. Figure 2 The components shown can be implemented in hardware, software, or a combination of software and hardware.

[0064] Figure 3 A circuit structure diagram of a dynamic on-resistance test circuit for a semiconductor device provided in an embodiment of the present application, referring to Figure 3 The dynamic on-resistance test circuit 110 of the semiconductor device may include: a power input control circuit 111, a first switch SW1, a second switch SW2, a half-bridge circuit 112, a drive switch Q3, an inductor L, and a first resistor R1. For example, the input end of the power input control circuit 111 is used to couple the DC power supply V DCThe first output terminal is coupled to the first end of the half-bridge circuit 112, and the second output terminal is coupled to the second end of the half-bridge circuit 112, the first test terminal SD1, and the second end of the first resistor R1. Thus, the power input control circuit 111 controls the connection or disconnection between the DC power supply VDC and the half-bridge circuit 112, thereby connecting the DC power supply VDC to the test circuit 110. Furthermore, the first end of the inductor L is coupled to the midpoint M0 of the bridge arm of the half-bridge circuit 112, the first end of the first switch SW1, and the first end of the second switch SW2. The second end of the inductor L is coupled to the second end of the second switch SW2 and the first end of the drive switch Q3. The second end of the first switch SW1 is coupled to the first end of the first resistor R1, the third end of the first switch SW1 is coupled to the second end of the drive switch Q3, and the third end of the second switch SW2 is coupled to the second test terminal SD2. The first test terminal SD1 is coupled to the first end of the semiconductor device under test, and the second test terminal SD2 is coupled to the second end of the semiconductor device under test. With this arrangement, by controlling the on / off states of the first switch SW1 and the second switch SW2, the semiconductor device under test can be placed in different test modes, thereby providing a variety of combined test conditions for the semiconductor device under test. Furthermore, the controller 120 is coupled to the control terminal of the power input control circuit 111, the control terminal of the first switch SW1, the control terminal of the second switch SW2, the control terminal of the half-bridge circuit 112, and the control terminal of the drive switch Q3. After coupling the semiconductor device under test to the test circuit 110, the controller 120 is further coupled to the control terminal of the semiconductor device under test. The controller 120 then outputs switching signals to the power input control circuit 111, the first switch SW1, the second switch SW2, the half-bridge circuit 112, the drive switch Q3, and the semiconductor device under test, respectively, to control the on / off states of the power input control circuit 111, the first switch SW1, the second switch SW2, the half-bridge circuit 112, the drive switch Q3, and the semiconductor device under test, thereby controlling the semiconductor device under test to be in different operating modes. That is to say, through the mutual cooperation of the power input control circuit 111, the first switching switch SW1, the second switching switch SW2, the half-bridge circuit 112, the drive switch Q3, the inductor L and the first resistor R1, the dynamic on-resistance of the semiconductor device under test under different influencing factors can be accurately tested, and the test requirements of the dynamic on-resistance of the semiconductor device under test when it is turned on in the first quadrant and the third quadrant can be simultaneously met.

[0065] In a specific implementation, the semiconductor device to be tested may be a GaN semiconductor device (such as an enhancement-mode GaN semiconductor device), and the first end of the semiconductor device to be tested may be the drain of the GaN semiconductor device, and the second end of the semiconductor device to be tested may be the source of the GaN semiconductor device.

[0066] Figure 4 A specific circuit structure diagram of a dynamic on-resistance test circuit for a semiconductor device provided in an embodiment of the present application, referring to Figure 4 The power input control circuit 111 includes a first control switch SC1 and a second control switch SC2. The first end of the first control switch SC1 is coupled to the positive electrode of the DC power supply VDC, and the second end of the first control switch SC1 serves as a first output end. Furthermore, the first end of the second control switch SC2 is coupled to the negative electrode of the DC power supply VDC, and the second end of the second control switch SC2 serves as a second output end. This configuration achieves a simple-structured power input control circuit 111, making it easier to use. This not only allows for controlling the connection and disconnection of the DC power supply VDC, but also reduces production costs. In a specific application, the controller 120 can be coupled to the control end of the first control switch SC1 and the control end of the second control switch SC2, and output a switching signal to the first control switch SC1 and the second control switch SC2 to control the connection and disconnection of the first control switch SC1 and the second control switch SC2.

[0067] Reference Figure 4 The half-bridge circuit 112 includes a first bridge arm switch Q1 and a second bridge arm switch Q2. The first end of the first bridge arm switch Q1 is coupled to the first output end, the first end of the second bridge arm switch Q2 is coupled to the second output end, and the second end of the first bridge arm switch Q1 and the second end of the second bridge arm switch Q2 are coupled to the bridge arm midpoint M0. This configuration enables a simple half-bridge circuit 112, making it easier to implement and reducing production costs. In a specific application, the controller 120 can be coupled to the control end of the first bridge arm switch Q1 and the control end of the second bridge arm switch Q2, and output switching signals to the first bridge arm switch Q1 and the second bridge arm switch Q2 to control the on and off of the first bridge arm switch Q1 and the second bridge arm switch Q2.

[0068] Figure 5 A schematic diagram of a circuit structure for coupling a test circuit and a semiconductor device to be tested provided in an embodiment of the present application, referring to Figure 5 The controller 120 can provide switching signals to the first control switch SC1, the second control switch SC2, the first bridge arm switch Q1, the second bridge arm switch Q2, the first switching switch SW1, the second switching switch SW2, the drive switch Q3, and the semiconductor device under test DM to control their on and off states, thereby controlling the semiconductor device under test DM to operate in different operating modes. The operating modes include a forward conduction hard switching mode, a forward conduction soft switching mode, and a reverse conduction soft switching mode. The operating process of each operating mode is described below.

[0069] 1. Forward conduction hard switching mode: The semiconductor device under test DM in the forward conduction hard switching mode includes: a first stage, a second stage, and a third stage.

[0070] In the first stage, refer to Figure 6 , Figure 6 Another circuit structure diagram of the test circuit provided in an embodiment of the present application coupled with the semiconductor device under test. The controller 120 controls the first and third terminals of the first switching switch SW1 to be turned on, and the second and third terminals of the second switching switch SW2 to be turned on. Furthermore, the controller 120 controls the first control switch SC1, the second control switch SC2, the first bridge arm switch Q1, and the semiconductor device under test DM to be turned on, and controls the remaining switches to be turned off. In this stage, a first high-level drive pulse signal with a long pulse width is input to the control terminal of the semiconductor device under test DM, and the semiconductor device under test DM is turned on. Furthermore, the DC power supply VDC charges the inductor L through the first bridge arm switch Q1, thereby implementing a current building process for the inductor L. Based on this, the load current (i.e., the inductor L current), a test influencing factor of the dynamic on-resistance of the semiconductor device under test DM, can be changed by changing the length of the charging time of the inductor L in this stage, i.e., changing the duration of this stage.

[0071] In the second stage, refer to Figure 6 Controller 120 controls the first and third terminals of the first switching switch SW1 to be conductive, and the second and third terminals of the second switching switch SW2 to be conductive. Furthermore, controller 120 controls the first control switch SC1, the second control switch SC2, the first bridge arm switch Q1, and the drive switch Q3 to be conductive, and controls the remaining switches to be disconnected. During this phase, a low-level signal is input to the control terminal of the semiconductor device under test DM, disconnecting the semiconductor device under test DM and allowing the inductor L to continue flowing. The current in inductor L remains substantially constant during this phase. Based on this, by controlling the duration of this phase, another test factor influencing the dynamic on-resistance of the semiconductor device under test DM—the duration of the off-state voltage stress—can be controlled.

[0072] In the third stage, refer to Figure 6 , the controller 120 controls the first and third terminals of the first switching switch SW1 to be turned on, and the second and third terminals of the second switching switch SW2 to be turned on. In addition, the controller 120 also controls the first control switch SC1, the second control switch SC2, the first bridge arm switch Q1, and the semiconductor device under test DM to be turned on, and controls the remaining switches to be turned off. In this stage, the control terminal of the semiconductor device under test DM inputs a second high-level driving pulse signal with a shorter pulse width, and the semiconductor device under test DM is turned on. In addition, this stage is a key stage for testing the dynamic on-resistance. The data collector 130 can collect the on-voltage V of the semiconductor device under test DM during this stage. D1and the conduction current I D1 , and based on the on-state voltage V D1 and the conduction current I D1 Determine the dynamic on-resistance value of the semiconductor device under test DM. For example, the data collector 130 can measure the on-state voltage waveform of the semiconductor device under test DM during the on-state period and calculate its on-state voltage average value V DS , the average on-state voltage V DS That is the on-state voltage V D1 In addition, the data collector 130 can also collect the drain current I of the semiconductor device to be tested at this stage. DS , the drain current I DS That is the conduction current I D1 , and then calculate the final dynamic on-resistance value.

[0073] In summary, by controlling the operation of test circuit 110, the semiconductor device under test can be placed in a forward-conducting hard-switching mode, thereby enabling dynamic on-resistance testing of the semiconductor device under test under hard-switching conditions. Furthermore, another test factor affecting the semiconductor device under test—off-state voltage stress—can be addressed by adjusting the output voltage of DC power supply VDC before the first stage.

[0074] 2. Forward conduction soft switching mode: The semiconductor device under test DM in the forward conduction soft switching mode includes: the first stage, the second stage, the third stage, the fourth stage, the fifth stage, the sixth stage and the seventh stage.

[0075] In the first stage, refer to Figure 7 , Figure 7 A schematic diagram of another circuit structure for coupling a test circuit and a semiconductor device under test provided in an embodiment of the present application. The controller 120 controls the second and third terminals of the first switching switch SW1 to be conductive, and the second and third terminals of the second switching switch SW2 to be conductive. Furthermore, the controller 120 controls the first control switch SC1, the second control switch SC2, the first bridge arm switch Q1, and the semiconductor device under test DM to be conductive, and controls the remaining switches to be disconnected. During this phase, a high-level signal is input to the control terminal of the semiconductor device under test DM, turning on the semiconductor device under test DM. Furthermore, the DC power supply VDC charges the inductor L through the first bridge arm switch Q1, causing the current in the inductor L to increase.

[0076] In the second stage, refer to Figure 7, the controller 120 controls the second and third terminals of the first switching switch SW1 to be conductive, and the second and third terminals of the second switching switch SW2 to be conductive. Furthermore, the controller 120 controls the first control switch SC1, the second control switch SC2, and the first bridge arm switch Q1 to be conductive, and controls the remaining switches to be disconnected. During this phase, a low-level signal is input to the control terminal of the semiconductor device under test DM, disconnecting the semiconductor device under test DM. The inductor L resonates with the parasitic capacitances at the drain and source terminals of the driver switch Q3 and the semiconductor device under test DM. The capacitance at the driver switch Q3 is discharged, while the capacitance at the driver switch DM is charged. The current value of the inductor L decreases slightly. If the voltage at the driver switch Q3 drops to zero, a high-level signal is input to the control terminal of the driver switch Q3, causing the driver switch Q3 to achieve zero-voltage turn-on.

[0077] In the third stage, refer to Figure 7 Controller 120 controls the second and third terminals of first switch SW1 to be conductive, and the second and third terminals of second switch SW2 to be conductive. Furthermore, controller 120 controls the first control switch SC1, second control switch SC2, first bridge arm switch Q1, and drive switch Q3 to be conductive, and controls the remaining switches to be disconnected. During this phase, when the voltage across drive switch Q3 drops to zero, a high-level signal is input to the control terminal of drive switch Q3, causing drive switch Q3 to achieve zero-voltage turn-on. Furthermore, during this phase, the DC power supply VDC and inductor L supply power to first resistor R1, causing the current in inductor L to decrease.

[0078] In the fourth stage, refer to Figure 7 , the controller 120 controls the second and third terminals of the first switching switch SW1 to be conductive, and the second and third terminals of the second switching switch SW2 to be conductive. Furthermore, the controller 120 controls the first control switch SC1, the second control switch SC2, and the drive switch Q3 in the power input control circuit 111 to be conductive, and controls the remaining switches to be disconnected. During this phase, the inductor L resonates with the parasitic capacitance across the drain and source of the first and second bridge arm switches Q1 and Q2, discharging the capacitance across the second bridge arm switch Q2 and charging the capacitance across the first bridge arm switch Q1. If the voltage across the second bridge arm switch Q2 drops to zero, a high-level signal is input to the control terminal of the second bridge arm switch Q2, causing the second bridge arm switch Q2 to be turned on at zero voltage.

[0079] In the fifth stage, refer to Figure 7Controller 120 turns on the second and third terminals of first switch SW1 and second and third terminals of second switch SW2. Controller 120 also turns on first control switch SC1, second control switch SC2, second bridge arm switch Q2, and drive switch Q3, and turns off all other switches. During this phase, inductor L supplies energy to first resistor R1, causing the current in inductor L to decrease. At this point, the semiconductor device under test DM has a forward withstand voltage.

[0080] In the sixth stage, refer to Figure 7 Controller 120 controls the second and third terminals of first switch SW1 to be conductive, and the second and third terminals of second switch SW2 to be conductive. Controller 120 also controls the first control switch SC1, the second control switch SC2, and the second bridge arm switch Q2 to be conductive, and controls the remaining switches to be disconnected. During this phase, inductor L resonates with the parasitic capacitance across the drain and source of drive switch Q3 and the semiconductor device under test DM, discharging the capacitance across the semiconductor device under test DM. If the voltage across the semiconductor device under test DM drops to zero, a high-level signal is input to the control terminal of the semiconductor device under test DM, causing the semiconductor device under test DM to turn on at zero voltage.

[0081] In the seventh stage, refer to Figure 7 , the controller 120 controls the second and third terminals of the first switching switch SW1 to be turned on, and the second and third terminals of the second switching switch SW2 to be turned on, and the controller 120 also controls the first control switch SC1, the second control switch SC2, the second bridge arm switch Q2, and the semiconductor device under test DM to be turned on. In this stage, when the voltage across the semiconductor device under test DM drops to zero, a high-level signal is input to the control terminal of the semiconductor device under test DM, and the semiconductor device under test DM is turned on at zero voltage. In addition, this stage is a key stage for testing the dynamic on-resistance. The data collector 130 can collect the on-voltage V of the semiconductor device under test DM at this stage. D2 and the conduction current I D2 , and based on the on-state voltage V D2 and the conduction current I D2 Determine the dynamic on-resistance value of the semiconductor device under test DM. For example, the data collector 130 can measure the on-state voltage waveform of the semiconductor device under test DM during the on-state period and calculate its on-state voltage average value V DS , the average on-state voltage V DS That is the on-state voltage V D2 In addition, the data collector 130 can also collect the drain current I of the semiconductor device DM under test at this stage. DS , the drain current I DS That is the conduction current I D2, and then calculate the final dynamic on-resistance value.

[0082] In summary, by controlling the operation of the test circuit, the semiconductor device under test can be placed in a forward-conducting soft-switching mode, thereby enabling dynamic on-resistance testing of the semiconductor device under test during first-quadrant conduction under soft-switching conditions. Furthermore, with respect to switching frequency and duty cycle, another factor influencing the test of the semiconductor device under test, dynamic on-resistance testing of the semiconductor device under test can be achieved under different switching frequencies and duty cycles by adjusting the duration from the start of the first stage to the end of the seventh stage.

[0083] 3. Reverse conduction soft switching mode: When the semiconductor device under test DM is in the forward conduction soft switching mode, the following stages are included: first stage, second stage, third stage, fourth stage, fifth stage, sixth stage and seventh stage.

[0084] In the first stage, refer to Figure 7 Controller 120 turns on the second and third terminals of first switch SW1 and second and third terminals of second switch SW2. Controller 120 also turns on the first control switch SC1, second control switch SC2, first bridge arm switch Q1, and semiconductor device under test DM, and turns off all other switches. During this phase, a high-level signal is input to the control terminal of semiconductor device under test DM, turning it on. Furthermore, DC power supply VDC charges inductor L through first bridge arm switch Q1, causing the current in inductor L to increase.

[0085] In the second stage, refer to Figure 7 , the controller 120 controls the second and third terminals of the first switching switch SW1 to be conductive, and the second and third terminals of the second switching switch SW2 to be conductive. Furthermore, the controller 120 controls the first control switch SC1, the second control switch SC2, and the first bridge arm switch Q1 to be conductive, and controls the remaining switches to be disconnected. During this phase, a low-level signal is input to the control terminal of the semiconductor device under test DM, disconnecting the semiconductor device under test DM. The inductor L resonates with the parasitic capacitances at the drain and source terminals of the driver switch Q3 and the semiconductor device under test DM. The capacitance at the driver switch Q3 is discharged, while the capacitance at the driver switch DM is charged. The current value of the inductor L decreases slightly. If the voltage at the driver switch Q3 drops to zero, a high-level signal is input to the control terminal of the driver switch Q3, causing the driver switch Q3 to achieve zero-voltage turn-on.

[0086] In the third stage, refer to Figure 7Controller 120 controls the second and third terminals of first switch SW1 to be conductive, and the second and third terminals of second switch SW2 to be conductive. Furthermore, controller 120 controls the first control switch SC1, second control switch SC2, first bridge arm switch Q1, and drive switch Q3 to be conductive, and controls the remaining switches to be disconnected. During this phase, when the voltage across drive switch Q3 drops to zero, a high-level signal is input to the control terminal of drive switch Q3, causing drive switch Q3 to achieve zero-voltage turn-on. Furthermore, during this phase, the DC power supply VDC and inductor L supply power to first resistor R1, causing the current in inductor L to decrease.

[0087] In the fourth stage, refer to Figure 7 , the controller 120 controls the second and third terminals of the first switching switch SW1 to be conductive, and the second and third terminals of the second switching switch SW2 to be conductive. Furthermore, the controller 120 controls the first control switch SC1, the second control switch SC2, and the drive switch Q3 in the power input control circuit 111 to be conductive, and controls the remaining switches to be disconnected. During this phase, the inductor L resonates with the parasitic capacitance across the drain and source of the first and second bridge arm switches Q1 and Q2, discharging the capacitance across the second bridge arm switch Q2 and charging the capacitance across the first bridge arm switch Q1. If the voltage across the second bridge arm switch Q2 drops to zero, a high-level signal is input to the control terminal of the second bridge arm switch Q2, causing the second bridge arm switch Q2 to be turned on at zero voltage.

[0088] In the fifth stage, refer to Figure 8 , Figure 8 This is another circuit diagram of the coupling of the test circuit 110 and the semiconductor device under test provided in an embodiment of the present application. The controller 120 controls the second and third terminals of the first switching switch SW1 to be conductive, and the first and third terminals of the second switching switch SW2 to be conductive. Furthermore, the controller 120 controls the first control switch SC1, the second control switch SC2, the second bridge arm switch Q2, and the drive switch Q3 to be conductive, and controls the remaining switches to be disconnected. During this phase, the inductor L provides energy to the first resistor R1, causing the current in the inductor L to decrease, and the semiconductor device under test DM to withstand reverse voltage.

[0089] In the sixth phase, the controller 120 controls the second and third terminals of the first switch SW1 to be conductive, the first and third terminals of the second switch SW2 to be conductive, and the first and third terminals of the second switch SW2 to be conductive. Furthermore, the controller 120 controls the first control switch SC1, the second control switch SC2, and the second bridge arm switch Q2 to be conductive, and controls the remaining switches to be disconnected. During this phase, the inductor L resonates with the parasitic capacitance across the drain and source of the drive switch Q3 and the semiconductor device under test DM, discharging the capacitance across the semiconductor device under test DM. If the voltage across the semiconductor device under test DM drops to zero, a high-level signal is input to the control terminal of the semiconductor device under test DM, causing the semiconductor device under test DM to turn on at zero voltage.

[0090] In the seventh stage, the controller 120 controls the second and third terminals of the first switching switch SW1 to be turned on, and the first and third terminals of the second switching switch SW2 to be turned on. In addition, the controller 120 also controls the first control switch SC1, the second control switch SC2, the second bridge arm switch Q2, and the semiconductor device under test DM to be turned on. In this stage, when the voltage across the two terminals of the semiconductor device under test DM drops to zero, a high-level signal is input to the control terminal of the semiconductor device under test DM, and the semiconductor device under test DM is turned on at zero voltage. In addition, this stage is a key stage for testing the dynamic on-resistance. The data collector 130 can collect the on-voltage V of the semiconductor device under test DM during this stage. D3 and the conduction current I D23 , and based on the on-state voltage V D3 and the conduction current I D3 Determine the dynamic on-resistance value of the semiconductor device under test DM. For example, the data collector 130 can measure the on-state voltage waveform of the semiconductor device under test DM during the on-state period and calculate its on-state voltage average value V DS , the average on-state voltage V DS That is the on-state voltage V D3 In addition, the data collector 130 can also collect the drain current I of the semiconductor device DM under test at this stage. DS , the drain current I DS That is the conduction current I D3 , and then calculate the final dynamic on-resistance value.

[0091] In summary, by controlling the operation of test circuit 110, the semiconductor device under test can be placed in a forward-conducting soft-switching mode, thereby enabling dynamic on-resistance testing of the semiconductor device under test during third-quadrant conduction under soft-switching conditions. Furthermore, with respect to switching frequency and duty cycle, another factor influencing the test of the semiconductor device under test, dynamic on-resistance testing of the semiconductor device under test can be achieved under different switching frequency and duty cycle conditions by adjusting the duration from the start of the first stage to the end of the seventh stage.

[0092] Figure 9 A specific circuit structure diagram of a dynamic on-resistance test circuit for a semiconductor device provided in an embodiment of the present application, referring to Figure 9 The liquid crystal display panel in this embodiment is modified with respect to the test circuit 110 in the above embodiment. The similarities are not repeated here. The difference is that the test circuit 110 also includes: a first capacitor C1, a second capacitor C2 and a clamping circuit 113, wherein the first capacitor C1 is coupled to the first capacitor C1 between the first output terminal and the second output terminal, the second capacitor C2 is coupled between the first end and the second end of the first resistor R1, and the clamping circuit 113 is coupled to the first detection terminal and the second detection terminal, so as to limit the voltage display range of the oscilloscope through the clamping circuit 113 and improve the vertical resolution of the oscilloscope. In addition, the half-bridge circuit 112 also includes a second resistor R2, and the second end of the second bridge arm switch Q2 is coupled to the midpoint of the bridge arm through the second resistor R2, and the current is limited by the second resistor R2. It is understandable that the clamping circuit in the embodiment of the present application can be set to various topologies, which are not specifically limited here.

[0093] It is worth mentioning that Figure 9 The working process of the test circuit 110 shown can refer to the above Figure 4 The working process of the test circuit 110 is not described in detail here.

[0094] The above content is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, and they should all be covered by the protection scope of the present application.

Claims

1. A dynamic on-resistance test circuit for a semiconductor device, characterized in that: include: A power input control circuit, a first switch, a second switch, a half-bridge circuit, a drive switch, an inductor, and a first resistor; The input end of the power input control circuit is used to couple a DC power supply, the first output end is coupled to the first end of the half-bridge circuit, and the second output end is coupled to the second end of the half-bridge circuit, the first test end, and the second end of the first resistor, respectively. The power input control circuit is used to control the conduction or disconnection between the DC power supply and the half-bridge circuit; The first end of the inductor is coupled to the midpoint of the bridge arm of the half-bridge circuit, the first end of the first switch, and the first end of the second switch, respectively; the second end of the inductor is coupled to the second end of the second switch and the first end of the drive switch, respectively; The second end of the first switch is coupled to the first end of the first resistor, and the third end of the first switch is coupled to the second end of the driving switch; The third terminal of the second switch is coupled to the second test terminal; The first test end is used to couple to a first end of a semiconductor device to be tested, and the second test end is used to couple to a second end of the semiconductor device to be tested.

2. The test circuit according to claim 1, wherein: The power input control circuit includes a first control switch and a second control switch; The first end of the first control switch is used to couple to the positive electrode of the DC power supply, and the second end of the first control switch serves as the first output end; The first end of the second control switch is used to couple to the negative electrode of the DC power supply, and the second end of the second control switch serves as the second output end.

3. The test circuit according to claim 1 or 2, characterized in that: Also includes: A first capacitor coupled between the first output terminal and the second output terminal, or a second capacitor coupled between the first terminal and the second terminal of the first resistor.

4. The test circuit according to any one of claims 1 to 3, wherein: The half-bridge circuit comprises: a first bridge arm switch and a second bridge arm switch; The first end of the first bridge arm switch is coupled to the first output end, the first end of the second bridge arm switch is coupled to the second output end, and the second end of the first bridge arm switch and the second end of the second bridge arm switch are coupled to the bridge arm midpoint.

5. The test circuit according to claim 4, wherein: The half-bridge circuit further includes: a second resistor; and a second end of the second bridge arm switch is coupled to the bridge arm midpoint via the second resistor.

6. The test circuit according to any one of claims 1 to 5, characterized in that: A clamping circuit is also included, and the clamping circuit is coupled to the first detection terminal and the second detection terminal.

7. A device for testing the dynamic on-resistance of a semiconductor device, characterized in that: include: A controller, a data collector, and a dynamic on-resistance test circuit for a semiconductor device according to any one of claims 1 to 6; The controller is coupled to the test circuit and is configured to provide a switching signal to the test circuit for controlling the power input control circuit, the first switch, the second switch, the half-bridge circuit, the drive switch, and the semiconductor device under test, so as to control the semiconductor device under test to operate in different operating modes; wherein the operating modes include a forward conducting hard switching mode, a forward conducting soft switching mode, and a reverse conducting soft switching mode; The data collector is coupled to the test circuit and is used to collect the on-state voltage and on-state current of the semiconductor device under test when the semiconductor device under test is in different operating modes, and determine the dynamic on-state resistance of the semiconductor device under test based on the on-state voltage and the on-state current.

8. The testing device according to claim 7, wherein: When the semiconductor device under test is in the forward conduction hard switching mode, the process includes: a first stage, a second stage and a third stage; In the first stage, the first end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on; In the second stage, the first terminal and the third terminal of the first switch are turned on, the second terminal and the third terminal of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the drive switch are all turned on; In the third stage, the first end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on; The data collector is further configured to collect the on-state voltage and on-state current of the semiconductor device under test in the third stage.

9. The testing device according to claim 7 or 8, characterized in that: When the semiconductor device to be tested is in the forward conduction soft switching mode, the process includes: a first stage, a second stage, a third stage, a fourth stage, a fifth stage, a sixth stage and a seventh stage; In the first stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on; In the second stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit and the first bridge arm switch in the half-bridge circuit are all turned on; In the third stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the drive switch are all turned on; In the fourth stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, as well as the drive switch, are all turned on; In the fifth stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the second bridge arm switch in the half-bridge circuit, and the drive switch are all turned on; In the sixth stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit and the second bridge arm switch in the half-bridge circuit are all turned on; In the seventh stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the second bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on; The data collector is further configured to collect the on-state voltage and on-state current of the semiconductor device under test in the seventh stage.

10. The testing device according to any one of claims 7 to 9, characterized in that: When the semiconductor device to be tested is in the reverse conducting soft switching mode, the process includes: a first stage, a second stage, a third stage, a fourth stage, a fifth stage, a sixth stage and a seventh stage; In the first stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on; In the second stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit and the first bridge arm switch in the half-bridge circuit are all turned on; In the third stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the first bridge arm switch in the half-bridge circuit, and the drive switch are all turned on; In the fourth stage, the second end and the third end of the first switch are turned on, the second end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, as well as the drive switch, are all turned on; In the fifth stage, the second end and the third end of the first switch are turned on, the first end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the second bridge arm switch in the half-bridge circuit, and the drive switch are all turned on; In the sixth stage, the second end and the third end of the first switch are turned on, the first end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit and the second bridge arm switch in the half-bridge circuit are all turned on; In the seventh stage, the second end and the third end of the first switch are turned on, the first end and the third end of the second switch are turned on, and the first control switch and the second control switch in the power input control circuit, the second bridge arm switch in the half-bridge circuit, and the semiconductor device under test are all turned on; The data collector is further configured to collect the on-state voltage and on-state current of the semiconductor device under test in the seventh stage.

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