Sampling method, device and product for power semiconductor wafer test

Abstract

The invention discloses a sampling method, device and product for power semiconductor wafer testing, and the sampling method specifically comprises the steps: dividing a chuck body into a current loop part and at least one voltage detection loop part, and enabling the current loop part and the at least one voltage detection loop part to be electrically insulated and isolated; the wafer to be detected is respectively contacted with the current loop part and all the voltage detection loop parts; the wafer to be tested, the current loop part, the test machine and the probe card form a current loop through the source current lead SF and the drain current lead DF, and the wafer to be tested, the voltage detection loop part, the test machine and the probe card form a voltage detection loop through the source voltage lead SS and the drain voltage lead DS; the method comprises the following steps of: testing a wafer to be tested, reading a current parameter through a current loop, measuring a voltage parameter through a voltage detection loop, and measuring and calculating the on-resistance of the wafer test according to the measured parameter. According to the invention, the influence of the contact resistance of the wafer drain electrode and the chuck on the power semiconductor wafer test can be avoided, and the precision of the large-current test item is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing, and in particular to a sampling method, device and product for power semiconductor wafer testing. Background Art

[0002] In power semiconductor wafer testing, device on-resistance (Rdson) and body diode forward voltage (Vsd) are two important high-current test items, with test currents typically reaching hundreds of amperes. Existing high-current testing solutions measure device voltage by sampling the voltage difference between the device source and the chuck using a probe card. However, this also factors in the voltage across the contact resistance between the wafer drain and the chuck, ultimately resulting in an overly high on-resistance value and inaccurate measurements of body diode forward voltage (Vsd) and Rdson.

[0003] While conventional technology uses the Kelvin four-wire method for wafer testing in an attempt to obtain accurate Rdson values, due to the high test current and the contact resistance between the wafer drain and the chuck, conventional techniques cannot effectively eliminate contact resistance. Other methods are required to offset or approximate the impact of contact resistance on the test, which is cumbersome and complex. Furthermore, the actual contact resistance that affects testing varies for different devices (DIEs) on the wafer surface. Using a unified offset calculation method makes it difficult to ensure the stability of the Rdson measurement accuracy for different devices (DIEs). Summary of the Invention

[0004] The purpose of this application is to overcome the shortcomings of the existing technology and provide a sampling method, device and product for power semiconductor wafer testing, which can avoid the influence of the contact resistance between the wafer drain and the chuck on the power semiconductor wafer testing and improve the accuracy of large current test items.

[0005] In a first aspect, the present application provides a sampling method for power semiconductor wafer testing, which uses a chuck body to perform high current performance testing on a wafer to be tested, and is characterized by comprising the following steps: The chuck body is divided into a current loop portion and at least one voltage detection loop portion, wherein the current loop portion and the voltage detection loop portion are electrically insulated and isolated from each other; A wafer to be tested is placed on the chuck body, and the wafer to be tested is in contact with the current loop portion and all voltage detection loop portions respectively; a current loop is formed between the wafer to be tested, the current loop portion, the test machine, and the probe card via the source current lead SF and the drain current lead DF; a voltage detection loop is formed between the wafer to be tested, the voltage detection loop portion, the test machine, and the probe card via the source voltage lead SS and the drain voltage lead DS; A wafer test is performed on the wafer to be tested, current parameters are read through a current loop, voltage parameters are measured through a voltage detection loop, and on-resistance measurement of the wafer test is performed based on the measured parameters.

[0006] By adopting the above technical solution, the traditional chuck body is divided into a current loop part and a voltage detection loop part, wherein the current loop part and the voltage detection loop part are electrically insulated and isolated from each other, thereby achieving the distinction between the current loop and the voltage loop, and realizing true Kelvin four-wire measurement, avoiding the influence of the contact resistance between the wafer to be tested and the chuck body on the detection, and improving the accuracy of high-current test items of wafer testing.

[0007] Preferably, a detection channel is opened inside the current loop portion, and the voltage detection loop portion is arranged in the detection channel.

[0008] By adopting the above technical solution, the current loop portion and the voltage detection loop are organically combined to form a whole, which is conducive to the realization of Kelvin four-wire measurement wiring.

[0009] Preferably, the current loop part is divided into several detection partitions, each detection partition is provided with a detection channel, and each detection channel is provided with a voltage detection loop part. For wafer testing in any detection partition, the voltage parameters measured by the voltage detection loop part of the corresponding partition are used for measurement.

[0010] By adopting the above technical solution and setting a plurality of detection partitions, the average distance between the detection position and the device under test is reduced, and the detection error between devices under test at different positions can be further reduced.

[0011] Preferably, the source current lead SF and the source voltage lead SS are connected to a probe card, and the probes of the probe card are connected to the wafer to be tested; the drain current lead DF is connected to the current loop part, connecting the current loop part to the test machine; the drain voltage lead DS is connected to the voltage detection loop part, connecting the voltage detection loop part to the test machine.

[0012] Through the above technical solution, a wiring method for the source current lead SF, the source voltage lead SS, the drain current lead DF and the drain voltage lead DS is provided under the condition that the current loop part and the voltage detection loop part of the chuck body are distinguished, which can realize the true Kelvin four-wire measurement.

[0013] In a second aspect, the present application provides a device for testing power semiconductor wafers, including a chuck body, and employing the following technical solutions: The chuck body includes a current loop part, at least one voltage detection loop part and at least one insulating isolation part, and the voltage detection loop part corresponds to the insulating isolation part one by one; a detection channel for accommodating the voltage detection loop part and the insulating isolation part is provided inside the current loop part, and the insulating isolation part is located between the current loop part and the voltage detection loop part to physically isolate and insulate the two, the top surfaces of the current loop part, the voltage detection loop and the insulating isolation part are flush, the top surface of the current loop part supports the wafer to be tested, and the top surface of the voltage detection loop part abuts against the drain on the bottom surface of the wafer to be tested.

[0014] Through the above technical solution, a chuck body structure is provided, which realizes insulation isolation between the current loop part and the voltage detection loop part of the chuck body through the insulating isolation part, and can realize the semiconductor wafer testing method based on Kelvin four-wire measurement of the present application.

[0015] Preferably, the device of the present application also includes a chuck bracket for loading the chuck body, the chuck bracket includes a substrate, the upper surface of the substrate is provided with a limiting structure for limiting the loading position of the current loop part, the voltage detection loop part and the insulating isolation part, the limiting structure includes a current loop part limiting structure and a voltage detection loop part limiting structure.

[0016] Through the above technical solution, the chuck body is loaded through the chuck bracket, the loading position of the chuck body can be limited, and a certain pre-tightening stress can be provided, which helps to reliably fix the chuck body and ensure the stability of the chuck body when it is displaced or subjected to force.

[0017] Preferably, the substrate or the current loop portion is provided with a wiring channel leading to the loading position of the voltage detection loop portion; and an insulating lining is provided in the wiring channel provided in the current loop portion and leading to the voltage detection loop portion.

[0018] Through the above technical solution, when wiring based on the Kelvin four-wire method is performed, under the wiring condition that the voltage detection circuit is set inside the current detection circuit, a wiring channel directly leading to the voltage detection circuit is provided, thereby realizing the independence of the voltage detection circuit.

[0019] Preferably, the voltage detection loop portion is a thimble with a diameter of 5 mm.

[0020] By adopting the above technical solution, the diameter of the voltage detection circuit part is optimized, which can ensure that the main structure of the chuck body has ample space and high mechanical strength, without affecting the realization of other functions of the chuck body and the layout of the structure, so that the function and structure of the chuck body are not significantly different from those in conventional technology, and no additional adjustment is required.

[0021] Preferably, the insulating isolation portion is made of polyetheretherketone or glass fiber reinforced epoxy resin.

[0022] The material of the insulating isolation part provided by the above technical solution has excellent electrical insulation performance, good machine strength performance and good high temperature resistance.

[0023] In a third aspect, the present application provides a computer program product, which includes a computer program or instructions, so that the computer program or instructions can implement the steps in the above-mentioned sampling method for power semiconductor wafer testing.

[0024] In summary, this application includes at least one of the following beneficial technical effects: 1. This application can eliminate the influence of the contact resistance between the wafer drain and the chuck when performing wafer testing on the wafer.

[0025] 2. This application can improve the test accuracy of large-power test items in wafer testing.

[0026] 3. This application can simplify the wafer testing process and improve testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 (a) is a wiring diagram for wafer testing using the conventional Kelvin four-wire method; Figure 1(b) is the equivalent circuit diagram of Figure 1(a); FIG2( a ) is a wiring diagram of a sampling method for wafer testing using the Kelvin four-wire method in an embodiment of the present application; Figure 2(b) is the equivalent circuit diagram of Figure 2(a); Figure 3 A top view of a chuck body of a device for power semiconductor wafer testing according to an embodiment of the present application; Figure 4 A cross-sectional view of a chuck body of a device for power semiconductor wafer testing according to an embodiment of the present application; Figure 5 A schematic diagram of a chuck body according to another embodiment of the present application; Figure 6 A schematic diagram of a chuck body according to another embodiment of the present application; Figure 7 This is a schematic diagram of a chuck body loaded on a chuck support of a device for power semiconductor wafer testing according to an embodiment of the present application; Figure 8 A top view of a chuck support of a device for power semiconductor wafer testing according to an embodiment of the present application; Figure 9 A schematic diagram of a chuck support of an apparatus for power semiconductor wafer testing according to another embodiment of the present application.

[0028] Figure numerals: 1, chuck; 2, wafer to be tested; 31, current circuit part; 32, voltage detection circuit part; 33, insulation isolation part; 4, substrate; 41, slide groove; 42, reset rod; 43, wiring channel; 51, limit block; 52, limit cylinder. DETAILED DESCRIPTION

[0029] This specific embodiment is merely an explanation of the present application and is not a limitation of the present application. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed, but as long as they are within the scope of the present application, they are protected by patent law.

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. It should be noted that in the optional embodiments of the present application, when the embodiments in the present application are applied to specific products or technologies, the object information and other related data involved need to obtain the object's permission or consent, and the collection, use and processing of the relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions. In other words, if the embodiments of the present application involve data related to the object, it needs to be obtained through the authorization and consent of the object, the authorization and consent of the relevant departments, and in compliance with the relevant laws, regulations and standards of the country and region. If personal information is involved in the embodiments, the acquisition of all personal information requires the consent of the individual. If sensitive information is involved, the separate consent of the information subject needs to be obtained. The embodiments also need to be implemented with the authorization and consent of the object.

[0031] The embodiments of the present application are described in further detail below with reference to the accompanying drawings.

[0032] Figure 1(a) shows a wiring diagram for wafer testing using the conventional four-wire Kelvin method. In conventional technology, wafer 2 under test is placed on chuck 1, which is a single metal conductor. The contact resistance between wafer 2 under test and chuck 1 is denoted as Rc. A current loop is formed between wafer 2 under test, chuck 1, test machine (not shown), and probe card (not shown) via source current lead SF and drain current lead DF. A voltage detection loop is formed between wafer 2 under test, chuck 1, test machine (not shown), and probe card (not shown) via source voltage lead SS and drain voltage lead DS.

[0033] Its equivalent circuit diagram is shown in Figure 1(b), where R1 and R4 are the wiring resistances of the current loop, R2 and R3 are the wiring resistances of the voltage detection loop, Rc is the contact resistance, and Rdson is the on-resistance of the device under test. Because the voltmeter's internal resistance is large, the current in the voltage detection loop is very small, and the corresponding voltage generated by R2 and R3 is also very small, having almost no effect on the voltage detection result. When the wires are in perfect contact, R1 and R4 have no effect on the voltage measurement result. Therefore, the conventional wiring method based on the Kelvin four-wire method can effectively eliminate the influence of wiring resistance. However, because the current and voltage sampling loops in the conventional technology are both connected to the wafer under test through the chuck, the actual measured voltage V_measure = V_Rc + V_ds = I*(Rc + Rdson), where V_Rc is the contact resistance voltage between the wafer drain and the chuck, and V_ds is the drain-source voltage of the device under test. Therefore, the conventional Kelvin four-wire wiring method cannot eliminate the influence of the contact resistance Rc and cannot accurately measure Rdson.

[0034] In one embodiment of the present application, the sampling method for power semiconductor wafer testing of the present application is used, and a wiring diagram for wafer testing based on the Kelvin four-wire method is shown in Figure 2(a). The wafer 2 to be tested is placed on the chuck body. The source current lead SF and the drain current lead DF form a current loop with the wafer 2 to be tested, the current loop unit 31, the test machine (not shown in the figure), and the probe card (not shown in the figure). The source voltage lead SS and the drain voltage lead DS form a voltage detection loop with the wafer 2 to be tested, the voltage detection loop unit 32, the test machine (not shown in the figure), and the probe card (not shown in the figure). Furthermore, the source current lead SF and the source voltage lead SS are connected to a probe card, the probes of which are connected to the wafer under test. The drain current lead DF is connected to the current loop portion 31 and is connected to the drain of the wafer under test through the current loop portion 31. The drain voltage lead DS is connected to the voltage detection loop portion 32 and is connected to the drain of the wafer under test through the voltage detection loop portion 32. The contact resistance between the wafer under test 2 and the current loop portion 31 is denoted as Rc1, and the contact resistance between the wafer under test 2 and the voltage detection loop portion 32 is denoted as Rc2.

[0035] Its equivalent circuit diagram is shown in Figure 2 (b), where R1 and R4 are the wiring resistances of the current loop, R2 and R3 are the wiring resistances of the voltage detection loop, Rc1 is the contact resistance of the current loop, Rc2 is the contact resistance of the voltage detection loop, and Rdson is the on-resistance of the device under test. The difference between this embodiment and the conventional technology is that since the internal resistance of the voltmeter is very large, the current in the voltage detection loop is very small, and the voltage generated by Rc2 is also very small, which has almost no effect on the voltage detection result. When the wires are in perfect contact, Rc1 has no effect on the voltage measurement result. Therefore, in this solution, the actual measured voltage V_measure = V_ds = I*Rdson, and the value of Rdson can be directly obtained through the current value and voltage measurement value, and the influence of contact resistance can be effectively avoided, making the measurement of Rdson accurate.

[0036] In another embodiment of the present application, a chuck body scheme of a device for power semiconductor wafer testing according to a wiring diagram is as follows: Figure 3 and Figure 4 As shown, the chuck body includes a current loop portion 31, a voltage detection loop portion 32, and an insulating isolation portion 33. The current loop portion 31 is a cylindrical structure, with a detection channel extending along its axis to accommodate the voltage detection loop portion and the insulating isolation portion. The voltage detection loop portion 32 is a cylindrical structure, while the insulating isolation portion 33 is a tubular structure. The insulating isolation portion 33 is located between the current loop portion 31 and the voltage detection loop portion 32, providing physical and insulating isolation between the two.

[0037] The top surfaces of the current loop portion 31, the voltage detection loop 32 and the insulating isolation portion 33 are flush, ensuring that the upper surface of the chuck body is flat, avoiding warping of the wafer to be tested after being placed thereon, and ensuring that the current loop portion 31 and the voltage detection loop 32 form effective contact with the bottom surface of the wafer to be tested. The top surface of the current loop portion 31 supports the wafer to be tested. The method of fixing the wafer to be tested is the existing conventional technology. For example, one implementation method is to fix the wafer to be tested by vacuum adsorption. The top surface of the voltage detection loop portion 32 abuts against the bottom surface drain of the wafer to be tested. For the vertical conductive structure power device targeted by this application, the drain (Drain) is directly connected through the backside metallization of the wafer (Backside Metallization) to form a common drain, and the DIE drain on the back side of the wafer has the same potential.

[0038] Those skilled in the art will understand that the description of the relative positions of the current loop portion 31 and the voltage detection loop portion 32 in the above figures and embodiments is merely an example provided for the convenience of explanation and understanding of the embodiments of the present application, and does not constitute a limitation on the present application. As long as the voltage detection loop portion 32 can effectively contact the wafer to be tested, the voltage detection loop portion 32 can be set at any position of the current loop portion 31. For example, in other embodiments, refer to Figure 5 The voltage detection loop portion is arranged on one side of the current loop portion 31 to provide a more convenient connection port setting position, reduce the connection difficulty, and realize a clear distinction between the drain current lead DF and the drain voltage lead DS.

[0039] In another embodiment of the present application, please refer to Figure 6 . In order to shorten the average distance difference between each DIE of the wafer to be tested and the test position as much as possible, so that the test conditions of each DIE are as close as possible, in order to further reduce the test error, the current loop part 31 is divided into several detection partitions, each detection partition is provided with a detection channel, and each detection channel is provided with a voltage detection loop part 32. For the wafer test of any detection partition, the voltage parameters measured by the voltage detection loop part of the corresponding partition are used for measurement. In this embodiment, the current test part 31 is divided into four sector-shaped areas A, B, C, and D that are symmetrical about the center, and a voltage detection loop part 32 is set at the edge position of each sector-shaped area. The actual number and actual setting position of the detection partitions, detection channels and voltage detection loop parts 32 can be adjusted accordingly according to the actual functions and design requirements of the chuck body. The above embodiments do not constitute a limitation of the present application scheme.

[0040] In another embodiment, see Figure 7 and Figure 8The device for testing power semiconductor wafers includes a chuck holder for loading a chuck body. The chuck holder provides physical support for the chuck body, ensuring the structural integrity and stability of the chuck body, and enabling electrical circuit connection between the chuck body and the test machine. The chuck holder includes a base plate 4, the upper surface of which is provided with a limiting structure for limiting the loading position of the current loop portion 31, the voltage detection loop portion 32, and the insulating isolation portion 33. The limiting structure includes a current loop portion limiting structure and a voltage detection loop portion limiting structure. The chuck holder limits the specific loading position of the current loop portion 31, the voltage detection loop portion 32, and the insulating isolation portion 33 of the chuck body through the limiting structure, and can provide a certain pre-tightening stress, which helps to improve the structural stability of the chuck body. For example, when the probe card is physically contacted with the pad or bump of the wafer to be tested to form an electrical connection, the limiting structure ensures that the chuck body supporting the wafer to be tested is stable and does not displace or deform, thereby ensuring the reliability of the electrical connection during the test. The chuck bracket, including the base plate 4 and the limiting structure, is made of the same insulating material as the insulating isolation part 31 .

[0041] In order to implement the method for power semiconductor wafer testing according to the embodiment of the present application, the wiring method for wafer testing based on the Kelvin four-wire method requires that the drain voltage lead DS be directly connected to the voltage detection loop portion 32, thereby directly sampling the voltage at both ends of the device under test. However, since the voltage loop detection portion 32 is disposed within the detection channel inside the current loop portion 31, the drain voltage lead DS connected to the voltage detection loop portion 32 needs to be led outward. Therefore, in another embodiment, please refer to Figure 7 , a wiring channel 43 leading to the loading position of the voltage detection loop portion is provided on the substrate 4. Through the wiring channel 43, wiring is performed from the bottom of the voltage detection loop portion 32, and then led out through the bottom or side of the substrate to connect to the detection machine to achieve connectivity of the voltage detection loop. The above embodiment is an implementation method for connecting the voltage loop portion 32 to the drain voltage lead DS. In addition, the connection can also be achieved by providing a wiring channel leading to the voltage loop portion on the side of the current loop portion. Since it is necessary to ensure electrical insulation isolation between the current loop portion 31 and the voltage detection loop portion 32, this implementation method of the wiring channel requires an insulating lining to be arranged in the wiring channel.

[0042] In another embodiment, see Figure 7 and Figure 8 The current loop unit's position-limiting structure consists of four limit blocks 51. These four limit blocks 51 are arranged in a cross shape, surrounding the loading position of the current loop unit 31 and located in four directions of the loading position. The current loop unit 31 is loaded vertically onto the chuck bracket from top to bottom, with the outer circumference of the current loop unit 31 in close contact with the inner sidewalls of each limit block.

[0043] In another embodiment, see Figure 9 The base plate 4 defines a slot 41 for a stopper 51 to slide within. The stopper 51 is slidably disposed within the slot 41 and is connected to a reset lever 42. When the current circuit unit 31 is loaded onto the base plate 4, the reset lever 42 pulls the stopper 51 away from its base position, increasing the space available for loading the current circuit unit 31 and reducing loading difficulty. After the current circuit unit 31 is loaded into place, the reset lever 42 pushes the stopper 51 back to its base position, precisely limiting the loading position of the current circuit unit 31 and providing preload stress.

[0044] In another embodiment, see Figure 7 and Figure 8 The voltage detection circuit portion's limiting structure comprises a limiting cylinder 52, which is positioned at the loading position of the voltage detection circuit portion 32. When the current circuit portion 31 is loaded onto the chuck bracket, the inner circumferential surface of the current circuit portion 31 is in close contact with the outer circumferential surface of the limiting cylinder 52. The voltage detection circuit portion 32 is then positioned from top to bottom within the detection channel and connected to the chuck bracket. At this point, the outer circumferential surface of the voltage detection circuit portion 32 is in close contact with the inner circumferential surface of the limiting cylinder 52. The inner and outer diameters of the limiting cylinder 52 are consistent with those of the insulating isolation portion. The insulating isolation portion 33 is inserted into the gap of the detection channel and stacked on the limiting cylinder 52, achieving physical and insulated isolation between the current circuit portion 31 and the voltage detection circuit portion. Therefore, to ensure that the top surfaces of the current circuit portion 31, the voltage detection circuit 32, and the insulating isolation portion 33 are flush, the actual height of the insulating isolation portion 33 is the height of the current circuit portion 31 (voltage detection circuit 32) minus the height of the limiting cylinder 52.

[0045] Those skilled in the art will understand that the above-mentioned limiting structure is merely an example of the embodiment of the present application and does not constitute a limitation to the scheme of the present application. Modifications made to the specific implementation of the limiting structure to achieve the same limiting and fixing function of the chuck body on the chuck bracket should be included in the scope of protection of the present application.

[0046] In another embodiment, the difference in radius between the end faces of the current loop portion 31 and the voltage detection loop portion 32 is greater than the radius of the voltage detection loop portion 32, so that in the overall structure of the chuck body, the current loop portion 31 is the actual main structure and occupies a larger volume. The current loop portion 31 is responsible for supporting the wafer to be measured, and its diameter needs to be larger than the diameter of the wafer to be measured. At the same time, other functional structures of the chuck body also need to be implemented within the spatial range of the current loop portion 31. For example, in order to achieve vacuum adsorption of the wafer to be measured, it is necessary to distribute air holes on the upper surface of the current loop portion and to set an air channel inside the current loop portion; in order to accurately position the wafer, it is necessary to integrate an alignment module into the current loop portion 31; the chuck body can also be integrated with a heating device. Therefore, the diameter of the current loop portion 31 can be significantly larger than the diameter of the voltage detection loop portion 32 to ensure ample space for the current loop portion.

[0047] More specifically, in one embodiment, the voltage detection circuit portion 32 is a 5 mm diameter ejector pin. Since the voltage detection circuit portion 32 functions solely to connect the voltage detection circuit and measure voltage, a smaller diameter can also meet its functional requirements while ensuring convenient wiring. In other embodiments, the voltage detection circuit portion 32 can also be constructed with a larger diameter, similarly provided with vacuum adsorption holes and airways, without affecting voltage detection.

[0048] In another embodiment, the material of the current loop portion 31 and the voltage detection loop portion 32 is a gold-plated good conductor material to ensure the effective conduction of the electrical signal. Furthermore, the material of the current loop portion 31 and the voltage detection loop portion 32 is a material close to the thermal expansion coefficient of the wafer to be measured. Specifically, in this embodiment, the material of the wafer is selected from single crystal silicon, polycrystalline silicon or amorphous silicon; the wafer can also be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors; the wafer can also be a ceramic substrate such as aluminum oxide, a quartz or glass substrate or other semiconductor materials. Exemplarily, in this embodiment, the wafer is silicon carbide.

[0049] In another embodiment, the insulating spacer 33 is made of PEEK (polyetheretherketone) or FR4 (glass fiber reinforced epoxy resin). The insulating spacer made of the above materials can achieve good electrical insulation performance, high temperature resistance, mechanical strength and chemical stability.

[0050] In another embodiment, a computer program product of the present application includes a computer program or instructions, which enable the computer program or instructions to implement the steps in the above-described sampling method for power semiconductor wafer testing. Those skilled in the art will clearly understand that for ease and brevity of description, the specific working procedures of the steps in the above-described sampling method for power semiconductor wafer testing can refer to the corresponding procedures in the aforementioned method embodiments and will not be repeated here.

[0051] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state drive).

[0052] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A sampling method for power semiconductor wafer testing, using a chuck body to perform high current performance testing on the wafer to be tested, characterized in that: The steps include: The chuck body is divided into a current loop portion and at least one voltage detection loop portion, wherein the current loop portion and the voltage detection loop portion are electrically insulated and isolated from each other; A wafer to be tested is placed on the chuck body, and the wafer to be tested is in contact with the current loop portion and all voltage detection loop portions respectively; a current loop is formed between the wafer to be tested, the current loop portion, the test machine, and the probe card via the source current lead SF and the drain current lead DF; a voltage detection loop is formed between the wafer to be tested, the voltage detection loop portion, the test machine, and the probe card via the source voltage lead SS and the drain voltage lead DS; A wafer test is performed on the wafer to be tested, current parameters are read through a current loop, voltage parameters are measured through a voltage detection loop, and on-resistance measurement of the wafer test is performed based on the measured parameters.

2. The sampling method for power semiconductor wafer testing according to claim 1, characterized in that: A detection channel is opened inside the current loop portion, and the voltage detection loop portion is arranged in the detection channel.

3. The sampling method for power semiconductor wafer testing according to claim 2, characterized in that: The current loop part is composed of several detection partitions, each detection partition is provided with a detection channel, and each detection channel is provided with a voltage detection loop part. For wafer testing in any detection partition, the voltage parameters measured by the voltage detection loop part of the corresponding partition are used for measurement and calculation.

4. The sampling method for power semiconductor wafer testing according to claim 1, characterized in that: The source current lead SF and the source voltage lead SS are connected to a probe card, and the probes of the probe card are connected to the wafer to be tested; the drain current lead DF is connected to the current loop part, connecting the current loop part to the test machine; the drain voltage lead DS is connected to the voltage detection loop part, connecting the voltage detection loop part to the test machine.

5. A device for testing power semiconductor wafers, comprising a chuck body, characterized in that: The chuck body includes a current loop part, at least one voltage detection loop part and at least one insulating isolation part, and the voltage detection loop part corresponds to the insulating isolation part one by one; a detection channel for accommodating the voltage detection loop part and the insulating isolation part is provided inside the current loop part, and the insulating isolation part is located between the current loop part and the voltage detection loop part to physically isolate and insulate the two, the top surfaces of the current loop part, the voltage detection loop and the insulating isolation part are flush, the top surface of the current loop part supports the wafer to be tested, and the top surface of the voltage detection loop part abuts against the drain on the bottom surface of the wafer to be tested.

6. The device for power semiconductor wafer testing according to claim 5, characterized in that: It also includes a chuck bracket for loading the chuck body, the chuck bracket includes a base plate, the upper surface of the base plate is provided with a limiting structure for limiting the loading position of the current loop part, the voltage detection loop part and the insulating isolation part, the limiting structure includes a current loop part limiting structure and a voltage detection loop part limiting structure.

7. The device for power semiconductor wafer testing according to claim 6, characterized in that: The substrate or the current loop portion is provided with a wiring channel leading to a loading position of the voltage detection loop portion; the wiring channel provided by the current loop portion and leading to the voltage detection loop portion is provided with an insulating lining.

8. The device for power semiconductor wafer testing according to claim 5, characterized in that: The voltage detection loop portion is a thimble with a diameter of 5 mm.

9. The device for power semiconductor wafer testing according to claim 5, characterized in that: The insulating isolation part is made of polyetheretherketone or glass fiber reinforced epoxy resin.

10. A computer program product, characterized in that The computer program product includes a computer program or instructions, so that the computer program or instructions can implement the steps of the sampling method for power semiconductor wafer testing according to any one of claims 1 to 4.

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