Semiconductor device

Abstract

A semiconductor device includes a lower semiconductor die including a plurality of lower elements, a lower interconnect region, and a plurality of lower via structures; and an upper semiconductor die including a plurality of upper elements and an upper interconnection region, the upper semiconductor die stacked on the lower semiconductor die in one direction. Some of the plurality of lower elements and some of the plurality of upper elements provide: a first ring oscillator outputting a reference clock signal generated through a signal transmission path, the signal transmission path including a first via structure, the first via structure being some of the plurality of lower via structures; and a second ring oscillator outputting a test clock signal generated through a signal transmission path including a second via structure different from the first via structure among the plurality of via structures.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0031562 filed on March 5, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to semiconductor devices. Background Art

[0004] Semiconductor devices may include various circuits required for performing computations. To improve semiconductor device performance and reduce power consumption, a three-dimensional (3D) semiconductor device has been proposed. In this device, the circuits included in the device are distributed across multiple semiconductor dies, and the dies are stacked. In a 3D semiconductor device, at least some of the circuits included in different semiconductor dies can be connected to each other via via structures to exchange data signals, clock signals, and the like. Summary of the Invention

[0005] Due to the high degree of interconnection in modern semiconductor devices, in order to improve the reliability and integration of 3D semiconductor devices, it is beneficial to accurately determine the delay characteristics of signals between semiconductor dies stacked on each other.

[0006] Some aspects of the present disclosure improve the reliability of a semiconductor device including semiconductor dies connected by a via structure and stacked on each other by accurately determining delay characteristics of signals transmitted between the semiconductor dies.

[0007] According to some embodiments, a semiconductor device is provided, comprising: a lower semiconductor die, the lower semiconductor die comprising: a lower substrate; a plurality of lower standard cells disposed on the lower substrate; a plurality of via structures passing through the lower substrate; and a plurality of pads exposed to the outside; and an upper semiconductor die comprising: an upper substrate; and a plurality of upper standard cells disposed on the upper substrate, the upper semiconductor die being stacked on the lower semiconductor die. The plurality of lower standard cells and some of the plurality of upper standard cells can provide a first logic gate and a second logic gate. The first logic gate, a first lower reference cell that is a portion of the plurality of lower standard cells, a first upper reference cell that is a portion of the plurality of upper standard cells, and a first via structure in the plurality of via structures can provide a first ring oscillator. The second logic gate, a second lower reference cell that is another portion of the plurality of lower standard cells, a second upper reference cell that is another portion of the plurality of upper standard cells, a second via structure in the plurality of via structures, and a test circuit connected between the second via structure and an input terminal of the second logic gate can provide a second ring oscillator. The first ring oscillator may output a reference clock signal to a first pad among the plurality of pads, and the second ring oscillator may output a test clock signal to a second pad among the plurality of pads.

[0008] According to some embodiments, a semiconductor device is provided, comprising: a lower semiconductor die, the lower semiconductor die comprising: a lower element region comprising a plurality of lower elements disposed on a lower substrate; a lower interconnect region disposed on the lower element region; and a plurality of lower via structures passing through the lower substrate; and an upper semiconductor die, the upper semiconductor die comprising: an upper element region comprising a plurality of upper elements disposed on the upper substrate; and an upper interconnect region disposed on the upper element region, the upper semiconductor die being stacked on the lower semiconductor die in one direction. Some of the plurality of lower elements and some of the plurality of upper elements can provide a first ring oscillator and a second ring oscillator, the first ring oscillator outputting a reference clock signal generated from a signal transmission path comprising a first via structure from among the plurality of lower via structures, and the second ring oscillator outputting a test clock signal generated from a signal transmission path comprising a second via structure from among the plurality of via structures, different from the first via structure.

[0009] According to some embodiments, a semiconductor device is provided, including a lower semiconductor die and an upper semiconductor die stacked on each other, the semiconductor device including: a first ring oscillator, the first ring oscillator including: a first lower unit circuit provided by some of the lower standard cells included in the lower semiconductor die; a first upper unit circuit provided by some of the upper standard cells included in the upper semiconductor die, the first upper unit circuit being alternately connected to the first lower unit circuit; and a first logic gate having a first input terminal and a second input terminal, the first input terminal receiving an enable signal, the second input terminal being connected to one of the first lower unit circuit and the first upper unit circuit; and a second ring oscillator including: a second lower unit circuit provided by other of the lower standard cells; a second upper unit circuit provided by other of the upper standard cells, the second upper unit circuit being alternately connected to the second lower unit circuit; a second logic gate having a first input terminal and a second input terminal, the first input terminal receiving the enable signal, the second input terminal being connected to one of the second lower unit circuit and the second upper unit circuit; and a test circuit delaying an original clock signal input to the second input terminal of the second logic gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic diagram illustrating an example of a semiconductor device;

[0012] Figure 2A 、 Figure 2B and Figure 3 is a schematic diagram illustrating an example of a semiconductor device;

[0013] Figure 4A and Figure 4B is a schematic circuit diagram showing an example of a ring oscillator;

[0014] Figure 5 and Figure 6 is a schematic diagram illustrating an example of a semiconductor device;

[0015] Figure 7 is a diagram illustrating an operation example of a semiconductor device;

[0016] Figure 8 is a schematic diagram illustrating an example of a semiconductor device;

[0017] Figure 9 is a diagram showing an operation example of a semiconductor device;

[0018] Figure 10 and Figure 11 is a schematic diagram illustrating an example of a semiconductor device;

[0019] Figure 12 and Figure 13 is a schematic diagram illustrating an example of a semiconductor device; and

[0020] Figures 14 to 16 is a schematic diagram illustrating an example of a semiconductor device. DETAILED DESCRIPTION

[0021] Reference Figure 1 , semiconductor device 10 includes a lower semiconductor die 20 and an upper semiconductor die 30. The lower semiconductor die 20 and the upper semiconductor die 30 can be stacked along a first direction (Z-axis direction). For example, the lower semiconductor die 20 and the upper semiconductor die 30 can be electrically connected to each other, so that they can operate while exchanging clock signals and / or data signals. In some embodiments, the lower semiconductor die 20 and the upper semiconductor die 30 can provide semiconductor chips that perform various functions.

[0022] Lower semiconductor die 20 may include a first lower region 21 and a second lower region 22, wherein second lower region 22 includes a lower substrate. Upper semiconductor die 30 may include a first upper region 31 and a second upper region 32, wherein second upper region 32 includes an upper substrate. In lower semiconductor die 20, first lower region 21 may include a lower substrate and a plurality of via structures 40 passing through the lower substrate, and second lower region 22 may include a plurality of lower elements, an interconnection pattern for connecting the plurality of lower elements, and an insulating layer provided with the interconnection pattern.

[0023] At least some of the plurality of lower elements included in lower semiconductor die 20 may include a plurality of lower standard cells arranged along the second direction (X-axis direction) and the third direction (Y-axis direction). Each of the plurality of lower standard cells may include a predefined logic circuit.

[0024] The first upper region 31 may include an upper substrate, and the second upper region 32 may include a plurality of upper elements, an interconnection pattern for connecting the plurality of upper elements to each other, and an insulating layer provided with the interconnection pattern. The plurality of upper elements may include a plurality of upper standard cells arranged along the second direction and the third direction, and each of the plurality of upper standard cells may include a predefined logic circuit. Figure 1 In the illustrated semiconductor device 10 , a lower semiconductor die 20 and an upper semiconductor die 30 are stacked on each other such that a first lower region 21 of the lower semiconductor die 20 and a second upper region 32 of the upper semiconductor die 30 are adjacent to each other.

[0025] Reference Figure 1, lower semiconductor die 20 (in this example, different from upper semiconductor die 30) includes a plurality of via structures 40. Each of the plurality of via structures 40 may be a through-silicon via (TSV) passing through the lower substrate of lower semiconductor die 20. In some embodiments, the plurality of via structures 40 pass through first lower region 21 and may optionally pass through second lower region 22.

[0026] Surfaces of the plurality of via structures 40 may be exposed to the outside of the lower substrate included in the first lower region 21 and may be connected to pads formed on the surface of the second upper region 32. Surfaces of the plurality of via structures 40 may be connected to pads formed on the surface of the second lower region 22. Thus, the lower semiconductor die 20 and the upper semiconductor die 30 may be electrically connected to each other through the plurality of via structures 40.

[0027] As described above, when the semiconductor device 10 operates, the lower semiconductor die 20 and the upper semiconductor die 30 can operate by exchanging clock signals and / or data signals with each other. A transmission path for the clock signal and / or data signal can be provided through the plurality of via structures 40, and an input / output circuit that transmits or receives a signal through the plurality of via structures 40 can be connected to the plurality of via structures 40. Therefore, for stable operation of the semiconductor device 10, it may be useful to accurately determine the delay characteristics between the lower semiconductor die 20 and the upper semiconductor die 30.

[0028] In some embodiments, a ring oscillator is included in semiconductor device 10, and the ring oscillator transmits clock signals from lower semiconductor die 20 and upper semiconductor die 30 through at least some of the plurality of via structures 40. Semiconductor device 10 may include a first ring oscillator that generates a reference clock signal, and a second ring oscillator that generates a test clock signal through a test cell or test TSV on which delay characteristics are to be measured. The frequency difference and / or phase difference between the reference clock signal generated in semiconductor device 10 and the test clock signal can be detected to accurately measure the signal delay characteristics of the test cell or test TSV, thereby improving the reliability of semiconductor device 10.

[0029] Figure 2A 、 Figure 2B and Figure 3 is a schematic diagram illustrating an example of a semiconductor device according to some embodiments.

[0030] First, refer to Figure 2A, semiconductor device 100 may include a lower semiconductor die 110 and an upper semiconductor die 120 stacked on each other. Lower semiconductor die 110 may include a lower substrate 111, a lower element region 112, a lower interconnection region 113, etc., and upper semiconductor die 120 may include an upper substrate 121, an upper element region 122, an upper interconnection region 123, etc. A plurality of elements (e.g., circuit elements) may be provided in each of element regions 112 and 122, and an interconnection pattern and an insulating layer may be provided in each of interconnection regions 113 and 123.

[0031] The lower semiconductor die 110 may further include a plurality of via structures 116 passing through the lower substrate 111. Each of the plurality of via structures 116 may be a TSV passing through the lower substrate 111. Figure 2A , each of the plurality of via structures 116 is shown as passing through the lower substrate 111, the lower element region 112, and the lower interconnect region 113. However, in some embodiments, the plurality of via structures 116 are formed to pass through the lower substrate 111 (e.g., not through the lower interconnect region 113) and are electrically connected to other via structures formed in the lower interconnect region 113. One surface (e.g., the top surface) of each of the plurality of via structures 116 can be connected to a pad 114 exposed to the outside of the lower interconnect region 113, and another surface (e.g., the bottom surface) of each of the plurality of via structures 116 can be connected to a pad 115 formed on one surface of the lower substrate 111. In some embodiments, the pad 115 exposed to the outside from one surface of the lower substrate 111 is connected to an external circuit board.

[0032] The pads 114 can be electrically connected to the pads 124 through a plurality of microbumps 130, and the pads 124 are exposed outside the upper interconnection region 123 of the upper semiconductor die 120. Therefore, the upper semiconductor die 120 and the lower semiconductor die 110 can be electrically connected to each other through the plurality of via structures 116, and signals input and output to the pads 115 through an external circuit board or the like can be transmitted to the upper semiconductor die 120. The plurality of via structures 116 can provide a signal transmission path between the upper semiconductor die 120 and the lower semiconductor die 110.

[0033] like Figure 2A As shown, the lower interconnection region 113 and the upper interconnection region 123 may be disposed between the lower element region 112 and the upper element region 122. In addition, the lower element region 112 and the upper element region 122 may be disposed between the lower substrate 111 and the upper substrate 121.

[0034] Reference Figure 2BA semiconductor device 100A according to some embodiments may include a lower semiconductor die 110A and an upper semiconductor die 120 stacked on each other. The lower semiconductor die 110A may include a lower substrate 111A, a lower element region 112A, a lower interconnection region 113A, etc., and the upper semiconductor die 120 may include an upper substrate 121, an upper element region 122, an upper interconnection region 123, etc.

[0035] Lower semiconductor die 110A may further include a plurality of via structures 116A. Each of via structures 116A may be a TSV having a region passing through lower substrate 111A. One surface of each of via structures 116A may be connected to pad 114A formed on one surface of lower substrate 111A, and another surface of each of via structures 116A may be connected to pad 115A exposed outside lower interconnect region 113A. In some embodiments, pad 115A exposed outside lower interconnect region 113A is connected to an external circuit board.

[0036] The pads 114A may be electrically connected to the pads 124 through the plurality of microbumps 130, and the pads 124 are exposed outside the upper interconnection region 123 of the upper semiconductor die 120. Thus, the upper semiconductor die 120 and the lower semiconductor die 110A may be electrically connected to each other through the plurality of via structures 116A, and the plurality of via structures 116A may provide a signal transmission path between the upper semiconductor die 120 and the lower semiconductor die 110A.

[0037] like Figure 2B As shown, upper interconnection region 123 may be provided between lower element region 112A and upper element region 122, and lower interconnection region 113A may not be provided between lower element region 112A and upper element region 122. For example, lower element region 112A may be provided between lower interconnection region 113A and upper element region 122. In addition, lower substrate 111A may be provided between lower element region 112A and upper interconnection region 123.

[0038] Reference Figure 3 , the semiconductor device 200 according to some embodiments includes a lower semiconductor die 210 and an upper semiconductor die 220 stacked on each other. Figures 2A to 2B As described above, the lower semiconductor die 210 may include a lower substrate 211 , a lower element region 212 , a lower interconnection region 213 , etc., and the upper semiconductor die 220 may include an upper substrate 221 , an upper element region 222 , an upper interconnection region 223 , etc.

[0039] like Figure 3As shown, lower semiconductor die 210 may include a plurality of lower via structures 216, and upper semiconductor die 220 may include a plurality of upper via structures 226. Each of lower and upper via structures 216 and 226 may be a TSV having an area passing through substrates 211 and 221.

[0040] One surface of each of the plurality of lower via structures 216 may be connected to a pad 214 formed on one surface of the lower substrate 211, and the other surface of each of the plurality of lower via structures 216 may be connected to a pad 215 exposed outside the lower interconnection region 213. One surface (e.g., the lower surface) of each of the plurality of upper via structures 226 may be connected to a pad 224 formed on one surface of the upper substrate 221, and the other surface (e.g., the upper surface) of each of the plurality of upper via structures 226 may be connected to a pad 225 exposed outside the upper interconnection region 223. In some embodiments, the pad 225 exposed outside the upper interconnection region 223 may be omitted.

[0041] The pads 214 exposed outward from one surface of the lower substrate 211 and the pads 224 exposed outward from one surface of the upper substrate 221 may be connected to each other through a plurality of micro bumps 230. Thus, the upper semiconductor die 220 and the lower semiconductor die 210 may be electrically connected to each other through a plurality of lower via structures 216 and a plurality of upper via structures 226. The plurality of lower via structures 216 and the plurality of upper via structures 226 may provide a signal transmission path between the upper semiconductor die 220 and the lower semiconductor die 210.

[0042] Figure 4A and Figure 4B is a schematic circuit diagram illustrating a ring oscillator included in a semiconductor device according to some embodiments.

[0043] The semiconductor device may include a first ring oscillator 300 that generates a reference clock signal, and a second ring oscillator 310 that generates a test clock signal, wherein the test clock signal has a frequency different from that of the reference clock signal. In some embodiments, the test clock signal and the reference clock signal may have not only a frequency difference but also a phase difference. The second ring oscillator 310 may further include a test circuit connected to the front end of the output terminal of the first ring oscillator 300, and the frequency difference and / or phase difference between the reference clock signal and the test clock signal may be generated by the test circuit.

[0044] Reference Figure 4AThe first ring oscillator 300 may include a first logic gate 301 and a first inverter circuit 303, in which a plurality of inverters are connected to one another. The inverters included in the first inverter circuit 303 may be connected to one another in series, and the number of inverters included in the first inverter circuit 303 may be an odd number. Therefore, the first inverter circuit 303 may invert the output of the first logic gate 301 to generate an output signal, and the output signal may be an inverted signal of the output of the first logic gate 301. The output terminal of the first inverter circuit 303 may be connected to the first pad 305.

[0045] One of the input terminals of the first logic gate 301 may receive an enable signal EN, and the other input terminal may be connected to an output terminal of the first inverting circuit 303. When the enable signal EN is set to have a voltage level corresponding to a logical value of "1," the output of the first logic gate 301 may be inverted by the first inverting circuit 303 and output to the first pad 305. In an initial state, when the first logic gate 301 outputs an output voltage corresponding to "0," a voltage corresponding to "1" may be output to the first pad 305.

[0046] The voltage of the first pad 305 can be fed back to the first logic gate 301, so that the output voltage of the first logic gate 301 can be adjusted to a voltage level corresponding to "1". Using such a process, a reference clock signal having a predetermined frequency can be output to the first pad 305. The period of the reference clock signal can be determined by the number of the plurality of inverters included in the first inverter circuit 303 and / or the RC characteristics of each of the plurality of inverters.

[0047] Reference Figure 4B The second ring oscillator 310 may include a second logic gate 311, a second inverter circuit 313, and a test circuit TC. The second inverter circuit 313 may include a plurality of inverters connected in series, and the number of inverters included in the second inverter circuit 313 may be an odd number. Therefore, the second inverter circuit 313 may invert the output of the second logic gate 311 to generate an output signal, and the output signal may be an inverted signal of the output of the second logic gate 311. The number of inverters included in the second inverter circuit 313 may be equal to the number of inverters included in the first inverter circuit 303. The output terminal of the second inverter circuit 313 may be connected to the second pad 315.

[0048] One of the input terminals of the second logic gate 311 may receive an enable signal EN, and the other input terminal may be connected to an output terminal of the second inverting circuit 313. The first logic gate 301 and the second logic gate 311 may receive the same enable signal EN. The operation of the second ring oscillator 310 may be similar to that of the first ring oscillator 300. When the enable signal EN is set to a voltage level corresponding to a logical value of "1", the output of the second logic gate 311 may be inverted by the second inverting circuit 313 and input to the test circuit TC.

[0049] The test circuit TC may include a plurality of test cells connected in series. Each of the plurality of test cells may include a single circuit, and the plurality of test cells may include the same circuit. The test circuit TC may be configured not to invert the output voltage of the second inverter circuit 313.

[0050] The signal generated by second logic gate 311 and second inverting circuit 313 may be the same as the reference clock signal output by first ring oscillator 300 to first pad 305. A test clock signal having a frequency and / or phase obtained by changing the frequency and / or phase of the reference clock signal may be output to second pad 315 through test circuit TC. The frequency difference and / or phase difference between the test clock signal and the reference clock signal may be determined by the number of test cells included in test circuit TC and / or the characteristics of each test cell.

[0051] For example, a reference clock signal is measured at the first pad 305 of the semiconductor device and a test clock signal is measured at the second pad 315 of the semiconductor device, and a frequency difference and / or phase difference between the reference clock signal and the test clock signal can be calculated. For example, the difference between a single cycle of the reference clock signal and a single cycle of the test clock signal can be detected and divided by the number of test cells included in the test circuit TC, thereby determining the signal delay characteristics of the single test cell.

[0052] Reference Figure 5 and Figure 6 , a semiconductor device 400 according to some embodiments includes a lower semiconductor die 410 and an upper semiconductor die 420. Each of the lower semiconductor die 410 and the upper semiconductor die 420 may include a substrate, a device region, and an interconnection region, and may provide a plurality of standard cells by providing a plurality of devices in the device region and at least one interconnection pattern among interconnection patterns provided in the interconnection region.

[0053] Some of the plurality of lower standard cells included in the lower semiconductor die 410 may be connected to some of the plurality of upper standard cells included in the upper semiconductor die 420 through a via structure 415 passing through the lower substrate. Therefore, the lower semiconductor die 410 and the upper semiconductor die 420 may operate while exchanging signals with each other.

[0054] Reference Figure 5 The first ring oscillator may include a first logic gate LG1, a plurality of first lower reference cells 411, a plurality of first upper reference cells 421, and a plurality of first via structures 415. The first logic gate LG1 is shown as a NAND gate, but may be implemented as an AND gate, a NOR gate, etc. The first logic gate LG1 may be provided by at least one lower standard cell among the plurality of lower standard cells.

[0055] The plurality of first lower reference cells 411 may be some of the lower standard cells included in the lower semiconductor die 410, and the plurality of first upper reference cells 421 may be some of the upper standard cells included in the upper semiconductor die 420. In some embodiments, each of the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 may include elements manufactured using semiconductor processes having different scales. For example, a single element included in each of the plurality of first lower reference cells 411 may be manufactured using a 5nm process, and a single element included in each of the plurality of first upper reference cells 421 may be manufactured using a 3nm process.

[0056] The plurality of first lower reference cells 411 may provide a plurality of first unit circuits UC1 together with some of the plurality of first via structures 415. The plurality of first upper reference cells 421 may provide a plurality of second unit circuits UC2 together with other first via structures 415. Each of the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 may provide a circuit for inputting and outputting signals through the plurality of first via structures 415.

[0057] like Figure 5 As shown, the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 may be connected in series with each other and may be arranged alternately. The number and type of the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 may vary depending on the first logic gate LG1. In the case where the first logic gate LG1 is a NAND gate, as in Figure 5In the example of FIG, each of the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 can be implemented as a non-inverting cell that outputs an output signal without inverting an input signal. For example, each of the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 can include a buffer, a delay circuit, and the like.

[0058] One of the input terminals of the first logic gate LG1 can receive an enable signal EN, and the other input terminal can be connected to the first pad PD1 (the output terminal of the first ring oscillator). When the enable signal EN is set to a voltage level corresponding to a logical value of "1," the first logic gate LG1 can invert the voltage of the first pad PD1 and output the inverted voltage. Therefore, each of the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 can be configured as a non-inverting cell, allowing a reference clock signal having a predetermined frequency to be output from the first pad PD1.

[0059] In the case where the first logic gate LG1 is a logic gate that does not invert the voltage of the first pad PD1, the configuration of the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 may vary. For example, in the case where the first logic gate LG1 is an AND gate, when the enable signal EN is set to have a voltage level corresponding to a logic value of "1", the first logic gate LG1 may output the voltage of the first pad PD1 without change.

[0060] Therefore, when the first logic gate LG1 is an AND gate, the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 can invert the output voltage of the first logic gate LG1 and apply the inverted output voltage to the first pad PD1, so that the first pad PD1 can output a reference clock signal having a predetermined frequency. The output voltage of the first logic gate LG1 can be inverted in the upper reference cell 421 and applied to the first pad PD1. In this case, each of the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 can include an inverter. For example, each of the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 can be configured as an inverting cell that inverts an input signal to output an output signal, and the total number of the plurality of first lower reference cells 411 and the plurality of first upper reference cells 421 can be an odd number. When the first logic gate LG1 is a NOR gate, when the enable signal EN has a voltage level corresponding to "0", the first ring oscillator can transmit the reference clock signal to the first pad PD1.

[0061] Reference Figure 6The second ring oscillator may include a second logic gate LG2, a plurality of second lower reference cells 412, a plurality of second upper reference cells 422, and a plurality of second via structures 416. The second logic gate LG2 is shown as a NAND gate, but may be implemented as an AND gate, a NOR gate, etc., and may be implemented as the same logic gate as the first logic gate LG1. The second logic gate LG2 may be provided by at least one of the plurality of lower standard cells.

[0062] The plurality of second lower reference cells 412 may be some of the lower standard cells included in the lower semiconductor die 410, and the plurality of second upper reference cells 422 may be some of the upper standard cells included in the upper semiconductor die 420. In some embodiments, each of the plurality of second lower reference cells 412 and the plurality of second upper reference cells 422 may include elements manufactured using semiconductor processes having different scales.

[0063] The plurality of second lower reference cells 412 may provide a plurality of first unit circuits UC1 together with some of the plurality of second via structures 416. The plurality of second upper reference cells 422 may provide a plurality of second unit circuits UC2 together with other second via structures 416. Each of the plurality of second lower reference cells 412 and the plurality of second upper reference cells 422 may provide a circuit capable of transmitting and receiving signals through the plurality of second via structures 416.

[0064] The plurality of second lower reference cells 412 and the plurality of second upper reference cells 422 can be connected in series and arranged alternately. The number and type of the plurality of second lower reference cells 412 can be the same as the number and type of the plurality of first lower reference cells 411 included in the first ring oscillator. Furthermore, the number and type of the plurality of second upper reference cells 422 can be the same as the number and type of the plurality of first upper reference cells 421 included in the first ring oscillator. Therefore, the first unit circuit UC1, which is located at the end along the transmission path of the output signal of the second logic gate LG2, can output a clock signal that is the same as the reference clock signal output by the first ring oscillator to the first pad PD1.

[0065] However, the second ring oscillator may further include a test circuit TC connected to a node between the input terminal of the second logic gate LG2 and the second pad PD2, and connected between the first unit circuit UC1 and the second pad PD2 and the second logic gate LG2. The test circuit TC may include test cells 418, which are some of the plurality of lower standard cells included in the lower semiconductor die 410. The test cells 418 may be connected in series with each other, and the frequency and phase of the first test clock signal output to the second pad PD2 may be determined based on the characteristics of the logic circuit provided by each test cell 418 and the number of test cells 418.

[0066] For example, the test circuit TC can be configured to output an output signal without inverting the input signal. The frequency difference and / or phase difference between the first test clock signal output to the second pad PD2 and the reference clock signal output to the first pad PD1 can be determined by the delay characteristics of the test circuit TC.

[0067] Figure 7 An example of a reference clock signal CKREF output to the first pad PD1 and a first test clock signal CKDET1 output to the second pad PD2 is shown. Figure 7 In the example of FIG. 1 , the reference clock signal CKREF has a first period TP1 , and the first test clock signal CKDET1 has a second period TP2 longer than the first period TP1 . In addition, the first test clock signal CKDET1 has a phase that lags behind by a first delay time TD1 .

[0068] The reference clock signal CKREF may be measured at the first pad PD1, and the first test clock signal CKDET1 may be measured at the second pad PD2 to calculate a difference between the first period TP1 and the second period TP2, thereby determining a delay characteristic of the test cell 418. For example, the difference between the first period TP1 and the second period TP2 may be divided by the number of test cells 418, thereby determining a signal delay characteristic of a single test cell 418.

[0069] Reference Figure 8 , the semiconductor device 400 according to some embodiments of the present disclosure may include a third ring oscillator. The third ring oscillator may be the same as that described above with reference to Figure 5 and Figure 6 The first and second ring oscillators are described as being included together in a single semiconductor device 400. However, in some embodiments, the single semiconductor device 400 may include only the first and second ring oscillators, or only the first and third ring oscillators.

[0070] The third ring oscillator includes a third logic gate LG3, a plurality of third lower reference units 413, a plurality of third upper reference units 423 and a plurality of third via structures 417. Figure 6 In a similar manner to the second ring oscillator described above, the third logic gate LG3 may include the same logic gate as the first logic gate LG1 of the first ring oscillator and may be provided by at least one of the plurality of lower standard cells. Furthermore, the number of the plurality of third lower reference cells 413 may be the same as the number of the plurality of first lower reference cells 411, and the logic circuit provided by each of the plurality of third lower reference cells 413 may be the same as the logic circuit provided by each of the plurality of first lower reference cells 411.

[0071] The number of the plurality of third upper reference cells 423 may be the same as the number of the plurality of first upper reference cells 421, and the logic circuit provided by each of the plurality of third upper reference cells 423 may be the same as the logic circuit provided by each of the plurality of first upper reference cells 421. Therefore, the first unit circuit UC1 provided at the endmost along the transmission path of the output signal of the third logic gate LG3 may output the same clock signal as the reference clock signal output by the first ring oscillator to the first pad PD1.

[0072] like Figure 8 As shown, the third ring oscillator may further include a test circuit TV connected between the input terminal of the third logic gate LG3 and the third pad PD3. The test circuit TV included in the third ring oscillator may include two or more test via structures 419 for electrically connecting the lower semiconductor die 410 and the upper semiconductor die 420 to each other. The test via structures 419 can be connected to each other in series without requiring an input / output circuit. Therefore, the frequency and / or phase of the second test clock signal output to the third pad PD3 can be determined based on the characteristics of each test via structure 419 and the number of test via structures 419.

[0073] Figure 9 An example of a reference clock signal CKREF output to the first pad PD1 and a second test clock signal CKDET2 output to the third pad PD3 is shown. Figure 8 In the example, the test circuit TV may include only test via structures 419 connected to each other, without including a logic circuit for processing signals, so that in some cases the frequency of the second test clock signal CKDET2 may be the same as the frequency of the reference clock signal CKREF generated by the first ring oscillator.

[0074] Reference Figure 9, the second test clock signal CKDET2 may have a third period TP3 that is different from the first period TP1 of the reference clock signal CKREF. Furthermore, or conversely, the second test clock signal CKDET2 may have a phase that lags behind the reference clock signal CKREF by a second delay time TD2. A difference between the first period TP1 of the reference clock signal CKREF measured at the first pad PD1 and the third period TP3 of the second test clock signal CKDET2 measured at the third pad PD3 may be calculated to determine the delay characteristics of the test via structure 419. For example, the difference between the first period TP1 and the third period TP3 may be divided by the number of test via structures 419 to determine the signal delay characteristics of a single via structure included in the semiconductor device 400.

[0075] As reference Figures 5 to 9 As described above, a semiconductor device (e.g., semiconductor device 400) may include a first ring oscillator that generates a reference clock signal CKREF, and a second ring oscillator and / or a third ring oscillator that include test circuits TC and TV on which signal delay characteristics measurements are to be performed. Test circuit TC may be configured to include a test cell 418 on which signal delay characteristics measurements are to be performed, and the frequency and / or phase of a test clock signal CKDET1 output by test circuit TC may be compared with the frequency and / or phase of the reference clock signal CKREF to determine the signal delay characteristics of test cell 418. Furthermore, test circuit TV may be configured to include a test via structure 419, and the frequency and / or phase of a test clock signal CKDET2 output by test circuit TV may be compared with the frequency and / or phase of the reference clock signal CKREF to determine the signal delay characteristics of test via structure 419.

[0076] In some embodiments, the signal delay characteristics occurring in one of the lower semiconductor die 410 and the upper semiconductor die 420 can be compared with the signal delay characteristics occurring between the lower semiconductor die 410 and the upper semiconductor die 420, thereby analyzing the signal delay characteristics of the semiconductor device 400 having a three-dimensional structure. For example, each of the reference ring oscillator generating the reference clock signal and the test ring oscillator generating the test clock signal can be implemented using only standard cells included in the lower semiconductor die 410, and the test ring oscillator can be implemented to include a test circuit TC including the test cell 418.

[0077] The frequencies and / or phases of the reference clock signal and the test clock signal respectively output by the reference ring oscillator and the test ring oscillator implemented only in the lower semiconductor die 410 may be compared with each other to analyze the signal delay characteristics of the test unit 418. In addition, the signal delay characteristics of the test unit 418 analyzed using the reference ring oscillator and the test ring oscillator of the lower semiconductor die 410 may be compared with the signal delay characteristics of the test unit 418 analyzed using the reference ring oscillator and the test ring oscillator of the lower semiconductor die 410. Figure 5 and Figure 6 The signal delay characteristics of the test unit 418 analyzed by the first ring oscillator and the second ring oscillator are compared to determine the influence of the three-dimensional structure of the semiconductor device 400 on the signal delay characteristics.

[0078] In reference Figures 5 to 9 In the described example, logic gates LG1, LG2, and LG3 for implementing a ring oscillator are shown as being included in lower semiconductor die 410 along with pads PD1, PD2, and PD3 to which the ring oscillator outputs a clock signal, but the arrangement of circuit elements is not limited thereto. For example, logic gates LG1, LG2, and LG3 may be included in upper semiconductor die 420, and pads PD1, PD2, and PD3 for outputting clock signals may be included in lower semiconductor die 410. In this case, the paths connecting the input terminals of logic gates LG1, LG2, and LG3 to pads PD1, PD2, and PD3 may include via structures.

[0079] Reference Figure 10 and Figure 11 , the semiconductor device 500 may include a lower semiconductor die 510 and an upper semiconductor die 520. Each of the lower semiconductor die 510 and the upper semiconductor die 520 may include a substrate, a component region, and an interconnection region. A plurality of standard cells may be provided by a plurality of components disposed in the component region and some of the interconnection patterns disposed in the interconnection region. Some of the plurality of lower standard cells disposed in the lower semiconductor die 510 may be connected to some of the plurality of upper standard cells disposed in the upper semiconductor die 520 through a via structure 515 passing through the substrate of the lower semiconductor die 510.

[0080] Figure 10 An example of a first ring oscillator included in the semiconductor device 500 is shown. Figure 10 The first ring oscillator may include a first logic gate LG1, a plurality of first lower reference cells 511, a plurality of first upper reference cells 521, and a plurality of first via structures 515. The first logic gate LG1 is shown as a NAND gate, but may also be implemented as an AND gate, a NOR gate, etc.

[0081] The plurality of first lower reference cells 511 may be some of the lower standard cells included in the lower semiconductor die 510, and the plurality of first upper reference cells 521 may be some of the upper standard cells included in the upper semiconductor die 520. In some embodiments, each of the plurality of first lower reference cells 511 and the plurality of first upper reference cells 521 may include elements manufactured using semiconductor processes having different scales.

[0082] The plurality of first lower reference cells 511 may provide a plurality of first unit circuits UC1 together with some of the plurality of first via structures 515. The plurality of first upper reference cells 521 may provide a plurality of second unit circuits UC2 together with other first via structures 515. In some embodiments, each of the plurality of first lower reference cells 511 and the plurality of first upper reference cells 521 provides a circuit capable of transmitting and receiving signals through the plurality of first via structures 515.

[0083] One of the input terminals of the first logic gate LG1 can receive an enable signal EN, and the other input terminal can be connected to the first pad PD1 (the output terminal of the first ring oscillator). When the enable signal EN is set to a voltage level corresponding to a logical value of "1," the first logic gate LG1 can invert the voltage of the first pad PD1 and output the inverted voltage. Each of the plurality of first lower reference cells 511 and the plurality of first upper reference cells 521 can provide a logic circuit that does not invert the phase of the input signal, allowing the first pad PD1 to output a reference clock signal having a predetermined frequency. However, if the first logic gate LG1 is a logic gate that does not invert the voltage of the first pad PD1 (e.g., an AND gate), each of the plurality of first lower reference cells 511 and the plurality of first upper reference cells 521 can provide a logic circuit that inverts the phase of the input signal. In this case, the total number of the plurality of first unit circuits UC1 and the plurality of second unit circuits UC2 can be an odd number.

[0084] Figure 11 An example of a second ring oscillator included in the semiconductor device 500 is shown. Figure 11 The second ring oscillator may include a second logic gate LG2, a plurality of second lower reference cells 512, a plurality of second upper reference cells 522, and a plurality of second via structures 516. The second logic gate LG2 may be implemented as the same logic gate as the first logic gate LG1.

[0085] The plurality of second lower reference cells 512 may provide a plurality of first unit circuits UC1 together with some of the plurality of second via structures 516. The plurality of second upper reference cells 522 may provide a plurality of second unit circuits UC2 together with other second via structures 516. Each of the plurality of second lower reference cells 512 and the plurality of second upper reference cells 522 may provide a circuit capable of exchanging and receiving signals through the plurality of second via structures 516.

[0086] The number and type of the plurality of second lower reference cells 512 may be the same as the number and type of the plurality of first lower reference cells 511 included in the first ring oscillator. Furthermore, the number and type of the plurality of second upper reference cells 522 may be the same as the number and type of the plurality of first upper reference cells 521 included in the first ring oscillator. Therefore, the first unit circuit UC1, which is located at the end along the transmission path of the output signal of the second logic gate LG2, can output the same clock signal as the reference clock signal output by the first ring oscillator to the first pad PD1.

[0087] However, the second ring oscillator may further include a test circuit TC connected between the input terminal of the second logic gate LG2 and the second pad PD2. The test circuit TC may include test cells 518, which are some of the plurality of lower standard cells included in the lower semiconductor die 510. The test cells 518 may be connected in series with each other, and the frequency and phase of the first test clock signal output to the second pad PD2 may be determined based on the characteristics of the logic circuit provided by each test cell 518 and the number of test cells 518.

[0088] The test circuit TC may be configured to output an output signal without inverting the input signal or changing the frequency of the input signal. Therefore, the signal output to the second pad PD2 may have the same frequency as the signal output to the first pad PD1.

[0089] Reference Figure 10 and Figure 11 Each of the first ring oscillator and the second ring oscillator may include a frequency divider DIV. In the first ring oscillator, the frequency divider DIV may be connected to the front end of the first pad PD1. In the second ring oscillator, the frequency divider DIV may be connected to the front end of the second pad PD2. Using the first ring oscillator as an example, the frequency divider DIV may output a reference clock signal by reducing the frequency of the original clock signal generated by the first logic gate LG1, the plurality of first unit circuits UC1, and the plurality of second unit circuits UC2. For example, the frequency divider DIV may include a plurality of flip-flops connected in series.

[0090] For example, when the frequency of the original clock signal generated by the first logic gate LG1, the plurality of first unit circuits UC1, and the plurality of second unit circuits UC2 is too high, it may be difficult to accurately detect the original clock signal from the first pad PD1. Figure 10 and Figure 11 As shown, by connecting the frequency divider DIV to the front ends of the pads PD1 and PD2 in the first ring oscillator and the second ring oscillator, the frequency of the clock signal can be reduced.

[0091] As described above, the frequency of the clock signal generated by the ring oscillator can be changed according to the number of unit circuits UC1 and UC2 connected to the logic gates LG1 and LG2 in the ring oscillator. For example, as the number of unit circuits UC1 and UC2 increases, the period of the clock signal can be increased and the frequency of the clock signal can be reduced. Figure 10 and Figure 11 As shown, a frequency divider DIV can be used to reduce the frequency of the clock signal generated by the unit circuits UC1 and UC2. Therefore, in order to realize the ring oscillator, the number of unit circuits UC1 and UC2 connected to the logic gates LG1 and LG2 can be reduced.

[0092] Reference Figure 12 and Figure 13 , the semiconductor device 600 may include a lower semiconductor die 610 and an upper semiconductor die 620 stacked on each other in one direction. Figure 12 and Figure 13 As shown, the lower semiconductor die 610 and the upper semiconductor die 620 may be stacked such that a lower substrate of the lower semiconductor die 610 and an upper substrate of the upper semiconductor die 620 are adjacent to each other in one direction.

[0093] For example, the semiconductor device 600 may have the same Figure 3 The structure in the example described is similar to the structure in Figure 12 and Figure 13 As shown, the lower semiconductor die 610 may include a plurality of lower via structures, and the upper semiconductor die 620 may include a plurality of upper via structures. The plurality of lower via structures and the plurality of upper via structures may be connected to each other to form a signal transmission path between the lower semiconductor die 610 and the upper semiconductor die 620.

[0094] Figure 12 FIG. 6 shows a structure of a first ring oscillator included in the semiconductor device 600, which outputs a reference clock signal to the first pad PD1. Figure 12The first ring oscillator may include a first logic gate LG1, a plurality of first lower reference cells 611, a plurality of first upper reference cells 621, a plurality of first lower via structures 615, and a plurality of second upper via structures 625. The first logic gate LG1 is shown as a NAND gate, but may be implemented as an AND gate, a NOR gate, etc.

[0095] The plurality of first lower reference cells 611 may be some of the lower standard cells included in the lower semiconductor die 610, and the plurality of first upper reference cells 621 may be some of the upper standard cells included in the upper semiconductor die 620. In some embodiments, each of the plurality of first lower reference cells 611 and the plurality of first upper reference cells 621 may include elements manufactured using semiconductor processes having different scales.

[0096] The plurality of first lower reference cells 611 may provide a plurality of first unit circuits UC1 together with some of the plurality of first lower via structures 615 and the plurality of second upper via structures 625. The plurality of first upper reference cells 621 may provide a plurality of second unit circuits UC2 together with other of the plurality of first lower via structures 615 and the plurality of second upper via structures 625. The plurality of first unit circuits UC1 and the plurality of second unit circuits UC2 may be alternately arranged and connected in series with each other.

[0097] like Figure 12 As shown, the first logic gate LG1 and the first pad PD1 may be included in the upper semiconductor die 620. The first pad PD1 may be exposed from the interconnection region of the upper semiconductor die 620. Therefore, the reference clock signal generated by the first ring oscillator may be detected by performing a probing operation on the first pad PD1. The operation of the first ring oscillator generating the reference clock signal may be understood with reference to the above example.

[0098] Figure 13 FIG. 6 shows a structure of a second ring oscillator included in the semiconductor device 600, which outputs a test clock signal to the second pad PD2. Figure 13 The second ring oscillator may include a second logic gate LG2 , a plurality of second lower reference cells 612 , a plurality of second upper reference cells 622 , a plurality of second lower via structures 625 , and a plurality of second upper via structures 626 .

[0099] The plurality of second lower reference cells 612 may be some of the lower standard cells included in the lower semiconductor die 610, and the plurality of second upper reference cells 622 may be some of the upper standard cells included in the upper semiconductor die 620. The number of the plurality of second lower reference cells 612 may be the same as the number of the plurality of first lower reference cells 611, and the logic circuit provided by each of the plurality of second lower reference cells 612 may be the same as the logic circuit provided by each of the plurality of first lower reference cells 611. The number of the plurality of second upper reference cells 622 may be the same as the number of the plurality of first upper reference cells 621, and the logic circuit provided by each of the plurality of second upper reference cells 622 may be the same as the logic circuit provided by each of the plurality of first upper reference cells 621.

[0100] Therefore, the clock signal input to the test circuit TC can have the same frequency as the reference clock signal output by the first ring oscillator. The test circuit TC may include a plurality of test cells 628 connected in series, and the plurality of test cells 628 may be some of the upper standard cells included in the upper semiconductor die 620. The frequency and phase of the test clock signal output to the second pad PD2 may be determined according to the number of the plurality of test cells 628 and the signal delay characteristics occurring in the logic circuit provided by each of the plurality of test cells 628.

[0101] For example, a reference clock signal is measured at a first pad PD1 of the semiconductor device, a test clock signal is measured at a second pad PD2 of the semiconductor device, and a period difference between the reference clock signal and the test clock signal is calculated. For example, the period difference between the reference clock signal and the test clock signal can be divided by the number of test cells 628 to determine the signal delay characteristics of the logic circuit implemented as a single test cell 628.

[0102] In reference Figure 12 and Figure 13 In the depicted example, in some embodiments, pads PD1 and PD2 for detecting a clock signal may be provided in the lower semiconductor die 610, unlike the logic gates LG1 and LG2 provided in the upper semiconductor die 620 in this example. For example, input terminals of the logic gates LG1 and LG2 to which clock signals are fed back may be connected to via structures and thus electrically connected to the pads PD1 and PD2 provided in the lower semiconductor die 610.

[0103] Reference Figures 14 to 16 , the semiconductor device 700 includes a lower semiconductor die 710 and an upper semiconductor die 720 stacked on each other in one direction. Figures 14 to 16In the depicted example, logic gates LG1 , LG2 , and LG3 for implementing a ring oscillator and pads PD1 , PD2 , and PD3 for detecting a clock signal generated by the ring oscillator are included in different semiconductor dies 710 and 720 .

[0104] Figure 14 FIG. 7 shows a first ring oscillator included in the semiconductor device 700, which outputs a reference clock signal to the first pad PD1. Figure 14 The first ring oscillator may include a first logic gate LG1, a plurality of first lower reference units 711, a plurality of first upper reference units 721, a plurality of first via structures 715, etc. An enable signal EN may be input to a first input terminal of the first logic gate LG1, and an original clock signal may be fed back to a second input terminal of the first logic gate LG1.

[0105] The plurality of first lower reference cells 711 may be some of the lower standard cells included in the lower semiconductor die 710, and the plurality of first upper reference cells 721 may be some of the upper standard cells included in the upper semiconductor die 720. In some embodiments, each of the plurality of first lower reference cells 711 and the plurality of first upper reference cells 721 may include an element manufactured using a semiconductor process having a different scale. At least one of the plurality of upper standard cells may provide a first logic gate LG1.

[0106] The plurality of first lower reference cells 711, together with some of the plurality of first lower via structures 715, provide a plurality of first unit circuits UC1. The plurality of first upper reference cells 721, together with other of the plurality of first lower via structures 715, provide a plurality of second unit circuits UC2. The plurality of first unit circuits UC1 and the plurality of second unit circuits UC2 may be alternately arranged and connected in series with each other.

[0107] like Figure 14 As shown, the first pad PD1 can be connected to a node between the first unit circuit UC1 and the second unit circuit UC2, which are sequentially connected from the input terminal of the first logic gate LG1 (e.g., the node closest to the input terminal of the first logic gate LG1). Therefore, the reference clock signal can be output to the first pad PD1 without passing through a via structure other than the plurality of first via structures 715 included in the first ring oscillator.

[0108] Figure 15 FIG. 7 shows a second ring oscillator included in the semiconductor device 700, which outputs a first test clock signal to the second pad PD2. Figure 15The second ring oscillator may include a second logic gate LG2, a plurality of second lower reference units 712, a plurality of second upper reference units 722, a plurality of second via structures 716, etc. An enable signal EN may be input to a first input terminal of the second logic gate LG2, and the original clock signal may be fed back to a second input terminal of the second logic gate LG2.

[0109] The number of the plurality of second lower reference cells 712 may be the same as the number of the plurality of first lower reference cells 711, and the logic circuit provided by each of the plurality of second lower reference cells 712 may be the same as the logic circuit provided by each of the plurality of first lower reference cells 711. The number of the plurality of second upper reference cells 722 may be the same as the number of the plurality of first upper reference cells 721, and the logic circuit provided by each of the plurality of second upper reference cells 722 may be the same as the logic circuit provided by each of the plurality of first upper reference cells 721. At least one of the plurality of upper standard cells may provide a second logic gate LG2.

[0110] Therefore, the original clock signal fed back to the second input terminal of the first logic gate LG1 can be the same as the original clock signal fed back to the second input terminal of the second logic gate LG2. In addition, in the second ring oscillator, the clock signal sent to the test circuit connected to the node between the first unit circuit UC1 and the second unit circuit UC2 sequentially connected to the second input terminal can be a signal substantially the same as the reference clock signal output by the first ring oscillator to the first pad PD1.

[0111] Therefore, the first test clock signal output to the second pad PD2 may have a frequency difference and / or a phase difference relative to the reference clock signal output to the first pad PD1. The frequency difference and / or phase difference between the reference clock signal and the first test clock signal may be determined by the test circuit TC. For example, the difference between the period of the reference clock signal and the period of the first test clock signal may be determined based on the number of test cells 728 included in the test circuit TC and the signal delay characteristics of the logic circuit provided by a single test cell 728. Therefore, the period difference between the reference clock signal and the first test clock signal may be divided by the number of test cells 728 to determine the signal delay characteristics of the logic circuit provided by a single test cell 728.

[0112] Figure 16 A third ring oscillator is shown included in the semiconductor device 700. Figure 15 A second ring oscillator together with or instead of Figure 15 The second ring oscillator outputs a second test clock signal to the third pad PD3. Figure 16The third ring oscillator may include a third logic gate LG3, a plurality of third lower reference units 713, a plurality of third upper reference units 723, a plurality of third via structures 717, etc. An enable signal EN may be input to a first input terminal of the third logic gate LG3, and the original clock signal may be fed back to a third input terminal of the third logic gate LG3.

[0113] The number of the plurality of third lower reference cells 713 may be the same as the number of the plurality of first lower reference cells 711, and the logic circuit provided by each of the plurality of third lower reference cells 713 may be the same as the logic circuit provided by each of the plurality of first lower reference cells 711. The number of the plurality of third upper reference cells 723 may be the same as the number of the plurality of first upper reference cells 721, and the logic circuit provided by each of the plurality of third upper reference cells 723 may be the same as the logic circuit provided by each of the plurality of first upper reference cells 721. At least one of the plurality of upper standard cells may provide a third logic gate LG3.

[0114] Therefore, the original clock signal fed back to the second input terminal of the first logic gate LG1 can be the same as the original clock signal fed back to the third input terminal of the third logic gate LG3. In addition, in the third ring oscillator, the clock signal input to the test circuit TV can be a signal substantially the same as the reference clock signal output by the first ring oscillator to the first pad PD1.

[0115] The second test clock signal output to the third pad PD3 may have a frequency difference and / or a phase difference relative to the reference clock signal output to the first pad PD1. The second test clock signal may have the same frequency as the reference clock signal. For example, the frequency difference and / or phase difference between the reference clock signal and the second test clock signal may be determined based on the number of test via structures 719 included in the test circuit TV and the signal delay characteristics caused by the resistance component, capacitance component, etc. of each test via structure 719. In some embodiments, the difference between one cycle of the reference clock signal and one cycle of the second test clock signal may be divided by the number of test via structures 719 to determine the signal delay characteristics occurring in a single test via structure 719.

[0116] According to some embodiments of the present disclosure, such as Figures 1 to 16As described above, a semiconductor device including stacked semiconductor dies may include a first ring oscillator that generates a reference clock signal, and a second ring oscillator that includes cells and / or TSVs on which delay characteristic measurements are to be performed. The frequency and / or phase of the reference clock signal output by the first ring oscillator may be compared with the frequency and / or phase of the test clock signal output by the second ring oscillator to accurately determine the delay characteristics of the cells and / or TSVs included in the semiconductor device, thereby improving the performance and reliability of the semiconductor device.

[0117] Although the present disclosure contains many specific implementation details, these details should not be interpreted as limiting the scope of the possible claims. Certain features described in the present disclosure in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, different features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in any appropriate sub-combination. In addition, although features may be described as working in certain combinations, in some cases, one or more features from a combination may be deleted from the combination, and a combination may be directed to a sub-combination or a variant of a sub-combination.

[0118] While various examples have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure.

Claims

1. A semiconductor device comprising: The lower semiconductor die comprises: Lower substrate, A plurality of lower standard cells are provided on the lower substrate, a plurality of via structures extending in the lower substrate, and a plurality of pads; and The upper semiconductor die includes: upper substrate, and A plurality of upper standard cells are provided on the upper substrate, the upper semiconductor die is stacked on the lower semiconductor die, wherein the first plurality of standard cells among the plurality of lower standard cells and the plurality of upper standard cells include a first logic gate and a second logic gate, The first logic gate, a first lower reference cell as part of the plurality of lower standard cells, a first upper reference cell as part of the plurality of upper standard cells, and a first via structure of the plurality of via structures together form a first ring oscillator. The second logic gate, a second lower reference cell as another part of the plurality of lower standard cells, a second upper reference cell as another part of the plurality of upper standard cells, a second via structure among the plurality of via structures, and a test circuit connected between the second via structure and an input terminal of the second logic gate together form a second ring oscillator, and The first ring oscillator is configured to output a reference clock signal to a first pad among the plurality of pads, and the second ring oscillator is configured to output a test clock signal to a second pad among the plurality of pads.

2. The semiconductor device according to claim 1, wherein The test circuit includes a lower test cell, and wherein the lower test cell includes a lower standard cell among the plurality of lower standard cells.

3. The semiconductor device according to claim 1, wherein The test circuit includes an upper test cell, and wherein the upper test cell includes an upper standard cell among the plurality of upper standard cells.

4. The semiconductor device according to claim 1, wherein The test circuit includes a test via structure, and wherein the test via structure includes a via structure of the plurality of via structures.

5. The semiconductor device according to claim 1, wherein: An output terminal of the first logic gate is directly connected to one of the first lower reference cell, the first upper reference cell, and the first via structure, and An output terminal of the second logic gate is directly connected to one of the second lower reference cell, the second upper reference cell, and the second via structure. The semiconductor device according to claim 5 , wherein: Respective input terminals of the first logic gate and the second logic gate are configured to receive an enable signal.

7. The semiconductor device according to claim 1, wherein: The number of the first lower reference units is equal to the number of the second lower reference units, The number of the first upper reference cells is equal to the number of the second upper reference cells, and The number of the first via structures is equal to the number of the second via structures.

8. The semiconductor device according to claim 7, wherein: each of the first lower reference cells includes a logic circuit configured to operate identically to the logic circuit included in each of the second lower reference cells, and Each of the first upper reference cells includes a logic circuit configured to operate identically to a logic circuit included in each of the second upper reference cells.

9. The semiconductor device according to claim 1, wherein: Each of the first logic gate and the second logic gate is a NAND gate, and Each of the first lower reference cell, the first upper reference cell, the second lower reference cell, and the second upper reference cell is a non-inverting cell.

10. The semiconductor device according to claim 1, wherein: Each of the first logic gate and the second logic gate is a NOR gate or an AND gate, Each of the first lower reference cell, the first upper reference cell, the second lower reference cell, and the second upper reference cell is an inverting cell, and A total number of the first lower reference cell and the first upper reference cell is an odd number, and a total number of the second lower reference cell and the second upper reference cell is an odd number.

11. The semiconductor device according to claim 1 , wherein: The first ring oscillator includes a first frequency divider connected to the first pad, and The second ring oscillator includes a second frequency divider connected to the second pad.

12. The semiconductor device according to claim 1, wherein Each of the first lower reference cell, the first upper reference cell, the second lower reference cell, and the second upper reference cell includes a circuit configured to input and output a signal through the first via structure or the second via structure.

13. A semiconductor device comprising: The lower semiconductor die comprises: a lower element region, comprising a plurality of lower elements disposed on a lower substrate, a lower interconnection region disposed on the lower element region, and a plurality of lower via structures extending in the lower substrate; and The upper semiconductor die includes: an upper element region including a plurality of upper elements disposed on an upper substrate, and an upper interconnection region disposed on the upper element region, wherein the upper semiconductor die is stacked on the lower semiconductor die along a first direction, wherein the first lower element among the plurality of lower elements and the first upper element among the plurality of upper elements together form: a first ring oscillator configured to output a reference clock signal generated on a signal transmission path including a first via structure among the plurality of lower via structures, and The second ring oscillator is configured to output a test clock signal generated on a signal transmission path including a second via structure different from the first via structure among the plurality of lower via structures.

14. The semiconductor device according to claim 13, wherein Along the first direction, the upper interconnection region is arranged between the lower element region and the upper element region.

15. The semiconductor device according to claim 14, wherein The upper interconnection region and the lower interconnection region are arranged between the lower element region and the upper element region along the first direction.

16. The semiconductor device according to claim 13, wherein The number of the first via structures is equal to the number of the second via structures.

17. The semiconductor device according to claim 13, wherein The lower element region or the upper element region includes: a first logic gate included in the first ring oscillator, and A second logic gate is included in the second ring oscillator.

18. The semiconductor device according to claim 17, wherein The lower interconnection region or the upper interconnection region comprises: a first pad to which the reference clock signal is output, and The second pad is where the test clock signal is output.

19. A semiconductor device comprising a lower semiconductor die and an upper semiconductor die stacked on each other, the semiconductor device comprising: A first ring oscillator comprising: a first lower unit circuit included in a first lower standard cell among the lower standard cells, the lower standard cell included in the lower semiconductor die, a first upper unit circuit included in a first upper standard cell among upper standard cells included in the upper semiconductor die, wherein the first upper unit circuit and the first lower unit circuit are alternately connected to each other, and a first logic gate having a first input terminal configured to receive an enable signal and a second input terminal connected to one of the first lower unit circuit and the first upper unit circuit; and A second ring oscillator comprising: a second lower unit circuit included in a second lower standard cell among the lower standard cells; a second upper unit circuit included in a second upper standard cell among the upper standard cells, wherein the second upper unit circuit and the second lower unit circuit are alternately connected to each other, a second logic gate having a first input terminal configured to receive the enable signal and a second input terminal connected to one of the second lower unit circuit and the second upper unit circuit, and The test circuit is configured to delay the original clock signal input to the second input terminal of the second logic gate.

20. The semiconductor device according to claim 19, wherein: The first ring oscillator is configured to output a reference clock signal input to the second input terminal of the first logic gate to a first pad, and The second ring oscillator is configured to output a test clock signal to a second pad, the test clock signal including an original clock signal that has been delayed by the test circuit.

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