Circuit function test method based on scan chain recombination

Abstract

The invention discloses a circuit function test method based on scan chain recombination, which comprises the following steps of: setting a function register as a plurality of groups of multi-modular redundancy registers, and setting a voter at the output end of each group of multi-modular redundancy registers; reconstructing each group of multi-modular redundancy registers into at least one scan chain according to a scan chain structure; setting a scanning enabling end of a multiplexer connected with the first group of multi-modular redundancy registers to be in an activated state, and repeating the following iteration steps from the first group of multi-modular redundancy registers, a test response sequence used for the circuit function test is output at the tail end; the input test excitation sequence is transmitted to each redundancy register unit of the multimode redundancy register of the current group; the test excitation sequence is output through the voter arranged at the output end of the current group of multi-modular redundancy registers and then serves as the input of the next group of multi-modular redundancy registers.

Description

Technical Field

[0001] The present invention relates to functional testing, in particular to a circuit functional testing method based on scan chain reorganization. Background Art

[0002] As chip integration continues to increase, testing chip circuit functionality is becoming increasingly important in the overall design process. Traditional chip testing processes rely primarily on manually generating test sequences using simulation-driven stimuli and then comparing the simulation model's response with the hardware circuit to verify circuit functionality. While widely used, this approach faces significant challenges in testing efficiency and accuracy when applied to large-scale, complex chip systems.

[0003] Chinese invention patent CN113312879A discloses a chip circuit functional testing system, method, device, and storage medium. This system automatically extracts instruction streams from software simulation results through a stimulus generation module to generate target verification stimuli. This system then combines an execution module with a reference model to perform parallel verification of the circuit under test. Verification results are then compared with a checker to improve verification efficiency and consistency. However, this solution targets general functional circuit designs and does not consider the verification complexity of redundant circuit structures in high-reliability chips. Summary of the Invention

[0004] The present invention provides a circuit function testing method based on scan chain reorganization to solve the technical problem that the existing technology does not consider the testing complexity of redundant circuit structures in high-reliability chips. It significantly optimizes the functional test path design and test process of high-reliability circuits under multi-mode redundant structures, and is suitable for circuit function testing requirements in scenarios such as high reliability and strong interference sensitivity.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: The present invention provides a circuit function testing method based on scan chain reorganization, comprising: Setting the function registers as multiple groups of multi-module redundant registers, and setting a voter at the output end of each group of the multi-module redundant registers; Reconstructing each group of the multi-mode redundant registers into at least one scan chain according to a scan chain structure; wherein an input end of the scan chain is connected to an input end of the test stimulus sequence, and an output end of the scan chain is connected to an output end of the test response sequence; Setting a scan enable terminal of a multiplexer connected to the first group of multi-mode redundant registers to an activated state, and starting from the first group of multi-mode redundant registers, repeating the following iterative steps, so that a test stimulus sequence is processed sequentially by each group of multi-mode redundant registers in the scan chain and a voter provided at an output terminal of each group of multi-mode redundant registers, and then outputting a test response sequence for the circuit function test at the end of the scan chain: Transmitting the input test stimulus sequence to each redundant register unit of the multi-module redundant register of the current group; The test stimulus sequence is outputted by the voter provided at the output end of the multi-module redundant register of the current group, and then serves as the input of the multi-module redundant register of the next group.

[0006] In an optional embodiment, each group of the multi-module redundant registers includes at least three redundant register units arranged in parallel.

[0007] In an optional embodiment, the processing of the test stimulus sequence by the voter includes: performing a majority vote on the output data of each redundant register unit in the corresponding group of multi-module redundant registers, and outputting a voting result consistent with the majority data.

[0008] In an optional embodiment, the multiplexer has the scan enable terminal and at least one input channel; the method further includes: During the functional test phase, the scan enable terminal is set to an activated state so that the scan enable terminal selects a test stimulus sequence as an input of the multi-mode redundant register.

[0009] In an optional embodiment, the multiplexer has the scan enable terminal and at least two input channels; the method further includes: During the functional test phase, the scan enable terminal is set to an activated state so that the scan enable terminal selects a test stimulus sequence as the input of the first group of the multi-mode redundant registers and selects the output of the voter of the previous group of the multi-mode redundant registers as the input of other groups of the multi-mode redundant registers.

[0010] In an optional embodiment, reconstructing each group of the multi-module redundant registers into at least one scan chain according to a scan chain structure includes: Grouping the redundant register units of each group of the multi-module redundant registers according to a physical layout or a logical order; Establishing a series path between each group of the multi-module redundant registers and an adjacent group of the multi-module redundant registers by connecting the output end of the voter to the input end of the multiplexer; The series paths are connected in sequence to form a continuous scan chain path.

[0011] In an optional embodiment, the method further includes: before setting the scan enable end of the multiplexer connected to the first group of the multi-mode redundant registers to an activated state, generating the test stimulus sequence through an automatic test vector generation tool, and adapting the test path according to the reconstructed structure of the scan chain so that the test stimulus sequence conforms to the logical path of the current scan chain.

[0012] In an optional embodiment, the method further includes: after outputting a test response sequence for the circuit function test at the end, comparing the test stimulus sequence and the test response sequence, and verifying that the circuit function is correct after redundancy when the test stimulus sequence and the test response sequence are the same.

[0013] In an optional embodiment, when the test stimulus sequence and the test response sequence are different, a new test stimulus sequence is reloaded, and the iterative steps are repeated starting from the first group of the multi-mode redundant registers, so that a new test response sequence for the circuit functional test is output at the end, and the new test stimulus sequence and the new test response sequence are compared.

[0014] The beneficial effects brought about by the technical solution provided by the present invention include at least: 1. The present invention realizes the step-by-step transmission of the test stimulus sequence in the scan chain by setting a multiplexer between redundant register groups and using a scan enable terminal to control the selection of different data paths, thereby avoiding the problems of complex manual construction of test paths and incomplete test processes in traditional multi-mode redundant designs.

[0015] 2. The present invention reconstructs multiple groups of multi-mode redundant registers into at least one or more scan chains in a scan chain structure, and configures paths based on physical layout or logical order, so that the scan chain structure can adapt to different circuit layouts and functional requirements, thereby improving the reusability and adaptability of the test path.

[0016] 3. The present invention sets a scan enable terminal of the multiplexer to dynamically select the test stimulus sequence or the output of the previous set of voters as the register group input at different stages, thereby realizing the switching between the scan chain mode and the functional mode during the test process and enhancing the dynamic controllability of the test link.

[0017] 4. The present invention combines an automatic test vector generation tool to automatically generate an adaptive test stimulus sequence based on the scan chain reconstruction path, ensuring that the stimulus sequence conforms to the current link topology, thereby improving the validity of test data and the comprehensiveness of circuit function testing.

[0018] 5. The present invention ensures the consistency of the output results of each group of multi-mode redundant registers through a majority voting mechanism, and improves the functional correctness testing capability of redundant circuits under fault environments such as electromagnetic interference and bit flipping. It is particularly suitable for chip circuit testing needs in high-reliability fields.

[0019] 6. When the test response sequence is inconsistent, the present invention automatically reloads the test stimulus sequence and repeats the scanning process, supports multiple iterative comparison tests, and enhances the detection capability of abnormal paths and faulty nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0021] Figure 1 This is an overall schematic diagram of a scan chain combined with a reinforcement circuit provided by an embodiment of the present invention; Figure 2 Schematic diagram of a scan chain transmission method under general circumstances provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of adding a multi-module redundant register and establishing a connection relationship provided by an embodiment of the present invention; Figure 4 This is a schematic diagram of changing the register type and adding a MUX selector according to an embodiment of the present invention; Figure 5 This is a schematic diagram of adding a voting device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. The following embodiments are implemented based on the technical solutions of the present invention, and detailed implementation methods and specific operating procedures are given, but the scope of protection of the present invention is not limited to the following embodiments. Obviously, the embodiments described are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0023] In the present invention, words such as "in one possible embodiment," "exemplary," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in the present invention as "in one possible embodiment," "exemplary," or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "in one possible embodiment," "exemplary," or "for example" is intended to present the relevant concepts in a concrete manner.

[0024] The present invention provides a circuit function testing method based on scan chain reorganization, comprising: S101, setting the function registers into multiple groups of multi-module redundant registers, and setting a voter at the output end of each group of the multi-module redundant registers.

[0025] In this embodiment, the multi-module redundant register may be a synchronous trigger register, an edge trigger register, or a delay trigger register, and the voter may be a majority voting logic device.

[0026] Exemplarily, the multi-module redundant registers are replaced by original functional registers with scan inputs, while the replaced multi-module redundant registers are standard data trigger registers. For example, the original functional registers are split into five groups of multi-module redundant registers, each group consisting of three D flip-flops, with the voter using three-input majority decision logic. By sequentially controlling the multiplexers, the test stimulus sequence is transmitted to each group of registers, and a test response sequence is output at the end for subsequent functional comparison.

[0027] In an optional embodiment, each group of the multi-module redundant registers includes at least three redundant register units arranged in parallel.

[0028] For example, each multi-module redundant register group consists of three D flip-flops, designated FFx_1, FFx_2, and FFx_3. These three registers receive input signals in parallel and their outputs are connected to the voter. Furthermore, to improve reliability, this can be expanded to five or seven D flip-flops, using a 5 / 7 decision logic.

[0029] In an optional embodiment, the processing of the test stimulus sequence by the voter includes: performing a majority vote on the output data of each redundant register unit in the corresponding group of multi-module redundant registers, and outputting a voting result consistent with the majority data.

[0030] Exemplarily, in the implementation of the voter, a hardware majority voter Majority_x is used, whose input ends respectively receive the output signals of the three register units of the corresponding register group, and judge whether the outputs of at least two register units are the same through circuit logic, and output the voting result consistent with the majority data. The voter can be implemented using synchronous or asynchronous logic.

[0031] S102: Reconstruct each group of the multi-module redundant registers into at least one scan chain according to a scan chain structure.

[0032] The input end of the scan chain is connected to the input end of the test stimulus sequence, and the output end is connected to the output end of the test response sequence.

[0033] Exemplarily, the scan chain is a configurable multi-scan chain structure, each of which transmits different segments of the test stimulus sequence in parallel to speed up the test process. Scan chain reconstruction methods include sequential reconstruction and / or segment-by-segment reconstruction to support dynamic topology switching of the scan chain structure. For example, during the test process initialization phase, each group of multi-mode redundant registers is first reconstructed into a scan chain through the connection path of the multiplexer and the voter according to the logical order of the scan chain; wherein the starting end test_si of the scan chain inputs the first group of registers through MUX_1, and the ending end test_so is output from the last group of voters.

[0034] In an optional embodiment, reconstructing each group of the multi-module redundant registers into at least one scan chain according to a scan chain structure includes: Grouping the redundant register units of each group of the multi-module redundant registers according to a physical layout or a logical order; Establishing a series path between each group of the multi-module redundant registers and an adjacent group of the multi-module redundant registers by connecting the output end of the voter to the input end of the multiplexer; The series paths are connected in sequence to form a continuous scan chain path.

[0035] Exemplarily, the reconstruction order of the scan chain can be configured according to the physical layout or logical function order of the chip layout; in the physical layout mode, adjacent register groups are preferentially selected for series connection; in the logical order mode, the register groups are connected according to the execution order of the functional blocks; a series path is established between each group of registers through the output end of the voter Majority_x and the input end of MUX_(x+1) to form a continuous scan chain.

[0036] In an optional embodiment, the method further includes: before setting the scan enable end of the multiplexer connected to the first group of the multi-mode redundant registers to an activated state, generating the test stimulus sequence through an automatic test vector generation tool, and adapting the test path according to the reconstructed structure of the scan chain so that the test stimulus sequence conforms to the logical path of the current scan chain.

[0037] For example, commercial automatic test vector generation ATPG tools such as Synopsys, Mentor or Cadence are used to automatically generate test stimulus sequences that match the scan chain paths. The test stimulus data follows the scan chain topology and is injected into each group of multi-mode redundant registers step by step to cover all functional paths and potential fault nodes.

[0038] S103, setting the scan enable end of the multiplexer connected to the first group of the multi-mode redundant registers to an activated state, and starting from the first group of the multi-mode redundant registers, repeating the following iterative steps S103a and S103b, so that the test stimulus sequence is processed by each group of the multi-mode redundant registers and the voter set at the output end of each group of the multi-mode redundant registers in turn, and then outputting a test response sequence for the circuit function test at the end.

[0039] S103a, transmitting the input test stimulus sequence to each redundant register unit of the multi-module redundant register of the current group.

[0040] S103b: The test stimulus sequence is outputted by the voter provided at the output end of the multi-module redundant register of the current group, and then serves as the input of the multi-module redundant register of the next group.

[0041] In this embodiment, the multiplexer may have a control interface that supports dynamic switching between the scanning mode and the functional mode, and may be restored to the original functional connection in the non-scanning state.

[0042] In an optional embodiment, the multiplexer has the scan enable terminal and at least one input channel; the method further includes: During the functional test phase, the scan enable terminal is set to an activated state so that the scan enable terminal selects a test stimulus sequence as an input of the multi-mode redundant register.

[0043] For example, during the functional test phase, the scan enable terminal SE of the multiplexer is set high, allowing the inputs of the first set of multi-module redundant registers to be directly injected from the test stimulus sequence test_si. The input channels of the multiplexer can be implemented using a hardware multiplexing structure, and the SE control signal is dynamically configured through the chip test control interface.

[0044] In an optional embodiment, the multiplexer has the scan enable terminal and at least two input channels; the method further includes: During the functional test phase, the scan enable terminal is set to an activated state so that the scan enable terminal selects a test stimulus sequence as the input of the first group of the multi-mode redundant registers and selects the output of the voter of the previous group of the multi-mode redundant registers as the input of other groups of the multi-mode redundant registers.

[0045] Exemplarily, a multiplexer with at least two input channels is used for different register groups. The multiplexer input for the first group of registers is test_si, while the multiplexer inputs for the remaining groups of registers are derived from the Majority_(n-1)_out output of the previous group of voters. During the scan chain transfer phase, all SE control signals remain active to ensure data is loaded from test_si. During the function transfer phase, the SE control signals are turned off, switching to the voter cascade input.

[0046] In an optional embodiment, the method further includes: after outputting a test response sequence for the circuit function test at the end, comparing the test stimulus sequence and the test response sequence, and verifying that the circuit function is correct after redundancy when the test stimulus sequence and the test response sequence are the same.

[0047] For example, after the scan chain transmission is completed, the test response sequence test_so output by the terminal is compared bit by bit with the initial test stimulus sequence test_si through an on-chip comparison circuit or an external comparison module. If the two are completely consistent, the redundantly reinforced circuit is considered to be functional correctly and the test passes.

[0048] In an optional embodiment, when the test stimulus sequence and the test response sequence are different, a new test stimulus sequence is reloaded, and the iterative steps are repeated starting from the first group of the multi-mode redundant registers, so that a new test response sequence for the circuit functional test is output at the end, and the new test stimulus sequence and the new test response sequence are compared.

[0049] Functional testing can therefore include multiple comparisons of the test stimulus sequence and the test response sequence to identify potential errors in the scan chain path. For example, if the test response sequence is inconsistent with the test stimulus sequence, the control module reloads a new test stimulus sequence (test_si), transmits it through the scan chain again, and acquires the test response sequence (test_so). This process can be iterated a preset number of times, such as three or five times, to ensure that the fault path is fully exposed, improving test coverage and accuracy.

[0050] Based on the above method, the present invention realizes the step-by-step transmission of the test stimulus sequence in the scan chain by setting a multiplexer between the redundant register groups and using the scan enable terminal to control the selection of different data paths, thereby avoiding the problems of complex manual construction of test paths and incomplete test processes under traditional multi-mode redundancy design. The present invention reconstructs multiple groups of multi-mode redundant registers into at least one or more scan chains with a scan chain structure, and configures the paths based on the physical layout or logical order, so that the scan chain structure can adapt to different circuit layouts and functional requirements, thereby improving the reusability and adaptability of the test path. The present invention dynamically selects the test stimulus sequence or the output of the previous group of voters as the register group input at different stages by setting the scan enable terminal of the multiplexer, thereby realizing the switching between the scan chain mode and the functional mode during the test process, and enhancing the dynamic controllability of the test link. The present invention is combined with an automatic test vector generation tool to automatically generate an adaptive test stimulus sequence based on the scan chain reconstruction path, ensuring that the stimulus sequence conforms to the current link topology, improving the validity of the test data and the comprehensiveness of the circuit function test. This invention uses a majority voting mechanism to ensure the consistency of output results from each group of multi-module redundant registers, improving the ability to test the functional correctness of redundant circuits in environments with faults such as electromagnetic interference and bit flips. It is particularly suitable for testing chip circuits in high-reliability applications. When the test response sequence is inconsistent, the invention automatically reloads the test stimulus sequence and repeats the scanning process, supporting multiple iterative comparison tests and enhancing the detection of abnormal paths and faulty nodes.

[0051] The operating state of logic chips can be affected by electromagnetic interference generated by radio frequency transmitters and power supplies, causing circuit "0" and "1" bit flips and leading to logic errors. High-speed data transmission control chips are responsible for the transmission, forwarding, and storage of high-speed data. They are core components of data storage systems and place extremely high demands on the reliability of the chip's internal circuitry. Internal registers are used for temporary storage of instructions and data. When a bit flip occurs, it can lead to system errors such as data transmission errors, bus locks, and disk failures.

[0052] Multi-mode redundancy (MMR) is an effective and widely used reinforcement technology for high-reliability circuit design. However, the addition of redundant registers complicates circuit functionality testing. This paper addresses this issue by providing a circuit functionality testing method based on scan chain reorganization. By constructing one or more MMR register scan chains, this method simplifies the test vector generation process and effectively tests the functional correctness of redundantly reinforced high-reliability circuits.

[0053] The purpose of the present invention is to provide a circuit functional testing method based on scan chain reorganization, aiming to solve the technical problem of difficulty in generating verification vectors when performing functional testing on redundant reinforced high-reliability circuits in the prior art.

[0054] In one possible implementation, a scan chain structure can be constructed for the original functional registers. Then, multi-mode redundant replacement operations can be performed on the original functional registers in steps, and each group of multi-mode redundant registers can be strung together into a chain to reconstruct the scan chain characteristics. This allows the use of ATPG tools to automatically generate test vectors. During functional testing, the scan chain design concept can be used to reconstruct each group of multi-mode redundant registers into a scan chain. The test stimulus sequence test_si is transmitted to the first group of multi-mode redundant register circuits via selector MUX1. The data is then selected by voter 1 and transmitted to the next group of multi-mode redundant circuits. Finally, a test response sequence test_so can be obtained at the data output of the last group of circuits. Specifically, the test stimulus sequence test_si can be transmitted through a series of multi-mode redundant circuits and output as the test response sequence test_so. Figure 1 FIG. 1 is an overall schematic diagram of a scan chain combined with a reinforcement circuit according to an embodiment of the present invention. Figure 1 As shown in the figure, after the test stimulus sequence test_si passes through each set of multi-mode redundant reinforced circuits, the test response sequence test_so is generated at the receiving end. By comparing test_so with tset_si, for example, by collecting the transmitted data at the data receiving end, the differences between the test_so and tset_si sequences can be compared to verify the functional correctness of the high-reliability circuit. If the two sequences are identical, the circuit function after redundancy is correct, or in other words, the high-reliability circuit function after redundancy reinforcement is verified to be correct.

[0055] Specifically, the scan chain transmission may mainly include the following steps: Step 1: When the SE terminal of MUX1 is set to 1, the test stimulus sequence test_si passes through the 1 port of MUX1 and is output from the Y terminal; Step 2: Connect the Y port of MUX1 in step 1 to the D port of the multi-mode redundant register; Step 3: Connect the output port Q of the multi-module redundant register in step 2 to the input port of voter 1; Step 4: Connect the data obtained from the voter in step 3 to port 1 of MUX2; Step 5: After repeated iterations of steps 1 to 4, the test response sequence test_so is finally output at the receiving end.

[0056] Among them, the scan chain transmission is mainly the process of transmitting the test stimulus sequence test_si through the multi-mode redundant register.

[0057] Figure 2 FIG. 1 is a schematic diagram of a scan chain transmission method under general circumstances provided by an embodiment of the present invention. Figure 2As shown in the figure, the scan chain is generally composed of SDFF type registers with SI ports. The test stimulus sequence test_si is connected to the SI end of register FF1_1, and the data output Q of FF1_1 is connected to the SI end of the next register FF2_1, and so on, and finally the test response sequence test_so is received.

[0058] Figure 3 FIG. 1 is a schematic diagram of adding a multi-module redundant register and establishing a connection relationship provided by an embodiment of the present invention. Figure 3 As shown, in high-reliability circuit design, register FF*_1 is replicated to increase design stability. Taking triple-module redundancy as an example, two redundant registers, FF*_2 and FF*_3, are added. However, these two newly added registers are of the standard DFF type. The data input terminals D of these three registers are then connected together. Each set of redundant circuits operates identically.

[0059] Figure 4 Schematic diagram of changing register type and adding MUX selector provided by an embodiment of the present invention. Figure 4 As shown in the figure, after physical design layout, the type of the initial register FF*_1 is changed from SDFF to DFF, a data selector MUX is added, and the original connections are reorganized. The sequence test_si is input through port 1 of MUX1, and the Y terminal of MUX1 is connected to the D terminals of registers FF1_1, FF1_2, and FF1_3. Each group of redundant circuits operates identically.

[0060] Figure 5 This is a schematic diagram of adding a voting device according to an embodiment of the present invention. Figure 5 As shown, a voter is added and the output terminals Q of FF*_1, FF*_2, and FF*_3 are connected to it. The final sequence test_so is output by the voter. At this point, a complete scan chain structure is built.

[0061] As can be seen, this embodiment provides a circuit functional testing method based on scan chain reorganization. By reorganizing multi-mode redundant registers into scan chains, the functional characteristics of the scan chains are restored, allowing the automatic generation of test vectors using ATPG tools. This invention not only simplifies the test vector generation process, but also allows the use of scan chain test vectors to verify the functional correctness of high-reliability circuits after redundancy reinforcement.

[0062] Furthermore, it should be noted that the present invention may be provided as a system, apparatus, or computer program product. Thus, embodiments of the present invention may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code.

[0063] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as the combination of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0064] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0065] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. The terms "comprises," "includes," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further restrictions, an element defined by the phrase "comprises a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0066] Finally, it should be noted that the above is a preferred embodiment of the present invention. It should be noted that although the preferred embodiment of the present invention has been described, it is clear that those skilled in the art, once they understand the basic inventive concept of the present invention, can make various improvements and modifications without departing from the principles of the present invention. Such improvements and modifications should also be considered as within the scope of protection of the present invention. Therefore, the appended claims are intended to be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the embodiments of the present invention.

Claims

1. A circuit function testing method based on scan chain reorganization, characterized in that: include: Setting the function registers as multiple groups of multi-module redundant registers, and setting a voter at the output end of each group of the multi-module redundant registers; Reconstructing each group of the multi-mode redundant registers into at least one scan chain according to a scan chain structure; wherein an input end of the scan chain is connected to an input end of the test stimulus sequence, and an output end of the scan chain is connected to an output end of the test response sequence; Setting a scan enable terminal of a multiplexer connected to the first group of multi-mode redundant registers to an activated state, and starting from the first group of multi-mode redundant registers, repeating the following iterative steps, so that a test stimulus sequence is processed sequentially by each group of multi-mode redundant registers in the scan chain and a voter provided at an output terminal of each group of multi-mode redundant registers, and then outputting a test response sequence for the circuit function test at the end of the scan chain: Transmitting the input test stimulus sequence to each redundant register unit of the multi-module redundant register of the current group; The test stimulus sequence is outputted by the voter provided at the output end of the multi-module redundant register of the current group, and then serves as the input of the multi-module redundant register of the next group.

2. The circuit function testing method based on scan chain reorganization according to claim 1, characterized in that: Each group of the multi-module redundant registers includes at least three redundant register units arranged in parallel.

3. The circuit function testing method based on scan chain reorganization according to claim 2, characterized in that: The processing of the test stimulus sequence by the voter includes: performing a majority vote on the output data of each redundant register unit in the corresponding group of multi-module redundant registers, and outputting a voting result consistent with the majority data.

4. The circuit function testing method based on scan chain reorganization according to claim 1, characterized in that: The multiplexer has the scan enable terminal and at least one input channel; the method further includes: During the functional test phase, the scan enable terminal is set to an activated state so that the scan enable terminal selects a test stimulus sequence as an input of the multi-mode redundant register.

5. The circuit function testing method based on scan chain reorganization according to claim 1, characterized in that: The multiplexer has the scan enable terminal and at least two input channels; the method further includes: During the functional test phase, the scan enable terminal is set to an activated state so that the scan enable terminal selects a test stimulus sequence as the input of the first group of multi-mode redundant registers and selects the output of the voter of the previous group of multi-mode redundant registers as the input of other groups of multi-mode redundant registers.

6. The circuit function testing method based on scan chain reorganization according to claim 1, characterized in that: The reconstructing each group of the multi-module redundant registers into at least one scan chain according to the scan chain structure includes: Grouping the redundant register units of each group of the multi-module redundant registers according to a physical layout or a logical order; Establishing a series path between each group of the multi-module redundant registers and an adjacent group of the multi-module redundant registers by connecting the output end of the voter to the input end of the multiplexer; The series paths are connected in sequence to form a continuous scan chain path.

7. The circuit function testing method based on scan chain reorganization according to claim 1, characterized in that: The method also includes: before setting the scan enable terminal of the multiplexer connected to the first group of the multi-mode redundant registers to an activated state, generating the test stimulus sequence through an automatic test vector generation tool, and adapting the test path according to the reconstructed structure of the scan chain so that the test stimulus sequence conforms to the logical path of the current scan chain.

8. The circuit function testing method based on scan chain reorganization according to claim 1, characterized in that: The method further includes: after outputting a test response sequence for the circuit function test at the end, comparing the test stimulus sequence and the test response sequence, and verifying that the circuit function is correct after redundancy if the test stimulus sequence and the test response sequence are identical.

9. The circuit function testing method based on scan chain reorganization according to claim 8, characterized in that: When the test stimulus sequence and the test response sequence are different, a new test stimulus sequence is reloaded, and the iterative steps are repeated starting from the first group of the multi-mode redundant registers, so that a new test response sequence for the circuit functional test is output at the end, and the new test stimulus sequence and the new test response sequence are compared.

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