A server system and a control method of an NVMe card slot indicator light

Abstract

The application provides a server system and a control method of an NVMe card slot indicator light. The server system provided by the application comprises a PCIe expansion board and an NVMe backboard. The PCIe expansion board is provided with a PCIe switch chip and an expansion CPLD, and the NVMe backboard is provided with a backboard CPLD and a plurality of NVMe card slots for mounting NVMe solid state disks. Each card slot comprises an indicator light for indicating the state of the card slot. The expansion CPLD simulates a PCA9555 chip as an I2C slave device in a first mode to communicate with the PCIe switch chip. The expansion CPLD can also communicate with the backboard CPLD as an I2C master device in a second mode. Through the two working modes of the expansion CPLD, the control of the hard disk indicator light can be realized without modifying the hardware structure and firmware of the mainboard and backboard. Different NVMe backboards can be adapted, the NVMe backboard can be reused, and the firmware does not need to be modified, thereby reducing the maintenance cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a server system and a control method for an NVMe card slot indicator light. BACKGROUND

[0002] To improve the scalability and hot-plug capability of NVMe solid-state disks, a PCIe expansion board and an NVMe backplane distributed structure are usually used in a server system, a multi-channel communication link management is realized through a PCIe Switch chip, and state monitoring and indicator light control are realized through an I²C or VPP interface. For the hard disk status indicator light on the NVMe backplane, the PCA9555 I²C expansion chip is usually directly controlled by the mainboard or management module through the I²C bus to update the indicator light status. However, in the case of a server using a PCIe expansion board to relay connect multiple NVMe hard disks, the mainboard is not directly connected to the hard disk backplane, but is connected through the PCIe Switch chip. Therefore, the mainboard cannot directly access the PCA9555 chip on the hard disk backplane to control the indicator light.

[0003] In addition, the PCIe Switch chips of different PCIe expansion board manufacturers differ in the format, bit stream structure and addressing method of processing I²C control instructions, which results in that a unified light control logic cannot be used in the cross-board communication path, thereby affecting the visibility of the running status of the NVMe hard disk and the fault diagnosis efficiency. In order to adapt to different mainboard architectures and expansion board designs, the hard disk backplane needs to separately develop adaptive firmware for PCIe Switch chips or management chips of different manufacturers, which increases the system design complexity and maintenance cost. SUMMARY

[0004] Therefore, the present application provides a server system and a control method for an NVMe card slot indicator light, which realizes the control of the hard disk indicator light without modifying the hardware structure of the mainboard and the backplane.

[0005] Specifically, the present application is realized through the following technical solutions:

[0006] The first aspect of the present application provides a server system, which comprises a PCIe expansion board and an NVMe backplane; the PCIe expansion board is provided with a PCIe Switch chip and an expansion CPLD, the NVMe backplane is provided with a backplane CPLD and a plurality of NVMe card slots for mounting NVMe solid-state disks, each card slot comprises an indicator light for indicating the state of the card slot; wherein,

[0007] The expansion CPLD is configured to simulate an I2C interface behavior of a PCA9555 chip in a first mode to communicate with the PCIe switch chip as an I2C slave device;

[0008] The PCIe switch chip is configured to write a light state acquisition request to the expansion CPLD through a standard I2C protocol;

[0009] The expansion CPLD is further configured to enter a second mode after acquiring the light state acquisition request, and communicate with the backplane CPLD as an I2C master device in the second mode to acquire state information of a plurality of NVMe card slots from the backplane CPLD;

[0010] The expansion CPLD is further configured to switch back to the first mode after acquiring the state information of the plurality of NVMe card slots, and feed back the state information of the plurality of NVMe card slots to the PCIe switch chip in the first mode;

[0011] The PCIe switch chip is further configured to generate a control signal according to the state information of the plurality of NVMe card slots, and send the control signal to the expansion CPLD when the expansion CPLD is in the first mode;

[0012] The expansion CPLD is further configured to send the control signal to the backplane CPLD in the second mode to instruct the backplane CPLD to control states of indicator lights of the card slots.

[0013] The second aspect of the present application provides a control method of an NVMe card slot indicator light, which is applied to the server system provided in any one of the first aspect of the present application, and the control method comprises:

[0014] The expansion CPLD simulates an I2C interface behavior of a PCA9555 chip in a first mode to communicate with the PCIe switch chip as an I2C slave device;

[0015] The PCIe switch chip is configured to write a light state acquisition request to the expansion CPLD through a standard I2C protocol;

[0016] The expansion CPLD is further configured to enter a second mode after acquiring the light state acquisition request, and communicate with the backplane CPLD as an I2C master device in the second mode to acquire state information of a plurality of NVMe card slots from the backplane CPLD;

[0017] The expansion CPLD is further configured to switch back to the first mode after acquiring the state information of the plurality of NVMe card slots, and feed back the state information of the plurality of NVMe card slots to the PCIe switch chip in the first mode;

[0018] The PCIe Switch chip generates a control signal according to the state information of the plurality of NVMe card slots, and sends the control signal to the extension CPLD when the extension CPLD is in the first mode;

[0019] The extension CPLD sends the control signal to the backplane CPLD in the second mode to instruct the backplane CPLD to control the state of the indicator light of each card slot.

[0020] The server system provided by the present application comprises a PCIe expansion board, a backplane CPLD, and a plurality of NVMe card slots for mounting NVMe solid state disks. Further, the extension CPLD is enabled to work in a first mode and a second mode. In the first mode, the extension CPLD communicates with the PCIe Switch chip to realize the functions of feeding back state information or receiving control signals. In the second mode, the extension CPLD communicates with the backplane CPLD to realize the functions of obtaining state information or sending control signals. In this way, the multi-mode working mode of the extension CPLD can adapt to different hard disk backplanes, thereby enhancing the reusability and expandability of the system. In addition, this scheme effectively reduces the maintenance and development costs without modifying the hardware and firmware of the motherboard or the backplane, and enhances the stability and reliability of the system by simplifying the control logic. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 FIG. 1 is a structural schematic diagram of a server system according to an embodiment of the present application;

[0022] Figure 2 FIG. 4 is a flowchart of a control method for an NVMe card slot indicator light according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] The exemplary embodiments will be described in detail herein with reference to the attached drawings; like numbers refer to like elements throughout. The following detailed description does not represent all embodiments consistent with the present application.

[0024] The terms used in the present application are merely for the purpose of describing particular embodiments and are not intended to limit the present application. As used in the present application, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "and / or," as used herein, refer to and encompass any or all possible combinations of one or more of the associated listed items.

[0025] It should be understood that, although the terms first, second, third, etc. can be employed in this application to describe various information, these information should not be limited to these terms. These terms are only used to differentiate one piece of information from another piece of information. For example, without departing from the scope of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon" or "in response to determining".

[0026] The specific embodiments are given below to introduce the technical solutions of the present application in detail.

[0027] Figure 1 The schematic diagram of the server system embodiment provided by the present application is shown in FIG. 1. Please refer to Figure 1 The server system provided by the present embodiment comprises a PCIe (Peripheral Component Interconnect Express, referred to as PCIe) expansion board and an NVMe (Non-Volatile Memory Express, referred to as NVMe) backboard. The PCIe expansion board is provided with a PCIe Switch chip and an expansion CPLD (Complex Programmable Logic Device, referred to as CPLD). The NVMe backboard is provided with a backboard CPLD and a plurality of NVMe card slots for installing NVMe solid state disks. Each card slot comprises an indicator lamp for indicating the state of the card slot.

[0028] The expansion CPLD is used to simulate the I²C (Inter-Integrated Circuit bus) interface behavior of the PCA9555 chip as an I²C slave device to communicate with the PCIe Switch chip in the first mode.

[0029] The PCIe Switch chip is used to write a lamp state acquisition request to the expansion CPLD through a standard I²C protocol.

[0030] The expansion CPLD is further used to enter the second mode after acquiring the lamp state acquisition request, and communicate with the backboard CPLD as an I²C master device in the second mode to acquire the state information of the plurality of NVMe card slots from the backboard CPLD.

[0031] The expansion CPLD is further used to switch back to the first mode after acquiring the state information of the plurality of NVMe card slots, and feed back the state information of the plurality of NVMe card slots to the PCIe Switch chip in the first mode.

[0032] The PCIe Switch chip is further configured to generate a control signal according to the state information of the plurality of NVMe slots and send the control signal to the extension CPLD when the extension CPLD is in the first mode.

[0033] The extension CPLD is further configured to send the control signal to the backplane CPLD in the second mode to instruct the backplane CPLD to control the states of the indicator lights of the slots.

[0034] The server system provided by the embodiment provides a server system structure supporting a general NVMe backplane, and is especially suitable for a configuration scenario of expanding hard disks through a PCIe Switch. The server system can solve the compatibility and maintenance problems caused by the differences in PCA9555 bit stream definitions in different control modes.

[0035] It should be noted that the extension CPLD supports the first mode and the second mode. In the first mode, the extension CPLD communicates with the PCIe Switch chip as an I2C slave device. In addition, in the first mode, the extension CPLD can perform a write operation and a read operation. In the write operation, the extension CPLD supports the PCIe Switch chip to write data to the extension CPLD and can receive a control signal from the PCIe Switch chip. In the read operation, the extension CPLD supports the PCIe Switch chip to read data in the extension CPLD, that is, the PCIe Switch chip reads the state information of the plurality of NVMe slots obtained by the extension CPLD.

[0036] Further, in the second mode, the extension CPLD also supports the write operation and the read operation. In the write operation, the extension CPLD acts as a master device and can write a control signal to the backplane CPLD. In the read operation, the extension CPLD can obtain the state information of the plurality of NVMe slots from the backplane CPLD.

[0037] Through the write operation in the first mode and the write operation in the second mode, the extension CPLD can transmit the control signal of the PCIe Switch chip to the backplane CPLD. Through the read operation in the second mode and the read operation in the first mode, the extension CPLD can feed back the state information of the plurality of NVMe slots to the PCIe Switch chip. The extension CPLD acts as a bridge for communication between the PCIe Switch chip and the backplane CPLD and realizes the communication between the PCIe Switch chip and the backplane CPLD. In this way, the control of the indicator lights of the NVMe slots can be realized without changing the structures and firmware of the motherboard and the backplane, and the NVMe backplane can be compatible.

[0038] The working principle of the server system will be described in detail below.

[0039] Specifically, refer to Figure 2, when the expansion CPLD is in the first mode, the expansion CPLD, as a slave device, simulates the I2C interface behavior of a PCA9555 chip through an internal programmable logic structure to respond to an I2C access request initiated by the PCIe Switch chip as a master device, such as address matching, register read / write response, etc., and the simulation behavior can be achieved through a solidified register address mapping and state response mechanism.

[0040] It should be noted that the PCA9555 is a chip widely used for digital input / output (I / O) expansion, which has 16 ports, and the functions of the ports can be defined based on actual needs to meet the needs of the present application.

[0041] Further, referring to Figure 2 , the expansion CPLD can be internally configured with one or more I2C addresses compatible with the PCA9555, each of which is mapped to a virtual input / output register area, and can respond to access requests of different I2C master devices in different clock cycles.

[0042] Further, the PCIe Switch chip, as a master device on the I2C bus, can periodically or according to an interrupt mechanism (when the server is powered on or a hard disk is plugged in, etc.) send a lamp state acquisition request to the expansion CPLD.

[0043] Specifically, the lamp state reading request can adopt a standard I2C bus write format, and can also be accompanied by a specified register address, slot number, or command code, for identifying the specific card slot state type to be acquired.

[0044] Further, the expansion CPLD automatically switches from the first mode to the second mode after receiving the lamp state reading request, and in the second mode, the expansion CPLD acts as a master device. That is, the expansion CPLD initiates a query request to the backplane CPLD through the I2C bus, and the backplane CPLD feeds back the card slot state information collected and cached in advance to the expansion CPLD, which can be sourced from a GPIO input pin or from other IO expansion chips such as PCA9555.

[0045] Specifically, the card slot state information usually includes information such as whether the hard disk is in place, whether it is powered on, whether it is in an active state, and whether there is a fault. Specifically, the card slot state information can be in the form of a single byte, a bitmap, or a compressed package, etc.

[0046] Further, when the expansion CPLD completes the card slot state information reading, it switches back to the first mode, i.e., switches to a slave device, and when the PCIe Switch accesses the virtual registers of the expansion CPLD again, the NVMe card slot state information can be read.

[0047] Further, the PCIe Switch generates corresponding lamp control signals according to the read slot state information. For example, the lamp is off when the hard disk is not in place; the green color flashes when in the reading state; the red lamp is always on when there is a fault; the blue color flashes when positioning is needed, etc.

[0048] Further, the PCIe Switch generates a plurality of control signals according to different slot positions, and writes the control signals into the expansion CPLD as a master device through the I2C bus. In order to support fast response, the expansion CPLD can realize the mapping block of the register inside, and sets the mapping table and the priority corresponding mechanism for each control signal, to ensure that the control signal is processed in real time and accurately.

[0049] Further, the expansion CPLD switches to the second mode again after receiving the control signal, that is, as an I2C master device, actively forwards the control signal to the backplane CPLD through the I2C bus. After receiving the control signal, the backplane CPLD analyzes the card slot identifier and lamp control information contained in the control instruction, and sets the corresponding GPIO (General-purpose input / output, referred to as GPIO) output level according to the control signal analysis result, and drives the hardware circuit to control the LED state indicator on the card slot to complete the lighting, flashing or extinguishing action of the lamp.

[0050] It should be noted that the control signal can be directly output by the backplane CPLD, supporting parallel control of multiple hard disk state indicators.

[0051] The server system provided in the embodiment simulates the communication between the PCA9555 chip and the PCIe Switch chip through the expansion CPLD, translates and bridges the complex protocol, overcomes the compatibility problems of PCIe Switch chips from different manufacturers in terms of I2C instruction format, register mapping, address coding, etc., and realizes unified management and control of the NVMe hard disk indicator lamp state without changing the hardware structure of the motherboard or backplane.

[0052] Optionally, in a possible implementation manner, the expansion CPLD, in the first mode, as an I2C slave device, is specifically used for executing the following write operation process:

[0053] Receive the start signal and the first device address carrying the write bit from the PCIe Switch chip, and respond to the response signal to the PCIe Switch chip when the first device address matches successfully;

[0054] Receive and cache the first target register address sent by the PCIe Switch chip;

[0055] receive the control word data sent by the PCIe Switch chip, and write the control word data into the first output port register corresponding to the first target register address of the cache; the first output port register is a register used to cache the control word issued by the PCIe Switch chip; the control word is used to indicate the control command of the indicator light of at least one card slot in the plurality of NVMe card slots;

[0056] receive the stop signal sent by the PCIe Switch chip, and complete the current write operation.

[0057] Specifically, the PCIe Switch chip acts as an I2C master device, and when initiating a write operation, it will send a start signal (START), a device address (7 bits) plus a write bit (bit=0), a target register address (such as an output port register address 0x02), and a one-byte control word data (indicating the specific command of card slot indicator light control, such as lighting, extinguishing or flashing, etc.) on the I2C bus in turn, and finally sends a stop signal (STOP) to mark the completion of the write operation, and the write process completely simulates the I2C register operation format of the PCA9555 chip.

[0058] Specifically, after receiving the start signal sent by the PCIe Switch chip, the expansion CPLD starts to wait to receive the following address information. The PCIe Switch chip will then send the first device address carrying the write bit. If the address matches the first virtual I2C device address simulated by the expansion CPLD, i.e., an acknowledgement signal (ACK) is sent to the PCIe Switch chip, indicating that the target address has been successfully received and confirmed. If the address does not match, it will not respond and remain in the default silent state of the I2C slave device.

[0059] Further, after the first device address is successfully matched, the PCIe Switch chip sends the first data word as the first target register address, which is temporarily stored in the cache area by the expansion CPLD for subsequent positioning and writing of control words. For the scenario of continuous write operation, the expansion CPLD will automatically increment the internal register address to realize sequential writing of multiple registers. The first target register address is usually used to identify a logical port associated with the status information of a certain NVMe card slot, such as a register segment bit corresponding to the control of a certain card slot indicator light.

[0060] Further, to support the control of the multi-card slot indicator light, the extended CPLD implements a set of output port registers consistent with the structure of PCA9555. When a control word is written, the extended CPLD performs assignment operation on different registers through address selection logic. After completing the control word writing, the extended CPLD generates a GPIO output signal according to the value of the current register, which is used to control the working state of the indicator light on the NVMe card slot. Different register bit segments can control the card slot indicator light activity, failure, positioning or other customized light state signals. After the control signal is buffered and output, the corresponding level output is realized by driving the LED physical pin.

[0061] Further, the PCIe Switch chip sends a stop signal (STOP) after completing data writing, and the extended CPLD recognizes the stop signal and ends the current write operation process. In the subsequent operation period, the extended CPLD can choose to immediately or delay format conversion of the control word in the first output port register, and deliver the control signal to the backplane CPLD when entering the second mode, to realize control of the NVMe card slot status indicator light.

[0062] Optionally, in a possible implementation, after completing the write operation as a slave device, the extended CPLD switches to the second mode as an I2C master device to perform the write operation of writing the control word to the backplane CPLD. The write operation process specifically includes:

[0063] initiating a start signal to the backplane CPLD and sending a second device address of the backplane CPLD, to instruct the backplane CPLD to, after receiving the second device address, match the second device address, and return a second response signal to the extended CPLD upon successful matching;

[0064] after receiving the second response signal, sending a second target register address to the backplane CPLD;

[0065] sending the control word written in the first output port register as write data to the backplane CPLD, to enable the backplane CPLD to generate a corresponding LED control signal according to the control word, and drive the indicator light of the corresponding card slot in the plurality of NVMe card slots based on the LED control signal.

[0066] Specifically, after completing the slave device response and internal register write entry in the first mode, the extended CPLD automatically switches to the second mode. In the second mode, the extended CPLD initiatively initiates communication with the backplane CPLD as a master device on the I2C bus, to complete the control word issuing process to the backplane CPLD.

[0067] Specifically, in the second mode, the extended CPLD first initiates a standard start signal (START) to the backplane CPLD through the I2C bus, then sends the first device address of the backplane CPLD, and appends a write bit (bit = 0) to the least significant bit to form a second device address.

[0068] Further, the backplane CPLD detects the second device address on the I2C bus, and after the second device address matches the address of the backplane CPLD, feeds back a second response signal (ACK) to confirm the establishment of the master-slave communication relationship.

[0069] Further, after receiving the second response signal (ACK), the backplane CPLD sends a second target register address for indicating the register region to be accessed or written. Commonly used implementation paths of the second target register address include a static mapping mode, a dynamic indexing mode, and a register link forwarding mode. In this application, the static mapping mode is adopted, that is, a solid mapping table of card slot numbers and register addresses is pre-set in the extended CPLD, for example, the 0th NVMe card slot corresponds to the register address 0x02 in the backplane CPLD, the 1st card slot corresponds to 0x03, and so on; the CPLD calculates the target address through hard coding or configuration registers.

[0070] Further, after completing the register addressing, the extended CPLD sends the control word (for example, 8-bit value for controlling the light state) of the first output port register obtained in the first mode to the backplane CPLD as a data byte. The control word is used to explicitly indicate the target state of the LED corresponding to a certain NVMe card slot, for example, the 1st bit is high to indicate that the active indicator light is on, and the 3rd bit is low to indicate that the fault indicator light is off.

[0071] Further, after receiving the control word, the backplane CPLD parses the specific control meaning represented by each bit according to the combination of the second target register address and the control bit, and converts it into the actual GPIO output level. For the implementation mode supporting the control of indicator lights of multiple NVMe card slots, the backplane CPLD can map each bit in the control word to the control line of the indicator light corresponding to a different card slot, so as to accurately control the state of the indicator light of multiple NVMe card slots. For example, when the control word is 8'b00000010, the 1st bit is high and the rest are low, which represents that only the green LED on the 1st NVMe card slot is on.

[0072] Optionally, the control word content described above can support multi-byte extended writing, and the extended CPLD can write data to multiple output registers of the backplane CPLD in sequence through the automatic incrementing of consecutive addresses in the second mode, to realize the simultaneous configuration of multiple card slot indicator lights. After the completion of the entire writing operation, the extended CPLD can send a stop signal (STOP) to end the current I2C transmission period.

[0073] It can be understood that, through the write operation in the first mode and the write operation in the second mode, the PCIe Switch chip can send data to the backplane CPLD.

[0074] Optionally, in a possible implementation of the application, the expansion CPLD functions as an I2C slave device in the first mode, and is further configured to perform the following read operation process:

[0075] receive a start signal and a device address carrying a write bit sent by the PCIe Switch chip, and return an acknowledgement signal after the device address is matched successfully;

[0076] receive and cache a target register address sent by the PCIe Switch chip, the target register address being used to specify a register to be read subsequently;

[0077] receive a repeated start signal and a device address carrying a read bit, and return an acknowledgement signal after the device address is matched successfully again;

[0078] read corresponding data from an internal register corresponding to the target register address according to the cached target register address, and load the read data to an I2C data line, so that the PCIe Switch chip reads the data; wherein the internal register corresponding to the target register address is an input port register used to store in-situ state information of a plurality of NVMe card slots, and the in-situ state information is obtained and cached by the expansion CPLD from the backplane CPLD in the second mode.

[0079] Specifically, the expansion CPLD receives an I2C start signal (START) and a device address carrying a write bit (bit0=0) initiated by the PCIe Switch chip. The device address is used to identify a target slave device that the PCIe Switch expects to access. When the received device address is matched successfully with a PCA9555 address simulated internally by the expansion CPLD, the expansion CPLD returns an acknowledgement signal (ACK) to the PCIe Switch chip, indicating that the current device is communicable.

[0080] Further, after receiving the acknowledgement signal, the PCIe Switch chip sends a target register address to the expansion CPLD, which is used to specify a target register to be read by the PCIe Switch chip (for example, the address of input port 0 is 0x00, and the address of input port 1 is 0x01). The expansion CPLD caches the register address in an internal register selection register unit, which is used as an address index for subsequent reading.

[0081] Further, the PCIe Switch sends a repeated start signal with a device address carrying a read bit (bit0 = 1). This step is a standard operation process in the I2C protocol, aiming to complete the read operation switching without releasing the control right of the I2C bus. If this repeated start signal is omitted and the read request is directly re-sent, the bus may be interrupted or occupied by other master devices.

[0082] Further, after the extended CPLD receives the device address carrying the read bit, the extended CPLD returns an acknowledgement signal again, and according to the target register address cached previously, extracts data from the corresponding internal register and loads the data to the I2C bus, so that the PCIe Switch chip reads the data.

[0083] It should be noted that the internal register is an input port register, mainly used for storing the NVMe card slot state information obtained from the backplane CPLD. These state information includes the in-place flag, whether connected, whether powered on and other key information of each hard disk card slot. In the second working mode, the extended CPLD communicates with the backplane CPLD as an I2C master device and updates the register content in real time, so as to provide accurate query feedback to the PCIe Switch in the first mode.

[0084] Optionally, in a possible implementation manner of the application, the extended CPLD, as an I2C master device in the second mode, is further specifically configured to perform the following read operation process:

[0085] initiate an I2C start signal to the backplane CPLD, and send a device address carrying a write bit, to instruct the backplane CPLD to match the device address after receiving the device address, and return a third acknowledgement signal to the extended CPLD after the matching is successful;

[0086] after receiving the third acknowledgement signal returned by the backplane CPLD, send a target register address for specifying a register to be read;

[0087] send a repeated start signal and a device address carrying a read bit;

[0088] after receiving the acknowledgement signal of the backplane CPLD again, read the register value of the target register from the backplane CPLD, and cache the read register value to an input port register on the device, so as to respond to the read operation request of the PCIe Switch chip when the device is an I2C slave device in the first mode; wherein the target register stores state information of a plurality of NVMe card slots.

[0089] Specifically, the extension CPLD initiates a start signal (START) through the I2C bus, and then sends a device address carrying a write bit (bit0 = 0), which corresponds to the preset response address of the backplane CPLD in the I2C bus. After receiving the device address, the backplane CPLD returns a third response signal if the address matches successfully, confirming the establishment of a communication relationship.

[0090] Further, after receiving the third response signal of the backplane CPLD, the extension CPLD sends a target register address for specifying the internal register of the backplane CPLD to be read.

[0091] Specifically, the extension CPLD sends a repeated start signal and the same device address, but this time the least significant bit (R / W bit) is set to 1, indicating that this operation is a read operation. The backplane CPLD performs address matching again and returns a response signal after a successful match, and then loads the data in the target register onto the I2C bus data line.

[0092] Further, after receiving the data in the target register, the extension CPLD caches it as a register value in its internal input port register, so that after switching back to the first mode next time, it can provide the cached data to the PCIe Switch chip as an I2C slave device for reading.

[0093] It can be understood that through the read operation in the second mode and the read operation in the first mode, the status information of the plurality of NVMe card slots obtained from the backplane CPLD can be sent to the PCIe Switch chip.

[0094] Optionally, in a possible implementation manner of the present application, when the extension CPLD reads the status information from the backplane CPLD as an I2C master device in the second mode, it acquires the status information based on any of the following mechanisms:

[0095] Based on a polling mechanism, the I2C read operation is initiated periodically to obtain the status information stored in the backplane CPLD, so as to ensure that the status information in the input register is the latest value;

[0096] Alternatively,

[0097] The I2C read operation is initiated when an interrupt signal from the backplane CPLD is detected, and the status information in the input port register is updated; wherein the interrupt signal is sent by the backplane CPLD to the extension CPLD actively when the backplane CPLD detects a change in the card slot state.

[0098] Specifically, under the polling mechanism, after the extension CPLD enters the second mode, an internal timer or state machine control unit is started to periodically initiate an I2C read operation to the backplane CPLD. For example, every interval of a preset time window (e.g., 10 ms, 100 ms, or longer, set according to the requirements of the system on the refresh rate of the indicator light), the extension CPLD sends a start signal, a device address, and a register address to the backplane CPLD in turn through the I2C protocol to complete data communication with the target register. In this way, even if the card slot state does not change, the data in the input register can be continuously updated, which is suitable for server system scenarios with high real-time data requirements.

[0099] Alternatively, the backplane CPLD is configured with an interrupt output signal line, and state change detection logic is implemented inside, for example: monitoring whether the edge of the in-place state, power supply state, active state, etc. of any one NVMe card slot changes (e.g., low to high, high to low). Once a state change is detected, the backplane CPLD immediately sends an interrupt notification signal to the extension CPLD. After receiving the interrupt notification signal, the extension CPLD switches to the second mode, initiates an I2C read operation to obtain the latest state information, and updates the cached value in the input port register. This method is suitable for applications that are more sensitive to system bandwidth or power consumption, and reduces unnecessary polling operations through "state triggered" reading behavior to improve processing efficiency.

[0100] It should be noted that the two mechanisms are not mutually exclusive. The extension CPLD can also use both mechanisms in some system configurations and dynamically switch strategies according to application priorities. For example, when the system is idle or the state changes frequently, the interrupt state triggering mechanism is used; and after a period of time without interrupt signals, it automatically falls back to the polling mode for backup refresh.

[0101] As can be understood from the foregoing description, the service system provided by the embodiment has at least the following advantages:

[0102] (1) No need to modify hardware and firmware, can adapt to different NVMe backplanes

[0103] By using the cooperative design of the extension CPLD and the backplane CPLD, the control function of the indicator light can be realized on the existing hardware architecture without modifying the hardware design of the motherboard and the backplane. In addition, through the interaction between the extension CPLD and the PCIe switch chip, and between the extension CPLD and the backplane CPLD, the indicator light control can be realized under the existing firmware architecture without modifying the firmware, so that the firmware can maintain its original stability and compatibility, avoiding system instability problems caused by firmware updates or modifications.

[0104] Further, by extending the communication and control logic between the CPLD and the backplane CPLD, the system can be adapted to various types of NVMe backplanes without the need for individual customization design for each backplane. Whether it is a hardware version update or the introduction of a new model backplane, the changes can be adapted by extending the CPLD, without the need for redesigning each new backplane. In this way, the reuse of backplane hardware is achieved, reducing the cost of design, production and maintenance

[0105] (2) Improve system scalability and flexibility

[0106] The extension CPLD supports both the first mode and the second mode, which can flexibly switch between the I2C slave device and the I2C master device, so that the system can dynamically adjust the working mode according to the demand, whether it is querying the card slot state of the backplane CPLD or feeding back the card slot state information to the PCIe switch, it can be smoothly carried out in different modes.

[0107] Through the extension CPLD, the status information of the NVMe card slot can be fed back to the PCIe switch chip in real time, so as to generate control signals, which can facilitate real-time adjustment of indicator lights or other control logic according to the state of the card slot, and can improve the scalability and adaptability of the system.

[0108] (3) Reduce system complexity and cost

[0109] The server system does not need to use a separate PCA9555 chip for each NVMe card slot, but uses the extension CPLD and the backplane CPLD to realize the state analysis of multiple NVMe card slots. In this way, the complexity and cost of hardware are reduced, and the need for additional hardware is reduced.

[0110] Through the cooperation of the extension CPLD and the backplane CPLD, more complex functions can be realized with fewer hardware resources, reducing the cost of system development and maintenance.

[0111] (4) Improve system maintenance and management efficiency

[0112] All card slot status information is ultimately fed back to the PCIe switch chip through the extension CPLD, simplifying the data processing and control process. The PCIe switch chip generates control signals according to the feedback information, and then controls the hard disk backplane indicator light. Such a design makes firmware maintenance more centralized, avoiding complex distributed control logic.

[0113] According to the cooperation of the backplane CPLD and the extension CPLD, the indicator light state of multiple card slots can be flexibly controlled, which not only improves the user's interactive experience, but also facilitates real-time monitoring of hardware status.

[0114] (5) Enhance the stability and reliability of the system

[0115] By extending the precise timing control between the CPLD and the backplane CPLD, the accuracy of the state acquisition and feedback of the NVMe card slot can be effectively guaranteed, and the control signals generated by the PCIe Switch can ensure the state of each card slot indicator light to be unified and synchronized in the system, thereby reducing the system instability caused by signal interference or timing errors.

[0116] In summary, the server system flexibly uses the cooperative work of the extension CPLD, the backplane CPLD and the PCIe Switch chip, which not only simplifies the hardware design and improves the scalability of the system, but also reduces the cost and enhances the stability and maintainability of the system.

[0117] The server system provided by the embodiment is provided with a PCIe expansion board and an NVMe backplane; the PCIe Switch chip and the extension CPLD are arranged on the PCIe expansion board, the backplane CPLD and a plurality of NVMe card slots for mounting NVMe solid state disks are arranged on the NVMe backplane, further, the extension CPLD is enabled to work in a first mode and a second mode, which can communicate with the PCIe Switch chip in the first mode to realize the functions of feeding back state information or receiving control signals, and communicate with the backplane CPLD in the second mode to realize the functions of acquiring state information or sending control signals, so that the multi-mode working mode of the extension CPLD can adapt to different hard disk backplanes, thereby enhancing the reusability and scalability of the system. In addition, the scheme effectively reduces the maintenance and development costs without modifying the hardware and firmware of the mainboard or backplane, and enhances the stability and reliability of the system by simplifying the control logic.

[0118] In addition to providing a server system, the present application also provides a control method for an NVMe card slot indicator light. The control method for the NVMe card slot indicator light provided by the present application is applied to any of the above server systems, and will be introduced as follows:

[0119] Figure 2 The flowchart of the first embodiment of the control method for the NVMe card slot indicator light provided by the present application is shown in FIG. 1. Figure 2 The control method for the NVMe card slot indicator light provided by the present embodiment is applied to any of the above server systems, and the control method comprises the following steps.

[0120] S301, the extension CPLD simulates the I2C interface behavior of the PCA9555 chip in the first mode, and communicates with the PCIe Switch chip as an I2C slave device;

[0121] Specifically, in the first mode, the extension CPLD simulates the I2C interface behavior of the PCA9555 chip as a slave device to communicate with the PCIe Switch chip. That is, one or more I2C address spaces compatible with the PCA9555 are preset in the extension CPLD, and each address is mapped to a group of output port register regions, so that it has the ability to respond to the I2C write request sent by the PCIe Switch. For specific implementation and implementation principles, please refer to the description in the previous embodiment, which will not be repeated here.

[0122] S302, the PCIe Switch chip writes a lamp state acquisition request to the extension CPLD through a standard I2C protocol.

[0123] Specifically, the PCIe Switch sends an I2C start signal, a device address with a write flag, the extension CPLD identifies the device address and returns an acknowledgement signal after a successful match. Then the PCIe Switch continues to send a target register address (used to specify the lamp control register) and a control word data representing the control signal. The extension CPLD writes the control word into the output port register corresponding to the previously cached register address, completing a write operation under the PCA9555 protocol.

[0124] S303, the extension CPLD enters the second mode after acquiring the lamp state acquisition request, and communicates with the backplane CPLD as an I2C master device in the second mode to acquire state information of a plurality of NVMe card slots from the backplane CPLD.

[0125] Specifically, the extension CPLD will automatically switch to the second mode after completing the above write operation. In this mode, the extension CPLD initiates communication with the backplane CPLD as a master device to acquire state information of a plurality of NVMe card slots.

[0126] S304, the extension CPLD switches back to the first mode after acquiring the state information of the plurality of NVMe card slots, and feeds back the state information of the plurality of NVMe card slots to the PCIe Switch chip in the first mode.

[0127] Specifically, the extension CPLD switches back to the first mode after reading the state information of the plurality of NVMe card slots, and re-simulates the slave device behavior of the PCA9555 chip. When the PCIe Switch chip initiates a read request as an I2C master device, the extension CPLD loads the cached card slot state information onto the I2C bus for the PCIe Switch chip to read, realizing the feedback of the state information.

[0128] S305, the PCIe Switch chip generates a control signal according to the state information of the plurality of NVMe card slots, and sends the control signal to the expansion CPLD when the expansion CPLD is in the first mode;

[0129] Specifically, after obtaining the state information of the plurality of NVMe card slots, the PCIe Switch chip judges the working state of each card slot based on a preset light control rule, for example, whether the hard disk is in place, whether it is faulty or active. According to the judgment result, the PCIe Switch generates a corresponding control signal. When the expansion CPLD is in the first mode, that is, in the state of simulating an I2C slave device, the PCIe Switch sends the control signal to the expansion CPLD in the form of a control word through a standard I2C write operation.

[0130] S306, the expansion CPLD sends the control signal to the backplane CPLD in the second mode to instruct the backplane CPLD to control the state of the indicator light of each card slot.

[0131] Specifically, after receiving the control signal issued by the PCIe Switch chip, the expansion CPLD switches to the second mode and acts as an I2C master device to establish communication with the backplane CPLD through the I2C bus. The expansion CPLD sends a write operation instruction to the backplane CPLD, and writes the control signal in the form of a control word to a target register address. After receiving the control word, the backplane CPLD drives the state indicator light on each NVMe card slot according to the command, realizes display effects such as lighting green, red, blue or flashing, and thus completes the entire indicator light control closed loop.

[0132] The control method of the NVMe card slot indicator light provided in the application can make the expansion CPLD assume the roles of I2C slave device and master device in different modes, so that it can be compatible with multiple PCIe Switch instruction formats for hard disk indicator light control without modifying the hardware structure of the motherboard and the backplane.

[0133] Optionally, the method further comprises:

[0134] The expansion CPLD receives a start signal and a first device address carrying a write bit from the PCIe Switch chip, and responds to an acknowledgement signal from the PCIe Switch chip when the first device address matches successfully;

[0135] The expansion CPLD receives and caches the first target register address sent by the PCIe Switch chip;

[0136] The extended CPLD receives control word data sent by the PCIe Switch chip and writes the control word data into a first output port register corresponding to the first target register address in the cache; the first output port register is a register used to cache the control word issued by the PCIe Switch chip; the control word is used to indicate a control command for an indicator light of at least one card slot in the plurality of NVMe card slots;

[0137] The extended CPLD receives a stop signal sent by the PCIe Switch chip to complete the current write operation.

[0138] For specific implementation processes and principles of the above steps, refer to the descriptions in the foregoing embodiments, which will not be repeated here.

[0139] The method provided in this embodiment is that the extended CPLD receives a write operation instruction of the PCIe Switch chip as a slave device in the first mode, including receiving a start signal, matching a device address, receiving a register address and a control word, and writing the control word into a specified output register to indicate a control command for a specific NVMe card slot indicator light. After the operation is completed, the CPLD receives a stop signal to complete the data write process.

[0140] Optionally, the method further includes:

[0141] The extended CPLD initiates a start signal to the backplane CPLD and sends a second device address of the backplane CLPD to instruct the backplane CPLD to match the second device address after receiving the second device address, and return a second response signal to the extended CPLD after the matching is successful;

[0142] The extended CPLD sends a second target register address to the backplane CPLD after receiving the second response signal.

[0143] The extended CPLD sends the control word written into the first output port register to the backplane CPLD as write data, so that the backplane CPLD generates a corresponding LED control signal according to the control word, and drives an indicator light of a corresponding card slot in the plurality of NVMe card slots based on the LED control signal.

[0144] For specific implementation processes and principles of the above steps, refer to the descriptions in the foregoing embodiments, which will not be repeated here.

[0145] The method provided by the embodiment extends the CPLD as an I2C master device to communicate with the backplane CPLD through the I2C bus. After the extension CPLD sends a device address and completes address matching, a control word is written into a second target register of the backplane CPLD, so that the backplane CPLD generates a corresponding LED control signal, thereby controlling the display state of the corresponding indicator light in the plurality of NVMe card slots.

[0146] Optionally, the method further comprises:

[0147] The extension CPLD receives the start signal and the device address carrying the write bit sent by the PCIe Switch chip, and returns an acknowledgement signal after successful device address matching;

[0148] The extension CPLD receives and caches the target register address sent by the PCIe Switch chip, and the target register address is used to specify the subsequent read register;

[0149] The extension CPLD receives the repeated start signal and the device address carrying the read bit, and returns an acknowledgement signal after the device address is matched again;

[0150] The extension CPLD reads corresponding data from an internal register corresponding to the cached target register address, and loads the read data to the I2C data line, so that the PCIe Switch chip reads the data; wherein the internal register corresponding to the target register address is an input port register used to store the in-slot state information of the plurality of NVMe card slots, and the in-slot state information is obtained and cached by the extension CPLD accessing the backplane CPLD in the second mode.

[0151] The specific implementation process and implementation principle of the above steps can be referred to the description in the foregoing embodiments, which will not be repeated here.

[0152] In the first mode, the method provided by the embodiment loads the in-slot state information read from the backplane CPLD in advance to the I2C bus by the extension CPLD, so that the PCIe Switch chip reads the data.

[0153] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A server system, characterized by The server system comprises a PCIe expansion board and an NVMe backboard; the PCIe expansion board is provided with a PCIe Switch chip and an expansion CPLD, and the NVMe backboard is provided with a backboard CPLD and a plurality of NVMe card slots for mounting NVMe solid state disks, each card slot comprising an indicator lamp for indicating the state of the card slot; The expansion CPLD is configured to simulate the I2C interface behavior of a PCA9555 chip in a first mode and communicate with the PCIe Switch chip as an I2C slave device; The PCIe Switch chip is configured to write a lamp state acquisition request to the expansion CPLD through a standard I2C protocol; The expansion CPLD is further configured to enter a second mode after acquiring the lamp state acquisition request and communicate with the backboard CPLD as an I2C master device to acquire the state information of the plurality of NVMe card slots from the backboard CPLD; The expansion CPLD is further configured to switch back to the first mode after acquiring the state information of the plurality of NVMe card slots and feed back the state information of the plurality of NVMe card slots to the PCIe Switch chip in the first mode; The PCIe Switch chip is further configured to generate a control signal according to the state information of the plurality of NVMe card slots and send the control signal to the expansion CPLD when the expansion CPLD is in the first mode; The expansion CPLD is further configured to send the control signal to the backboard CPLD in the second mode to instruct the backboard CPLD to control the state of the indicator lamp of each card slot; The expansion CPLD in the first mode as an I2C slave device is specifically configured to perform the following write operation process: Receive a start signal and a first device address carrying a write bit from the PCIe Switch chip, and respond to an acknowledgement signal from the PCIe Switch chip when the first device address matches successfully; Receive and cache a first target register address sent by the PCIe Switch chip; Receive control word data sent by the PCIe Switch chip and write the control word data into a first output port register corresponding to the cached first target register address; The first output port register is a register for caching control words issued by the PCIe Switch chip; the control word is used to indicate a control command for the indicator lamp of at least one card slot in the plurality of NVMe card slots; Receive a stop signal sent by the PCIe Switch chip to complete the write operation.

2. The server system of claim 1, wherein, After completing the write operation as a slave device, the expansion CPLD switches to the second mode as an I2C master device and performs a write operation of writing a control word to the backboard CPLD, and the write operation process specifically comprises: initiating a start signal to the backplane CPLD and sending a second device address of the backplane CPLD to instruct the backplane CPLD to, upon receiving the second device address, match the second device address and return a second response signal to the expansion CPLD upon a successful match; sending a second target register address to the backplane CPLD upon receiving the second response signal; sending the control word written into the first output port register to the backplane CPLD as write data to cause the backplane CPLD to generate a corresponding LED control signal according to the control word and drive an indicator light of a corresponding card slot in the plurality of NVMe card slots based on the LED control signal.

3. The server system of claim 1, wherein, The expansion CPLD, in the first mode, functions as an I2C slave device, and is further configured to perform the following read operation process: receiving a start signal and a device address carrying a write bit sent by the PCIe Switch chip and returning a response signal upon a successful match of the device address; receiving and buffering a target register address sent by the PCIe Switch chip, the target register address being used to specify a register to be read subsequently; receiving a repeated start signal and a device address carrying a read bit and returning a response signal upon a successful match of the device address again; reading corresponding data from an internal register corresponding to the target register address and loading the read data onto I2C data lines to cause the PCIe Switch chip to read the data, wherein the internal register corresponding to the target register address is an input port register used to store in-situ state information of a plurality of NVMe card slots, and the in-situ state information is obtained and buffered by the expansion CPLD from the backplane CPLD in the second mode.

4. The server system of claim 3, wherein, The expansion CPLD, in the second mode, functions as an I2C master device, and is further configured to perform the following read operation process: initiating an I2C start signal to the backplane CPLD and sending a device address carrying a write bit to instruct the backplane CPLD to, upon receiving the device address, match the device address and return a third response signal to the expansion CPLD upon a successful match; sending a target register address to specify a register to be read upon receiving the third response signal returned by the backplane CPLD; sending a repeated start signal and a device address carrying a read bit; reading a register value of a target register from the backplane CPLD upon receiving a response signal from the backplane CPLD again and buffering the read register value into an input port register on the device to be used by the device to respond to a read operation request of the PCIe Switch chip when the device functions as an I2C slave device in the first mode, wherein the target register stores state information of a plurality of NVMe card slots.

5. The server system of claim 4, wherein, When the expansion CPLD, in the second mode, functions as an I2C master device, reads state information from the backplane CPLD, the state information is obtained based on any one of the following mechanisms: Based on the polling mechanism, periodically initiate I2C read operation to obtain the state information stored in the backplane CPLD, to ensure that the state information in the input register is the latest value; Or, Initiate I2C read operation when detecting the interrupt signal from the backplane CPLD, update the state information in the input port register; wherein the interrupt signal is the backplane CPLD detects the card slot state change, and actively sends to the expansion CPLD. 6.A control method of an NVMe slot indicator light, characterized by, The control method is applied to the server system of any one of claims 1-5, and the control method comprises: The expansion CPLD simulates the I2C interface behavior of the PCA9555 chip in the first mode, as an I2C slave device to communicate with the PCIe switch chip; The PCIe switch chip writes a lamp state acquisition request to the expansion CPLD through a standard I2C protocol; The expansion CPLD enters the second mode after obtaining the lamp state acquisition request, and communicates with the backplane CPLD as an I2C master device in the second mode to obtain the state information of the plurality of NVMe card slots from the backplane CPLD; The expansion CPLD switches back to the first mode after obtaining the state information of the plurality of NVMe card slots, and feeds back the state information of the plurality of NVMe card slots to the PCIe switch chip in the first mode; The PCIe switch chip generates a control signal according to the state information of the plurality of NVMe card slots, and sends the control signal to the expansion CPLD when the expansion CPLD is in the first mode; The expansion CPLD sends the control signal to the backplane CPLD in the second mode to instruct the backplane CPLD to control the state of the indicator light of each card slot; The expansion CPLD receives a start signal and a first device address carrying a write bit from the PCIe switch chip, and responds to an acknowledgement signal to the PCIe switch chip when the first device address matches successfully; The expansion CPLD receives and caches the first target register address sent by the PCIe switch chip; The expansion CPLD receives the control word data sent by the PCIe switch chip, and writes the control word data into the first output port register corresponding to the cached first target register address; the first output port register is a register for caching the control word issued by the PCIe switch chip; the control word is used to represent the control command for the indicator light of at least one card slot in the plurality of NVMe card slots; The expansion CPLD receives the stop signal sent by the PCIe switch chip to complete the write operation.

7. The method of claim 6, wherein, The method further comprises: The expansion CPLD initiates a start signal to the backplane CPLD and sends a second device address of the backplane CPLD to instruct the backplane CPLD to match the second device address upon receiving the second device address and return a second response signal to the expansion CPLD upon successful matching; The expansion CPLD sends a second target register address to the backplane CPLD after receiving the second response signal; The expansion CPLD sends the control word written in the first output port register to the backplane CPLD as write data, so that the backplane CPLD generates a corresponding LED control signal according to the control word, and drives the indicator light of the corresponding card slot in the plurality of NVMe card slots based on the LED control signal.

8. The method of claim 6, wherein, The method further comprises: The expansion CPLD receives a start signal and a device address carrying a write bit sent by the PCIe Switch chip, and returns a response signal upon successful device address matching; The expansion CPLD receives and caches a target register address sent by the PCIe Switch chip, the target register address being used to specify a subsequent read register; The expansion CPLD receives a repeated start signal and a device address carrying a read bit, and returns a response signal upon successful device address matching again; The expansion CPLD reads corresponding data from an internal register corresponding to the cached target register address according to the target register address, and loads the read data to an I2C data line, so that the PCIe Switch chip reads the data; wherein the internal register corresponding to the target register address is an input port register used to store in-situ state information of a plurality of NVMe card slots, and the in-situ state information is obtained and cached by the expansion CPLD accessing the backplane CPLD in a second mode.

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