A data processing system with adaptive PCIe bandwidth

Abstract

This application relates to the field of data transmission technology, and in particular to an adaptive PCIe bandwidth data processing system. This system divides target data into N sub-data segments. A first task unit corresponding to a first communication link and a second task unit corresponding to a second communication link compete for processing of each sub-data segment. When either the first or second communication link is idle, the corresponding task unit updates the processing identifier. After a successful update, the task unit processes the sub-data segment corresponding to the processing identifier. This eliminates the need to pre-allocate the amount of data to be processed for different communication links; instead, it processes the sub-data segments based on the real-time status of the communication links. This effectively improves the bandwidth utilization of each communication link, thereby enhancing the efficiency of data transmission and processing in multi-GPU chip interconnect scenarios.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and in particular to a data processing system with adaptive PCIe bandwidth. Background Technology

[0002] Currently, the demand for computing power is exploding in many fields such as scientific research, artificial intelligence, and big data analysis. However, a single GPU chip is increasingly unable to meet the growing demand for computing power. Therefore, existing technologies propose to form GPU clusters composed of multiple GPU chips to provide more powerful computing power to cope with increasingly complex and large-scale computing tasks.

[0003] In a GPU cluster, there is a communication requirement between GPU chips. In existing technologies, multiple GPU chips can typically be connected to a PCIe switch to achieve interconnection between them, or multiple GPU chips can be interconnected through pre-set connections. Existing methods can apply both interconnection methods simultaneously to improve data transmission efficiency. However, applying both interconnection methods simultaneously requires allocating the amount of data transmitted and processed on different communication links to maximize bandwidth utilization and thus improve data transmission and processing efficiency.

[0004] In existing technologies, the amount of data allocated to communication links based on PCIe switch interconnection is usually determined based on the reference bandwidth given by the PCIe version. However, due to factors such as line interference, voltage fluctuations, and hardware connections, the actual bandwidth of communication links based on PCIe switch interconnection may be difficult to reach the given reference bandwidth. This makes it difficult for communication links based on PCIe switch interconnection to complete the transmission and processing of allocated data within the expected time, reducing bandwidth utilization and the efficiency of data transmission and processing.

[0005] Therefore, improving the efficiency of data transmission and processing in multi-GPU chip interconnect scenarios has become an urgent problem to be solved. Summary of the Invention

[0006] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0007] An adaptive PCIe bandwidth data processing system includes: a PCIe switch, M GPU chips, a processor, and a memory storing a computer program. The M GPU chips are interconnected via the PCIe switch to form a first communication link, and the M GPU chips are interconnected via a preset connection to form a second communication link. The first communication link corresponds to a first task unit, and the second communication link corresponds to a second task unit. M is a positive integer. When the computer program is executed by the processor, the following steps are implemented:

[0008] S101, divide the target data A to be processed into N sub-data {a1, a2, ..., a...} n , ..., a N}, where a n Let n be the nth sub-data, where n is a n The corresponding sub-data identifier, n is an integer in the range [1, N].

[0009] S102, when the first communication link is idle, the first task unit updates the processing identifier. If the first task unit successfully updates the processing identifier, the sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier is processed through the first communication link. The initial value of the processing identifier is 0.

[0010] S103, when the second communication link is idle, the second task unit updates the processing identifier. If the second task unit successfully updates the processing identifier, the sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier is processed through the second communication link.

[0011] S104, whenever the processing identifier is successfully updated, the updated processing identifier is detected. If the updated processing identifier meets the preset conditions, the processing of the target data A is completed.

[0012] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the adaptive PCIe bandwidth data processing system provided by the present invention achieves considerable technological advancement and practicality, and has broad industrial application value. It has at least the following advantages:

[0013] This invention divides the target data into N sub-data. The first task unit corresponding to the first communication link and the second task unit corresponding to the second communication link compete for the processing of the sub-data. When either the first or second communication link is idle, the corresponding task unit updates the processing identifier. After the update is successful, the task unit processes the sub-data corresponding to the processing identifier. There is no need to pre-allocate the amount of data to be processed for different communication links. Instead, the processing of sub-data is performed according to the real-time status of the communication links, thereby effectively improving the bandwidth utilization of each communication link and thus improving the efficiency of data transmission and processing in multi-GPU chip interconnection scenarios. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a flowchart illustrating the execution of a computer program by a processor in an adaptive PCIe bandwidth data processing system, as provided in an embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] This embodiment provides a data processing system that adapts to PCIe bandwidth. See [link / reference] Figure 1 This is a flowchart illustrating the execution of a computer program by a processor in an adaptive PCIe bandwidth data processing system according to an embodiment of the present invention. The system includes: a PCIe switch, M GPU chips, a processor, and a memory storing the computer program. The M GPU chips are interconnected through the PCIe switch to form a first communication link, and the M GPU chips are interconnected through a preset connection relationship to form a second communication link. The first communication link corresponds to a first task unit, and the second communication link corresponds to a second task unit. M is a positive integer. When the computer program is executed by the processor, the following steps are implemented:

[0018] S101, divide the target data A to be processed into N sub-data {a1, a2, ..., a...} n , ..., a N}, where a n Let n be the nth sub-data, where n is a n The corresponding sub-data identifier, where n is an integer in the range [1, N];

[0019] S102, when the first communication link is idle, the first task unit updates the processing identifier. If the first task unit successfully updates the processing identifier, the sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier is processed through the first communication link. The initial value of the processing identifier is 0.

[0020] S103, when the second communication link is idle, the second task unit updates the processing identifier. If the second task unit successfully updates the processing identifier, the sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier is processed through the second communication link.

[0021] S104, whenever the processing identifier is successfully updated, the updated processing identifier is detected. If the updated processing identifier meets the preset conditions, the processing of the target data A is completed.

[0022] In this embodiment, the PCIe switch is connected to M GPU chips to enable data routing and exchange among the M GPU chips. Taking a single PCIe switch as an example, the number of GPU chips M should be less than or equal to the number of ports on the PCIe switch.

[0023] There is a preset connection between each pair of GPU chips to support data transmission between GPU chips. A first communication link can be formed to interconnect M GPU chips through a PCIe switch, and a second communication link can be formed to interconnect M GPU chips through the preset connection.

[0024] The first task unit can be used to request sub-data to be processed in the first communication link, and the second task unit can be used to request sub-data to be processed in the second communication link.

[0025] Specifically, in this embodiment, the data volume corresponding to the N sub-data obtained by dividing the target data can be the same.

[0026] The status of a communication link can include idle and busy states, and the processing identifier can be a global variable.

[0027] In one specific implementation, the step of updating the processing identifier by the first task unit when the first communication link is in an idle state includes:

[0028] When the first communication link is idle, the first task unit performs an atomic addition operation on the processing identifier at the current moment.

[0029] An atomic addition operation is an indivisible operation that cannot be interrupted by operations from other threads or processes during its execution. Specifically, when an atomic addition operation is performed on a processing identifier, it adds a specified increment to the current value of the processing identifier. In this embodiment, the increment is 1. This process is atomic, meaning it either succeeds completely or fails completely; partial execution is not possible.

[0030] In one specific implementation, the step of updating the processing identifier by the second task unit when the second communication link is in an idle state includes:

[0031] When the second communication link is idle, the second task unit performs an atomic addition operation on the processing identifier at the current moment.

[0032] The first task unit and the second task unit can update the processing identifier independently. Since the update of the processing identifier is an atomic addition operation, even if the first task unit and the second task unit update the processing identifier at the same time, only one of the first task unit and the second task unit can successfully update the processing identifier. Accordingly, the sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier is processed by the communication link corresponding to the task unit that successfully updated the processing identifier.

[0033] In one specific implementation, the first communication link is in an idle state when there is no sub-data to be processed in the first communication link.

[0034] Specifically, when there is no sub-data to be processed in the first communication link, the state of the first communication link can be idle; when there is sub-data to be processed in the first communication link, the state of the first communication link can be busy.

[0035] In one specific implementation, the second communication link is in an idle state when there is no sub-data to be processed in the second communication link.

[0036] Specifically, when there is no sub-data to be processed in the second communication link, the state of the second communication link can be idle; when there is sub-data to be processed in the second communication link, the state of the second communication link can be busy.

[0037] In one specific implementation, the step of processing the sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier through the first communication link includes:

[0038] The sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier is processed by the set communication algorithm through the first communication link;

[0039] The step of processing the sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier through the second communication link includes:

[0040] The sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier is processed by the set communication algorithm through the second communication link.

[0041] Among them, ensemble communication algorithms can include all-reduce algorithms, all-gather algorithms, reduce-scatter algorithms, all-to-all algorithms, etc.

[0042] In one specific implementation, the preset condition is: the updated processing identifier is greater than N.

[0043] When the updated processing identifier is greater than N, it means that all sub-data have been allocated to the first communication link or the second communication link for data processing, and the allocation of sub-data can be stopped at this time.

[0044] In one specific implementation, step S104 further includes:

[0045] If the updated processing identifier does not meet the preset conditions, then return to the execution steps S102 and S103.

[0046] When the updated processing identifier is less than or equal to N, it indicates that some sub-data has not been assigned to the first or second communication link for data processing. In this case, it is necessary to return to the execution of steps S102 and S103. That is, when either the first or second communication link is in an idle state, the task unit corresponding to the idle communication link requests to update the processing identifier so that the sub-data can be assigned to the idle communication link for data processing. It should be noted that steps S102 and S103 are processed in parallel and there is no sequential order. That is, when the first communication link is in an idle state, the first task unit updates the processing identifier, and when the second communication link is in an idle state, the second task unit updates the processing identifier.

[0047] In this embodiment, the target data is divided into N sub-data. The first task unit corresponding to the first communication link and the second task unit corresponding to the second communication link compete for the processing of the sub-data. When either the first or second communication link is idle, the corresponding task unit updates the processing identifier. After the update is successful, the task unit processes the sub-data corresponding to the processing identifier. There is no need to pre-allocate the amount of data to be processed for different communication links. Instead, the sub-data is processed according to the real-time status of the communication links, which can effectively improve the bandwidth utilization of each communication link and thus improve the efficiency of data transmission and processing in multi-GPU chip interconnection scenarios.

[0048] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A data processing system with adaptive PCIe bandwidth, characterized in that, The system includes: a PCIe switch, M GPU chips, a processor, and a memory storing a computer program. The M GPU chips are interconnected via the PCIe switch to form a first communication link, and are interconnected with each other via a preset connection to form a second communication link. The first communication link corresponds to a first task unit, and the second communication link corresponds to a second task unit. M is a positive integer. When the computer program is executed by the processor, the following steps are implemented: S101, divide the target data A to be processed into N sub-data {a1, a2, ..., a...} n , ..., a N }, where a n Let n be the nth sub-data, where n is a n The corresponding sub-data identifier, where n is an integer in the range [1, N]; S102, when the first communication link is idle, the first task unit updates the processing identifier. If the first task unit successfully updates the processing identifier, the sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier is processed through the first communication link. The initial value of the processing identifier is 0. S103, when the second communication link is idle, the second task unit updates the processing identifier. If the second task unit successfully updates the processing identifier, the sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier is processed through the second communication link. S104, whenever the processing identifier is successfully updated, the updated processing identifier is detected. If the updated processing identifier meets the preset conditions, the processing of the target data A is completed.

2. The self-adapting PCIe bandwidth data processing system of claim 1, wherein, When the first communication link is in an idle state, the first task unit updates the processing identifier, including: When the first communication link is idle, the first task unit performs an atomic addition operation on the processing identifier at the current moment.

3. The adaptive PCIe bandwidth data processing system according to claim 1, characterized in that, When the second communication link is idle, the second task unit updates the processing identifier, including: When the second communication link is idle, the second task unit performs an atomic addition operation on the processing identifier at the current moment.

4. The self-adapting PCIe bandwidth data processing system of claim 1, wherein, When there is no sub-data to be processed in the first communication link, the first communication link is in an idle state.

5. The self-adapting PCIe bandwidth data processing system of claim 1, wherein, When there is no sub-data to be processed in the second communication link, the second communication link is in an idle state.

6. The self-adapting PCIe bandwidth data processing system of claim 1, wherein, The step of processing the sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier through the first communication link includes: The sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier is processed by the set communication algorithm through the first communication link; The step of processing the sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier through the second communication link includes: The sub-data corresponding to the sub-data identifier that is the same as the updated processing identifier is processed by the set communication algorithm through the second communication link.

7. The self-adapting PCIe bandwidth data processing system of claim 1, wherein, The preset condition is: the updated processing identifier is greater than N.

8. The self-adapting PCIe bandwidth data processing system of claim 1, wherein, Step S104 also includes: If the updated processing identifier does not meet the preset conditions, then return to the execution steps S102 and S103.

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