Intelligent DSP processor architecture based on RISC-V expansion

Through the intelligent DSP processor architecture based on RISC-V extension, the problems of insufficient resource utilization and latency in edge computing devices in AI/DSP hybrid task processing are solved, and efficient dynamic switching and collaborative processing of hardware resources are achieved, thereby improving processing efficiency.

CN120596431AActive Publication Date: 2025-09-05HUNAN GREAT WALL GALAXY TECH CO LTD
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Patent Information

Application Number
CN202511110700.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-08-08
Publication Date
2025-09-05
Estimated Expiration
2045-08-08

AI Technical Summary

Technical Problem

In traditional solutions, edge computing devices face problems such as insufficient hardware resource utilization, high power consumption in data transfer, high latency, and insufficient efficiency of the RISC-V RVV instruction set when handling AI inference and real-time signal processing, making it impossible to efficiently and collaboratively process AI/DSP hybrid tasks.

Method used

It adopts an intelligent DSP processor architecture based on RISC-V extension, and through components such as vector launch queue, scoreboard, vector decoding and launch logic, vector register file, execution unit, AI-DSP hybrid computing unit, combined with RISC-V RVV extended instruction set, it realizes dynamic switching and optimization of hardware resources, and supports efficient coordinated processing of AI matrix multiplication and DSP complex operations.

Benefits of technology

It achieves efficient collaborative processing of AI and DSP tasks, improves hardware resource utilization, reduces the latency of mixed tasks, and improves processing efficiency.

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Abstract

The invention relates to an intelligent DSP (Digital Signal Processor) architecture based on RISC-V (Reduced Initiation Standard-Video) extension, which is characterized in that a topology is dynamically switched through a hardware multiplexing parallel array, so that the same hardware unit can be switched into an AI matrix multiplication or DSP complex number operation mode in real time, the dynamic switching of the AI matrix multiplication and the DSP complex number operation is realized, the resource idleness of a discrete architecture is avoided, the efficient collaboration of AI and DSP tasks is realized, and the reliability of the architecture is improved. The utilization rate of hardware resources is improved; meanwhile, single-cycle operation is achieved through a newly-added special instruction set, namely, an RISC-V RVV extended instruction set, and a circular buffer manager is designed to eliminate software simulation overhead, so that AI / DSP mixed task time delay is effectively reduced, and high-performance AI / DSP mixed task cooperative processing is achieved.
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Citation Information

Patent Citations

  • Neural network extension execution computer system based on RISC-V

    CN119539001A