Compensation method, digital circuit, electronic equipment and computer readable storage medium

Abstract

The invention provides a compensation method, a digital circuit, electronic equipment and a computer readable storage medium, and the method comprises the steps: 1), adjusting the size of a load capacitor of a to-be-compensated digital circuit, and carrying out the simulation, and obtaining a corresponding output voltage waveform; 2) calculating a voltage conversion rate, and removing the load capacitance corresponding to the voltage conversion rate smaller than a set value; 3) selecting capacitance values of N load capacitors in the reduced value range and simulating the capacitance values; 4) establishing a linear regression equation based on each output voltage waveform in the step 3), and establishing a corresponding relation with the voltage surge; and (5) setting the capacitance value of the load capacitor according to the requirement, and realizing the compensation for the distortion of the output voltage. According to the invention, a mode of externally hanging the load capacitor is adopted, the problem that transient voltage signals and voltage conversion speed are mutually restrained is solved, and compensation of signal distortion is realized; the capacitance value of the load capacitor can be visually, simply and conveniently determined; and the method is suitable for a single gate-level circuit and a digital circuit module with a multi-level gate-level circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a compensation method, a digital circuit, an electronic device, and a computer-readable storage medium. Background Art

[0002] Spikes refer to transient voltage signals (voltage spikes) or current signals (current spikes) with abnormal amplitudes that occur briefly in a circuit. Figure 1 As shown, transient voltage surges can have amplitudes significantly greater or less than the normal voltage signal, severely impacting system stability. These surges are primarily caused by lightning, power outages, tripped circuit breakers, short circuits, malfunctions of power companies, electromagnetic pulses (EMPs, with frequencies ranging from 100kHz to 1MHz) generated by electromagnetic field energy, inductive surges, and transient operations of other high-power equipment on the same power supply (such as switching operations and fault clearing).

[0003] The voltage conversion rate (Slew Rate, SR) is also known as the slew rate. It is the amplitude of the voltage rise in a period of 1 microsecond or 1 nanosecond. Intuitively speaking, it is the time required for the square wave voltage to rise from the trough to the peak. The units are usually V / s, V / ms, V / μs and V / ns. The voltage conversion rate is an important parameter that affects and induces transient intermodulation distortion (slow voltage conversion speed will increase transient intermodulation distortion). It is a major indicator to measure the speed performance of the standard unit (STD cell). Taking the op amp as an example, (Where V is voltage and t is time), for a square wave, dt tends to 0, then the voltage conversion rate SR tends to infinity. That is to say, only an op amp with an infinite voltage conversion rate SR can process a standard square wave normally. Therefore, any op amp cannot process a square wave normally, and the output waveform will inevitably be distorted, such as Figure 2 As shown, the input signal Vin is a standard square wave signal, and the output signal Vout is deformed due to a low voltage conversion rate.

[0004] Excessive surge amplitude variation and low voltage conversion rate are two key factors that cause digital signal distortion. Therefore, how to improve the signal distortion caused by surges and voltage conversion rate in digital circuits has become one of the urgent problems to be solved by technicians in this field.

[0005] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a compensation method, a digital circuit, an electronic device and a computer-readable storage medium for solving the problem of digital signal distortion in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a compensation method, which at least includes:

[0008] 1) providing a digital circuit to be compensated, setting a load capacitor at the output end of the digital circuit to be compensated, adjusting the size of the load capacitor and simulating the digital circuit to be compensated respectively to obtain a corresponding output voltage waveform;

[0009] 2) calculating the voltage conversion rate corresponding to each load capacitor based on each output voltage waveform, and removing the load capacitor corresponding to a voltage conversion rate less than a set value to narrow the value range of the load capacitor;

[0010] 3) selecting N values ​​of the load capacitor within the reduced value range, and simulating the corresponding output voltage waveforms, where N is a natural number greater than or equal to 2;

[0011] 4) Establishing a linear regression equation for the capacitance of the load capacitor and the voltage conversion rate corresponding to each output voltage waveform obtained in step 3), and establishing a corresponding relationship with the voltage surge; wherein, the larger the load capacitance, the smaller the voltage conversion rate and the smaller the voltage surge;

[0012] 5) Based on the relationship among the load capacitance, the voltage conversion rate, and the voltage surge, the capacitance of the load capacitance is set as needed to balance the voltage conversion rate and the voltage surge, thereby compensating for output voltage distortion.

[0013] Optionally, the digital circuit to be compensated is a gate-level circuit or a digital circuit module connected to the same power supply.

[0014] Optionally, in step 1), the value range of the load capacitance is set to 0-10 pF.

[0015] Optionally, the starting value of the voltage conversion rate is the voltage conversion rate corresponding to when the capacitance of the load capacitor is 0.

[0016] Optionally, in step 4), multiple linear regression equations are established, and the linear regression equation with the highest fitting degree is selected as the final linear regression equation of the capacitance of the load capacitor and the voltage conversion rate.

[0017] More optionally, the linear regression equation includes at least one of a simple linear regression equation, a polynomial linear regression equation and a logarithmic linear regression equation.

[0018] Optionally, when the voltage surge disappears, a load capacitance value corresponding to the maximum voltage conversion rate is selected, and the load capacitance value is allocated to the digital circuit to be compensated.

[0019] More optionally, when the voltage surge is less than a preset voltage, it is determined that the voltage surge disappears.

[0020] To achieve the above-mentioned purpose and other related purposes, the present invention also provides a digital circuit, which at least includes: a digital module and a load capacitor, one end of the load capacitor is connected to the output end of the digital module, and the other end is grounded; wherein the capacitance of the load capacitor is determined based on the above-mentioned compensation method.

[0021] To achieve the above-mentioned object and other related objects, the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is used to implement the above-mentioned compensation method.

[0022] To achieve the above-mentioned and other related objectives, the present invention further provides an electronic device, comprising at least:

[0023] An instruction memory and a processor; the instruction memory and the processor are communicatively connected to each other, the instruction memory stores computer instructions, and the processor executes the above compensation method by executing the computer instructions.

[0024] As described above, the compensation method, digital circuit, electronic device and computer-readable storage medium of the present invention have the following features:

[0025] Beneficial effects:

[0026] The present invention uses an external load capacitor to solve the problem of the mutual restraint between transient voltage signals (voltage surges) and voltage conversion speed (transient intermodulation distortion), balance the surge and voltage conversion rate (obtain the desired transient voltage signal and / or voltage conversion speed), and achieve signal distortion compensation.

[0027] The present invention determines the range of load capacitance using voltage conversion rate (transient intermodulation distortion) and obtains a linear regression model. Based on the results of this model, the load capacitance value and the voltage conversion rate can be directly determined by quantitative calculation results while eliminating surges to a certain extent, thereby determining the load capacitance value in an intuitive and simple manner.

[0028] The present invention is a quantitative analysis method applicable to both single gate-level circuits and digital circuit modules with multiple gate-level circuits. When applied to digital circuit modules, it can also resolve transient voltage signals (voltage surges) and slow voltage conversion speeds (transient intermodulation distortion) caused by transient operations of other high-power devices on the same power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 The waveform diagram shows a voltage surge.

[0030] Figure 2 Shown is a schematic diagram of the output voltage simulation waveform of the op amp.

[0031] Figure 3 Shown is a flow chart of the compensation method of the present invention.

[0032] Figure 4 Shown is a structural schematic diagram of the digital circuit to be compensated according to the present invention.

[0033] Figure 5 It is a schematic diagram showing the output voltage waveform of the digital circuit to be compensated of the present invention when no load capacitance is set.

[0034] Figure 6 Shown is a schematic diagram of the output voltage waveform of the digital circuit to be compensated according to the present invention when the load capacitors have different capacitance values.

[0035] Figure 7 Display as Figure 6 A partial enlarged diagram of the voltage surge.

[0036] Figure 8 Display as Figure 6 A partial enlarged schematic diagram of the falling edge.

[0037] Figure 9 It is a schematic diagram showing the output voltage waveform of the digital circuit to be compensated according to the present invention after the value range of the load capacitance is narrowed.

[0038] Figure 10 Display as Figure 9 A partial enlarged schematic diagram of the falling edge.

[0039] Figure 11 Display as Figure 9 A partial enlarged diagram of the voltage surge.

[0040] Figure 12 It is a schematic diagram showing the relationship among load capacitance, voltage conversion rate and voltage surge of the present invention.

[0041] Figure 13 Shown is a structural schematic diagram of the digital circuit of the present invention.

[0042] Figure 14 Shown is a schematic structural diagram of the electronic device of the present invention.

[0043] Component number description

[0044] 1 Digital circuit to be compensated

[0045] 2 Digital Circuits

[0046] 21 digital modules

[0047] 3 Electronic devices

[0048] 31 processors

[0049] 32 instruction memory DETAILED DESCRIPTION

[0050] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] See also Figure 3-Figure 14 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0052] like Figure 3 As shown, the present invention provides a compensation method for compensating for the distortion of a digital signal, the compensation method comprising:

[0053] 1) Provide a digital circuit 1 to be compensated, set a load capacitor CL at the output end of the digital circuit 1 to be compensated, adjust the size of the load capacitor CL and simulate the digital circuit 1 to be compensated to obtain a corresponding output voltage waveform.

[0054] Specifically, in this embodiment, a NAND gate circuit is taken as an example. In actual use, any gate-level circuit or digital circuit module connected to the same power supply can be used as the digital circuit 1 to be compensated, and is not limited to this embodiment. Figure 4 As shown in the embodiment, the first digital signal V1 and the second digital signal V2 are input to the first and second input terminals of the NAND gate nand respectively, and after the NAND logic operation, the voltage transient signal Vout is output. Figure 4 The digital circuit 1 to be compensated is simulated. In this example, the simulation program with integrated circuit emphasis (SPICE) is used for simulation and transient analysis. In actual use, any software that can realize simulation is applicable to the present invention. Figure 5As shown in FIG. 1 , when the load capacitor CL is not set, an abnormal peak (voltage surge) with a large amplitude will appear when the output voltage waveform jumps from a high level to a low level, but the voltage conversion rate SR is relatively large at this time.

[0055] Specifically, then, a load capacitor CL is set at the output end of the digital circuit 1 to be compensated, such as Figure 4 As shown, and adjust the capacitance of the load capacitor CL; as an example, the capacitance of the load capacitor CL can be set to 3 groups of intervals, and 5 values ​​are selected in each interval. In actual use, the number of intervals and the number of values ​​selected in each interval are set as needed, which is not limited to this embodiment. In this example, the value range of the load capacitor CL is set to 0~10pF. Within this range, load capacitors CL with capacitance values ​​of 0, 1fF, 10fF, 100fF, and 1pF are selected and plugged in, and the corresponding output voltage waveform is obtained, as shown Figure 6 The voltage surge when the output voltage jumps from high level to low level is further amplified, as shown in Figure 7 As shown in the figure, as the capacitance of the load capacitor CL increases, the voltage surge gradually improves; conversely, the smaller the capacitance of the load capacitor CL is, the more severe the voltage surge becomes. When the load capacitor CL is set to 0, 1fF, and 10fF, there is a significant voltage surge. Further amplifying the falling edge of the output voltage, as shown in the figure, Figure 8 As shown in the figure, as the load capacitor CL increases, the voltage conversion rate deteriorates. Conversely, as the load capacitor CL decreases, the voltage conversion rate improves. When the load capacitor CL is set to 100fF and 1pF, the falling edge decreases slowly at a certain angle, resulting in a significant delay. This shows that with external load capacitor CL, voltage surge and voltage conversion rate are mutually constrained, and a balance between the two must be achieved based on needs.

[0056] It should be noted that the value range of the load capacitor CL in step 1) needs to cover the case where the voltage surge is large and the voltage conversion efficiency is large, and the case where the voltage surge disappears and the voltage conversion efficiency is small, and can be set according to specific circuit parameters.

[0057] 2) The voltage conversion rate corresponding to each load capacitance CL is calculated based on each output voltage waveform, and the load capacitance CL corresponding to a voltage conversion rate less than a set value is removed to narrow the value range of the load capacitance CL.

[0058] Specifically, based on the formula Calculate the voltage conversion ratio of each output voltage waveform. In this example, the voltage conversion ratio corresponding to each capacitor value is shown in the following table:

[0059] Load capacitor value Voltage conversion rate CL=0 62.06G CL=1fF 55.85G CL=10fF 30.74G CL=100fF 4.33G CL=1pF 460.19M

[0060] Table 1

[0061] The starting value of the voltage conversion rate is the voltage conversion rate corresponding to a load capacitor CL value of 0. The set value can be set according to actual needs and is not detailed here. In this embodiment, the range of the load capacitor CL is narrowed based on the voltage conversion rate, and the range of the load capacitor value is narrowed to 0-10fF.

[0062] 3) Select N values ​​of the load capacitor CL within the reduced value range, and simulate the corresponding output voltage waveforms respectively, where N is a natural number greater than or equal to 2.

[0063] Specifically, in this embodiment, N is set to 5, and the capacitance values ​​are 0, 2.5fF, 5fF, 7.5fF, and 10fF, respectively. Figure 9 As shown in , the waveforms corresponding to the various capacitance values ​​basically overlap, and the waveforms are close to square waves; Figure 10 The figure shows a partial enlarged view of the falling edge of the output voltage; Figure 11 The figure shows a zoomed-in view of a voltage surge when the output voltage transitions from a high level to a low level. In practice, the value of N can be set as needed. A larger N value increases the accuracy of the linear regression equation established in step 4 (e.g., it can be verified using redundant data), but this also results in slower data processing.

[0064] It should be noted that when selecting the capacitance of the load capacitor within the value range, the value can be uniform, or more data can be obtained in a certain area (ie, non-uniform), which will not be described in detail here.

[0065] 4) A linear regression equation is established for the capacitance of the load capacitor CL and the voltage conversion rate corresponding to each output voltage waveform obtained in step 3), and a corresponding relationship is established with the voltage surge.

[0066] Specifically, also based on the formula The voltage conversion rate of each output voltage waveform is calculated, and a linear regression equation is established between the capacitance of the load capacitor CL and the voltage conversion rate. This includes but is not limited to a simple linear regression equation, a polynomial linear regression equation, and a logarithmic linear regression equation. Any linear regression equation that can reflect the relationship between the load capacitance and the voltage conversion rate is applicable and will not be detailed here.

[0067] As an example, the simple linear regression equation satisfies:

[0068] y=ax+b;

[0069] 0≤R1 2 ≤1;

[0070] Among them, y is the voltage conversion rate, x is the value of the load capacitance, a is the coefficient, b is the constant term, R1 2 is the fit of the simple linear regression equation to the observed data.

[0071] As an example, the polynomial linear regression equation satisfies:

[0072] y=cx n +dx n-1 +...ex+f;

[0073] 0≤R2 2 ≤1;

[0074] Among them, y is the voltage conversion rate, x is the value of the load capacitance, c, d, e are coefficients, f is a constant term, R2 2 is the fit of the polynomial linear regression equation to the observed data.

[0075] As an example, the log-linear regression equation satisfies:

[0076] y=gln(x)+h;

[0077] 0≤R3 2 ≤1;

[0078] Among them, y is the voltage conversion rate, x is the value of the load capacitance, g is the coefficient, h is the constant term, R3 2 is the fit of the log-linear regression equation to the observed data.

[0079] It should be noted that any linear regression equation can be selected to describe the relationship between load capacitance and voltage conversion rate, or multiple linear regression equations can be established (for example, simple linear regression equation, polynomial linear regression equation and logarithmic linear regression equation are established), and the fitting degree R can be selected. 2 The highest linear regression equation is taken as the final linear regression equation; where R 2 The value ranges from 0 to 1. If R 2 = 0, it means that the model does not explain any variability of the dependent variable; if R 2 =1, it means that the model fully explains the variability of the dependent variable, R 2 The closer it is to 1, the higher the degree of fit, and the more it reflects the actual data distribution.

[0080] Specifically, in this embodiment, a simple linear regression equation is used to describe the relationship between load capacitance and voltage conversion rate. Based on the simulation results of step 3), it is obtained that: y = -7.617x + 66.469, R 2 =0.9537.

[0081] Specifically, the relationship between load capacitance, voltage conversion rate and voltage surge is established, such as Figure 12 The relationship between the voltage conversion rate and the maximum output voltage corresponding to each capacitance value is shown in the following table:

[0082] Load capacitor value (fF) Voltage conversion rate Maximum output voltage (V) CL=0 62.06G 1.142889 CL=2.5 48.84G 1.131257 CL=5 41.14G 1.12491 CL=7.5 35.31G 1.120801 CL=10 30.74G 1.117906

[0083] Table 2

[0084] 5) Based on the relationship between load capacitance, voltage conversion rate and voltage surge, the capacitance of load capacitance CL is set as needed to balance the voltage conversion rate and voltage surge to achieve distortion compensation.

[0085] Specifically, based on Figure 12 The relationship between the linear regression model and the voltage surge can be obtained, and the corresponding load capacitor CL can be configured according to the needs. For example, if the voltage surge requirement is high, a load capacitor CL with a larger capacitance can be selected accordingly, and if the voltage conversion rate requirement is high, a load capacitor CL with a smaller capacitance can be selected accordingly.

[0086] As an example, when the voltage surge disappears, the load capacitance value corresponding to the maximum voltage conversion rate is selected and assigned to the digital circuit to be compensated. The voltage surge disappears when the voltage surge is less than a preset voltage. The preset voltage is set based on the actual application and is not described in detail here. In the present invention, the voltage surge is the absolute value of the difference between the transient voltage value and the normal voltage value. The transient voltage value can be greater than the normal voltage value (a sudden upward change) or less than the normal voltage value (a sudden downward change).

[0087] like Figure 13 As shown, the present invention further provides a digital circuit 2, which at least includes: a digital module 21 and a load capacitor CL, one end of the load capacitor CL is connected to the output end of the digital module 21, and the other end is grounded; wherein the capacitance of the load capacitor CL is determined based on the compensation method of the present invention to achieve compensation for the output voltage of the digital module 21 and alleviate signal distortion.

[0088] like Figure 14 As shown, the present invention provides an electronic device 3, which may include a processor 31 and an instruction memory 32, wherein the processor 31 and the instruction memory 32 may be connected to each other through a communication interface based on a bus or other methods.

[0089] Specifically, the processor 31 can be any type of available device with information processing capabilities, such as a central processing unit or a digital signal processor, etc., which is used to execute computer instructions stored in the instruction memory 32 to implement the compensation method of the present invention; the instruction memory 32 is connected to the processor 31 and can be various available storage media for storing instructions executable by the processor 31.

[0090] The present invention also provides a computer-readable storage medium having a computer program stored thereon, the computer program being used to implement the compensation method of the present invention. Those skilled in the art will appreciate that all or part of the process steps in the compensation method of the present invention can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the process steps of the compensation method of the present invention. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); the storage medium can also include a combination of the aforementioned types of memory.

[0091] In summary, the present invention provides a compensation method, a digital circuit, an electronic device, and a computer-readable storage medium. The compensation method includes: 1) providing a digital circuit to be compensated, setting a load capacitor at the output end of the digital circuit to be compensated, adjusting the size of the load capacitor, and simulating the digital circuit to be compensated to obtain a corresponding output voltage waveform; 2) calculating the voltage conversion rate corresponding to each load capacitor based on each output voltage waveform, removing the load capacitor corresponding to a voltage conversion rate less than a set value to narrow the value range of the load capacitor; 3) selecting N load capacitor values ​​within the narrowed value range, and simulating each to obtain a corresponding output voltage waveform, where N is a natural number greater than or equal to 2; 4) establishing a linear regression equation for the capacitance and voltage conversion rate of the load capacitor corresponding to each output voltage waveform obtained in step 3), and establishing a corresponding relationship with the voltage surge; wherein a larger load capacitance is associated with a smaller voltage conversion rate and a smaller voltage surge; and 5) setting the capacitance of the load capacitor as needed based on the relationship between the load capacitance, the voltage conversion rate, and the voltage surge to balance the voltage conversion rate and the voltage surge, thereby compensating for output voltage distortion. The present invention employs external load capacitors to address the interplay between transient voltage signals (voltage surges) and voltage conversion speed (transient intermodulation distortion), thereby compensating for signal distortion. The load capacitor value can be determined intuitively and easily, and the method is applicable to both single-gate circuits and digital circuit modules with multiple gate-level circuits. Therefore, the present invention effectively overcomes the shortcomings of existing technologies and possesses high industrial value.

[0092] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A compensation method, characterized in that: The compensation method at least includes: 1) providing a digital circuit to be compensated, setting a load capacitor at the output end of the digital circuit to be compensated, adjusting the size of the load capacitor and simulating the digital circuit to be compensated respectively to obtain a corresponding output voltage waveform; 2) calculating the voltage conversion rate corresponding to each load capacitor based on each output voltage waveform, and removing the load capacitor corresponding to a voltage conversion rate less than a set value to narrow the value range of the load capacitor; 3) selecting N values ​​of the load capacitor within the reduced value range, and simulating the corresponding output voltage waveforms, where N is a natural number greater than or equal to 2; 4) Establishing a linear regression equation for the capacitance of the load capacitor and the voltage conversion rate corresponding to each output voltage waveform obtained in step 3), and establishing a corresponding relationship with the voltage surge; wherein, the larger the load capacitance, the smaller the voltage conversion rate and the smaller the voltage surge; 5) Based on the relationship among the load capacitance, the voltage conversion rate, and the voltage surge, the capacitance of the load capacitance is set as needed to balance the voltage conversion rate and the voltage surge, thereby compensating for output voltage distortion.

2. The compensation method according to claim 1, wherein: The digital circuit to be compensated is a gate-level circuit or a digital circuit module connected to the same power supply.

3. The compensation method according to claim 1, wherein: In step 1), the value range of the load capacitance is set to 0-10 pF.

4. The compensation method according to claim 1, wherein: The initial value of the voltage conversion rate is the voltage conversion rate corresponding to when the capacitance of the load capacitor is 0.

5. The compensation method according to claim 1, wherein: In step 4), multiple linear regression equations are established, and the linear regression equation with the highest fitting degree is selected as the final linear regression equation of the capacitance of the load capacitor and the voltage conversion rate.

6. The compensation method according to any one of claims 1 or 5, characterized in that: The linear regression equation includes at least one of a simple linear regression equation, a polynomial linear regression equation and a logarithmic linear regression equation.

7. The compensation method according to claim 1, wherein: When the voltage surge disappears, a load capacitance value corresponding to the maximum voltage conversion rate is selected, and the load capacitance value is allocated to the digital circuit to be compensated.

8. The compensation method according to claim 7, characterized in that: When the voltage surge is less than a preset voltage, it is determined that the voltage surge disappears.

9. A digital circuit, characterized in that: The digital circuit at least includes: a digital module and a load capacitor, one end of the load capacitor is connected to the output end of the digital module, and the other end is grounded; The capacitance of the load capacitor is determined based on the compensation method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is used to implement the compensation method according to any one of claims 1 to 8.

11. An electronic device, characterized in that: The electronic device includes at least: an instruction memory and a processor; the instruction memory and the processor are communicatively connected to each other, the instruction memory stores computer instructions, and the processor executes the compensation method according to any one of claims 1 to 8 by executing the computer instructions.

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