High-speed parallel read-write method, equipment and device for frequency division radio frequency identification

Abstract

The invention provides a high-speed parallel read-write method, equipment and device for frequency division radio frequency identification, and relates to the technical field of backscatter communication, the method is applied to the high-speed parallel read-write equipment for frequency division radio frequency identification, and the method comprises the following steps: combining downlink excitation signals of RFID read-write sessions of a plurality of sub-bands into a composite signal through a digital up-converter; the amplified composite signals are transmitted to the frequency division multiplexing RFID tags through the transmitting antenna, and the amplified composite signals are used for exciting the frequency division multiplexing RFID tags of different sub-bands; receiving a multi-band backscattering signal reflected by the frequency division multiplexing RFID tag, separating the multi-band backscattering signal through a digital down converter, and distributing the multi-band backscattering signal to an independent read-write session corresponding to each sub-band for demodulation processing; and performing real-time demodulation on the separated backscattering signals of each sub-band through an FPGA real-time demodulation module to obtain demodulated data of each sub-band. According to the invention, the system design complexity of the read-write equipment is simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of backscatter communication, and in particular to a high-speed parallel reading and writing method, equipment and device for frequency division radio frequency identification. Background Art

[0002] Radio frequency identification (RFID) is a typical passive IoT technology. Passive tags are energized by the carrier wave transmitted by the reader and then reflect or absorb it to modulate information, transmitting identification information to the reader. This technology has been widely used in logistics tracking, asset management, product traceability and anti-counterfeiting, industrial assembly lines, and other fields. Traditional RFID in the ultra-high frequency (UHF) band uses time-division multiplexing, leveraging the EPC Gen-2 protocol to avoid collisions. Tags are read and written one by one, and only one tag can be read or written at a time.

[0003] Because traditional UHF radio frequency identification (RFID) can only perform time-division multiplexing (TDM), resulting in low read and write efficiency and unsupported by other multiplexing methods, new passive RFID tags have emerged to improve the spectrum efficiency of RFID read and write processes. Unlike traditional tags that respond to carrier excitation across the entire RFID frequency band, these tags feature frequency-division multiplexing (FDM). Each tag responds only to a specific sub-band within the RFID frequency band. This allows a large number of tags to have different response bands, achieving FDM across the entire frequency band.

[0004] RFID tags utilizing frequency division multiplexing (FDM) enable efficient parallel reading and writing, meaning they can read and write simultaneously within multiple frequency sub-bands without interfering with each other. A common approach involves using multiple traditional readers, each operating in a frequency division multiple access (FDMA) band. To eliminate potential interference between readers operating in different frequency bands, each reader must be equipped with a corresponding RF filter. However, this parallel reading and writing approach requires an increasing number of readers as the number of sub-bands increases, significantly increasing costs and system complexity, making it difficult to implement in practice. Summary of the Invention

[0005] The present invention provides a high-speed parallel reading and writing method, device and apparatus for frequency-division radio frequency identification, which is used to solve the defect in the prior art that the number of readers and writers increases with the number of sub-bands, resulting in a sharp increase in cost and system complexity. It realizes the merging and separation of RFID signals of multiple sub-segments through a single device, realizes flexible multi-band processing, and simplifies the system design complexity of the reading and writing device.

[0006] In a first aspect, the present invention provides a high-speed parallel reading and writing method for frequency-division radio frequency identification, which is applied to a high-speed parallel reading and writing device for frequency-division radio frequency identification; the high-speed parallel reading and writing device for frequency-division radio frequency identification includes a digital up-converter DUC, a digital down-converter DDC, a power amplifier, a transmitting antenna, a receiving antenna, and a field programmable gate array (FPGA) real-time demodulation module; the method comprises the following steps: The downlink excitation signals of the radio frequency identification (RFID) read / write sessions of multiple sub-bands are combined into a composite signal through the digital up converter DUC; each of the RFID read / write sessions executes a complete product electronic code (EPC) read / write protocol process; amplifying the composite signal by the power amplifier, and transmitting the amplified composite signal to the frequency division multiplexing RFID tag through the transmitting antenna; the amplified composite signal is used to stimulate the frequency division multiplexing RFID tags of different sub-bands; receiving, via the receiving antenna, a multi-band backscattered signal reflected by the frequency-division multiplexed RFID tag; Separating the multi-band backscatter signals by the digital down converter DDC to obtain separated backscatter signals of each sub-band, and allocating the separated backscatter signals of each sub-band to an independent RFID read / write session for demodulation processing; The separated backscatter signals of each sub-frequency band are demodulated in real time on the FPGA platform by the FPGA real-time demodulation module to obtain demodulated data of each sub-frequency band.

[0007] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, the downlink excitation signals of RFID reading and writing sessions of multiple sub-bands are combined into a composite signal by the digital up converter DUC, including: Upsampling the downlink excitation signal of each sub-frequency band to obtain the upsampled downlink excitation signal of each sub-frequency band; The up-sampled downlink excitation signal of each sub-band is mixed with the corresponding sub-band carrier and then superimposed to form the composite signal.

[0008] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, the high-speed parallel reading and writing device for frequency division radio frequency identification further includes a digital predistortion module and a directional coupler; the amplifying the composite signal by the power amplifier further includes: Feeding back the amplified composite signal output by the power amplifier to the digital predistortion module through the directional coupler; The digital predistortion module performs digital predistortion processing and compensates for nonlinear effects based on a Volterra series model to eliminate mutual interference between multiple sub-frequency bands.

[0009] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, the digital pre-distortion processing is performed by the digital pre-distortion module, and nonlinear effects are compensated based on the Volterra series model, including: Analyzing the composite signal before and after amplification by the digital predistortion module, estimating a nonlinear model and calculating a coefficient matrix; An inverse function of the nonlinear model is calculated, and predistortion processing is performed on each input baseband signal based on the inverse function of the nonlinear model so that the predistorted signal generates inverse nonlinear compensation when passing through the power amplifier, thereby obtaining a target baseband signal after linear amplification.

[0010] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, the multi-band backscattered signal is separated by the digital down converter DDC to obtain the separated backscattered signals of each sub-band, including: For the backscattered signals of each sub-frequency band, the backscattered signals of each sub-frequency band are mixed with the conjugate of the carrier of each sub-frequency band, and non-target frequency band signals other than each sub-frequency band in the multiple frequency bands are filtered out to obtain the processed scattered signals of each sub-frequency band; Down-sampling is performed on the processed scattered signals of each sub-frequency band to obtain the separated backscattered signals of each sub-frequency band.

[0011] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, the backscattered signals of each separated sub-band are demodulated in real time on an FPGA platform to obtain demodulated data of each sub-band, including: For any separated sub-band backscatter signal, removing a DC component of the excitation carrier by sliding average based on the separated sub-band backscatter signal; A matched filter is used to match the preamble sequence contained in the data packet backscattered by the tag to achieve time synchronization of the data frame, and a phase-locked loop is used to perform fine-grained clock recovery. Performing channel estimation and equalization based on the preamble sequence, and optimizing division and square root operations in the channel estimation and equalization using a preset lookup table to map the reflection state to a fixed position in the in-phase orthogonal IQ domain; The target decoder extracts a bit stream transmitted by the tag, and determines the bit stream as the demodulated data of the sub-band.

[0012] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, the method further includes: Introducing an asynchronous transmission mechanism in the RFID read / write sessions of the multiple sub-bands so that the downlink excitation signals of different sub-bands are not aligned in timing, thereby preventing traditional RFID tags from being excited; The asynchronous transmission mechanism is implemented by the following steps: Ensure that the downlink excitation signal of each sub-band RFID read / write session has random delay in timing, and that the command duration, idle time slot distribution, and tag clock offset between each RFID read / write session are different, so that the combined signal envelope cannot be interpreted as a legitimate command by traditional RFID tags.

[0013] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, the method further includes: Detecting and ignoring backscatter signals reflected by conventional RFID tags due to transient synchronization; wherein the backscatter signals appear as identical RN16 response signals simultaneously appearing in the multiple sub-bands, wherein the RN16 response signals are 16-bit random numbers; The method of detecting and ignoring backscattered signals reflected by conventional RFID tags due to short synchronization may include: Monitor the synchronization of the RN16 response signals in the RFID read / write sessions of each sub-band. If the same RN16 response signal appears simultaneously in multiple sub-bands, determine that the RN16 response signal is a backscattered signal reflected by a traditional RFID tag. The backscattered signal reflected by the conventional RFID tag is discarded.

[0014] In a second aspect, the present invention further provides a high-speed parallel read-write device for frequency division radio frequency identification, the high-speed parallel read-write device for frequency division radio frequency identification comprising a digital up converter DUC, a digital down converter DDC, a power amplifier, a transmitting antenna, a receiving antenna, and an FPGA real-time demodulation module; wherein, The digital up converter DUC is used to combine the downlink excitation signals of the RFID read / write sessions of multiple sub-bands into a composite signal; each of the RFID read / write sessions executes a complete EPC read / write protocol process; The power amplifier is used to amplify the composite signal and transmit the amplified composite signal to the frequency division multiplexing RFID tag through the transmitting antenna; the amplified composite signal is used to excite the frequency division multiplexing RFID tags of different sub-bands; The receiving antenna is used to receive the multi-band backscattered signal reflected by the frequency division multiplexing RFID tag; The digital down converter DDC is used to separate the multi-band backscatter signals to obtain separated backscatter signals of each sub-band, and allocate the separated backscatter signals of each sub-band to an independent RFID read / write session for demodulation processing; The FPGA real-time demodulation module is used to perform real-time demodulation on the separated backscatter signals of each sub-frequency band on the FPGA platform to obtain demodulated data of each sub-frequency band.

[0015] In a third aspect, the present invention further provides a high-speed parallel read / write device for frequency division radio frequency identification, which is applied to a high-speed parallel read / write device for frequency division radio frequency identification; the high-speed parallel read / write device for frequency division radio frequency identification includes a digital up converter DUC, a digital down converter DDC, a power amplifier, a transmitting antenna, a receiving antenna, and a field programmable gate array (FPGA) real-time demodulation module; the device includes the following modules: A multi-band signal merging module is used to merge the downlink excitation signals of multiple sub-band radio frequency identification (RFID) read / write sessions into a composite signal through the digital up converter (DUC); each RFID read / write session executes a complete product electronic code (EPC) read / write protocol process; a transmitting module, configured to amplify the composite signal through the power amplifier and transmit the amplified composite signal to the frequency-division multiplexing RFID tag through the transmitting antenna; the amplified composite signal is used to excite the frequency-division multiplexing RFID tags of different sub-bands; a receiving module, configured to receive, through the receiving antenna, a multi-band backscattered signal reflected by the frequency-division multiplexed RFID tag; A multi-band signal separation module is used to separate the multi-band backscatter signals through the digital down converter DDC to obtain separated backscatter signals of each sub-band, and allocate the separated backscatter signals of each sub-band to an independent RFID read / write session for demodulation processing; The real-time demodulation module is used to perform real-time demodulation on the separated backscatter signals of each sub-frequency band on the FPGA platform through the FPGA real-time demodulation module to obtain demodulated data of each sub-frequency band.

[0016] In a fourth aspect, the present invention also provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the high-speed parallel reading and writing method for frequency-division radio frequency identification as described above is implemented.

[0017] In a fifth aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the high-speed parallel reading and writing method for frequency division radio frequency identification as described above.

[0018] In a sixth aspect, the present invention further provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned high-speed parallel reading and writing methods for frequency division radio frequency identification.

[0019] The present invention provides a high-speed parallel reading and writing method, device and apparatus for frequency division radio frequency identification. The method is applied to a high-speed parallel reading and writing device for frequency division radio frequency identification. The reading and writing device includes a digital up converter DUC, a digital down converter DDC, a power amplifier, a transmitting antenna, a receiving antenna and an FPGA real-time demodulation module. The method comprises: first, combining downlink excitation signals of RFID reading and writing sessions of multiple sub-bands into a composite signal through the digital up converter DUC, wherein each RFID reading and writing session executes a complete EPC reading and writing protocol process; then, amplifying the composite signal through the power amplifier, and transmitting the amplified composite signal through the transmitting antenna. The multi-band backscattered signal is transmitted to the frequency-division multiplexing RFID tag through a line, and the amplified composite signal is used to stimulate the frequency-division multiplexing RFID tags in different sub-bands. Furthermore, the multi-band backscattered signal reflected by the frequency-division multiplexing RFID tag is received by the receiving antenna, and the multi-band backscattered signal is separated by the digital down converter DDC to obtain the separated backscattered signals of each sub-band, and the separated backscattered signals of each sub-band are allocated to an independent RFID read-write session for demodulation processing. Furthermore, the separated backscattered signals of each sub-band are demodulated in real time on the FPGA platform by the FPGA real-time demodulation module to obtain the demodulated data of each sub-band.

[0020] The high-speed parallel read / write device for frequency-division radio frequency identification (FDM) in the present invention includes a digital upconverter (DUC) and a digital downconverter (DDC). The read / write device uses the DUC to combine the transmission signals of multiple read / write sessions and simultaneously transmits them at different frequencies to stimulate FDM RFID tags in different sub-bands and send downlink commands to FDM RFID tags in different sub-bands. After reflection, the uplink tag data from multiple different sub-bands is received by the read / write device and separated into multiple read / write sessions for independent processing by the digital downconverter. Each read / write session includes a high-speed real-time demodulation processing algorithm running on an FPGA platform, enabling decoding of RFID tag information in a single sub-band within a very short delay. In this way, the read / write sessions of each sub-band in the FDM RFID are separated and can run in parallel, while the processing logic of a standard RFID reader / writer can be uniformly reused, ensuring the robustness of parallel read / write in FDM scenarios. Furthermore, a single read / write device can perform multi-band flexible processing of RFID signals from multiple sub-segments, simplifying the system design complexity of the read / write device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 The figure is a flow chart of the high-speed parallel reading and writing method of frequency division radio frequency identification provided by the present invention.

[0023] Figure 2 It is a schematic diagram of the principle of the multi-band frequency division multiplexing RFID reading and writing method of the reader / writer provided by the present invention.

[0024] Figure 3 It is a schematic diagram of the principle of the reading and writing device provided by the present invention using a digital up-down converter to separate and combine multiple sub-band signals.

[0025] Figure 4a One of the schematic diagrams showing the mutual interference between frequency division multiplexing reading and writing in multiple frequency bands.

[0026] Figure 4b The second diagram shows the mutual interference between frequency division multiplexing reading and writing in multiple frequency bands.

[0027] Figure 5 This is a schematic diagram of using a digital predistortion linear power amplifier provided by the present invention to eliminate multi-band mutual interference.

[0028] Figure 6This is a schematic diagram of the RFID real-time demodulation process based on FPGA provided by the present invention.

[0029] Figure 7a One of the logic diagrams for preventing traditional RFID tags from interfering with high-speed parallel read / write devices reading and writing frequency-division multiplexing tags.

[0030] Figure 7b The second logical diagram shows how to avoid interference between traditional RFID tags and high-speed parallel read / write devices reading and writing frequency-division multiplexing tags.

[0031] Figure 8 A schematic structural diagram of a high-speed parallel read-write device for frequency division radio frequency identification provided by the present invention.

[0032] Figure 9 It is a structural diagram of a high-speed parallel reading and writing device for frequency division radio frequency identification provided by the present invention.

[0033] Figure 10 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0034] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0035] The following combination Figures 1-10 The invention describes the high-speed parallel reading and writing method, device and apparatus of frequency division radio frequency identification.

[0036] Figure 1 The present invention provides a high-speed parallel reading and writing method for frequency division radio frequency identification, which is applied to a high-speed parallel reading and writing device for frequency division radio frequency identification. The high-speed parallel reading and writing device for frequency division radio frequency identification includes a digital up converter DUC, a digital down converter DDC, a power amplifier, a transmitting antenna, a receiving antenna, and a field programmable gate array (FPGA) real-time demodulation module. Figure 1 As shown, the method includes the following steps: Step 101: Combine downlink excitation signals of multiple sub-band RFID read / write sessions into a composite signal through a digital up-converter (DUC); each RFID read / write session executes a complete product electronic code (EPC) read / write protocol process; Specifically, it should be noted that the executor of this embodiment is a high-speed parallel read / write device for frequency-division radio frequency identification. The high-speed parallel read / write device for frequency-division radio frequency identification includes a digital up converter (DUC), a digital down converter (DDC), a power amplifier, a transmitting antenna, a receiving antenna, and a field programmable gate array (FPGA) real-time demodulation module. It is used to implement multi-band reading and writing of RFID signals of multiple sub-segments through a single read / write device, thereby simplifying the system design complexity of the read / write device.

[0037] It should be noted that the method is implemented through an FPGA platform, and the hardware includes, for example, a Xilinx ZC706FPGA motherboard and an ADRV9375 RF daughterboard, and the baseband processing algorithms for each sub-band read and write session run in parallel on the FPGA through HDL code.

[0038] The method provided in this embodiment includes the following steps: First, the downlink excitation signals of RFID read / write sessions in multiple sub-bands are combined into a composite signal through a digital up-converter (DUC).

[0039] Traditional RFID readers use a single-frequency excitation signal to wake up the tag and modulate the downlink command signal using pulse interval encoding (PIE). The tag backscatters the excitation signal at a frequency of several hundred kilohertz, forming a narrowband signal around the carrier.

[0040] Figure 2 FIG. 1 is a schematic diagram showing the principle of the multi-band frequency division multiplexing RFID reading and writing method of the reader / writer provided by the present invention, as shown in FIG. Figure 2 As shown in the figure, for multi-band frequency division multiplexing RFID, such signals appear at multiple different frequency positions. For example, the read / write device includes read / write sessions of multiple frequency bands (such as F1, F2, F3, F4, and F5). The read / write sessions of multiple frequency bands are merged to obtain a merged excitation signal. The downlink excitation signal is sent to the FDMA RFID tag. After backscattering, the backscattered data of each frequency carrying its corresponding sub-band RFID tag is obtained.

[0041] In our integrated reader / writer design, RFID signals for each frequency are combined and separated to achieve flexible multi-band processing.

[0042] Among them, the read-write device uses a digital up-converter DUC to combine the excitation signals from multiple read-write sessions. The process includes up-sampling the signal and mixing it with the corresponding sub-frequency signal before handing it to the transmitting antenna.

[0043] A digital upconverter is a core module in modern communications systems, responsible for shifting baseband signals (low-frequency digital signals) to an intermediate frequency (IF) or radio frequency (RF) carrier for transmission via an antenna. Its core function is to achieve frequency shifting and sampling rate adjustment through digital signal processing (DSP).

[0044] A DUC typically consists of three parts: an interpolation filter, a numerically controlled oscillator, and a mixer. The interpolation filter increases the sampling rate of the baseband signal to meet the RF transmission rate requirements. The numerically controlled oscillator generates a digital local oscillator signal for mixing. The mixer multiplies the interpolated baseband signal with the numerically controlled oscillator (NCO) signal to achieve spectrum shifting.

[0045] Each RFID read / write session executes the complete EPC read / write protocol flow. Specifically, for each frequency band, the reader / write device of the present invention includes a traditional RFID read / write session, using standard RFID read / write logic to read and write tags within each sub-band. When using frequency-division multiplexing RFID tags with K sub-bands, the read / write rate can be increased by K times. For example, using frequency-division multiplexing tags with five sub-bands, a tag read rate of up to 5,000 times can be achieved.

[0046] Step 102: amplify the composite signal using a power amplifier, and transmit the amplified composite signal to the frequency division multiplexing RFID tag through a transmitting antenna; the amplified composite signal is used to excite the frequency division multiplexing RFID tags of different sub-bands; Specifically, after obtaining the combined composite signal, the frequency division multiplexing RFID tag needs to be awakened by the composite signal. The amplified composite signal is used to stimulate frequency division multiplexing RFID tags in different sub-bands.

[0047] For example, the composite signal is first amplified by a power amplifier, and then the amplified composite signal is transmitted to a frequency division multiplexing RFID tag through a transmitting antenna. For example, a frequency division multiplexing RFID tag is a tag that supports dynamic switching of operating frequencies and adapts to multi-band allocation.

[0048] Step 103: Receive the multi-band backscattered signal reflected by the frequency division multiplexing RFID tag through the receiving antenna; Specifically, since the amplified composite signal is used to excite frequency-division multiplexing RFID tags in different sub-bands, after receiving the downlink excitation signal, the frequency-division multiplexing RFID tag sends the uplink tag data in multiple different sub-bands to the reader after reflection and frequency division.

[0049] The reading and writing device receives the multi-band backscattered signal through a receiving antenna.

[0050] Step 104: Separate the multi-band backscatter signals using a digital down converter (DDC) to obtain separated backscatter signals of each sub-band, and assign the separated backscatter signals of each sub-band to an independent RFID read / write session for demodulation processing; Specifically, the reading and writing device receives a multi-band backscatter signal, and then separates the multi-band backscatter signal through a digital down converter DDC to obtain separated backscatter signals of each sub-band.

[0051] The digital downconverter (DDC) is a core module in modern communication systems and software-defined radios. It is responsible for converting high-frequency signals (such as RF or IF signals) into low-frequency baseband signals for subsequent digital signal processing (such as demodulation and decoding). Its core function is to achieve frequency shifting and rate adaptation of signals through digital mixing, filtering, and extraction. DDC usually consists of three parts: a mixer, a low-pass filter (LPF), and a decimator. The core functions of DDC include: Frequency shifting: Shifting high-frequency signals to baseband (zero IF) or lower IF.

[0052] Sampling rate reduction: Decimation is used to reduce the data rate and reduce the computational load of subsequent processing.

[0053] Signal filtering: Suppresses out-of-band noise and image frequencies, retaining valid signal components.

[0054] The specific process of the DDC receiving the tag backscatter signal in the present invention is as follows: (1) Input signal: The tag backscatter signal received by the reader (such as RN16 or EPC data), superimposed with carrier leakage and high-frequency noise.

[0055] (2) Down-conversion: The signal is moved to baseband through DDC to separate the in-phase / quadrature I / Q components.

[0056] (3) Filtering and extraction: Filter out carrier leakage and out-of-band interference, and reduce the data rate for decoding.

[0057] The backscattered signals from each separated sub-band are then assigned to independent RFID read / write sessions for demodulation. Each session executes the complete EPC protocol flow, and transmit power is evenly distributed across these multiple frequency bands. The reader / writer device provides an external computer connection via Ethernet for interacting with the reader / writer to adjust parameters and monitor the received baseband signal and tag ID data.

[0058] Step 105 : Demodulate the separated backscatter signals of each sub-band in real time on the FPGA platform through the FPGA real-time demodulation module to obtain demodulated data of each sub-band.

[0059] Specifically, the backscatter signal from any sub-band is demodulated by a separate RFID read / write session within that sub-band. That is, after receiving the separated backscatter signal from the frequency-division multiplexed RFID tags within its own frequency band, the reader / writer session in each sub-band performs a standard digital baseband demodulation process.

[0060] The standard digital baseband demodulation process includes, for example, removing the DC component introduced by the excitation carrier; a matched filter to match the leading sequence contained in the data packet backscattered by the tag to achieve time synchronization of the data frame; a channel equalization module uses the aligned leading sequence to perform channel estimation and channel equalization on the entire data packet; and a decoder using either FM0 or Miller coding to extract the bits transmitted by the tag uplink backscatter transmission to achieve real-time demodulation.

[0061] For multi-band frequency division multiplexing RFID tags, an integrated single reader is used to read and write frequency division multiplexing tags at multiple frequencies at the same time, without being affected by the existence of traditional tags within the reading and writing range, greatly improving the reading and writing speed of a single reader.

[0062] The method provided in this embodiment is applied to a high-speed parallel read / write device for frequency division radio frequency identification, wherein the read / write device includes a digital up converter DUC, a digital down converter DDC, a power amplifier, a transmitting antenna, a receiving antenna, and an FPGA real-time demodulation module; the method includes: first, combining downlink excitation signals of RFID read / write sessions of multiple sub-bands into a composite signal through the digital up converter DUC, wherein each RFID read / write session executes a complete EPC read / write protocol process; then, amplifying the composite signal through the power amplifier, and transmitting the amplified composite signal through the transmitting antenna to the frequency division multiplexing RFI. D tag, the amplified composite signal is used to excite frequency-division multiplexing RFID tags in different sub-bands; further, the multi-band backscatter signal reflected by the frequency-division multiplexing RFID tag is received by the receiving antenna, and the multi-band backscatter signal is separated by the digital down converter DDC to obtain the separated sub-band backscatter signals, and the separated sub-band backscatter signals are allocated to independent RFID read-write sessions for demodulation processing; then, the separated sub-band backscatter signals are demodulated in real time on the FPGA platform through the FPGA real-time demodulation module to obtain the demodulated data of each sub-band.

[0063] The high-speed parallel read / write device for frequency-division radio frequency identification (FDM) in the present invention includes a digital upconverter (DUC) and a digital downconverter (DDC). The read / write device uses the DUC to combine the transmission signals of multiple read / write sessions and simultaneously transmits them at different frequencies to stimulate FDM RFID tags in different sub-bands and send downlink commands to FDM RFID tags in different sub-bands. After reflection, the uplink tag data from multiple different sub-bands is received by the read / write device and separated into multiple read / write sessions for independent processing by the digital downconverter. Each read / write session includes a high-speed real-time demodulation processing algorithm running on an FPGA platform, enabling decoding of RFID tag information in a single sub-band within a very short delay. In this way, the read / write sessions of each sub-band in the FDM RFID are separated and can run in parallel, while the processing logic of a standard RFID reader / writer can be uniformly reused, ensuring the robustness of parallel read / write in FDM scenarios. Furthermore, a single read / write device can perform multi-band flexible processing of RFID signals from multiple sub-segments, simplifying the system design complexity of the read / write device.

[0064] According to a high-speed parallel read and write method for frequency division radio frequency identification provided by the present invention, downlink excitation signals of RFID read and write sessions in multiple sub-bands are combined into a composite signal through a digital up converter DUC, including: Upsampling the downlink excitation signal of each sub-frequency band to obtain the upsampled downlink excitation signal of each sub-frequency band; The upsampled downlink excitation signal of each sub-band is mixed with the corresponding sub-band carrier and then superimposed to form a composite signal.

[0065] Specifically, in some embodiments, the process of combining the multi-band signals in step 101 can be implemented by the following steps: First, the downlink excitation signal of each sub-band is upsampled to obtain the upsampled downlink excitation signal of each sub-band. Then, the upsampled downlink excitation signal of each sub-band is mixed with the corresponding sub-band carrier and superimposed to form a composite signal.

[0066] It is understandable that traditional RFID readers wake up tags through a single-frequency excitation signal and modulate downlink command signals using pulse interval encoding (PIE). Tags backscatter the excitation signal at a frequency of several hundred kilohertz, forming a narrowband signal around the carrier. Figure 2 As shown, for a multi-band frequency division multiplexing RFID tag, such signals will appear at multiple different frequency positions, and each frequency carries the data backscattered by its corresponding sub-band RFID tag.

[0067] In the high-speed parallel reading and writing of frequency division radio frequency identification of the present invention, RFID signals of each frequency are combined and separated to achieve flexible multi-band processing.

[0068] For example, Figure 3 This is a schematic diagram of the principle of the read-write device provided by the present invention using a digital up-down converter to separate and merge multiple sub-band signals, such as Figure 3 As shown, the high-speed parallel read / write device of frequency division radio frequency identification uses a digital up-converter (DUC) to combine the excitation signals from multiple read / write sessions. The process includes up-sampling the signal and mixing it with the corresponding sub-frequency (F1, Fi...FN) signals to obtain a composite signal, and then delivering the composite signal to the transmitting antenna.

[0069] In the method provided in this embodiment, the downlink excitation signal for each sub-band is first upsampled using a digital up-converter (DUC) to obtain the upsampled downlink excitation signal for each sub-band. The upsampled downlink excitation signal for each sub-band is then mixed with the corresponding sub-band carrier and superimposed to form a composite signal. The reader / writer device combines the transmit signals from multiple read / write sessions and simultaneously transmits them at different frequencies to stimulate frequency-division multiplexed RFID tags in different sub-bands and send downlink commands to them. The reader / writer device of the present invention processes multi-band RFID signals within a single device and utilizes a digital up-converter to precisely combine the multi-band RFID signals. This allows the antennas of multiple readers / writers to be combined into a single pair (one for transmission and one for reception), simplifying the system design complexity of the reader / writer device.

[0070] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, a high-speed parallel reading and writing device for frequency division radio frequency identification further includes a digital predistortion module and a directional coupler; a composite signal is amplified by a power amplifier, and further includes: Feeding the amplified composite signal output by the power amplifier back to the digital predistortion module through a directional coupler; Digital pre-distortion processing is performed through the digital pre-distortion module, and the nonlinear effect is compensated based on the Volterra series model to eliminate the mutual interference between multiple sub-bands.

[0071] Specifically, in some embodiments, the high-speed parallel read-write device for frequency division radio frequency identification further includes a digital pre-distortion module and a directional coupler.

[0072] Frequency-division radio frequency identification (FDM) high-speed parallel read / write devices separate and independently process frequency-division multiplexed RFID signals in different sub-bands. In theory, there should be no mutual interference between sub-bands. However, in practice, due to imperfect RF components, inter-band interference still occurs.

[0073] As mentioned above, the downlink excitation signals (PIE downlink commands) of multiple read and write sessions are combined together. This combined signal then needs to be amplified, for example, from 0dBm to 27dBm, before being sent to the antenna. Ideally, the power amplifier (PA) should amplify the input signal in a linear form. For example, if the input signal is x(t), the output should be However, in reality, RF power amplifiers are composed of nonlinear active devices (such as transistors), which have nonlinear effects such as gain saturation. Figure 4a This is a schematic diagram of the mutual interference between frequency division multiplexing read and write in multiple frequency bands. The horizontal axis represents input power, the vertical axis represents output power, the blue line represents the ideal amplification factor, and the orange line represents the real-world performance. Figure 4a As shown, the actual gain will gradually decrease with the increase of input power, which may cause interference between downlink excitation signals in different sub-bands.

[0074] Figure 4b This is the second diagram of the mutual interference between frequency division multiplexing reading and writing in multiple frequency bands. Figure 4b An example is presented. When two read / write sessions (bands F1 and F2) transmit the carrier of the excitation signal, if both sessions are transmitting the carrier to represent the "high" in PIE modulation, the power input to the amplifier reaches maximum, causing the amplifier to enter saturation. At this point, the amplified signal is relatively stable. Subsequently, when one session stops transmitting the carrier to represent the "low" in PIE modulation, the power input to the amplifier is halved, but the output power does not decrease year-on-year, but instead exceeds half (due to the nonlinear relationship between amplifier gain and input signal power). At this time, the other session, still transmitting the carrier to represent the "high" in PIE modulation, suddenly increases its transmission power. This generates interference at the receiving end of the same read / write session that closely resembles the tag's backscattered signal, potentially misleading the reader's receiving logic into misidentifying it as a tag's signal, thus causing interference.

[0075] The specific implementation process of amplifying the composite signal by the power amplifier in step 102 includes: To alleviate this interference, a mapping method is used to fit the nonlinear curve of gain and input power into a function , and calculate its inverse function , for each target input power , first pre-adjust its actual input power to , then input the nonlinear amplifier and theoretically get Linear amplification of power. However, this method cannot effectively solve the interference. This is because the power amplifier has a memory effect. The output at a certain moment depends not only on the input power at the current moment, but also on the historical input signal. Therefore Figure 4aThe nonlinear curve shown appears as a series of scattered points around a curve rather than a smooth curve.

[0076] In order to completely eliminate this interference, the Volterra series is used to characterize the nonlinearity of the amplifier: At any moment, the output signal of the power amplifier Input signals from the current time and the past time and coefficient matrix The specific values ​​of this coefficient matrix need to be estimated for a specific amplifier, K represents the number of rows in the coefficient matrix, and M represents the number of columns in the coefficient matrix.

[0077] In this implementation, digital pre-distortion (DPD) technology is introduced to linearize the power amplifier.

[0078] Specifically, the amplified composite signal output by the power amplifier is first fed back to the digital predistortion module through a directional coupler. Figure 5 FIG. 1 is a schematic diagram of using a digital predistortion linear power amplifier provided by the present invention to eliminate multi-band mutual interference, as shown in FIG. Figure 5 As shown in Figure 1, a small portion of the amplified signal from the power amplifier is fed back to the digital predistortion module via a directional coupler. It then enters the digital-to-analog converter (DAC) for estimation. The DAC signal is then sent to the power amplifier for amplification.

[0079] Then, digital pre-distortion processing is performed through the digital pre-distortion module to compensate for nonlinear effects based on the Volterra series model to eliminate mutual interference between multiple sub-bands.

[0080] In the method provided in this embodiment, a digital predistortion DPD module is introduced to linearize the power amplifier, thereby ensuring that the final transmit signal is linearly amplified, thereby completely solving the mutual interference problem between sub-bands from the root.

[0081] According to the present invention, a high-speed parallel reading and writing method for frequency division radio frequency identification is provided, which performs digital pre-distortion processing through a digital pre-distortion module and compensates for nonlinear effects based on a Volterra series model, including: The digital pre-distortion module analyzes the composite signal before and after amplification, estimates the nonlinear model and calculates the coefficient matrix; The inverse function of the nonlinear model is calculated, and pre-distortion processing is performed on each input baseband signal based on the inverse function of the nonlinear model so that the pre-distorted signal generates inverse nonlinear compensation when passing through the power amplifier, thereby obtaining the target baseband signal after linear amplification.

[0082] Specifically, in some embodiments, digital predistortion processing is performed by a digital predistortion module to compensate for nonlinear effects based on a Volterra series model, including: First, the composite signal before and after amplification is analyzed through the digital pre-distortion module, the nonlinear model is estimated, and the coefficient matrix is ​​calculated. Then, the inverse function of the nonlinear model is calculated. Based on the inverse function of the nonlinear model, each input baseband signal is pre-distorted so that the pre-distorted signal generates inverse nonlinear compensation when passing through the power amplifier, thereby obtaining the target baseband signal after linear amplification.

[0083] For example, the high-speed parallel read / write device of frequency division radio frequency identification estimates the nonlinear model and calculates the coefficient matrix by analyzing the composite signal (baseband signal) before and after amplification The digital pre-distortion (DPD) module then pre-distorts the original signal using a similar inverse function method, but now applies the inverse function to the baseband in-phase and quadrature (IQ) signals rather than just the power values. This ensures linear amplification of the final transmitted signal, fundamentally eliminating the problem of mutual interference between sub-bands.

[0084] In the method provided in this embodiment, a digital predistortion DPD module is introduced to linearize the power amplifier, ensuring that the final transmit signal is linearly amplified, thereby completely solving the mutual interference problem between sub-bands from the root.

[0085] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, a multi-band backscatter signal is separated by a digital down converter (DDC) to obtain separated backscatter signals of each sub-band, including: For the backscattered signals of each sub-band, the backscattered signals of each sub-band are mixed with the conjugate of the carrier of each sub-band respectively, and the non-target frequency band signals except the sub-band in the multi-band are filtered out to obtain the processed scattered signals of each sub-band; The processed scattered signals of each sub-frequency band are down-sampled to obtain separated backscattered signals of each sub-frequency band.

[0086] Specifically, in some embodiments, the specific implementation process of separating the multi-band backscattered signals by the digital down converter DDC in step 104 includes the following steps: First, for the backscattered signal of each sub-band, the backscattered signal of each sub-band is mixed with the conjugate of the carrier of each sub-band. Furthermore, after filtering out non-target frequency band signals except for each sub-frequency band in the multi-frequency bands, the processed scattered signals of each sub-frequency band are obtained.

[0087] For example, if the target frequency band currently being processed is frequency band F1, and the received backscattered signals include scattered signals from frequency bands F1, F2, F3, F4, and F5, then the backscattered signals from non-target frequency bands (F2, F3, F4, and F5) other than the currently processed frequency band F1 must be filtered out from the received backscattered signals of each sub-frequency band, retaining the backscattered signals from the target frequency band. The processing method for other target frequency bands is similar and is not further described here.

[0088] Furthermore, the processed scattered signals of each sub-frequency band are down-sampled to obtain separated backscattered signals of each sub-frequency band.

[0089] For example, Figure 3 As shown in the figure, the high-speed parallel read / write device of frequency division radio frequency identification uses a digital down converter (DDC) to separate the backscattered signals. The specific process includes: The received signal is mixed with the conjugate of the corresponding sub-frequency signal to move it to the center frequency, and then other frequency band signals are filtered out to obtain the target frequency band signal.

[0090] After that, the signal is sent to the standard reader decoding logic for fast decoding.

[0091] It should be noted that in order to implement the above-mentioned merging and separation processes in the form of real-time operations on the FPGA platform, the digital filtering and upsampling processes in the present invention are divided into multiple stages for processing, thereby reducing resource usage and computational delay without sacrificing performance.

[0092] In this way, the read and write sessions of each sub-band in the frequency division multiplexing RFID are separated and can run in parallel, while the processing logic of the standard RFID reader can be unified and reused.

[0093] However, to achieve stable multi-band reading in practice, two key interference sources must be addressed: interference from traditional tags and interference between sub-bands. Specific measures for interference avoidance will be discussed later.

[0094] In the method provided in this embodiment, after receiving the backscattered signals from each sub-band, a digital down-converter is used to separate the signals from each sub-band. Specifically, the digital down-converter first mixes the backscattered signals from each sub-band with the conjugate of the carrier wave of each sub-band, and then filters out non-target frequency band signals from the multi-band. This results in processed scattered signals from each sub-band. Furthermore, the processed scattered signals from each sub-band are down-sampled to obtain separated backscattered signals from each sub-band. This method processes multi-band RFID signals within a single reader / writer device and accurately separates the backscattered signals from multiple bands using a digital down-converter, simplifying the complexity of the reader / writer system design.

[0095] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, the backscattered signals of each separated sub-band are demodulated in real time on an FPGA platform to obtain demodulated data of each sub-band, including: For any separated sub-band backscatter signal, a DC component of the excitation carrier is removed by sliding average based on the separated sub-band backscatter signal; A matched filter is used to match the preamble sequence contained in the data packet backscattered by the tag to achieve time synchronization of the data frame, and a phase-locked loop is used to perform fine-grained clock recovery. Channel estimation and equalization are performed based on the preamble sequence. A preset lookup table is used to optimize the division and square root operations in the channel estimation and equalization, mapping the reflection state to a fixed position in the in-phase orthogonal IQ domain. The target decoder extracts the bit stream transmitted by the tag and determines the bit stream as the data after sub-band demodulation.

[0096] Specifically, in some embodiments, the FPGA real-time demodulation process in step 105 is implemented by the following steps: Figure 6 This is a schematic diagram of the RFID real-time demodulation process based on FPGA provided by the present invention, such as Figure 6 As shown, the method includes: First, for any separated sub-band backscatter signal, the DC component of the excitation carrier is removed by sliding average based on the separated sub-band backscatter signal RFID signal, that is, the DC component is removed.

[0097] In signal processing, removing DC offset is a key step in eliminating constant or low-frequency offset components in signals. This is particularly common in radio frequency (RF) systems, sensor signal processing, and communication systems. The following is a detailed explanation of the DC offset removal methods and principles for RFID signal processing: 1. Source of DC component In RFID systems, DC offset may be caused by the following reasons: Non-idealities of hardware circuits: bias voltage / current of amplifiers and mixers.

[0098] Carrier Leakage: The carrier signal transmitted by the reader is directly coupled to the receiving end.

[0099] Baseline shift from tag backscatter: Asymmetric reflections created when a passive tag modulates impedance.

[0100] 2. Methods for removing DC components (1) Hardware circuit method: such as AC coupling and differential amplifier circuit.

[0101] (2) Digital signal processing methods: such as mean subtraction, high-pass filter (HPF), and adaptive DC elimination.

[0102] An example of a process for processing backscattered signals in this embodiment is as follows: Step 1: Remove the DC component of the carrier leakage through AC coupling or digital high-pass filtering.

[0103] Step 2: Demodulate the remaining signal (such as FM0 decoding) to extract the RN16 or EPC data.

[0104] Furthermore, a matched filter can be used to match the preamble sequence contained in the data packets backscattered by the tag to achieve time synchronization of the data frame, and combined with a phase-locked loop for fine-grained clock recovery. Considering the high instability of passive tag clocks (clock deviation greater than 10%), this time synchronization is divided into two steps: coarse-grained time synchronization and fine-grained time adjustment to closely align the starting point of the data frame.

[0105] Afterwards, the channel equalization module performs channel estimation and channel equalization based on the aligned preamble sequence, and uses a preset lookup table to optimize the division and square root operations in channel estimation and equalization, mapping the reflection state to a fixed position in the IQ domain.

[0106] For example, channel estimation is performed with the help of aligned preamble sequences, and channel equalization is performed on the entire data packet, so that the two point clusters formed by the two reflection states of the passive tag uplink modulation in the IQ domain are equalized to the two positions (+1, 0) and (-1, 0).

[0107] Considering the large and rapidly changing clock drift of RFID chips, we implement a symbol synchronizer to achieve clock recovery. It first performs matched filtering on the entire data packet to leave out the changing modulated data peaks. Then, it synchronizes the symbols in the form of a feedback loop and obtains an accurate single modulated symbol to achieve decoded bits.

[0108] The latency bottlenecks in the above process within an FPGA primarily lie in the channel equalization process and the clock recovery module. Channel equalization involves complex mathematical operations, such as division and square root, which are prohibitively expensive to implement directly on an FPGA. By pre-storing the inverse and square root results in a lookup table, high-speed lookups replace on-the-fly calculations, accelerating the mathematical operations and reducing logic unit consumption. Furthermore, to accelerate clock recovery, a phase-locked loop (PLL)-based design, combined with a simple and efficient timing error detector, enables fast and accurate clock drift estimation and modulation symbol extraction.

[0109] Furthermore, a target decoder, such as an FM0 or Miller decoder, extracts the bit stream transmitted by the tag and converts it into sub-band demodulated data, enabling real-time demodulation of standard RFID tags using an FPGA platform. This is necessary because the reader / writer must support all EPC protocol-specified backscatter link frequencies (BLF) for high-speed reading and writing, as well as the need for digital pre-distortion (DPD).

[0110] The method provided in this embodiment performs real-time demodulation of the separated backscattered signals of each sub-band on an FPGA platform. The backscattered signals reflected by each sub-band are separated into multiple read / write sessions for independent processing. Each read / write session includes a high-speed real-time demodulation processing algorithm running on the FPGA platform, enabling decoding of the RFID tag information of a single sub-band to be completed within a very short delay.

[0111] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, the method further includes: An asynchronous transmission mechanism is introduced in RFID read / write sessions in multiple sub-bands, so that the downlink excitation signals of different sub-bands are not aligned in timing, thus preventing traditional RFID tags from being excited. The asynchronous transmission mechanism is implemented through the following steps: Ensure that the downlink excitation signal of each sub-band RFID read / write session has random delay in timing, and that the command duration, idle time slot distribution, and tag clock offset between each RFID read / write session are different, so that the combined signal envelope cannot be interpreted as a legitimate command by traditional RFID tags.

[0112] Specifically, in some embodiments, the method also includes avoiding interference from traditional RFID tags, that is, avoiding interference from traditional RFID tags on read-write frequency division multiplexing tags. In actual applications, traditional tags are inevitably present in the reading range of high-speed parallel reading and writing devices. Since high-speed parallel reading and writing devices are specifically designed for parallel reading and writing of new frequency division multiplexing RFID tags, traditional tags should not participate in this process. Once excited, the backscattered signals of these traditional tags will exist in all frequency division multiplexing sub-bands, affecting the normal reading and writing of all sub-bands. Therefore, the high-speed parallel reading and writing device of the present invention needs to avoid exciting traditional tags.

[0113] The specific implementation is as follows: An asynchronous transmission mechanism is introduced in RFID read and write sessions of multiple sub-bands, so that the downlink excitation signals of different sub-bands are not aligned in timing to prevent traditional RFID tags from being excited.

[0114] Since traditional tags have a broadband frequency response, they aggregate the downlink power of each frequency band when decoding downlink commands and extract the envelope information of the aggregated signal for demodulation. If the downlink command signals of multiple sub-band sessions of high-speed parallel reading and writing devices are completely synchronized, Figure 7a To avoid interference of traditional RFID tags with high-speed parallel reading and writing equipment, one of the logic diagrams of frequency division multiplexing tags is shown. Figure 7b To avoid the interference of traditional RFID tags on high-speed parallel reading and writing devices, the second logic diagram of the frequency division multiplexing tag is as follows: Figure 7a As shown in the figure, the downlink power of each frequency band (band F1, band F2, band F3) in the synchronous logic will still have the envelope of the standard RFID downlink command after aggregation, so the traditional tag will decode the command and be incorrectly stimulated. On the contrary, if the downlink signals are transmitted asynchronously, the envelope after aggregation will show irregular changes, such as Figure 7b As shown in the figure, in asynchronous logic, due to the extremely strict power variation and timing requirements of the PIE signal of the RFID downlink command, this type of envelope will not be recognized as a legitimate command by traditional tags. In this case, the traditional tags will receive the excitation signal power from the high-speed parallel read / write device, but they will remain in a dormant state and will not backscatter.

[0115] Furthermore, the asynchronous transmission mechanism is implemented through the following steps: To maintain such an asynchronous delay, we ensure that the RFID sessions of each sub-band are independent of each other.

[0116] Ensure that the downlink excitation signal of each sub-band RFID read / write session has random delay in timing, and that the command duration, idle time slot distribution, and tag clock offset between each RFID read / write session are different, so that the combined signal envelope cannot be interpreted as a legitimate command by traditional RFID tags.

[0117] Due to differences in command duration, clock offsets between the tags reading and writing, and the distribution of idle time slots, these sessions naturally generate asynchronous downlink command signals. Signals across multiple sub-bands rarely align perfectly to form a valid command structure for traditional tags. Even if downlink command signals occasionally achieve perfect synchronization, these differences can cause them to lose synchronization within a short period of time, leading to asynchronous delays.

[0118] To avoid interference with traditional tags, the method provided in this embodiment introduces an asynchronous transmission mechanism within RFID read / write sessions across multiple sub-bands. This mechanism causes the downlink excitation signals from different sub-bands to be time-delayed, preventing traditional RFID tags from being excited. This asynchronous transmission mechanism is implemented by ensuring that the downlink excitation signals for each sub-band RFID read / write session have randomized timing delays, and that the command duration, idle time slot distribution, and tag clock offset vary between sessions, preventing the combined signal envelope from being interpreted as a legitimate command by traditional RFID tags. This effectively avoids interference with traditional tags and achieves stable multi-band reading.

[0119] According to a high-speed parallel reading and writing method for frequency division radio frequency identification provided by the present invention, the method further includes: Detects and ignores backscatter signals reflected by traditional RFID tags due to transient synchronization. Backscatter signals appear as identical RN16 response signals appearing simultaneously in multiple sub-bands. The RN16 response signal is a 16-bit random number. Detects and ignores backscatter signals reflected by traditional RFID tags due to transient synchronization, including: Monitor the synchronization of RN16 response signals in RFID read and write sessions in each sub-band. If the same RN16 response signal appears simultaneously in multiple sub-bands, the RN16 response signal is identified as a backscattered signal reflected by a traditional RFID tag. Discards the backscattered signal reflected by traditional RFID tags.

[0120] Specifically, in some embodiments, despite the introduction of an asynchronous transmission mechanism to avoid interference with traditional tags, the high-speed parallel read / write device of the present invention may inevitably experience some brief signal synchronization during long-term operation. In this case, traditional tags will backscatter across all frequency bands, causing the same RN16 response signal to appear simultaneously in sessions across multiple sub-bands.

[0121] In order to better avoid interference from traditional tags in such situations, the method further includes: Detects and ignores backscattered signals reflected by conventional RFID tags due to short synchronization.

[0122] The backscatter signal appears as the same RN16 response signal in multiple sub-bands. The RN16 response signal is a 16-bit random number and is a key component of RFID systems, especially the EPCglobal UHF Class-1 Gen-2 protocol. Its function and mechanism are as follows: RN16 (Random Number): A 16-bit random number generated by an RFID tag in response to a reader query. It serves as a temporary session identifier and is used for subsequent communication verification and anti-collision processing.

[0123] The workflow of RN16 is as follows: the reader sends a Query command; the inventory cycle is started, triggering the tags within the range to prepare to respond; the tag generates an RN16 signal: each activated tag generates a unique 16-bit random number (RN16) and sends it to the reader via backscatter; the reader sends an ACK command: the reader embeds the received RN16 into the ACK command and sends it back to the tag; the tag verifies RN16: the tag checks whether the RN16 in the ACK matches the one generated by itself: the tag verifies RN16: the tag checks whether the RN16 in the ACK matches the one generated by itself: if it matches, the tag sends the stored data such as the EPC; if it does not match, the tag remains silent to avoid data conflicts.

[0124] RN16 is the core mechanism for achieving efficient communication, anti-collision and security verification in RFID systems. It ensures reliable data interaction in multi-tag environments through dynamic random numbers and session management.

[0125] Exemplarily, the specific implementation process of detecting and ignoring the backscattered signal reflected by the traditional RFID tag due to short synchronization includes the following steps: First, the synchronization of the RN16 response signals in the RFID read and write sessions of each sub-band is monitored. If the same RN16 response signal appears simultaneously in multiple sub-bands, the RN16 response signal is determined to be a backscattered signal reflected by a traditional RFID tag; further, the backscattered signal reflected by the traditional RFID tag is discarded.

[0126] The method provided in this embodiment allows the reading and writing device to detect these RN16 response signals that appear simultaneously, and ignore these traditional tags that are activated by mistake, and not respond to the RN16 signals they send. This can better avoid interference from traditional tags and achieve stable multi-band reading.

[0127] Figure 8 The present invention provides a high-speed parallel read-write device for frequency division radio frequency identification, as shown in FIG. Figure 8As shown, the high-speed parallel read-write device 800 for frequency division radio frequency identification includes a digital up-converter DUC810, a digital down-converter DDC820, a power amplifier 830, a transmitting antenna 840, a receiving antenna 850 and a field programmable gate array FPGA real-time demodulation module 860; wherein, The digital up-converter DUC810 is used to combine the downlink excitation signals of the radio frequency identification (RFID) read / write sessions of multiple sub-bands into a composite signal; each of the RFID read / write sessions executes a complete product electronic code (EPC) read / write protocol process; The power amplifier 820 is used to amplify the composite signal and transmit the amplified composite signal to the frequency division multiplexing RFID tag through the transmitting antenna; the amplified composite signal is used to excite the frequency division multiplexing RFID tags of different sub-bands; The receiving antenna 830 is used to receive the multi-band backscattered signal reflected by the frequency division multiplexing RFID tag; The digital down converter DDC840 is used to separate the multi-band backscatter signals to obtain separated sub-band backscatter signals, and allocate the separated sub-band backscatter signals to independent RFID read / write sessions for demodulation processing; The FPGA real-time demodulation module 850 is used to perform real-time demodulation on the separated backscatter signals of each sub-frequency band on the FPGA platform to obtain demodulated data of each sub-frequency band.

[0128] Specifically, the high-speed parallel read / write device of frequency division radio frequency identification includes a digital up converter DUC, a digital down converter DDC, a power amplifier, a transmitting antenna, a receiving antenna and an FPGA real-time demodulation module.

[0129] The digital up-converter DUC810 is used to combine the downlink excitation signals of multiple sub-band RFID read / write sessions into a composite signal, where each RFID read / write session executes the complete EPC read / write protocol process. The power amplifier 830 is then used to amplify the composite signal and transmit the amplified composite signal to the frequency-division multiplexed RFID tag via the transmitting antenna 840. The amplified composite signal is used to excite the frequency-division multiplexed RFID tags in different sub-bands. Furthermore, the receiving antenna 850 is used to receive the multi-band backscattered signal reflected by the frequency-division multiplexed RFID tag. The digital down-converter DDC820 is used to separate the multi-band backscattered signal to obtain separated sub-band backscattered signals, and distribute the separated sub-band backscattered signals to independent RFID read / write sessions for demodulation processing. Furthermore, the FPGA real-time demodulation module 860 is used to demodulate the separated sub-band backscattered signals in real time on the FPGA platform to obtain demodulated data for each sub-band.

[0130] In the present invention, the reader / writer device combines the transmission signals of multiple read / write sessions through a digital up-converter (DUC), which is sent simultaneously at different frequencies to stimulate frequency-division multiplexed RFID tags in different sub-bands and send downlink commands to frequency-division multiplexed RFID tags in different sub-bands. After reflection, the uplink tag data in multiple different sub-bands is received by the reader / writer device and separated into multiple read / write sessions through a digital down-converter for independent processing. Each read / write session contains a high-speed real-time demodulation processing algorithm running on an FPGA platform, which enables decoding of a single sub-band RFID tag information within a very short delay. In this way, the read / write sessions of each sub-band in the frequency-division multiplexed RFID are separated and can run in parallel. At the same time, the processing logic of the standard RFID reader / writer can be unified and reused, ensuring the robustness of parallel read / write in the frequency-division multiplexed scenario. Moreover, a single reader / writer can perform multi-band flexible processing of RFID signals of multiple sub-segments, simplifying the system design complexity of the reader / writer.

[0131] The high-speed parallel reading and writing device for frequency division radio frequency identification provided by the present invention is described below. The high-speed parallel reading and writing device for frequency division radio frequency identification described below and the high-speed parallel reading and writing method for frequency division radio frequency identification described above can be referred to each other.

[0132] Figure 9 This is a schematic diagram of the structure of the high-speed parallel read / write device for frequency division radio frequency identification provided by the present invention. The high-speed parallel read / write device for frequency division radio frequency identification 900 is applied to a high-speed parallel read / write device for frequency division radio frequency identification. The high-speed parallel read / write device for frequency division radio frequency identification includes a digital up converter DUC, a digital down converter DDC, a power amplifier, a transmitting antenna, a receiving antenna, and an FPGA real-time demodulation module. The high-speed parallel read / write device for frequency division radio frequency identification 900 includes the following modules: The multi-band signal merging module 910 is configured to merge the downlink excitation signals of the RFID read / write sessions of multiple sub-bands into a composite signal through the digital up converter DUC; each of the RFID read / write sessions executes a complete EPC read / write protocol process; The transmitting module 920 is configured to amplify the composite signal through the power amplifier and transmit the amplified composite signal to the frequency division multiplexing RFID tag through the transmitting antenna; the amplified composite signal is used to excite the frequency division multiplexing RFID tags of different sub-bands; A receiving module 930 is configured to receive, through the receiving antenna, the multi-band backscattered signal reflected by the frequency division multiplexing RFID tag; The multi-band signal separation module 940 is configured to separate the multi-band backscatter signals through the digital down converter DDC to obtain separated backscatter signals of each sub-band, and assign the separated backscatter signals of each sub-band to independent RFID read / write sessions for demodulation processing; The real-time demodulation module 950 is used to perform real-time demodulation on the separated backscatter signals of each sub-band on the FPGA platform through the FPGA real-time demodulation module to obtain demodulated data of each sub-band.

[0133] The device provided in this embodiment is applied to a high-speed parallel reading and writing device for frequency division radio frequency identification. The reading and writing device includes a digital up converter DUC, a digital down converter DDC, a power amplifier, a transmitting antenna, a receiving antenna and an FPGA real-time demodulation module; the device includes: a multi-band signal merging module 910, which is used to merge the downlink excitation signals of the RFID reading and writing sessions of multiple sub-bands into a composite signal through the digital up converter DUC, wherein each RFID reading and writing session executes a complete EPC reading and writing protocol process; then, a sending module 920 is used to amplify the composite signal through the power amplifier, and transmit the amplified composite signal to the frequency division multiplexing RFID tag through the transmitting antenna. After amplification, The composite signal is used to excite the frequency-division multiplexing RFID tags of different sub-bands; further, the receiving module 930 is used to receive the multi-band backscatter signal reflected by the frequency-division multiplexing RFID tag through the receiving antenna, and the multi-band signal separation module 940 is used to separate the multi-band backscatter signal through the digital down converter DDC to obtain the separated sub-band backscatter signals, and distribute the separated sub-band backscatter signals to independent RFID read-write sessions for demodulation processing; further, the real-time demodulation module 950 is used to demodulate the separated sub-band backscatter signals in real time on the FPGA platform through the FPGA real-time demodulation module to obtain the demodulated data of each sub-band.

[0134] The high-speed parallel read / write device for frequency-division radio frequency identification (FDM) in the present invention includes a digital upconverter (DUC) and a digital downconverter (DDC). The read / write device uses the DUC to combine the transmission signals of multiple read / write sessions and simultaneously transmits them at different frequencies to stimulate FDM RFID tags in different sub-bands and send downlink commands to FDM RFID tags in different sub-bands. After reflection, the uplink tag data from multiple different sub-bands is received by the read / write device and separated into multiple read / write sessions for independent processing by the digital downconverter. Each read / write session includes a high-speed real-time demodulation processing algorithm running on an FPGA platform, enabling decoding of RFID tag information in a single sub-band within a very short delay. In this way, the read / write sessions of each sub-band in the FDM RFID are separated and can run in parallel, while the processing logic of a standard RFID reader / writer can be uniformly reused, ensuring the robustness of parallel read / write in FDM scenarios. Furthermore, a single read / write device can perform multi-band flexible processing of RFID signals from multiple sub-segments, simplifying the system design complexity of the read / write device.

[0135] According to a high-speed parallel read-write device 900 for frequency division radio frequency identification provided by the present invention, the multi-band signal merging module 910 is specifically used for: Upsampling the downlink excitation signal of each sub-frequency band to obtain the upsampled downlink excitation signal of each sub-frequency band; The up-sampled downlink excitation signal of each sub-band is mixed with the corresponding sub-band carrier and then superimposed to form the composite signal.

[0136] According to a high-speed parallel read-write device 900 for frequency division radio frequency identification provided by the present invention, the sending module 920 is specifically configured to: Feeding back the amplified composite signal output by the power amplifier to the digital predistortion module through the directional coupler; The digital predistortion module performs digital predistortion processing and compensates for nonlinear effects based on a Volterra series model to eliminate mutual interference between multiple sub-frequency bands.

[0137] According to a high-speed parallel read-write device 900 for frequency division radio frequency identification provided by the present invention, the sending module 920 is further configured to: Analyzing the composite signal before and after amplification by the digital predistortion module, estimating a nonlinear model and calculating a coefficient matrix; An inverse function of the nonlinear model is calculated, and predistortion processing is performed on each input baseband signal based on the inverse function of the nonlinear model so that the predistorted signal generates inverse nonlinear compensation when passing through the power amplifier, thereby obtaining a target baseband signal after linear amplification.

[0138] According to a high-speed parallel read-write device 900 for frequency division radio frequency identification provided by the present invention, the multi-band signal separation module 940 is specifically used to: For the backscattered signals of each sub-frequency band, the backscattered signals of each sub-frequency band are mixed with the conjugate of the carrier of each sub-frequency band, and non-target frequency band signals other than each sub-frequency band in the multiple frequency bands are filtered out to obtain the processed scattered signals of each sub-frequency band; Down-sampling is performed on the processed scattered signals of each sub-frequency band to obtain the separated backscattered signals of each sub-frequency band.

[0139] According to a high-speed parallel read-write device 900 for frequency division radio frequency identification provided by the present invention, the real-time demodulation module 950 is specifically used for: For any separated sub-band backscatter signal, removing a DC component of the excitation carrier by sliding average based on the separated sub-band backscatter signal; A matched filter is used to match the preamble sequence contained in the data packet backscattered by the tag to achieve time synchronization of the data frame, and a phase-locked loop is used to perform fine-grained clock recovery. Performing channel estimation and equalization based on the preamble sequence, and optimizing division and square root operations in the channel estimation and equalization using a preset lookup table to map the reflection state to a fixed position in the in-phase orthogonal IQ domain; The target decoder extracts a bit stream transmitted by the tag, and determines the bit stream as the demodulated data of the sub-band.

[0140] According to the present invention, a high-speed parallel reading and writing device 900 for frequency division radio frequency identification is provided, wherein the device further comprises a traditional tag interference avoidance module; The traditional tag interference avoidance module is configured to: Introducing an asynchronous transmission mechanism in the RFID read / write sessions of the multiple sub-bands so that the downlink excitation signals of different sub-bands are not aligned in timing, thereby preventing traditional RFID tags from being excited; The asynchronous transmission mechanism is implemented by the following steps: Ensure that the downlink excitation signal of each sub-band RFID read / write session has random delay in timing, and that the command duration, idle time slot distribution, and tag clock offset between each RFID read / write session are different, so that the combined signal envelope cannot be interpreted as a legitimate command by traditional RFID tags.

[0141] According to a high-speed parallel reading and writing device 900 for frequency division radio frequency identification provided by the present invention, the device further includes an inter-sub-band interference avoidance module; The inter-sub-band interference avoidance module is configured to: Detecting and ignoring backscatter signals reflected by conventional RFID tags due to transient synchronization; wherein the backscatter signals appear as identical RN16 response signals simultaneously appearing in the multiple sub-bands, wherein the RN16 response signals are 16-bit random numbers; The inter-sub-band interference avoidance module is further configured to: Monitor the synchronization of the RN16 response signals in the RFID read / write sessions of each sub-band. If the same RN16 response signal appears simultaneously in multiple sub-bands, determine that the RN16 response signal is a backscattered signal reflected by a traditional RFID tag. The backscattered signal reflected by the conventional RFID tag is discarded.

[0142] Figure 10 An example of a physical structure diagram of an electronic device is shown below. Figure 10 As shown, the electronic device may include: a processor 1010, a communications interface 1020, a memory 1030, and a communication bus 1040, wherein the processor 1010, the communications interface 1020, and the memory 1030 communicate with each other via the communication bus 1040. The processor 1010 may call logic instructions in the memory 1030 to execute a high-speed parallel read and write method for frequency-division radio frequency identification. The method is applied to a high-speed parallel read and write device for frequency-division radio frequency identification; the high-speed parallel read and write device for frequency-division radio frequency identification includes a digital up converter (DUC), a digital down converter (DDC), a power amplifier, a transmitting antenna, a receiving antenna, and a field programmable gate array (FPGA) real-time demodulation module; the method includes: The downlink excitation signals of the radio frequency identification (RFID) read / write sessions of multiple sub-bands are combined into a composite signal through the digital up converter DUC; each of the RFID read / write sessions executes a complete product electronic code (EPC) read / write protocol process; amplifying the composite signal by the power amplifier, and transmitting the amplified composite signal to the frequency division multiplexing RFID tag through the transmitting antenna; the amplified composite signal is used to stimulate the frequency division multiplexing RFID tags of different sub-bands; receiving, via the receiving antenna, a multi-band backscattered signal reflected by the frequency-division multiplexed RFID tag; Separating the multi-band backscatter signals by the digital down converter DDC to obtain separated backscatter signals of each sub-band, and allocating the separated backscatter signals of each sub-band to an independent RFID read / write session for demodulation processing; The separated backscatter signals of each sub-frequency band are demodulated in real time on the FPGA platform by the FPGA real-time demodulation module to obtain demodulated data of each sub-frequency band.

[0143] Furthermore, the logic instructions in the aforementioned memory 1030 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0144] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the high-speed parallel reading and writing method for frequency-division radio frequency identification provided by the above methods. The method is applied to a high-speed parallel reading and writing device for frequency-division radio frequency identification; the high-speed parallel reading and writing device for frequency-division radio frequency identification includes a digital up converter DUC, a digital down converter DDC, a power amplifier, a transmitting antenna, a receiving antenna, and a field programmable gate array (FPGA) real-time demodulation module; the method includes: The downlink excitation signals of the radio frequency identification (RFID) read / write sessions of multiple sub-bands are combined into a composite signal through the digital up converter DUC; each of the RFID read / write sessions executes a complete product electronic code (EPC) read / write protocol process; amplifying the composite signal by the power amplifier, and transmitting the amplified composite signal to the frequency division multiplexing RFID tag through the transmitting antenna; the amplified composite signal is used to stimulate the frequency division multiplexing RFID tags of different sub-bands; receiving, via the receiving antenna, a multi-band backscattered signal reflected by the frequency-division multiplexed RFID tag; Separating the multi-band backscatter signals by the digital down converter DDC to obtain separated backscatter signals of each sub-band, and allocating the separated backscatter signals of each sub-band to an independent RFID read / write session for demodulation processing; The separated backscatter signals of each sub-frequency band are demodulated in real time on the FPGA platform by the FPGA real-time demodulation module to obtain demodulated data of each sub-frequency band.

[0145] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the high-speed parallel read / write method for frequency-division radio frequency identification provided by the above methods is implemented. The method is applied to a high-speed parallel read / write device for frequency-division radio frequency identification; the high-speed parallel read / write device for frequency-division radio frequency identification includes a digital up converter (DUC), a digital down converter (DDC), a power amplifier, a transmitting antenna, a receiving antenna, and a field programmable gate array (FPGA) real-time demodulation module; the method includes: The downlink excitation signals of the radio frequency identification (RFID) read / write sessions of multiple sub-bands are combined into a composite signal through the digital up converter DUC; each of the RFID read / write sessions executes a complete product electronic code (EPC) read / write protocol process; amplifying the composite signal by the power amplifier, and transmitting the amplified composite signal to the frequency division multiplexing RFID tag through the transmitting antenna; the amplified composite signal is used to stimulate the frequency division multiplexing RFID tags of different sub-bands; receiving, via the receiving antenna, a multi-band backscattered signal reflected by the frequency-division multiplexed RFID tag; Separating the multi-band backscatter signals by the digital down converter DDC to obtain separated backscatter signals of each sub-band, and allocating the separated backscatter signals of each sub-band to an independent RFID read / write session for demodulation processing; The separated backscatter signals of each sub-frequency band are demodulated in real time on the FPGA platform by the FPGA real-time demodulation module to obtain demodulated data of each sub-frequency band.

[0146] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0147] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A high-speed parallel reading and writing method for frequency division radio frequency identification, characterized in that: A high-speed parallel read / write device for frequency division radio frequency identification; the high-speed parallel read / write device for frequency division radio frequency identification includes a digital up converter DUC, a digital down converter DDC, a power amplifier, a transmitting antenna, a receiving antenna, and a field programmable gate array (FPGA) real-time demodulation module; the method includes: The downlink excitation signals of the radio frequency identification (RFID) read / write sessions of multiple sub-bands are combined into a composite signal through the digital up converter DUC; each of the RFID read / write sessions executes a complete product electronic code (EPC) read / write protocol process; amplifying the composite signal by the power amplifier, and transmitting the amplified composite signal to the frequency division multiplexing RFID tag through the transmitting antenna; the amplified composite signal is used to stimulate the frequency division multiplexing RFID tags of different sub-bands; receiving, via the receiving antenna, a multi-band backscattered signal reflected by the frequency-division multiplexed RFID tag; Separating the multi-band backscatter signals by the digital down converter DDC to obtain separated backscatter signals of each sub-band, and allocating the separated backscatter signals of each sub-band to an independent RFID read / write session for demodulation processing; The separated backscatter signals of each sub-frequency band are demodulated in real time on the FPGA platform by the FPGA real-time demodulation module to obtain demodulated data of each sub-frequency band.

2. The high-speed parallel reading and writing method for frequency division radio frequency identification according to claim 1, characterized in that: The step of combining downlink excitation signals of RFID read / write sessions of multiple sub-bands into a composite signal by the digital up converter DUC includes: Upsampling the downlink excitation signal of each sub-frequency band to obtain the upsampled downlink excitation signal of each sub-frequency band; The up-sampled downlink excitation signal of each sub-band is mixed with the corresponding sub-band carrier and then superimposed to form the composite signal.

3. The high-speed parallel reading and writing method for frequency division radio frequency identification according to claim 1, characterized in that: The high-speed parallel read-write device for frequency division radio frequency identification further includes a digital pre-distortion module and a directional coupler; the amplification of the composite signal by the power amplifier further includes: Feeding back the amplified composite signal output by the power amplifier to the digital predistortion module through the directional coupler; The digital predistortion module performs digital predistortion processing and compensates for nonlinear effects based on a Volterra series model to eliminate mutual interference between multiple sub-frequency bands.

4. The high-speed parallel reading and writing method for frequency division radio frequency identification according to claim 3, characterized in that: The digital predistortion module is used to perform digital predistortion processing, and nonlinear effects are compensated based on a Volterra series model, including: Analyzing the composite signal before and after amplification by the digital predistortion module, estimating a nonlinear model and calculating a coefficient matrix; An inverse function of the nonlinear model is calculated, and predistortion processing is performed on each input baseband signal based on the inverse function of the nonlinear model so that the predistorted signal generates inverse nonlinear compensation when passing through the power amplifier, thereby obtaining a target baseband signal after linear amplification.

5. The high-speed parallel reading and writing method for frequency division radio frequency identification according to claim 1, characterized in that: The step of separating the multi-band backscatter signals by the digital down converter DDC to obtain separated backscatter signals of each sub-band includes: For the backscattered signals of each sub-frequency band, the backscattered signals of each sub-frequency band are mixed with the conjugate of the carrier of each sub-frequency band, and non-target frequency band signals other than each sub-frequency band in the multiple frequency bands are filtered out to obtain the processed scattered signals of each sub-frequency band; Down-sampling is performed on the processed scattered signals of each sub-frequency band to obtain the separated backscattered signals of each sub-frequency band.

6. The high-speed parallel reading and writing method for frequency division radio frequency identification according to claim 1, characterized in that: The step of demodulating the separated backscattered signals of each sub-frequency band in real time on the FPGA platform to obtain demodulated data of each sub-frequency band includes: For any separated sub-band backscatter signal, removing a DC component of the excitation carrier by sliding average based on the separated sub-band backscatter signal; A matched filter is used to match the preamble sequence contained in the data packet backscattered by the tag to achieve time synchronization of the data frame, and a phase-locked loop is used to perform fine-grained clock recovery. Performing channel estimation and equalization based on the preamble sequence, and optimizing division and square root operations in the channel estimation and equalization using a preset lookup table to map the reflection state to a fixed position in the in-phase orthogonal IQ domain; The target decoder extracts a bit stream transmitted by the tag, and determines the bit stream as the demodulated data of the sub-band.

7. The high-speed parallel reading and writing method for frequency division radio frequency identification according to claim 1, characterized in that: The method further comprises: Introducing an asynchronous transmission mechanism in the RFID read / write sessions of the multiple sub-bands so that the downlink excitation signals of different sub-bands are not aligned in timing, thereby preventing traditional RFID tags from being excited; The asynchronous transmission mechanism is implemented by the following steps: Ensure that the downlink excitation signal of each sub-band RFID read / write session has random delay in timing, and that the command duration, idle time slot distribution, and tag clock offset between each RFID read / write session are different, so that the combined signal envelope cannot be interpreted as a legitimate command by traditional RFID tags.

8. The high-speed parallel reading and writing method for frequency division radio frequency identification according to claim 1, characterized in that: The method further comprises: Detecting and ignoring backscatter signals reflected by conventional RFID tags due to transient synchronization; wherein the backscatter signals appear as identical RN16 response signals simultaneously appearing in the multiple sub-bands, wherein the RN16 response signals are 16-bit random numbers; The method of detecting and ignoring backscattered signals reflected by conventional RFID tags due to short synchronization may include: Monitor the synchronization of the RN16 response signals in the RFID read / write sessions of each sub-band. If the same RN16 response signal appears simultaneously in multiple sub-bands, determine that the RN16 response signal is a backscattered signal reflected by a traditional RFID tag. The backscattered signal reflected by the conventional RFID tag is discarded.

9. A high-speed parallel read-write device for frequency division radio frequency identification, characterized in that: The high-speed parallel read-write device of the frequency division radio frequency identification includes a digital up converter DUC, a digital down converter DDC, a power amplifier, a transmitting antenna, a receiving antenna and an FPGA real-time demodulation module; wherein, The digital up converter DUC is used to combine the downlink excitation signals of the RFID read / write sessions of multiple sub-bands into a composite signal; each of the RFID read / write sessions executes a complete EPC read / write protocol process; The power amplifier is used to amplify the composite signal and transmit the amplified composite signal to the frequency division multiplexing RFID tag through the transmitting antenna; the amplified composite signal is used to excite the frequency division multiplexing RFID tags of different sub-bands; The receiving antenna is used to receive the multi-band backscattered signal reflected by the frequency division multiplexing RFID tag; The digital down converter DDC is used to separate the multi-band backscatter signals to obtain separated backscatter signals of each sub-band, and allocate the separated backscatter signals of each sub-band to an independent RFID read / write session for demodulation processing; The FPGA real-time demodulation module is used to perform real-time demodulation on the separated backscatter signals of each sub-frequency band on the FPGA platform to obtain demodulated data of each sub-frequency band.

10. A high-speed parallel read-write device for frequency division radio frequency identification, characterized in that: A high-speed parallel read / write device for frequency division radio frequency identification (FDI); the device comprises a digital up-converter (DUC), a digital down-converter (DDC), a power amplifier, a transmitting antenna, a receiving antenna, and a field programmable gate array (FPGA) real-time demodulation module; the device comprises: A multi-band signal merging module is used to merge the downlink excitation signals of multiple sub-band radio frequency identification (RFID) read / write sessions into a composite signal through the digital up converter (DUC); each RFID read / write session executes a complete product electronic code (EPC) read / write protocol process; a transmitting module, configured to amplify the composite signal through the power amplifier and transmit the amplified composite signal to the frequency-division multiplexing RFID tag through the transmitting antenna; the amplified composite signal is used to excite the frequency-division multiplexing RFID tags of different sub-bands; a receiving module, configured to receive, through the receiving antenna, a multi-band backscattered signal reflected by the frequency-division multiplexed RFID tag; A multi-band signal separation module is used to separate the multi-band backscatter signals through the digital down converter DDC to obtain separated backscatter signals of each sub-band, and allocate the separated backscatter signals of each sub-band to an independent RFID read / write session for demodulation processing; The real-time demodulation module is used to perform real-time demodulation on the separated backscatter signals of each sub-frequency band on the FPGA platform through the FPGA real-time demodulation module to obtain demodulated data of each sub-frequency band.

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