High-integration-level multi-valued tape reading SOC chip architecture and tape reading method
Through the highly integrated SOC chip architecture and dynamic voltage and frequency adjustment technology, the problems of reduced signal-to-noise ratio and high power consumption in multi-value storage systems are solved, and efficient and secure tape data reading and storage are achieved.
Patent Information
- Application Number
- CN202510731061.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-05-26
- Filing Date
- 2025-06-03
- Publication Date
- 2025-09-05
Smart Images
Figure CN120600057A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of magnetic tape storage technology, and in particular to a highly integrated multi-value magnetic tape reading SOC chip architecture and a magnetic tape reading method. Background Art
[0002] As data storage demands continue to grow, magnetic tape storage technology continues to attract attention due to its high capacity, low cost, and long-term storage capabilities. To further increase magnetic tape storage density, multi-valued storage technology has been introduced. By encoding multiple bits of information into a single magnetic domain, storage capacity can be significantly increased. However, multi-valued storage technology also places higher demands on the design of read channel chips. To address the issues of reduced signal-to-noise ratio and increased intersymbol interference associated with multi-valued storage, read channel chips must integrate more complex functional modules, such as high-speed analog-to-digital converters, adaptive equalizers, and efficient error correction coding modules. Traditional tape read systems typically use discrete chips to implement different functional modules, such as analog-to-digital converters, equalizers, decoders, and controllers. In recent years, with advances in semiconductor technology, system-on-chip (SoC) design has gradually become an effective solution for complex electronic system integration. By integrating multiple functional modules onto a single chip, SoCs can significantly reduce system size, power consumption, and cost, while improving performance and reliability.
[0003] Existing related technologies include:
[0004] (1) Discrete chip design
[0005] Discrete chip design is a design approach that distributes different functional modules or circuit units across multiple independent chips, with each chip responsible for a specific task or function. This design approach is typically suitable for scenarios requiring high system performance and flexibility. For example, in high-performance computing, embedded systems, or certain prototyping applications, discrete design allows developers to select and optimize independent chips for each functional module to meet specific requirements. Common discrete chip types for tape reading include read channel chips, controller chips, cache chips, and error detection and correction chips.
[0006] (2) Multi-value tape reading implemented by FPGA
[0007] A field-programmable gate array (FPGA) is a chip that can be programmed to perform various logic functions. Using FPGAs for multi-valued tape reading allows developers to flexibly configure internal logic units to implement signal reading, decoding, and data processing functions. The logic design can be modified at any time during development to accommodate different tape formats and protocols.
[0008] A shortcoming of existing technologies is that discrete chip design, a design approach that distributes different functional modules across multiple independent chips, also has some significant drawbacks. In a discrete design, multiple independent chips must work together through complex interfaces and interconnections. This not only increases the design difficulty but also makes the system debugging and testing process more cumbersome. Issues with timing synchronization, signal transmission quality, and compatibility between chips can lead to reduced system stability and performance. Furthermore, power consumption and thermal management are more prominent issues. The high power consumption and heat dissipation requirements of multiple independent chips can lead to higher overall system power consumption.
[0009] When implementing multi-value tape reading, FPGAs consume higher power than highly integrated SoC chips for equivalent functionality due to their internal logic resources and structural characteristics. In power-critical portable devices or systems requiring long-duration operation, high power consumption shortens battery life and increases cooling costs. Summary of the Invention
[0010] The purpose of the present invention is to overcome the deficiencies of the prior art. To achieve the above purpose, a highly integrated multi-value tape reading SOC chip architecture and a tape reading method are adopted to solve the problems raised in the above background technology.
[0011] A highly integrated multi-value tape reading SOC chip architecture, including a multi-value reading module, a data error correction module, a data compression module, a data encryption module, an adaptive equalizer, an interface module, and a dynamic voltage and frequency adjustment module;
[0012] The multi-value reading module is used to convert the multi-value encoded analog signal in the magnetic tape into a digital signal;
[0013] The data error correction module is used to detect and repair data errors through an error correction algorithm;
[0014] The data compression module is used to compress the error-corrected data to reduce storage space occupation;
[0015] The data encryption module is used to encrypt the compressed data based on an encryption algorithm;
[0016] The interface module is used to transmit the processed data to an external device;
[0017] The dynamic voltage and frequency adjustment module is used to dynamically adjust the voltage and frequency of the core module according to the system load to reduce power consumption.
[0018] As a further solution of the present invention: the multi-value reading module is composed of an analog front end, a high-speed analog-to-digital converter, an adaptive equalizer and a signal decoding module;
[0019] The analog front end is used to simulate the data in the tape into analog signals and then store them;
[0020] The high-speed analog-to-digital converter is used to convert the analog signal into a digital signal;
[0021] The adaptive equalizer is used to adjust the filter coefficients in real time and compensate for signal distortion;
[0022] The signal decoding module is used for multi-value encoding and resolves the equalized digital signal into binary data to improve storage density and reading accuracy.
[0023] As a further solution of the present invention: the data input end of the data error correction module is connected to the data output end of the multi-value reading module.
[0024] As a further solution of the present invention: the chip architecture further includes an AHB bus and an APB bus, and the AHB bus and the APB bus adopt a two-level architecture;
[0025] The AHB bus is connected to the CPU, cache, memory, and high-speed peripheral modules;
[0026] The APB bus is connected to the low-speed peripheral module and the control module through the AHB2APB bridge module.
[0027] As a further solution of the present invention: the AHB2APB bridge module adopts AHB and APB protocol conversion to support data interaction between the high-speed peripheral module and the low-speed peripheral module.
[0028] As a further solution of the present invention: the interface module adopts USB and PCIe transmission protocols to transmit the processed data to an external device.
[0029] As a further solution of the present invention: the chip architecture also includes a power management unit for turning off the power of non-critical modules in standby mode, or providing sufficient power when reading data.
[0030] The technical solution of the second aspect further provides a tape reading method using a highly integrated multi-value tape reading SOC chip architecture as described in any one of the above items, comprising the following steps:
[0031] S1, through the analog front end and high-speed analog-to-digital converter of the multi-value reading module, the multi-value encoded analog signal in the tape is converted into a digital signal, thereby improving the storage density and reading accuracy;
[0032] S2, temporarily storing the converted digital signal in a cache module to balance the difference in reading and processing speeds and prevent data loss;
[0033] S3. Use the data error correction module to detect and repair data errors based on the error correction algorithm to ensure data accuracy and completeness;
[0034] S4. Compress and encrypt the error-corrected data through the data compression module and transmit it to the external device through the interface module.
[0035] As a further solution of the present invention: the specific steps in step S1 include:
[0036] First, the received signal is sampled and quantized, the analog signal is converted into a digital signal and then transmitted to the data error correction module;
[0037] Then, based on the adaptive algorithm, the current error signal is calculated, that is, the difference between the actual received signal and the expected signal;
[0038] Finally, the parameters of the equalizer are adjusted according to the error signal to make the output of the equalizer closer to the desired signal.
[0039] As a further solution of the present invention: when the system is in standby or idle state, the dynamic voltage and frequency adjustment module automatically reduces the frequency and voltage of the chip to minimize energy consumption; at the same time, only the control and monitoring functions are maintained to reduce the power consumption of the chip to the lowest level.
[0040] Compared with the prior art, the present invention has the following technical effects:
[0041] The above technical solution achieves efficient conversion of tape analog signals to digital signals through a multi-value read module (integrating an analog front end, a high-speed ADC, an adaptive equalizer, and a decoder), supporting multi-value encoding to improve storage density. A two-level bus architecture (AHB and APB) coordinates data interaction between high-speed and low-speed modules, and ensures data integrity and security through data error correction, compression, and encryption modules. A dynamic voltage and frequency scaling module (DVFS) and a power management unit (PMU) are also introduced to dynamically optimize power consumption. Multi-value encoding and adaptive equalization technologies significantly improve tape storage density and signal reading accuracy. Error correction, compression, and encryption modules are used to ensure data reliability and security throughout the entire process. A modular design based on the AHB / APB bus improves system processing efficiency and compatibility. DVFS and PMU technologies effectively reduce chip power consumption, extend device battery life, and meet the needs of modern storage with high integration and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings:
[0043] Figure 1 This is a schematic diagram of the SOC chip architecture of the embodiment disclosed in this application;
[0044] Figure 2 This is a schematic structural diagram of a multi-value reading module according to an embodiment disclosed in this application;
[0045] Figure 3 This is a working principle diagram of the adaptive equalizer according to the embodiment disclosed in this application;
[0046] Figure 4 This is a flowchart of the dynamic voltage and frequency adjustment module according to the embodiment disclosed in this application. DETAILED DESCRIPTION
[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0048] Please refer to Figure 1 In an embodiment of the present invention, a highly integrated multi-value tape reading SOC chip architecture includes a multi-value reading module, a data error correction module, a data compression module, a data encryption module, an adaptive equalizer, an interface module, and a dynamic voltage and frequency adjustment module;
[0049] The multi-value reading module is used to convert the multi-value encoded analog signal in the magnetic tape into a digital signal;
[0050] The data error correction module is used to detect and repair data errors through an error correction algorithm;
[0051] The data compression module is used to compress the error-corrected data to reduce storage space occupation;
[0052] The data encryption module is used to encrypt the compressed data based on an encryption algorithm;
[0053] The interface module is used to transmit the processed data to an external device;
[0054] The dynamic voltage and frequency adjustment module is used to dynamically adjust the voltage and frequency of the core module according to the system load to reduce power consumption.
[0055] like Figure 1As shown in the figure, black arrows indicate data flow. Its structure primarily consists of a CPU, DMA, memory, data encryption module, data compression module, data error correction module, AHB bus, APB bus, AHB2APB module, interface module, and channel read module. The first-layer AHB bus connects to the CPU, cache, DMA, memory, data encryption module, data compression module, and control module. The second-layer APB bus, connected via the AHB2APB bridge module, primarily connects to the low-speed interface module, power management unit (PMU), control module, and multi-value read module.
[0056] In this embodiment, the multi-value reading module is composed of an analog front end, a high-speed analog-to-digital converter, an adaptive equalizer, and a signal decoding module;
[0057] The analog front end is used to simulate the data in the tape into analog signals and then store them;
[0058] The high-speed analog-to-digital converter is used to convert the analog signal into a digital signal;
[0059] The adaptive equalizer is used to adjust the filter coefficients in real time and compensate for signal distortion;
[0060] The signal decoding module is used for multi-value encoding and resolves the equalized digital signal into binary data to improve storage density and reading accuracy.
[0061] In a specific embodiment, Figure 2 As shown in the figure, the multi-value reading module integrates an analog front end, a high-speed analog-to-digital converter, an adaptive equalizer, an encoder, etc. to achieve efficient conversion from tape signals to digital data.
[0062] like Figure 3 The figure shows the working principle of the adaptive equalizer. First, a multi-value read head senses changes in the magnetic field of the tape. These changes represent different data bits on the tape. In multi-value storage, each magnetic domain may contain multiple bits of information, so the signal sensed by the head is typically an analog signal. This analog signal is gain-controlled by an amplification module to ensure that the signal amplitude is suitable for subsequent processing. Because multi-value storage signals are susceptible to noise and interference, the signal is then filtered and optimized by an adaptive equalizer to eliminate intersymbol interference and other environmental noise, thereby optimizing signal quality. The analog signal is then passed to a high-speed analog-to-digital converter, which converts it into a digital signal for use by subsequent processing modules. The digital signal is decoded by a signal decoding module and converted into specific digital data. To further improve signal reliability, the decoded data is error-checked and corrected by a data error correction module to ensure data integrity.
[0063] During signal transmission, non-ideal characteristics of the transmission medium, such as uneven magnetic powder in the tape and noise interference in the transmission line, can cause signal distortion, primarily manifesting as amplitude attenuation, phase shift, and intersymbol interference. For example, in tape storage, differences in magnetic powder density at different locations can cause varying signal amplitudes when reading, potentially interfering between adjacent data bits and causing signal waveform distortion. An adaptive equalizer, a device that automatically adjusts parameters based on signal transmission conditions to compensate for signal distortion, is widely used in fields such as tape reading and writing.
[0064] The adaptive equalizer first samples and quantizes the received signal, converting the analog signal into a digital signal before feeding it into the digital signal processing module. The adaptive algorithm then calculates the current error signal—the difference between the actual received signal and the desired signal. The equalizer parameters, such as the filter coefficients, are then adjusted based on the error signal to bring the equalizer output closer to the desired signal. This process repeats continuously as the signal continues to transmit, with the equalizer constantly monitoring and adjusting to adapt to real-time signal changes.
[0065] In this embodiment, the data input terminal of the data error correction module is connected to the data output terminal of the multi-value reading module.
[0066] In this embodiment, the chip architecture further includes an AHB bus and an APB bus, and the AHB bus and the APB bus adopt a two-level architecture;
[0067] The AHB bus is connected to the CPU, cache, memory, and high-speed peripheral modules;
[0068] The APB bus is connected to the low-speed peripheral module and the control module through the AHB2APB bridge module.
[0069] In this embodiment, the AHB2APB bridge module uses AHB and APB protocol conversion to support data interaction between the high-speed peripheral module and the low-speed peripheral module.
[0070] In this embodiment, the interface module uses USB and PCIe transmission protocols to transmit processed data to external devices.
[0071] In a specific implementation, a two-level bus structure of AHB and APB is adopted in the SoC architecture design, and an AHB2APB bridge module is used to achieve efficient connection and communication between high-performance modules and low-speed peripheral modules.
[0072] As the core of high-performance data transmission, the AHB bus connects modules such as the CPU, data error correction module, data encryption module, data compression module, cache, memory, and high-speed interface.
[0073] Among them, the CPU serves as the main control core, responsible for executing instructions and coordinating various operations of the system;
[0074] DMA is responsible for exchanging data directly between the memory and peripherals; the data error correction module detects and corrects errors in the read data to ensure data integrity; the data encryption module ensures data security; the data compression module improves storage efficiency through compression technology; the high-speed interface provides a high-speed data transmission channel for external devices, while the cache and memory are used to alleviate data transmission bottlenecks and store intermediate data, respectively.
[0075] In this embodiment, the chip architecture further includes a power management unit (PMU) for shutting down the power supply of non-critical modules in standby mode or providing sufficient power when data is being read.
[0076] On the other hand, the APB bus focuses on the communication of low-speed and control modules, connecting low-speed interfaces, control modules, multi-value reading modules and power modules.
[0077] The low-speed interface is responsible for communicating with external devices such as UART and I2C. The control module manages the SoC's operating status and module coordination. The multi-value read module reads multi-value signals from tape media and performs preliminary processing. The power module dynamically adjusts voltage and power consumption to achieve a low-power operating mode. The AHB2APB bridge module enables protocol conversion and data exchange between the AHB and APB, efficiently allocating high-performance tasks and low-speed control tasks. This improves system performance while reducing power consumption, ensuring the modularity and efficient operation of the entire SoC architecture.
[0078] In a specific embodiment, SOC low power consumption design
[0079] Low power design is one of the key technologies that are indispensable in highly integrated multi-value tape reading SoC chips. By adding dynamic voltage and frequency scaling and power management unit technology to the power module, the chip can intelligently adjust power consumption under different workloads and states, thereby significantly reducing energy consumption. While ensuring system performance, it effectively extends the battery life of the device and meets the needs of modern data storage systems for long-term operation and high efficiency. Dynamic Voltage and Frequency Scaling (DVFS) technology automatically adjusts voltage and frequency according to performance requirements under different workloads. Figure 4 As shown in the figure, when the system is in standby or idle state, DVFS automatically reduces the chip's frequency and voltage to minimize energy consumption. At this time, the chip's power consumption is minimized, maintaining only necessary control and monitoring functions. When the chip enters tape data reading mode, DVFS increases the chip's frequency and voltage to ensure that data processing and decoding tasks are completed efficiently without compromising performance.
[0080] The Power Management Unit (PMU) manages overall system power management, intelligently allocating power and optimizing power consumption based on different operating modes and load conditions. The PMU dynamically adjusts current output based on the needs of different modules, providing ample power to core modules during high-load data readout tasks and switching to low current output during standby to avoid unnecessary energy waste. When no tasks are being executed, the PMU automatically switches non-critical modules to sleep mode to minimize power consumption.
[0081] In this embodiment, the technical solution of the second aspect further provides a tape reading method using a highly integrated multi-value tape reading SOC chip architecture as described in any one of the above items, comprising the following steps:
[0082] S1, through the analog front end and high-speed analog-to-digital converter of the multi-value reading module, the multi-value encoded analog signal in the tape is converted into a digital signal, thereby improving the storage density and reading accuracy;
[0083] S2, temporarily storing the converted digital signal in a cache module to balance the difference in reading and processing speeds and prevent data loss;
[0084] S3. Use the data error correction module to detect and repair data errors based on the error correction algorithm to ensure data accuracy and completeness;
[0085] S4. Compress and encrypt the error-corrected data through the data compression module and transmit it to the external device through the interface module.
[0086] In this embodiment, the specific steps in step S1 include:
[0087] First, the received signal is sampled and quantized, the analog signal is converted into a digital signal and then transmitted to the data error correction module;
[0088] Then, based on the adaptive algorithm, the current error signal is calculated, that is, the difference between the actual received signal and the expected signal;
[0089] Finally, the parameters of the equalizer are adjusted according to the error signal to make the output of the equalizer closer to the desired signal.
[0090] In this embodiment, when the system is in standby or idle state, the dynamic voltage and frequency adjustment module automatically reduces the frequency and voltage of the chip to minimize energy consumption; at the same time, only the control and monitoring functions are maintained to reduce the power consumption of the chip to the lowest level.
[0091] The following is the working principle and working process of the embodiment disclosed in the present invention:
[0092] The SoC chip workflow begins with tape signal acquisition. First, the data on the tape is stored as analog signals. The read channel converts these analog signals into digital signals through an analog front-end and analog-to-digital conversion, supporting multi-value encoding to improve storage density and read accuracy. The converted digital signals are then stored in a cache module, which temporarily stores the data for subsequent processing and prevents data loss due to a mismatch between read and processing speeds. Next, the data enters the data error correction module, which uses advanced error correction technology to automatically detect and correct errors that may occur during the reading process, ensuring data accuracy and integrity. All data flow and module scheduling are managed by a controller, which coordinates the operations of various modules to ensure efficient system operation. After error correction, the data enters the data compression module, which reduces storage space usage and improves data transmission efficiency. If encryption is required, the data encryption module encrypts the compressed data using algorithms such as AES to ensure data security. Finally, the processed encrypted data is transmitted to an external device or storage system through an interface module. The interface module supports common transmission standards such as USB and PCIe, ensuring fast data transmission and compatibility.
[0093] Beneficial effects:
[0094] 1. By integrating multiple functional modules, the collaboration between modules is optimized, the delay of signal processing is reduced, and the accuracy and efficiency of data reading are improved.
[0095] 2. The integrated design significantly reduces the required external components and PCB area, reducing power consumption and production costs.
[0096] 3. By adding dynamic voltage and frequency adjustment and power management unit technology to the power module, the chip can intelligently adjust power consumption under different workloads and states, thereby significantly reducing energy consumption.
[0097] Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents, and all should be included within the scope of protection of the present invention.
Claims
1. A highly integrated multi-value tape reading SOC chip architecture, characterized in that: The chip architecture includes a multi-value reading module, a data error correction module, a data compression module, a data encryption module, an adaptive equalizer, an interface module, and a dynamic voltage and frequency adjustment module; The multi-value reading module is used to convert the multi-value encoded analog signal in the magnetic tape into a digital signal; The data error correction module is used to detect and repair data errors through an error correction algorithm; The data compression module is used to compress the error-corrected data to reduce storage space occupation; The data encryption module is used to encrypt the compressed data based on an encryption algorithm; The interface module is used to transmit the processed data to an external device; The dynamic voltage and frequency adjustment module is used to dynamically adjust the voltage and frequency of the core module according to the system load to reduce power consumption.
2. The highly integrated multi-value tape reading SOC chip architecture according to claim 1, characterized in that: The multi-value reading module is composed of an analog front end, a high-speed analog-to-digital converter, an adaptive equalizer and a signal decoding module; The analog front end is used to simulate the data in the tape into analog signals and then store them; The high-speed analog-to-digital converter is used to convert the analog signal into a digital signal; The adaptive equalizer is used to adjust the filter coefficients in real time and compensate for signal distortion; The signal decoding module is used for multi-value encoding and resolves the equalized digital signal into binary data to improve storage density and reading accuracy.
3. The highly integrated multi-value tape reading SOC chip architecture according to claim 1, characterized in that: The data input end of the data error correction module is connected to the data output end of the multi-value reading module.
4. The highly integrated multi-value tape reading SOC chip architecture according to claim 1, characterized in that: The chip architecture also includes an AHB bus and an APB bus, and the AHB bus and the APB bus adopt a two-level architecture; The AHB bus is connected to the CPU, cache, memory, and high-speed peripheral modules; The APB bus is connected to the low-speed peripheral module and the control module through the AHB2APB bridge module.
5. The highly integrated multi-value tape reading SOC chip architecture according to claim 4, characterized in that: The AHB2APB bridge module uses AHB and APB protocol conversion to support data interaction between high-speed peripheral modules and low-speed peripheral modules.
6. The highly integrated multi-value tape reading SOC chip architecture according to claim 5, characterized in that: The interface module adopts USB and PCIe transmission protocols to transmit processed data to external devices.
7. The highly integrated multi-value tape reading SOC chip architecture according to claim 1, characterized in that: The chip architecture also includes a power management unit for shutting down the power of non-critical modules in standby mode or providing sufficient power when reading data.
8. A tape reading method using a highly integrated multi-value tape reading SOC chip architecture according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1, through the analog front end and high-speed analog-to-digital converter of the multi-value reading module, the multi-value encoded analog signal in the tape is converted into a digital signal, thereby improving the storage density and reading accuracy; S2, temporarily storing the converted digital signal in a cache module to balance the difference in reading and processing speeds and prevent data loss; S3. Use the data error correction module to detect and repair data errors based on the error correction algorithm to ensure data accuracy and completeness; S4. Compress and encrypt the error-corrected data through the data compression module and transmit it to the external device through the interface module.
9. The tape reading method of the highly integrated multi-value tape reading SOC chip architecture according to claim 8, characterized in that: The specific steps in step S1 include: First, the received signal is sampled and quantized, the analog signal is converted into a digital signal and then transmitted to the data error correction module; Then, based on the adaptive algorithm, the current error signal is calculated, that is, the difference between the actual received signal and the expected signal; Finally, the parameters of the equalizer are adjusted according to the error signal to make the output of the equalizer closer to the desired signal.
10. The tape reading method of the highly integrated multi-value tape reading SOC chip architecture according to claim 8, characterized in that: When the system is in standby or idle state, the dynamic voltage and frequency adjustment module automatically reduces the frequency and voltage of the chip to minimize energy consumption; at the same time, it only maintains the control and monitoring functions to reduce the power consumption of the chip to the lowest level.