Control method of phase change memory and phase change memory

Abstract

The invention provides a control method of a phase change memory and the phase change memory. The method comprises the steps of obtaining the number of storage units; under the condition that the number of the storage units is smaller than a number threshold value, first reset operation is conducted on a first target storage unit in the multiple storage units, and the first reset operation comprises the steps that in a first time period, a first word line voltage is applied to a first word line coupled to the first target storage unit, and a second word line voltage is applied to a second word line coupled to the second target storage unit; applying a first bit line voltage and a first current to a first bit line coupled to the first target memory cell; in a second time period, a second word line voltage is applied to the first word line, a first bit line voltage and a first current are applied to the first bit line, and the second word line voltage is larger than the first word line voltage; in a third time period, a second word line voltage is applied to the first word line, a first bit line voltage and a second current are applied to the first bit line, and the second current is greater than the first current. Through the method, the overcharge current in the phase change memory can be reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a control method for a phase change memory and a phase change memory. Background Art

[0002] Phase-change memory includes a memory cell array, which includes multiple memory cells arranged in an array. In the prior art, resetting a target memory cell in the memory cell array typically occurs in two phases: a low wordline voltage is applied in the first phase, and a simultaneous increase in the wordline voltage and bitline current in the second phase. This simultaneous increase in wordline voltage and bitline current can result in excessive overcharge current.

[0003] Overcharge current can cause excessive heat, which in turn causes thermal crosstalk in the memory cell array, affecting the state of memory cells near the target memory cell, and at the same time degrading the cycle characteristics of the target memory cell, causing the target memory cell to fail faster.

[0004] Therefore, the excessive overcharge current in phase change memory is one of the problems that need to be solved urgently. Summary of the Invention

[0005] The present application proposes a control method for a phase change memory and a phase change memory to solve the technical problem of excessive overcharge current in the phase change memory in the prior art.

[0006] In a first aspect, embodiments of the present application provide a control method for a phase change memory, wherein the memory cell array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines, the method comprising:

[0007] Obtaining the number of the storage units;

[0008] When the number of the memory cells is less than a number threshold, performing a first reset operation on a first target memory cell among the plurality of memory cells, the first reset operation comprising: applying a first word line voltage to a first word line coupled to the first target memory cell, and applying a first bit line voltage and a first current to a first bit line coupled to the first target memory cell in a first time period;

[0009] In a second time period, a second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line, wherein the second word line voltage is greater than the first word line voltage;

[0010] In a third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and a second current are applied to the first bit line, where the second current is greater than the first current.

[0011] In some embodiments, the method further comprises:

[0012] When the number of the memory cells is greater than or equal to a number threshold, performing a second reset operation on a first target memory cell among the plurality of memory cells, the second reset operation comprising: applying the first word line voltage to the first word line, applying a second bit line voltage and the first current to the first bit line during the first time period, the second bit line voltage being greater than the first bit line voltage;

[0013] In the second time period, applying the second word line voltage to the first word line, and applying the first bit line voltage and the first current to the first bit line;

[0014] When it is determined that the first target memory cell is in a non-conducting state during the second time period, in the third time period, a third word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line to adjust the first target memory cell to a conducting state, and the third word line voltage is greater than the second word line voltage.

[0015] In some embodiments, after applying the second word line voltage to the first word line and applying the first bit line voltage and the first current to the first bit line, the method further includes:

[0016] When it is determined that the first target memory cell is in the on state during the second time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line during the third time period.

[0017] In some embodiments, the method further comprises:

[0018] When the number of the memory cells is greater than or equal to a number threshold, performing a third reset operation on a first target memory cell among the plurality of memory cells, the third reset operation comprising: applying the first word line voltage to the first word line, and applying a second bit line voltage and the first current to the first bit line during the first time period;

[0019] In a case where it is determined that the first target storage unit is in a conducting state during the first time period, detecting whether a line resistance of the first target storage unit is greater than a resistance threshold;

[0020] If it is determined that the line resistance of the first target memory cell is greater than a resistance threshold, in the second time period, applying a third word line voltage or the second word line voltage to the first word line, and applying the first bit line voltage and the first current to the first bit line;

[0021] In the third time period, the third word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

[0022] In some embodiments, after detecting whether the line resistance of the first target memory cell is greater than a resistance threshold, the method further includes:

[0023] When it is determined that the line resistance of the first target memory cell is less than or equal to a resistance threshold, applying the second word line voltage to the first word line and applying the first bit line voltage and the first current to the first bit line during the second time period;

[0024] In the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

[0025] In some embodiments, after detecting whether the line resistance of the first target memory cell is greater than a resistance threshold, the method further includes:

[0026] When it is determined that the line resistance of the first target memory cell is greater than a resistance threshold, determining a memory cell connected in series with the first target memory cell on the first word line as a second target memory cell;

[0027] When the third word line voltage is applied to the first word line, a bias voltage is applied to the second bit line coupled to the second target memory cell.

[0028] In some embodiments, after applying the first word line voltage to the first word line and applying the second bit line voltage and the first current to the first bit line, the method further includes:

[0029] When it is determined that the first target memory cell is in a non-conductive state during the first time period, the voltage applied to the first word line is set to 0, and the voltage and current applied to the first bit line are set to 0.

[0030] In some embodiments, the first word line voltage Vp1 is in the range of 0V<Vp1≤4V.

[0031] In some embodiments, the first current I1 is in a range of 20A≤I1≤80A.

[0032] In a second aspect, an embodiment of the present application provides a phase change memory, comprising:

[0033] A memory cell array comprising a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines;

[0034] The peripheral circuit coupled to the memory cell array is configured to control the memory cell array using the method described in any one of the above embodiments.

[0035] The technical solution of the present application can achieve the following beneficial effects: Based on the control method of the phase-change memory proposed in the embodiment of the present application, in the second time period, only the voltage of the first word line is changed, while the first current is maintained. In the third time period, only the current of the first word line is changed, while the voltage of the second word line is maintained. That is, the voltage and current are increased separately in different time periods, rather than increasing the voltage and current simultaneously. Therefore, the overcharge current from the second time period to the third time period is suppressed. In addition, in the first time period, a small first current is applied to the first word line, and the voltage is increased from the first word line voltage to the second word line voltage under the small first current, which can also suppress the overcharge current. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0037] Figure 1 A schematic flow chart of a control method for a phase change memory provided in an embodiment of the present application;

[0038] Figure 2 A schematic structural diagram of a phase change memory provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of a partial structure of a phase change memory provided in an embodiment of the present application;

[0040] Figure 4 A timing diagram of current and voltage provided in an embodiment of the present application;

[0041] Figure 5 A timing diagram of current and voltage provided in an embodiment of the present application;

[0042] Figure 6 A timing diagram of current and voltage provided in an embodiment of the present application;

[0043] Figure 7 A timing diagram of current and voltage provided in an embodiment of the present application;

[0044] Figure 8A timing diagram of current and voltage provided in an embodiment of the present application;

[0045] Figure 9 A timing diagram of current and voltage provided in an embodiment of the present application;

[0046] Figure 10 A timing diagram of current and voltage provided in an embodiment of the present application;

[0047] Figure 11 A timing diagram of current and voltage in a simulation experiment provided in an embodiment of the present application;

[0048] Figure 12 It is a timing diagram of current and voltage in the prior art;

[0049] Figure 13 This is a timing diagram of current and voltage in the prior art. DETAILED DESCRIPTION

[0050] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making any creative work are within the scope of protection of this application.

[0051] In the description of this application, it should be noted that, unless otherwise specified or limited, the term "and / or" herein is merely a description of an association relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. Furthermore, the character " / " herein, unless otherwise specified, generally indicates that the associated objects are in an "or" relationship.

[0052] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0053] The phase change memory includes a memory cell array, which includes a plurality of memory cells arranged in an array. In the prior art, there are two methods for performing a reset (RESET) operation on a target memory cell in the memory cell array. Method 1 can be found in Figure 12 As shown, it is divided into two stages. In the first stage, a small word line voltage is applied and a relatively large bit line current is applied. In the second stage, the word line voltage is increased and the relatively large bit line current is maintained. When the word line voltage suddenly increases, a large overcharge current will be generated. Method 2 can be referred to Figure 13 As shown, the process is divided into two phases. In the first phase, a relatively small wordline voltage and a relatively small bitline current are applied. In the second phase, the wordline voltage and bitline current are increased simultaneously. Due to the simultaneous increase in wordline voltage and bitline current, a large overcharge current is generated. The large overcharge current causes excessive heat, which in turn causes thermal crosstalk in the memory cell array, affecting the state of memory cells near the target memory cell and degrading the cycling characteristics of the target memory cell, causing the target memory cell to fail more quickly.

[0054] In view of the technical problem in the prior art that a phase change memory reset process easily generates a large overcharge current, the embodiments of the present application provide a control method for a phase change memory and a phase change memory to overcome the above problem.

[0055] A control method for a phase change memory and a phase change memory provided by the present application are introduced below with reference to the accompanying drawings.

[0056] See Figure 1 As shown, an embodiment of the present application provides a control method for a phase change memory, wherein the phase change memory includes a memory cell array, wherein the memory cell array includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines. The method includes:

[0057] S101: Obtain the number of the storage units;

[0058] When the number of the storage units is less than a number threshold, performing a first reset operation on a first target storage unit among the plurality of storage units, the first reset operation comprising:

[0059] S102: In a first time period, applying a first word line voltage to a first word line coupled to the first target memory cell, and applying a first bit line voltage and a first current to a first bit line coupled to the first target memory cell;

[0060] S103: in a second time period, applying a second word line voltage to the first word line, and applying the first bit line voltage and the first current to the first bit line, wherein the second word line voltage is greater than the first word line voltage;

[0061] S104: In a third time period, applying the second word line voltage to the first word line, and applying the first bit line voltage and a second current to the first bit line, wherein the second current is greater than the first current.

[0062] The phase change memory and the control method of the phase change memory will be described below with reference to the accompanying drawings.

[0063] Please refer to Figure 2 The phase-change memory includes a memory cell array, the memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines; the phase-change memory also includes a peripheral circuit coupled to the memory cell array. The memory cell array also includes a bit line power supply terminal and a word line power supply terminal, the bit line power supply terminal being coupled to the plurality of bit lines, and the word line power supply terminal being coupled to the plurality of word lines.

[0064] The memory cell includes a phase change memory cell, wherein the phase change memory cell includes a phase change element and a gating element connected in series with the phase change element. The phase change element includes a phase change material (PCM) unit. The gating element includes a material having ovonic threshold switch (OTS) properties.

[0065] The voltage across the memory cell is equal to the voltage of the word line minus the voltage of the bit line. Current can be applied to the memory cell through the bit line. If the phase change element is in a crystalline state (low resistance state), the memory cell has a first threshold voltage (a relatively small value). When the voltage across the memory cell is greater than the first threshold voltage, the gating element is turned on, and the memory cell as a whole exhibits a low resistance state. If the phase change element is in an amorphous state (high resistance state), the memory cell has a second threshold voltage (a relatively large value). The second voltage threshold is greater than the first voltage threshold. When the voltage across the memory cell is greater than the second threshold voltage, the gating element is turned on.

[0066] The process of a phase-change element transitioning from a high-resistance amorphous state to a low-resistance crystalline state is called a set (SET) operation. Before the set operation, a suitable voltage must be applied to turn on the gating element in the memory cell. If the phase-change element is in the amorphous state, the applied voltage must be greater than a second voltage threshold. After the gating element is turned on, the voltage and current across the memory cell are adjusted to meet the conditions for the set operation.

[0067] The process of a phase-change element transitioning from a low-resistance crystalline state to a high-resistance amorphous state is called a reset (RESET) operation. Before the reset operation, a suitable voltage must be applied to turn on the gating element in the memory cell. If the phase-change element is in the crystalline state, the applied voltage must be greater than a first voltage threshold. After the gating element turns on, the voltage and current across the memory cell are adjusted to meet the reset operation conditions.

[0068] WL1, WL2, WL3, and WL4 represent four different word lines, and BL1, BL2, BL3, and BL4 represent four different bit lines. Memory cells are connected in series at the junctions between the word lines and the bit lines. One of the multiple memory cells is selected as the first target memory cell. The word line coupled to the first target memory cell is referred to as the first word line (WL2 in this embodiment), and the bit line coupled to the first target memory cell is referred to as the first bit line (BL2 in this embodiment). The voltage applied to the first word line is denoted as the word line voltage Vp, which includes: a first word line voltage Vp1, a second word line voltage Vp2, and a third word line voltage Vp3. The voltage applied to the first bit line is denoted as the bit line voltage Vn, which includes: a first bit line voltage Vn1 and a second bit line voltage Vn2. The voltage across the first target memory cell is equal to Vp-Vn. A portion of the memory cells and the first target memory cells are connected in series to the first bit line. These memory cells are referred to as second target memory cells, and the bit lines coupled to the second target memory cells are referred to as second bit lines (BL1, BL3, and BL4 in this embodiment). The voltage applied to the second bit line is referred to as bias voltage Vbias. The voltage across the second target memory cells is equal to Vp - Vbias.

[0069] Please refer to Figure 3, a wordline voltage Vp can be applied to the first wordline through the first transistor Q1 and the second transistor Q2. The third transistor Q3 acts as a switch, and the on / off of the third transistor Q3 can be controlled by a peripheral circuit (not shown). The fourth transistor Q4 acts as a switch to control the on / off of the first current source A1. The fifth transistor Q5 acts as a switch to control the on / off of the second current source A2. The first current source A1 and the second current source A2 form a current mirror structure. A bitline voltage Vn can be applied to the first bitline through the fourth transistor Q4 and the fifth transistor Q5. The fourth transistor Q4 is connected to the first current source A1, and the fifth transistor Q5 is connected to the second current source A2. The first current source A1 and the second current source A2 can apply current to the first target memory cell through the first bitline. Specifically, the first wordline voltage is applied through the first transistor Q1, the second wordline voltage is applied through the second transistor Q2, the first bitline voltage is applied through the fourth transistor Q4, the second bitline voltage is applied through the fifth transistor Q5, the first current is applied through the first current source A1, and the second current is applied through the second current source A2. It should be noted that in this embodiment, two current sources (a first current source A1 and a second current source A2) are used as an example for schematic illustration. Other numbers of current sources can be provided as needed. The present application does not limit the specific number of current sources. Multiple current sources are connected in parallel, and different current values ​​can be applied to the first target memory cell by controlling the on / off of different current sources. In this embodiment, two transistors (a first transistor Q1 and a second transistor Q2) are connected to the word line power supply terminal as an example for schematic illustration. Other numbers of transistors can be provided as needed for connection to the word line power supply terminal. The present application does not limit the specific number of transistors. By controlling the on / off of the transistors connected to the word line power supply terminal, different word line voltages can be applied to the first target memory cell. Other circuit elements with switching functions (e.g., micro switches, thyristors) can also be used to replace transistors Q1 to Q5.

[0070] Please refer to Figure 1 and Figure 2 , execute step S101 to obtain the number of the storage units.

[0071] After obtaining the number of storage units, a detection is made as to whether the number of storage units is less than a quantity threshold. If the number of storage units is less than the quantity threshold, a first reset operation is performed on a first target storage unit among the plurality of storage units. If the number of storage units is greater than or equal to the quantity threshold, a second reset operation or a third reset operation is performed on the first target storage unit among the plurality of storage units. The quantity threshold may be 30 Gb.

[0072] When the number of memory cells is less than the number threshold, it means that the scale of the memory cell array is small and the physical positions of the memory cells are slightly different. Due to the small difference in physical positions, the characteristics of the memory cells are similar, which is manifested as small differences in the voltage thresholds of the memory cells (the threshold voltages include: a first voltage threshold, a second voltage threshold, and a voltage threshold that satisfies a reset operation). Therefore, when the number of memory cells is less than the number threshold, the distribution range of the voltage threshold of the memory cell array is small, which is suitable for the first reset operation with a simple control method.

[0073] When the number of storage cells is greater than or equal to the number threshold, it means that the scale of the storage cell array is large and the physical positions of the various storage cells vary greatly. Due to the large differences in physical positions, the characteristics of the various storage cells vary greatly, which is manifested in that the voltage thresholds of the various storage cells (the threshold voltages include: a first voltage threshold, a second voltage threshold, and a voltage threshold that satisfies a reset operation) vary greatly. Therefore, when the number of storage cells is greater than or equal to the number threshold, the distribution range of the voltage threshold of the storage cell array is large, which is suitable for the second reset operation or the third reset operation with a complex control method.

[0074] In some embodiments, a first reset operation can also be performed when the number of storage units is less than 30Gb; when the number of storage units is in the range of 30Gb to 80Gb, one of the first reset operation, the second reset operation, and the third reset operation can be selected; when the number of storage units is greater than 80Gb, one of the second reset operation and the third reset operation can be selected.

[0075] Please refer to Figure 1 、 Figure 2 、 Figure 4 , execute step S102, and when the number of the storage cells is less than the number threshold, perform a first reset operation on the first target storage cell among the multiple storage cells, the first reset operation including: in a first time period, applying a first word line voltage to the first word line coupled to the first target storage cell, and applying a first bit line voltage and a first current to the first bit line coupled to the first target storage cell.

[0076] The time sequence is divided into a starting phase, a first time period, a second time period, a third time period and a termination phase. In the starting phase and the termination phase, the voltage applied to the first word line is set to 0, and the voltage and current applied to the first bit line are set to 0.

[0077] The current applied to the first bit line includes a first current I1 and a second current I2. The voltage applied to the first bit line includes a first bit line voltage Vn1. The voltage applied to the first word line includes a first word line voltage Vp1 and a second word line voltage Vp2.

[0078] Please refer to Figure 1 、 Figure 2 、 Figure 4 , executing step S103, in a second time period, applying a second word line voltage to the first word line, applying the first bit line voltage and the first current to the first bit line, wherein the second word line voltage is greater than the first word line voltage.

[0079] Please refer to Figure 1 、 Figure 2 、 Figure 4 , executing step S104, in a third time period, applying the second word line voltage to the first word line, applying the first bit line voltage and a second current to the first bit line, wherein the second current is greater than the first current.

[0080] In some embodiments, the first word line voltage Vp1 is in the range of 0V<Vp1≤4V. The second word line voltage Vp2 is in the range of Vp1<Vp2≤5V, and Vp2≥3V.

[0081] In some embodiments, the first current I1 is in the range of 20 A≤I1≤80 A. The second current I2 is in the range of I1<I2≤200 A, and I2≥60 A.

[0082] In some embodiments, the first bit line voltage Vn1 is a negative value, and the range of the first bit line voltage Vn1 is -5V≤Vn1<0V.

[0083] Under the combined action of the first bit line voltage, the second current, and the second word line voltage, a reset operation may be performed on the first target memory cell.

[0084] Based on the above embodiment, in the second time period, only the voltage of the first word line is changed while maintaining the first current. In the third time period, only the current of the first word line is changed while maintaining the voltage of the second word line. That is, the voltage and current are increased separately in different time periods rather than increasing them simultaneously. Therefore, the overcharge current from the second time period to the third time period is suppressed. In addition, in the first time period, a small first current is applied to the first word line, and the voltage is increased from the first word line voltage to the second word line voltage under the small first current, which can also suppress the overcharge current.

[0085] In some embodiments, the magnitude of the overcharge current can be controlled by controlling the length of the second time period. When the second time period is longer, the overcharge current is better suppressed. When the second time period is shorter, a larger overcharge current will occur.

[0086] In some embodiments, see Figure 5 As shown, the method further includes:

[0087] S201: performing a second reset operation on a first target memory cell among the plurality of memory cells when the number of the memory cells is greater than or equal to a number threshold, the second reset operation comprising: applying the first word line voltage to the first word line, applying a second bit line voltage and the first current to the first bit line during the first time period, the second bit line voltage being greater than the first bit line voltage;

[0088] S202: In the second time period, applying the second word line voltage to the first word line, and applying the first bit line voltage and the first current to the first bit line;

[0089] S203: When it is determined that the first target memory cell is in a non-conducting state during the second time period, in the third time period, a third word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line to adjust the first target memory cell to a conducting state, and the third word line voltage is greater than the second word line voltage.

[0090] In some embodiments, after S202 , the method further includes: detecting a state of the first target memory cell to determine whether the first target memory cell is in a non-conductive state or a conductive state.

[0091] In some embodiments, detecting the state of the first target storage unit specifically includes:

[0092] S1: Detect whether the current passing through the first target memory cell is greater than a current threshold; the current threshold is a relatively small value, such as 1 uA or 10 uA;

[0093] S2: If the current passing through the first target memory cell is less than or equal to the current threshold, it indicates that the pass element in the first target memory cell is turned off, and the first target memory cell is now in a "non-conducting state";

[0094] S3: If the current passing through the first target memory cell is greater than the current threshold, it indicates that the pass element in the first target memory cell is turned on, and at this time the first target memory cell is “in the on state”.

[0095] The voltage applied to the first bit line further includes a second bit line voltage Vn2. The voltage applied to the first word line further includes a third word line voltage Vp3.

[0096] If the first target memory cell is "in a non-conducting state", it is necessary to increase the second word line voltage to the third word line voltage in the third time period so that the first target memory cell is "in a conducting state", and then use the third word line voltage, the first bit line voltage and the second current to jointly implement the reset operation.

[0097] In some embodiments, the third word line voltage Vp3 is in the range of Vp2<Vp3≤5V, and Vp3≥3V.

[0098] In some embodiments, the second bit line voltage Vn2 is in the range of -5V≤Vn2<0, Vn2>Vn1.

[0099] In some embodiments, see Figure 6 As shown, after S202, the method further includes:

[0100] S204: When it is determined that the first target memory cell is in the on state during the second time period, in the third time period, applying the second word line voltage to the first word line, and applying the first bit line voltage and the second current to the first bit line.

[0101] If the first target memory cell is “in the on state”, there is no need to increase the voltage of the first word line in the third time period, and the reset operation is achieved by the combined action of the second word line voltage, the first bit line voltage and the second current.

[0102] Based on the aforementioned second reset operation, regardless of whether the first target memory cell has completed the reset operation, the first target memory cell is reset again. If the reset operation is repeated, the first target memory cell remains in the amorphous state after the repeated reset operation. In the embodiment of the present application, the absolute value of the second bit line voltage is set to a relatively low value during the first time period, thereby suppressing overcharge current during the first time period (i.e., when the first target memory cell is turned on). In the second time period, while the current in the first bit line remains unchanged, the voltage of the first word line is increased and the voltage of the first word line is decreased, thereby suppressing overcharge current. In the second time period, a fast read operation is performed to detect the state of the first target memory cell to determine whether the first target memory cell is in a non-conducting or conducting state, thereby determining whether the voltage of the first word line needs to be further increased. If the first target memory cell is in a conducting state, the voltage of the first word line does not need to be increased, thereby ensuring a relatively low overcharge current and preventing an excessively high voltage on the first word line from affecting the cell performance. If the first target memory cell is in a non-conducting state, the voltage of the first word line is increased to ensure that it is in a conducting state before performing the reset operation.

[0103] In some embodiments, see Figure 7 、 Figure 8 As shown, Figure 7 and Figure 8 The difference is that Figure 7 In the second time period, the first word line voltage is directly increased to a relatively large third word line voltage. Figure 8In the second time period, the first word line voltage is increased to the second word line voltage, and then in the third time period, the second word line voltage is increased to the third word line voltage. The method further includes:

[0104] S301: performing a third reset operation on a first target memory cell among the plurality of memory cells when the number of the memory cells is greater than or equal to a number threshold, the third reset operation comprising: applying the first word line voltage to the first word line, and applying the second bit line voltage and the first current to the first bit line during the first time period;

[0105] S302: When it is determined that the first target storage unit is in the on state during the first time period, detecting whether a line resistance of the first target storage unit is greater than a resistance threshold;

[0106] S303: If it is determined that the line resistance of the first target memory cell is greater than a resistance threshold, apply a third word line voltage or the second word line voltage to the first word line, and apply the first bit line voltage and the first current to the first bit line during the second time period.

[0107] S304 : In the third time period, applying the third word line voltage to the first word line, and applying the first bit line voltage and the second current to the first bit line.

[0108] In some embodiments, after S301 , the method further includes: detecting a state of the first target memory cell to determine whether the first target memory cell is in a non-conductive state or a conductive state.

[0109] In some embodiments, the line resistance of the first target memory cell refers to the sum of the line resistance from the first target memory cell through the first word line to the word line power supply terminal and the line resistance from the first target memory cell through the first bit line to the bit line power supply terminal. A resistance threshold can be set at 10 kΩ. If the line resistance of the first target memory cell is greater than the resistance threshold, it indicates that the first target memory cell is far from the two power supply terminals and has a large line resistance. This line resistance will cause voltage division. Therefore, it is necessary to increase the first word line voltage to a larger third word line voltage to compensate for the voltage division caused by the line resistance. The reset operation is achieved by the combined action of the third word line voltage, the first bit line voltage, and the second current.

[0110] In some embodiments, see Figure 9 As shown, after detecting whether the line resistance of the first target memory cell is greater than a resistance threshold, the method further includes:

[0111] S305: When it is determined that the line resistance of the first target memory cell is less than or equal to a resistance threshold, applying the second word line voltage to the first word line, and applying the first bit line voltage and the first current to the first bit line in the second time period;

[0112] S306 : In the third time period, applying the second word line voltage to the first word line, and applying the first bit line voltage and the second current to the first bit line.

[0113] If the line resistance of the first target memory cell is less than or equal to the resistance threshold, it means that the first target memory cell is close to the two power supply terminals, the line resistance is small, and the influence of the line resistance voltage division can be ignored. Therefore, it is only necessary to increase the first word line voltage to the second word line voltage, and use the combined effect of the second word line voltage, the first bit line voltage and the second current to achieve the reset operation. In addition, since the second word line voltage is less than the third word line voltage, the overcharge current can also be suppressed.

[0114] In some embodiments, see Figure 10 As shown, after applying the first word line voltage to the first word line and applying the second bit line voltage and the first current to the first bit line, the method further includes:

[0115] S307 : When it is determined that the first target memory cell is in a non-conducting state during the first time period, the voltage applied to the first word line is set to 0, and the voltage and current applied to the first bit line are set to 0.

[0116] If the first target memory cell is in a non-conducting state during the first time period, it means that it has been reset and does not need to be reset again. In this case, the voltage applied to the first word line is set to 0, and the voltage and current applied to the first bit line are set to 0, which can protect the performance of the memory cell and reduce power loss.

[0117] The difference between the second reset operation and the third reset operation is that the second reset operation performs a reset operation again regardless of whether the first target memory cell has previously completed a reset operation. The third reset operation determines whether a reset operation should be performed currently based on the state of the first target memory cell: if the first target memory cell is in a non-conductive state (amorphous state, high-impedance state) during the first time period, it means that it has already undergone a reset operation and does not need to be reset again; if the first target memory cell is in a conductive state (crystalline state, low-impedance state) during the first time period, it means that the first target memory cell needs to be reset, and the corresponding voltage and current are increased at this time. The advantage of the third reset operation is that it effectively avoids re-resetting the first target memory cell that has already been reset, avoids unnecessary reset operations to generate overcharge current, and at the same time suppresses overcharge current during the reset operation of the crystalline first target memory cell.

[0118] In some embodiments, see Figure 7 、 Figure 8 As shown, after detecting whether the line resistance of the first target memory cell is greater than a resistance threshold, the method further includes:

[0119] S308: When it is determined that the line resistance of the first target memory cell is greater than a resistance threshold, determine a memory cell connected in series with the first target memory cell on the first word line as a second target memory cell;

[0120] S309 : When the third word line voltage is applied to the first word line, applying a bias voltage to a second bit line coupled to the second target memory cell.

[0121] When the third word line voltage is applied to the first word line, the voltage across the second target memory cell is also increased. Therefore, a bias voltage Vbias is applied to the second bit line coupled to the second target memory cell. The bias voltage Vbias is a positive value within the range of 0 < Vbias ≤ 2V. The voltage across the second target memory cell = Vp3 - Vbias. By setting the bias voltage, the voltage across the second target memory cell can be reduced, preventing the non-conducting second target memory cell from being mistakenly turned on.

[0122] See Figure 11 As shown, Figure 11 This is a schematic diagram of the simulation experiment results. It can be seen from L4 that when the voltage is switched, there will be an overcharge current but the absolute value is small. Only when the current source is switched subsequently will the current value increase significantly.

[0123] The present embodiment provides a phase change memory, including:

[0124] A memory cell array comprising a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines;

[0125] The peripheral circuit coupled to the memory cell array is configured to control the memory cell array using the method described in any one of the above embodiments.

[0126] It should be noted that the above method may also include other implementations according to the description of the phase change memory embodiment. The specific implementation methods can refer to the description of the relevant phase change memory control method embodiment, which will not be described in detail here.

[0127] The above-described methods or embodiments of phase-change memory are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art can understand and implement the present invention without inventive effort.

[0128] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0129] In summary, although the present application has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A control method for a phase change memory, wherein the phase change memory comprises a memory cell array, wherein the memory cell array comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines, wherein: The method comprises: Obtaining the number of the storage units; When the number of the storage units is less than a number threshold, performing a first reset operation on a first target storage unit among the plurality of storage units, the first reset operation comprising: In a first time period, applying a first word line voltage to a first word line coupled to the first target memory cell, and applying a first bit line voltage and a first current to a first bit line coupled to the first target memory cell; In a second time period, a second word line voltage is applied to the first word line, and the first bit line voltage and the first current are applied to the first bit line, wherein the second word line voltage is greater than the first word line voltage; In a third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and a second current are applied to the first bit line, where the second current is greater than the first current.

2. The method according to claim 1, characterized in that The method further comprises: When the number of the memory cells is greater than or equal to a number threshold, performing a second reset operation on a first target memory cell among the plurality of memory cells, the second reset operation comprising: applying the first word line voltage to the first word line, applying a second bit line voltage and the first current to the first bit line during the first time period, the second bit line voltage being greater than the first bit line voltage; In the second time period, applying the second word line voltage to the first word line, and applying the first bit line voltage and the first current to the first bit line; When it is determined that the first target memory cell is in a non-conducting state during the second time period, in the third time period, a third word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line to adjust the first target memory cell to a conducting state, and the third word line voltage is greater than the second word line voltage.

3. The method according to claim 2, characterized in that After applying the second word line voltage to the first word line and applying the first bit line voltage and the first current to the first bit line, the method further includes: When it is determined that the first target memory cell is in the on state during the second time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line during the third time period.

4. The method according to claim 2, characterized in that The method further comprises: When the number of the memory cells is greater than or equal to a number threshold, performing a third reset operation on a first target memory cell among the plurality of memory cells, the third reset operation comprising: applying the first word line voltage to the first word line, and applying a second bit line voltage and the first current to the first bit line during the first time period; In a case where it is determined that the first target storage unit is in a conducting state during the first time period, detecting whether a line resistance of the first target storage unit is greater than a resistance threshold; If it is determined that the line resistance of the first target memory cell is greater than a resistance threshold, in the second time period, applying a third word line voltage or the second word line voltage to the first word line, and applying the first bit line voltage and the first current to the first bit line; In the third time period, the third word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

5. The method according to claim 4, characterized in that After detecting whether the line resistance of the first target memory cell is greater than a resistance threshold, the method further includes: When it is determined that the line resistance of the first target memory cell is less than or equal to a resistance threshold, applying the second word line voltage to the first word line and applying the first bit line voltage and the first current to the first bit line during the second time period; In the third time period, the second word line voltage is applied to the first word line, and the first bit line voltage and the second current are applied to the first bit line.

6. The method according to claim 4, characterized in that After detecting whether the line resistance of the first target memory cell is greater than a resistance threshold, the method further includes: When it is determined that the line resistance of the first target memory cell is greater than a resistance threshold, determining a memory cell connected in series with the first target memory cell on the first word line as a second target memory cell; When the third word line voltage is applied to the first word line, a bias voltage is applied to the second bit line coupled to the second target memory cell.

7. The method according to claim 4, characterized in that After applying the first word line voltage to the first word line and applying the second bit line voltage and the first current to the first bit line, the method further includes: When it is determined that the first target memory cell is in a non-conductive state during the first time period, the voltage applied to the first word line is set to 0, and the voltage and current applied to the first bit line are set to 0.

8. The method according to claim 1, characterized in that The first word line voltage Vp1 is in the range of 0V<Vp1≤4V.

9. The method according to claim 1, characterized in that The range of the first current I1 is 20A≤I1≤80A.

10. A phase change memory, characterized in that: include: A memory cell array comprising a plurality of bit lines, a plurality of word lines, and a plurality of memory cells located between the plurality of bit lines and the plurality of word lines; A peripheral circuit coupled to the memory cell array is configured to control the memory cell array using the method according to any one of claims 1 to 9.

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