Memory peripheral circuit and memory

Abstract

The application discloses a peripheral circuit of a memory and the memory. The memory comprises a plurality of storage units. The peripheral circuit comprises a bit line decoder, and the bit line decoder comprises a plurality of gating units. Each gating unit comprises a first end coupled with a bit line of any storage unit, a second end for outputting a read signal of a selected storage unit, and a third end coupled between the first end and the second end and coupled with a local bit line of the memory. During a read operation on the selected storage unit, conduction is maintained between the first end and the third end, and after a preset time, conduction is maintained between the second end and the third end. The application increases the voltage offset of the second end and the third end after charge sharing, helps to form a clear voltage difference between the read signal and a reference signal, enhances the discrimination margin of a comparator, and improves the accuracy and stability of the read operation of the memory.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and particularly to a peripheral circuit and memory for a memory. Background Technology

[0002] In memory, data retrieval typically relies on charge sharing between bit lines (BLs) and data lines (DLs) to determine the state of a memory cell. Specifically, the current mainstream default read method usually includes the following steps: First, the selected bit line is disconnected from the data line, and then reconnected via control logic, thereby enabling charge sharing between the bit line and data line. The shared voltage value is input to a comparator, compared with a preset reference voltage, and the result is output after amplification.

[0003] However, when reading from a memory cell, deviations in parasitic capacitance during manufacturing may lead to insufficient voltage difference after charge sharing, which in turn affects the discrimination effect of the comparator amplifier and reduces reading accuracy and stability. Summary of the Invention

[0004] In view of the above-mentioned deficiencies of the prior art, the technical problem to be solved by this application is how to improve the accuracy and stability of memory read operations.

[0005] To address at least one of the aforementioned technical problems, this application discloses a peripheral circuit for a memory and a memory.

[0006] According to one aspect of this application, a peripheral circuit for a memory is provided, the memory including a memory array comprising a plurality of memory cells, the peripheral circuit for the memory including:

[0007] Bit-line decoder, including:

[0008] Multiple gating units, each of the gating units comprising:

[0009] The first end is coupled to the bit line of any of the aforementioned memory cells;

[0010] The second terminal is used to output the read signal of the selected storage cell;

[0011] The third terminal is coupled between the first and second terminals and is coupled to the local bit line of the memory.

[0012] Each of the gating units is configured as follows:

[0013] During the read operation on the selected storage unit, the first end and the third end are kept connected, and after the second end and the third end are disconnected for a preset time, the second end and the third end are connected again.

[0014] Optionally, each of the gating units includes:

[0015] The first line switch is connected between the second terminal and the third terminal;

[0016] The first bit line switch is configured to turn on after being turned off for a preset time during the reading operation of the selected memory cell.

[0017] Optionally, each of the gating units includes:

[0018] The second position line switch is connected between the first end and the third end;

[0019] The second bit line switch is configured to remain on during a read operation on the selected memory cell.

[0020] Optionally, the first bit line switch further includes a first control terminal, which is used to receive a first control signal to control the first bit line switch to be turned on or off; the second bit line switch further includes a second control terminal, which is used to receive a second control signal to control the second bit line switch to be turned on or off.

[0021] Optionally, the second bit line switch is a transistor, and the gate terminal of the transistor is the second control terminal;

[0022] During the read operation of the selected memory cell, the magnitude of the second control signal is positively or negatively correlated with the magnitude of the current between the first terminal and the third terminal.

[0023] Optionally, it also includes: a signal controller, configured to:

[0024] During the read operation of the selected memory cell, a first control signal is provided to the first control terminal and a second control signal is provided to the second control terminal. The first control signal is used to control the first bit line switch to turn on after a preset time of being turned off, and the second control signal is used to control the second bit line switch to remain on.

[0025] Optionally, each of the selection units further includes: a first control switch, one end of which is connected to the first control terminal, and the other end of which is used to receive a first control signal. The first control switch is configured to turn on after being turned off for a preset time during the process of reading the selected storage unit.

[0026] Optionally, it also includes: a signal controller, configured to:

[0027] During the read operation of the selected memory cell, a first control signal is provided to the first control terminal, a second control signal is provided to the second control terminal, and a first switch signal is provided to the first control switch. The first control signal is used to control the first bit line switch to be continuously turned on, the second control signal is used to control the second bit line switch to be continuously turned on, and the first switch signal is used to control the first control switch to be turned on after being turned off for a preset time.

[0028] Optionally, it also includes: a comparator having a first input terminal, a second input terminal, and an output terminal;

[0029] The first input terminal is used to input a reference signal;

[0030] The second input terminal, coupled to the second terminal, is used to receive the read signal;

[0031] The output terminal is used to output the comparison result between the reference signal and the read signal.

[0032] According to a second aspect of this application, a memory is provided, the memory comprising:

[0033] A storage array, comprising multiple storage units;

[0034] The peripheral circuitry of any of the above is coupled to the storage unit.

[0035] The peripheral circuit of the memory disclosed in the embodiments of this application can improve the accuracy and stability of memory read operations.

[0036] Specifically, this application introduces a three-terminal structure in the gating unit and employs a time-division multiplexing control method during the read operation of the selected memory cell. First, the first and third terminals are connected, while the third and second terminals are temporarily de-connected, allowing the bit line of the memory cell to connect with the local bit line. Then, the second and third terminals are connected, causing the second terminal to output a read signal. During the charge sharing process between the second and third terminals, in addition to the original parasitic capacitance, the local bit line's parasitic capacitance is introduced on the bit line side of the memory cell, effectively increasing the equivalent parasitic capacitance of the bit line. This results in a larger voltage offset after charge sharing between the second and third terminals, helping to create a significant voltage difference between the read signal and the reference signal, enhancing the comparator's discrimination margin, and improving the accuracy and stability of the memory read operation. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of the memory provided in the embodiments of this application;

[0039] Figure 2 The peripheral circuit of the memory provided in the embodiments of this application Figure 1 ;

[0040] Figure 3 The peripheral circuit of the memory provided in the embodiments of this application Figure 2 ;

[0041] Figure 4 A simulated diagram of the read signals of the peripheral circuit of the memory provided in an embodiment of this application;

[0042] Figure 5 A schematic diagram of the voltage waveform of the peripheral circuit of the memory provided in the embodiments of this application during data reading;

[0043] Figure 6 This is a graph showing the change of current on the bit line side over time.

[0044] Explanation of reference numerals in the attached figures:

[0045] 1. Storage array;

[0046] 2. Peripheral circuitry; 3. Bit line decoder; 4. Signal controller; 5. Storage unit; 6. Selected storage unit;

[0047] 21. Gating unit; 211. First terminal; 212. Second terminal; 213. Third terminal; 22. Comparator; 221. First input terminal; 222. Second input terminal; 223. Output terminal.

[0048] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0049] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments in this specification. All other embodiments obtained by those skilled in the art based on the embodiments in this specification without creative effort are within the scope of protection of this application.

[0050] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such as a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0051] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0052] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0053] In this document, the term "and / or" describes a relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0054] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0055] As described in the background art, when performing a read operation on a memory cell, the parasitic capacitance deviation during the manufacturing process may lead to insufficient voltage difference after charge sharing, thereby affecting the discrimination effect of the comparator and reducing the accuracy and stability of the read operation.

[0056] In Embodiment 1, the memory includes a memory array, which comprises multiple memory cells. The peripheral circuitry of the memory provided in Embodiment 1 includes a bit-line decoder and a comparator. The bit-line decoder includes multiple gating units, each gating unit having a first terminal and a second terminal. The first terminal is coupled to the bit line of any memory cell, and the second terminal is coupled to a data line for outputting a read signal for the selected memory cell. The comparator has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives a reference signal, the second input terminal is coupled to the second terminal of the gating unit for receiving the read signal of the selected memory cell, and the output terminal outputs the comparison result between the reference signal and the read signal.

[0057] In Embodiment 1, when performing a read operation on the selected memory cell, the connection between the first end and the second end of the gating unit is first disconnected. After maintaining the disconnected state for a preset time, the first end and the second end of the gating unit are then connected so that the second end outputs the read signal of the corresponding memory cell.

[0058] However, due to process errors and fluctuations in device parameters during actual chip manufacturing, the parasitic capacitance of bit lines and data lines may deviate from the design values. For example, the parasitic capacitance of bit lines may be less than expected, while the parasitic capacitance of data lines may be greater than expected. In this case, when the connection between the first and second terminals is broken and then reconnected, the bit lines and data lines will share charge after reconnection. Ultimately, the voltage on the data line may be closer to the reference signal voltage, meaning the voltage of the read signal output from the second terminal may be too close to the reference signal voltage. If the voltage difference between the two is lower than the comparator's minimum resolution threshold, the comparison result will be inaccurate, thereby reducing the read accuracy and stability of the memory.

[0059] Therefore, in order to improve the accuracy and stability of memory reading, Embodiment 2 provides a peripheral circuit for the memory.

[0060] Figure 1 This is a schematic diagram of the structure of the memory provided in the embodiments of this application, such as... Figure 1 As shown, the memory includes a storage array 1 and peripheral circuits 2, with the peripheral circuits 2 coupled to the storage array 1.

[0061] The storage array 1 corresponds to at least a portion of the phase-change memory and includes multiple word lines WL, multiple bit lines BL, and multiple storage cells 5. The storage cells 5 are located at the intersection of the word lines WL and the bit lines BL. Binary data can be written to or read from the storage cells 5.

[0062] Storage cell 5 includes crystalline and amorphous states, each corresponding to a different voltage threshold. By applying different forms of heat to storage cell 5, the crystalline and amorphous states can be switched. The crystalline state is defined as 1, corresponding to a lower threshold voltage, while the amorphous state is defined as 0, corresponding to a higher threshold voltage. Writing a "1" to storage cell 5 is defined as a set operation, and writing a "0" is defined as a reset operation. By applying a voltage greater than the threshold voltage of the set state but less than the threshold voltage of the reset state to the selected storage cell 6, the crystalline state storage cell 5 can be opened, but the amorphous state storage cell 5 cannot be opened, thus completing the reading of the storage cell 5's state.

[0063] Figure 2 The peripheral circuit of the memory provided in the embodiments of this application Figure 1 ,like Figure 2 As shown, the peripheral circuit of a memory disclosed in Embodiment 2 of this application includes a bit line decoder 3. The bit line decoder 3 includes multiple gating units 21, each gating unit 21 including a first terminal 211, a second terminal 212, and a third terminal 213. The first terminal 211 is coupled to the bit line BL of any memory cell 5; the second terminal 212 is used to output the read signal of the selected memory cell 6; the third terminal 213 is coupled between the first terminal 211 and the second terminal 212, and is coupled to the local bit line LBL of the memory. That is, the side of the first terminal 211 away from the second terminal 212 is coupled to the bit line BL of any memory cell 5, the local bit line LBL is coupled between the first terminal 211 and the second terminal 212, the side of the second terminal 212 away from the first terminal 211 is coupled to the first data line DL0, and the third terminal 213 is located between the first terminal 211 and the second terminal 212, and is coupled to the local bit line LBL.

[0064] During the reading operation of the selected storage unit 6, each gate unit 21 is configured to: keep the first end 211 and the third end 213 connected, and after disconnecting the second end 212 and the third end 213 for a preset time, connect the second end 212 and the third end 213.

[0065] This application introduces a three-terminal structure in the selection unit 21 and employs a time-division multiplexing control method during the read operation of the selected memory cell 6. First, the first terminal 211 and the third terminal 213 are connected, while the third terminal 213 and the second terminal 212 are temporarily de-connected, allowing the bit line BL of the selected memory cell 6 to connect with the local bit line LBL. Then, the second terminal 212 and the third terminal 213 are connected, causing the second terminal 212 to output a read signal. During the charge sharing process between the second terminal 212 and the third terminal 213, in addition to the existing parasitic capacitance, the selected memory cell 6's bit line side also incorporates the parasitic capacitance of the local bit line LBL, effectively increasing the equivalent parasitic capacitance on the bit line side. This increases the voltage offset after charge sharing between the second terminal 212 and the third terminal 213, helping to create a significant voltage difference between the read signal and the reference signal, enhancing the discrimination margin of the comparator 22, and improving the accuracy and stability of the memory read operation.

[0066] Continue to refer to Figure 2 The bit-line decoder 3 of the peripheral circuit of the memory disclosed in Embodiment 2 of this application further includes a comparator 22. The comparator 22 has a first input terminal 221, a second input terminal 222, and an output terminal 223. The first input terminal 221 is coupled to a second data line DL1 and is used to input a reference signal. The second input terminal 222 is coupled to a second terminal 212 via a first data line DL0 and is used to receive a read signal. The comparator 22 compares the reference signal and the read signal, and outputs the comparison result of the reference signal and the read signal through the output terminal 223.

[0067] like Figure 4 As shown, when performing a read operation on the selected memory cell 6, if the selected memory cell 6 is in the set state (indicating "read 1"), the bit line voltage of the selected memory cell 6 is V. BL-set If the selected memory cell 6 is in a reset state (indicating "read 0"), the bit line voltage of the selected memory cell 6 is V. BL-reset Before performing a read operation on the selected memory cell 6, the second terminal 212 is coupled to the data line DL0, and the voltage at the second terminal 212 is V. DL0 In Embodiment 1, after reading the selected memory cell 6 which is in the set state, the voltage of the read signal output by the second terminal 212 is V. DL0-set After reading the selected memory cell 6 which is in the reset state, the voltage of the read signal output by the second terminal 212 is V. DL0-reset In Embodiment 2, after reading the selected memory cell 6 in the set state, the voltage of the read signal output by the second terminal 212 is V. DL0-set’ After reading the selected memory cell 6 which is in the reset state, the voltage of the read signal output by the second terminal 212 is V.DL0-reset’ . Figure 4 The "first margin" and "second margin" shown represent the voltage of the read signal and the voltage V of the reference signal in Embodiment 1 and Embodiment 2, respectively. DL1-ref The voltage difference between them. As can be seen from the improvement in Embodiment 2, the second margin is greater than the first margin, which improves the margin for memory read discrimination.

[0068] Furthermore, referring to Figure 5 , Figure 5 This is a schematic diagram of the voltage waveform of the peripheral circuit of the memory provided in this application during data reading. The diagram shows the difference in voltage read margin between Embodiment 1 and Embodiment 2 after performing a read operation on the selected memory cell 6. Specifically, curve E represents the voltage waveform of the second terminal 212; curve F represents the voltage waveform of the first terminal 211; curve G represents the voltage waveform of the first input terminal 221; the first interval represents the voltage state of each terminal after reading the selected memory cell 6; ΔV represents the voltage difference between the second terminal 212 and the first input terminal 221; and the voltage of the first input terminal 221 represents the reference voltage.

[0069] Specifically, Figure 5 In graphs a, b, c, and d, the vertical axis represents voltage, and the horizontal axis represents time. The vertical axis scales of graphs a, b, c, and d are consistent, as are the horizontal axis scales. Figure 5 Figures a and b both show the reading operation performed on the selected storage unit 6 in the set state. Figure a shows the reading operation performed in Example 1, and Figure b shows the reading operation performed in Example 2. It can be clearly seen that in the first interval, ΔV2 in Example 2 is greater than ΔV1 in Example 1. Figure 5 Both diagrams c and d in the diagram represent the read operation of the selected storage unit 6 in the reset state. Diagram c shows the read operation performed in Example 1, and diagram d shows the read operation performed in Example 2. It can be clearly seen that in the first interval, ΔV4 in Example 2 is greater than ΔV3 in Example 1.

[0070] As can be seen from the above comparison, through the improvement of structure and control strategy, Embodiment 2 effectively increases the voltage difference between the read signal and the reference signal when "reading 1" and "reading 0", that is, increases the discrimination margin of the comparator, thereby improving the read accuracy and stability of the memory in the presence of parasitic capacitance deviation.

[0071] Reference Figure 2In Embodiment 2, each selection unit 21 further includes a first line switch SW1. The first line switch SW1 is connected between the second terminal 212 and the third terminal 213. Embodiment 2 achieves precise control of the read path by controlling the on and off of the first line switch SW1, thereby optimizing the charge sharing process and improving the voltage difference of the read signal. Specifically, the first line switch SW1 is configured to be turned on after being turned off for a preset time during the read operation of the selected memory cell 6, thereby ensuring that before the charge sharing between the second terminal 212 and the third terminal 213, only the bit line BL of the selected memory cell 6 is connected to the local bit line LBL, so that the parasitic capacitance of the local bit line LBL is introduced on the bit line side, effectively increasing the equivalent parasitic capacitance on the bit line side and improving the voltage offset and comparison discrimination margin.

[0072] In Embodiment 2, the first line switch SW1 has a first control terminal, which is used to receive a first control signal to control the first line switch SW1 to be turned on and off. The peripheral circuit 2 of the memory also includes a signal controller 4, which provides a first control signal to the first control terminal during the reading operation of the selected memory cell 6. The first control signal is used to control the first line switch SW1 to be turned on after a preset off time.

[0073] It is worth mentioning that the first line switch SW1 can be, but is not limited to, a PMOS transistor, an NMOS transistor, a bipolar junction transistor (BJT), or other semiconductor switching devices capable of implementing on / off control functions. When the first line switch SW1 is a PMOS transistor or an NMOS transistor, the gate terminals of the PMOS transistor and the NMOS transistor form the first control terminal of the first line switch SW1. When the first line switch SW1 is a bipolar junction transistor (BJT), the base terminal of the bipolar junction transistor (BJT) is the first control terminal of the first line switch SW1.

[0074] Continue to refer to Figure 2 In some other embodiments, each gating unit 21 further includes a second bit line switch SW2. The second bit line switch SW2 is connected between the first terminal 211 and the third terminal 213. In this embodiment, by controlling the on and off states of the second bit line switch SW2, precise control of the read path is achieved, thereby optimizing the charge sharing process and improving the voltage difference of the read signal. Specifically, the second bit line switch SW2 is configured to remain on during the read operation of the selected memory cell 6. This ensures that before the charge sharing between the second terminal 212 and the third terminal 213, the bit line BL of the selected memory cell 6 is connected to the local bit line LBL, so as to introduce the parasitic capacitance of the local bit line LBL on the bit line side, increase the equivalent parasitic capacitance on the bit line side, and improve the voltage offset and comparison discrimination margin.

[0075] In this embodiment, the second bit line switch SW2 has a second control terminal, which is used to receive a second control signal to control the second bit line switch SW2 to be turned on and off. During the process of reading the selected memory unit 6, the signal controller 4 also provides a second control signal to the second control terminal, which is used to control the second bit line switch SW2 to be continuously turned on.

[0076] It is worth mentioning that the second bit line switch SW2 can be, but is not limited to, a PMOS transistor, an NMOS transistor, a bipolar junction transistor (BJT), or other semiconductor switching devices capable of implementing on / off control functions. When the second bit line switch is a PMOS transistor or an NMOS transistor, the gate terminals of the PMOS transistor and the NMOS transistor form the second control terminal of the second bit line switch SW2. When the second bit line switch is a bipolar junction transistor (BJT), the base terminal of the bipolar junction transistor (BJT) is the second control terminal of the second bit line switch SW2.

[0077] When reading from the selected memory cell 6, the increased equivalent parasitic capacitance on the bit line side slows down the voltage drop rate, prolonging the reading process. If the voltage change on the bit line side is too slow or unclear, unselected memory cells 5 may also discharge, affecting their state and leading to incorrect reading results. To avoid this problem, in this embodiment, the second bit line switch SW2 is a transistor (either a PMOS or NMOS transistor). When the second bit line switch SW2 is an NMOS transistor, during the reading operation of the selected memory cell 6, the magnitude of the second control signal is positively correlated with the magnitude of the current between the first terminal 211 and the third terminal 213. Specifically, when the second control signal is large, the second bit line switch SW2 has strong conduction capability, and the current between the first terminal 211 and the third terminal 213 is large; when the second control signal is small, the second bit line switch SW2 has weak conduction capability, and the current between the first terminal 211 and the third terminal 213 is small. When the second bit line switch SW2 is a PMOS transistor, during the read operation of the selected memory cell 6, the magnitude of the second control signal is negatively correlated with the magnitude of the current between the first terminal 211 and the third terminal 213.

[0078] By setting the second bit line switch SW2 as a transistor, a suitable second control signal can be selected based on the size of the equivalent parasitic capacitance. By controlling the size of the second control signal, the conduction time of the second bit line switch SW2 can be controlled, reducing read interference and improving the read discrimination margin of the memory.

[0079] Taking the second bit line switch SW2 as an NMOS transistor as an example, refer to... Figure 6 , Figure 6This is a graph showing the change of current on the bit line side over time. Figure 6 The vertical axis represents the current value on the bit line side, and the horizontal axis represents time. Specifically, curve A represents the process of the bit line side current changing with time in the first case; curve B represents the process of the bit line side current changing with time in the second case; curve C represents the process of the bit line side current changing with time in the third case; and curve D represents the process of the bit line side current changing with time in the fourth case.

[0080] First case: The reading method involves keeping the first bit line switch SW1 on while performing a reading operation on the selected reading unit, and turning the second bit line switch SW2 on after a preset time (this reading method does not change the equivalent parasitic capacitance on the bit line side). Second case: The reading method is the same as in this embodiment, specifically, when performing a reading operation on the selected memory unit 6, keeping the second bit line switch SW2 on, and turning the first bit line switch SW1 on after a preset time. Third case: The reading method is the same as in the second case. Fourth case: The reading method is the same as in the second case. In the second case, the voltage value of the second control signal is less than that of the second control signal in the third case; the voltage value of the second control signal in the third case is less than that of the second control signal in the fourth case; and the voltage value of the second control signal in the fourth case is equal to that of the second control signal in the first case.

[0081] pass Figure 6 Curves A and D clearly show that, when the voltage values ​​of the second control signal are equal, the conduction time of the second bit line switch SW2 in the read method disclosed in this embodiment (keeping the second bit line switch SW2 on while performing a read operation on the selected read unit, and turning on the first bit line switch SW1 after a preset time) is greater than the conduction time of the second bit line switch SW2 in another read method (keeping the first bit line switch SW1 on while performing a read operation on the selected read unit, and turning on the second bit line switch SW2 after a preset time). This embodiment of the application does indeed increase the equivalent parasitic capacitance on the bit line side, which can effectively improve the margin of memory read discrimination, thereby improving the accuracy and stability of memory read operations.

[0082] pass Figure 6 Curves B, C, and D clearly show that when the selected read unit is read using the reading method disclosed in this embodiment, the conduction time of the second bit line switch SW2 can be controlled by changing the magnitude of the second control signal, thereby reducing read interference and further improving the accuracy and stability of the memory read operation.

[0083] Figure 3 The peripheral circuit of the memory provided in the embodiments of this application Figure 2 ,like Figure 3 As shown, Embodiment 3 of this application also discloses a peripheral circuit for a memory. Unlike the above embodiments, the decoder 3 further includes a first control switch SW3. One end of the first control switch SW3 is connected to a first control terminal, and the other end is used to receive a first control signal. The signal controller 4 is configured to: provide a first control signal to the first control terminal, a second control signal to the second control terminal, and a first switch signal to the first control switch SW3 during a read operation on the selected memory cell 6. The first control signal is used to control the first bit line switch SW1 to remain continuously on, the second control signal is used to control the second bit line switch SW2 to remain continuously on, and the first switch signal is used to control the first control switch SW3 to turn on after being turned off for a preset time. The first control switch SW3 is configured to turn on after being turned off for a preset time during a read operation on the selected memory cell 6. Embodiment 3 controls the first bit line switch SW1 to turn on after being turned off for a preset time by controlling the on and off states of the first control switch SW3.

[0084] This application also discloses a memory, which includes:

[0085] A storage array, comprising multiple storage units;

[0086] The peripheral circuitry of any of the above items is coupled to the memory cell.

[0087] This application also discloses an operation method for the above-mentioned memory, including:

[0088] Perform read operations on the selected memory cell, including:

[0089] Maintain continuity between the first and third terminals, and disconnect the second and third terminals;

[0090] After a preset time of disconnection between the second and third terminals, the connection between the second and third terminals is restored so that the second terminal outputs a read signal.

[0091] The above are merely optional embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A memory peripheral circuit, the memory comprising a memory array, the memory array comprising a plurality of memory cells, characterized by, The peripheral circuit comprises: a bit line decoder comprising: a plurality of gating units, each of which comprises: a first end coupled to a bit line of any of the memory cells; a second end for outputting a read signal of the selected memory cell; a third end coupled between the first end and the second end and coupled to a local bit line of the memory; a second bit line switch connected between the first end and the third end; the second bit line switch is configured to be continuously turned on during a read operation on the selected memory cell; each of the gating units is configured to: keep the first end and the third end turned on and disconnect the second end and the third end for a preset time during the read operation on the selected memory cell, and then turn on the second end and the third end.

2. The memory peripheral circuit of claim 1, wherein, each of the gating units comprises: a first bit line switch connected between the second end and the third end; the first bit line switch is configured to be turned on after a preset time during the read operation on the selected memory cell.

3. The peripheral circuit of the memory according to claim 2, wherein the first bit line switch further comprises a first control end for receiving a first control signal to control the first bit line switch to be turned on or turned off; and the second bit line switch further comprises a second control end for receiving a second control signal to control the second bit line switch to be turned on or turned off.

4. The memory peripheral circuit of claim 3, wherein, the second bit line switch is a transistor, and a gate end of the transistor is the second control end; during the read operation on the selected memory cell, the size of the second control signal is positively or negatively correlated with the current size between the first end and the third end.

5. The memory peripheral circuit of claim 3, wherein, further comprising: a signal controller configured to: provide the first control end with a first control signal and the second control end with a second control signal during the read operation on the selected memory cell, the first control signal being used to control the first bit line switch to be turned on after a preset time, and the second control signal being used to control the second bit line switch to be continuously turned on.

6. The memory peripheral circuit of claim 3, wherein, each of the gating units further comprises: a first control switch having one end connected to the first control end and the other end for receiving a first control signal, the first control switch being configured to be turned on after a preset time during the read operation on the selected memory cell.

7. The memory peripheral circuit of claim 6, wherein, further comprising: a signal controller configured to: provide the first control end with a first control signal, the second control end with a second control signal, and the first control switch with a first switch signal during the read operation on the selected memory cell, the first control signal being used to control the first bit line switch to be continuously turned on, the second control signal being used to control the second bit line switch to be continuously turned on, and the first switch signal being used to control the first control switch to be turned on after a preset time.

8. The memory peripheral circuit of claim 1, wherein, the bit line decoder further comprises: a comparator having a first input end, a second input end, and an output end; the first input end is used to input a reference signal; The second input terminal, coupled with the second terminal, is configured to receive the read signal. The output terminal is configured to output a comparison result of the reference signal and the read signal.

9. A memory, comprising: The memory comprises: a memory array comprising a plurality of memory cells; The peripheral circuit according to any one of claims 1-8, coupled with the memory cells.

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