Laminated ceramic electronic component

Abstract

The invention provides a laminated ceramic electronic component which satisfies the requirements of miniaturization and large capacitance and reduces the possibility of interlayer peeling. A laminated ceramic capacitor is provided with: a laminated body having two outer layer sections disposed on both sides of an inner layer section in a lamination direction, a first side spacer section positioned on a first side surface side of the inner layer section, and a second side spacer section positioned on a second side surface side; and external electrodes respectively disposed on the first end surface and the second end surface, in which the dimensions in the width direction of the inner layer section are substantially equal on the first main surface side and the second main surface side in the lamination direction, and in a cross-section passing through the lamination direction and the width direction at the center in the longitudinal direction, the dimensions in the width direction of the inner layer section are substantially equal. The dimension in the width direction of the first side spacing portion is substantially equal to the first main surface side and the second main surface side in the lamination direction, and the dimension in the width direction of the second side spacing portion gradually increases from the central portion in the lamination direction toward the second main surface side.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component. Background Art

[0002] Conventionally, multilayer ceramic capacitors are known as multilayer ceramic electronic components. These capacitors comprise a laminated body having an inner layer portion in which a plurality of internal dielectric layers and internal electrode layers are alternately stacked, and side spacers disposed on both sides of the inner layer portion in the width direction; and external electrodes disposed on both end surfaces of the laminated body.

[0003] Such a laminated ceramic capacitor is manufactured, for example, by cutting a mother block into a predetermined size to produce a laminate, and forming external electrodes on the laminate, wherein the mother block is formed by stacking a plurality of green sheets having a conductive paste printed on ceramic green sheets to serve as internal dielectric layers and forming the conductive paste to serve as internal electrode layers (for example, see Patent Document 1).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2000-357628

[0007] When cutting the mother block into a given size, the cutting is performed in both the longitudinal and width directions. In the width direction, the unprinted conductive paste spaces, which serve as side spacers, are cut from one direction in the stacking direction toward the other. The cutting blade is initially positioned approximately in the center of the conductive paste space, but as it moves from one direction in the stacking direction toward the other (from top to bottom), it gradually deviates from the center and may approach the conductive paste.

[0008] The bonding strength between the conductive paste and the ceramic green sheets is weaker than in areas directly stacked with ceramic green sheets that serve as side spacers. Therefore, as the cutting blade approaches the area printed with the conductive paste, downward force is applied to the conductive paste, potentially separating the ceramic green sheet printed with the conductive paste from the overlying ceramic green sheet, causing delamination.

[0009] In order to avoid such interlayer delamination, it is also conceivable to widen the width of the side spacers in both directions in the width direction from top to bottom so that the cutting blade can deviate in any direction in the width direction.

[0010] However, in recent years, multilayer ceramic capacitors have been required to be smaller and have higher capacitance. As the width of the side spacers increases in both directions from top to bottom, the width dimension of the lower conductive paste (i.e., the width dimension of the internal electrode layer) decreases, which is counterproductive to achieving both smaller size and higher capacitance. Summary of the Invention

[0011] Problems to be solved by the invention

[0012] An object of the present invention is to provide a multilayer ceramic electronic component that satisfies the requirements for miniaturization and increased electrostatic capacitance to a certain extent and reduces the possibility of interlayer delamination.

[0013] Technical solutions to solve problems

[0014] In order to solve the above-mentioned problems, the present invention provides a laminated ceramic electronic component, comprising a laminate and an external electrode, wherein the laminate comprises: an inner layer portion, on which an internal electrode layer and an internal dielectric layer are laminated; a first main surface and a second main surface, which are opposite to each other in a lamination direction; a first end surface and a second end surface, which are opposite to each other in a longitudinal direction intersecting the lamination direction; a first side surface and a second side surface, which are opposite to each other in a width direction intersecting the lamination direction and the longitudinal direction; two outer layer portions, which are arranged on both sides of the inner layer portion in the lamination direction; a first side spacer, which is located on the first side surface of the inner layer portion; and a second side spacer, which is located on the second side surface of the inner layer portion. On the second side surface of the inner layer portion, the external electrodes are respectively arranged on the first end surface and the second end surface, wherein the dimensions of the inner layer portion in the width direction are approximately equal on the first main surface side and the second main surface side in the stacking direction, and in a cross-section passing through the stacking direction and the width direction at the center in the length direction, the dimensions of the first side spacer in the width direction are approximately equal on the first main surface side and the second main surface side in the stacking direction, and the dimensions of the second side spacer in the width direction gradually increase from the center in the stacking direction toward the second main surface side.

[0015] Effects of the Invention

[0016] According to the present invention, it is possible to provide a multilayer ceramic electronic component that satisfies the demands for miniaturization and increased electrostatic capacitance to a certain extent and reduces the possibility of interlayer delamination. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic perspective view of a multilayer ceramic capacitor 1 according to the embodiment.

[0018] Figure 2 yes Figure 1 sectional view of the multilayer ceramic capacitor 1 taken along line II-II.

[0019] Figure 3 yes Figure 2 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III.

[0020] Figure 41 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1 .

[0021] Figure 5A It is a diagram for explaining a method of manufacturing the multilayer ceramic capacitor 1 .

[0022] Figure 5B It is a diagram for explaining a method of manufacturing the multilayer ceramic capacitor 1 .

[0023] Figure 6A It is a diagram showing a multilayer ceramic capacitor 1 according to a modified example of the present invention.

[0024] Figure 6B It is a diagram showing a multilayer ceramic capacitor 1 according to a modified example of the present invention.

[0025] Description of Reference Numerals

[0026] 1: Multilayer ceramic capacitors (multilayer ceramic electronic components);

[0027] 2: laminate;

[0028] 3: external electrode;

[0029] 4: inner dielectric layer;

[0030] 5: internal electrode layer;

[0031] 6: inner layer;

[0032] 7: outer layer;

[0033] 8: lateral septum;

[0034] 8A: first lateral septum;

[0035] 8B: Second lateral septum;

[0036] 11: inner layer;

[0037] 14: Ceramic green sheet;

[0038] 15: conductive paste;

[0039] 20: Mother block. DETAILED DESCRIPTION

[0040] Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to an embodiment of the present invention will be described. Figure 1 It is a schematic perspective view of a multilayer ceramic capacitor 1 according to the embodiment. Figure 2 yes Figure 1 sectional view of the multilayer ceramic capacitor 1 taken along line II-II. Figure 3 yes Figure 2 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III.

[0041] (Multilayer ceramic capacitor 1)

[0042] Multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a laminate 2 and a pair of external electrodes 3 provided at both ends of laminate 2. Laminate 2 includes an inner layer portion 6 in which a plurality of internal dielectric layers 4 and a plurality of internal electrode layers 5 are stacked.

[0043] In the following description, terms indicating directions of the multilayer ceramic capacitor 1 are used. In the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided is referred to as the longitudinal direction L. The direction in which the internal dielectric layers 4 and the internal electrode layers 5 are stacked is referred to as the stacking direction T. A direction intersecting both the longitudinal direction L and the stacking direction T is referred to as the width direction W. In the embodiment, the width direction W is orthogonal to both the longitudinal direction L and the stacking direction T.

[0044] If the dimension in the longitudinal direction L is defined as the L dimension, the L dimension of the multilayer ceramic capacitor 1 is preferably 0.2 mm or more and 10 mm or less. Furthermore, if the dimension in the stacking direction T is defined as the T dimension, the T dimension of the multilayer ceramic capacitor 1 is preferably 0.1 mm or more and 10 mm or less. Furthermore, if the dimension in the width direction W is defined as the W dimension, the W dimension of the multilayer ceramic capacitor 1 is preferably 0.1 mm or more and 10 mm or less. Furthermore, the L dimension of the multilayer ceramic capacitor 1 is not necessarily longer than the W dimension.

[0045] In the following description, among the six outer peripheral surfaces of the stacked body 2, a pair of outer peripheral surfaces opposing each other in the stacking direction T is referred to as the first principal surface A1 and the second principal surface A2, a pair of outer peripheral surfaces opposing each other in the width direction W is referred to as the first side surface B1 and the second side surface B2, and a pair of outer surfaces opposing each other in the longitudinal direction L is referred to as the first end surface C1 and the second end surface C2. Furthermore, when the first principal surface A1 and the second principal surface A2 are not particularly distinguished from each other in the description, they are collectively referred to as principal surfaces A, when the first side surface B1 and the second side surface B2 are not particularly distinguished from each other in the description, they are collectively referred to as side surfaces B, and when the first end surface C1 and the second end surface C2 are not particularly distinguished from each other in the description, they are collectively referred to as end surfaces C.

[0046] (Laminate 2)

[0047] The laminate 2 includes an inner layer portion 6 and outer layer portions 7 disposed on both main surface A sides of the inner layer portion 6. Figure 1As shown, the laminate 2 has a generally rectangular parallelepiped shape. The dimensions of the laminate 2 are not particularly limited, but the L dimension is preferably 0.2 mm or greater and 10 mm or less. Furthermore, the T dimension of the laminate 2 is preferably 0.1 mm or greater and 10 mm or less. Furthermore, the W dimension of the laminate 2 is preferably 0.1 mm or greater and 10 mm or less. Furthermore, the L dimension of the laminate 2 is not necessarily longer than the W dimension.

[0048] The corners and ridges of the laminate 2 are preferably rounded. A corner is where three surfaces of the laminate 2 intersect, and a ridge is where two surfaces of the laminate 2 intersect. Furthermore, a portion or all of the surface constituting the laminate 2 may be formed with irregularities.

[0049] In addition, the first main surface A1 of the laminate 2 is Figure 3 The cross section shown is curved to form a convex shape in which the central portion in the width direction W protrudes upward in the figure compared to both sides in the width direction W. The second main surface A2 is also Figure 3 The cross section shown is curved, with the center portion in the width direction W protruding downward in the figure compared to both sides. Furthermore, the protrusion amount T1 of the first main surface A1 is larger than the protrusion amount T2 of the second main surface A2.

[0050] The protrusion amount T1 of the first main surface A1 is the amount of protrusion T1 of the first side surface B1 and the second side surface B2 in the contours. Figure 3 denoted in the lamination direction T is a distance T1 between the upper end of the substantially straight portion on the first principal surface A1 side and the top of the convex shape protruding upward from the first principal surface A1 .

[0051] The protrusion amount T2 of the second main surface A2 is the amount of protrusion T2 of the first side surface B1 and the second side surface B2 in the contour. Figure 3 denoted in the lamination direction T is a distance T2 between the lower end of the substantially straight portion on the second principal surface A2 side and the top of the convex shape protruding downward from the second principal surface A2.

[0052] (Inner layer 6)

[0053] The inner layer portion 6 is formed by laminating a plurality of internal dielectric layers 4 and internal electrode layers 5 .

[0054] (Inner dielectric layer 4)

[0055] Internal dielectric layer 4 is composed of a dielectric material. For example, the dielectric material may be a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, the dielectric material may be a material containing these main components with minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds added thereto. A dielectric material containing BaTiO3 as a main component is particularly preferred.

[0056] The thickness of the internal dielectric layer 4 is preferably not less than 0.5 μm and not more than 15 μm. The number of internal dielectric layers 4 stacked is preferably not less than 10 and not more than 700. The number of internal dielectric layers 4 is the sum of the number of dielectric layers of the inner layer portion 11 and the number of dielectric layers of the first outer layer portion 7A and the second outer layer portion 7B.

[0057] (Internal electrode layer 5)

[0058] The internal electrode layers 5 include a plurality of first internal electrode layers 5A and a plurality of second internal electrode layers 5B. The first internal electrode layers 5A and the second internal electrode layers 5B are arranged alternately. In the case where there is no need to distinguish between the first internal electrode layers 5A and the second internal electrode layers 5B, they are collectively described as the internal electrode layers 5.

[0059] The thickness of each of the first internal electrode layer 5A and the second internal electrode layer 5B is preferably 0.2 μm to 2.0 μm, for example. The total number of the first internal electrode layers 5A and the second internal electrode layers 5B is preferably 10 to 700.

[0060] The first internal electrode layer 5A and the second internal electrode layer 5B are formed of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 5A and the second internal electrode layer 5B may also contain, for example, an Ag-Pd alloy.

[0061] The first internal electrode layer 5A includes a first opposing portion 5Aa that opposes the second internal electrode layer 5B, and a first lead portion 5Ab that extends from the first opposing portion 5Aa toward the first end face C1. The end of the first lead portion 5Ab is exposed at the first end face C1 and is electrically connected to the first external electrode 3A, described below. The second internal electrode layer 5B includes a second opposing portion 5Ba that opposes the first internal electrode layer 5A, and a second lead portion 5Bb that extends from the second opposing portion 5Ba toward the second end face C2. The end of the second lead portion 5Bb is electrically connected to the second external electrode 3B, described below.

[0062] Charges are stored in the first opposing portion 5Aa of the first internal electrode layer 5A and the second opposing portion 5Ba of the second internal electrode layer 5B, thereby functioning as a capacitor.

[0063] The shapes of the first opposing portion 5Aa and the second opposing portion 5Ba are not particularly limited, but a rectangular shape is preferred. However, rounded corners may be formed at the corners of the rectangular shape, and the corners of the rectangular shape may also be formed obliquely. The shapes of the first lead-out portion 5Ab and the second lead-out portion 5Bb are not particularly limited, but a rectangular shape is preferred. However, rounded corners may be formed at the corners of the rectangular shape, and the corners of the rectangular shape may also be formed obliquely.

[0064] (outer layer portion 7)

[0065] The outer layer portion 7 may also be made of the same dielectric ceramic material as the internal dielectric layer 4 of the inner layer portion 6.

[0066] (lateral spacing portion 8)

[0067] The laminate 2 has a first lateral spacing portion 8A disposed on the first side surface B1 side of the inner layer portion 6 and a second lateral spacing portion 8B disposed on the second side surface B2 side of the inner layer portion 6. In addition, when it is not necessary to particularly distinguish between the first lateral spacing portion 8A and the second lateral spacing portion 8B for description, they are uniformly described as the lateral spacing portion 8.

[0068] In Figure 3 In the cross-section shown, in the first lateral spacing portion 8A, the dimension W4 in the width direction W on the first main surface A1 side in the stacking direction T and the dimension W6 in the width direction W on the second main surface A2 side are substantially equal. Moreover, the dimension W5 in the width direction W at the central portion in the stacking direction T is the smallest. That is, compared with the dimension W4 in the width direction W on the first main surface A1 side in the stacking direction T and the dimension W6 in the width direction W on the second main surface A2 side, the dimension W5 in the width direction W at the central portion in the stacking direction T is smaller. However, the rate of change in the width direction W of the dimension of the first lateral spacing portion 8A in the stacking direction T is within 5%, so compared with the difference in the width direction W of the dimension of the second lateral spacing portion 8B described below, it is only a little bit, and it can be considered to be substantially fixed.

[0069] On the other hand, the dimension in the width direction W of the second lateral spacing portion 8B gradually increases from the central portion in the stacking direction T toward the second main surface A2 side. That is, when the dimension in the width direction W at the central portion in the stacking direction T is set as W2 and the dimension in the width direction W at the end portion on the second main surface A2 side in the stacking direction T is set as W3, W2 < W3, and from the central portion in the stacking direction T with the dimension in the width direction W being W2 toward the end portion on the second main surface A2 side in the stacking direction T with the dimension in the width direction W being W3, the dimension gradually increases from W2 to W3.

[0070] Furthermore, in the present embodiment, in the second lateral spacing portion 8B, when the dimension in the width direction W of the end portion on the first main surface A1 side in the stacking direction T is set to W1, W1 < W2 < W3, and the dimension gradually increases from W1 through W2 to W3 from the end portion on the first main surface A1 side in the stacking direction T toward the second main surface A2 side in the stacking direction T.

[0071] The maximum dimension in the width direction W of the second lateral spacing portion 8B is 1.5 times or more the minimum dimension in the width direction W of the second lateral spacing portion 8B. In the embodiment, the maximum dimension in the width direction W of the second lateral spacing portion 8B is W3, the minimum dimension in the width direction W of the second lateral spacing portion 8B is W1, and 1.5W1 < W3.

[0072] Here, the dimension in the width direction W connecting the outer surfaces of the first lateral spacing portion 8A and the second lateral spacing portion 8B (that is, the dimension in the width direction W of the inner layer portion 6) may be substantially equal on the first main surface A1 side and the second main surface A2 side in the stacking direction T. That is, the dimension W7 in the width direction W of the inner layer portion 6 on the first main surface A1 side may also be substantially equal to the dimension W8 in the width direction W of the inner layer portion 6 on the second main surface A2 side. Here, as long as the difference between the above-mentioned dimension W7 and dimension W8 is within 5%, it can be considered substantially equal. The rate of change in the dimension in the width direction W of the inner layer portion 6 along the stacking direction may also be 5% or less. Regarding the dimension in the width direction W of the inner layer portion 6, as long as the rate of change along the stacking direction is within 5%, it can be considered substantially fixed along the stacking direction.

[0073] In addition, W1 to W8, which are dimensions in the width direction W, and T1 and T2, which are dimensions in the stacking direction T, can be measured by the following method, that is, by grinding to expose the cross-section as shown in Figure 3 and then using a digital microscope to measure the exposed cross-section as the measurement object.

[0074] (External electrode 3)

[0075] The external electrode 3 includes a first external electrode 3A provided on the first end face C1 of the laminate 2 and a second external electrode 3B provided on the second end face C2 of the laminate 2. In addition, when it is not necessary to particularly distinguish between the first external electrode 3A and the second external electrode 3B for explanation, they are uniformly described as the external electrode 3. The external electrode 3 not only covers the end face C, but also covers a part of the end face C side of the main surface A and the side surface B.

[0076] The external electrode 3 respectively includes a base electrode layer 3a and a plating layer 3b disposed outside the base electrode layer 3a.

[0077] (Base electrode layer 3a)

[0078] The foundation electrode layer 3 a is electrically connected to the end portions of the lead portion 5Ab and the lead portion 5Bb of the internal electrode layer 5 exposed at the end surface C.

[0079] The base electrode layer 3a is a sintered layer. The sintered layer preferably contains either a metal component and a glass component or a ceramic component, or both. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as that of the internal dielectric layer 4, or a different type of ceramic material may be used. The ceramic component includes, for example, at least one selected from BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc. The main component metal of the base electrode layer 3a is preferably Cu.

[0080] The sintered layer is, for example, a sintered layer obtained by applying a conductive paste containing glass and metal to the laminate 2 and sintering it. The sintered layer can be formed by simultaneously sintering a pre-sintered laminate chip (a raw material for the laminate 2) having multiple internal electrodes and dielectric layers, and the conductive paste applied to the laminate chip. Alternatively, the sintered layer can be formed by sintering the laminate 2 to obtain the laminate 2, and then applying a conductive paste to the laminate 2 and sintering it. In the above-mentioned formation method, the sintered layer is preferably formed by sintering a paste to which a ceramic material has been added instead of the glass component. In this case, it is particularly preferred to use the same type of ceramic material as the internal dielectric layer 4 as the added ceramic material. The sintered layer can also be a plurality of layers.

[0081] The thickness of the foundation electrode layer 3 a provided on the end surface C in the longitudinal direction L is preferably about 2 μm or more and 220 μm or less in the center portion in the stacking direction T and the width direction W of the foundation electrode layer 3 a .

[0082] Regarding the thickness of the base electrode layer 3a provided on the main surface A (the thickness in the normal direction relative to the main surface A), in the central part of the base electrode layer 3a provided on the main surface A in the length direction L and the width direction W, for example, it is preferably greater than 4 μm and less than 40 μm.

[0083] Regarding the thickness of the base electrode layer 3a provided on the side surface B (the thickness in the normal direction relative to the side surface B), in the central portion in the longitudinal direction L and the stacking direction T of the base electrode layer 3a provided on the side surface B, it is preferably, for example, greater than 4 μm and less than 40 μm.

[0084] (Conductive resin layer)

[0085] A conductive resin layer may be disposed on the base electrode layer. The conductive resin layer contains a resin component and a metal component. The conductive resin layer comprises a thermosetting resin. The inclusion of a thermosetting resin makes the conductive resin layer softer than the base electrode layer. The ends of the conductive resin layer preferably contact the laminate 2.

[0086] The conductive resin layer functions as a buffer layer. Therefore, when warping stress is applied to the mounting substrate and physical impact is applied to the multilayer ceramic capacitor 1 due to this stress, cracks are less likely to form in the multilayer ceramic capacitor 1. Furthermore, when impacts due to thermal cycling are applied to the multilayer ceramic capacitor 1, cracks are less likely to form in the multilayer ceramic capacitor 1.

[0087] The thermosetting resin contained in the conductive resin layer can be a thermosetting resin such as epoxy resin, phenolic resin, urethane resin, silicone resin, or polyimide resin. Among these resins, epoxy resin is one of the most suitable resins. Epoxy resin has excellent heat resistance, moisture resistance, and adhesion.

[0088] The conductive resin layer preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the thermosetting resin, the curing agent can be a compound such as a phenol, an amine, an acid anhydride, an imidazole, an active ester, or an amide imide.

[0089] As described above, the conductive resin layer contains a metal component. This metal component allows the conductive resin layer to conduct electricity. The metal component in the conductive resin layer acts as a metal filler. The thickness of the conductive resin layer is preferably 10 μm to 150 μm.

[0090] Alternatively, the base electrode layer 3a may be omitted. Furthermore, the base electrode layer can be a thin film layer. If the base electrode layer is a thin film layer, the thin film layer can be formed using a thin film formation method such as sputtering or vapor deposition. The formed thin film layer is a layer in which metal particles are deposited. The thickness of the thin film layer is preferably 1 μm or less.

[0091] (Plating layer 3b)

[0092] The plating layer 3 b includes a Ni plating layer 3 b 1 and a Sn plating layer 3 b 2 .

[0093] (Ni plating layer 3b1)

[0094] The Ni plating layer 3b1 is disposed on the base electrode layer. The Ni plating layer 3b1 covers at least a portion of the base electrode layer. The Ni plating layer 3b1 prevents the base electrode layer and the like from being corroded by solder when the multilayer ceramic capacitor 1 is mounted.

[0095] (Sn plating layer 3b2)

[0096] The Sn plating layer 3b2 is disposed on the Ni plating layer 3b1. The Sn plating layer 3b2 covers at least a portion of the Ni plating layer 3b1.

[0097] Sn plating layer 3b2 has good solder wettability. Sn plating layer 3b2 facilitates mounting of multilayer ceramic capacitor 1 on a substrate, etc. The thickness of each of Ni plating layer 3b1 and Sn plating layer 3b2 is preferably 1 μm to 15 μm.

[0098] (Method for Manufacturing Multilayer Ceramic Capacitor 1)

[0099] Next, an example of a method for manufacturing the multilayer ceramic capacitor 1 will be described. Regarding the multilayer ceramic capacitor 1 of the embodiment, the method for manufacturing the multilayer ceramic capacitor 1 is not limited as long as the above requirements are met. However, a preferred manufacturing method includes the following steps. Figure 4 1 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1 . Figure 5A 1 is a diagram showing a plurality of ceramic green sheets 14 before lamination in a method of manufacturing the multilayer ceramic capacitor 1 . Figure 5B It is a cross-sectional view of a mother block 20 in which a plurality of ceramic green sheets 14 are stacked.

[0100] (Ceramic Green Sheet Production Process S1)

[0101] First, a ceramic slurry containing ceramic powder, a binder, and a solvent is applied in a sheet-like form on a carrier film to produce the ceramic green sheet 14 .

[0102] Next, conductive paste 15 containing metal powder, binder, plasticizer, dispersant and other additives, organic solvent and the like is printed on ceramic green sheet 14 by screen printing, inkjet printing, gravure printing or the like to form a stripe pattern.

[0103] Here, as described above, in the second side spacers 8B of the manufactured multilayer ceramic capacitor 1 according to the embodiment, Figure 3 As shown, the dimension increases gradually from the dimension W1 in the width direction W of the end portion on the first main surface A1 side in the stacking direction T to the second main surface A2 side in the stacking direction T, from W1 to W2 to W3. Moreover, the maximum dimension W3 in the width direction W of the second lateral spacer 8B is 1.5 times or more the minimum dimension W1 in the width direction W of the second lateral spacer 8B (1.5W1 <W3)。

[0104] Furthermore, in the first side spacer 8A of the multilayer ceramic capacitor 1, as shown in FIG. Figure 3 As shown, the dimension in the width direction W of the end portion on the first principal surface A1 side in the stacking direction T is W4, the dimension in the width direction W of the end portion on the second principal surface A2 side in the stacking direction T is W6, which is approximately equal to W4, and the dimension in the width direction W of the central portion in the stacking direction T is W5, which is smaller than W4 and W6. However, the rate of change in the dimension in the width direction W of the first lateral spacer 8A of the multilayer ceramic capacitor 1 in the stacking direction T is within 5%. Therefore, it is only slightly different from the change in the dimension in the width direction W of the second lateral spacer 8B. Furthermore, W4 is approximately equal to W1.

[0105] To manufacture such a multilayer ceramic capacitor 1 , the conductive paste 15 printed on the surfaces of the ceramic green sheets 14 is printed so that the size in the width direction W gradually decreases from the ceramic green sheet 14 t on the first main surface A1 side to the ceramic green sheet 14 d on the second main surface A2 side. Figure 5A The plurality of ceramic green sheets 14 are shown in which the conductive paste 15 is printed so that the width (ie, the dimension in the width direction W) gradually decreases from the first main surface A1 side toward the second main surface A2 side.

[0106] Regarding the ceramic green sheet 14t located closest to the first main surface A1 in the inner layer portion 6, the dimension of the conductive paste 15 in the width direction is the largest, that is, the gap between adjacent conductive pastes 15 in the width direction W is the smallest, approximately W1+W4 (the gap becomes W1+W4 after firing).

[0107] Regarding the ceramic green sheet 14 m located substantially in the center of the first and second principal surfaces A1 and A2 , the gap between adjacent conductive pastes 15 in the width direction W is substantially W2 + W5 (the gap becomes W2 + W5 after firing).

[0108] Regarding the ceramic green sheet 14d located closest to the second main surface A2 in the inner layer portion 6, the dimension in the width direction between the conductive pastes 15 is the smallest, that is, the gap between adjacent conductive pastes 15 in the width direction W is the largest, approximately W3+W6 (the gap becomes W3+W6 after firing).

[0109] (Lamination Step S2)

[0110] The ceramic green sheets 14 on which the conductive paste 15 is printed are stacked so that the conductive paste 15 is shifted by half a pitch between the ceramic green sheets 14 adjacent in the stacking direction T in the longitudinal direction L.

[0111] On the other hand, the ceramic green sheets 14 printed with the conductive paste 15 are stacked as shown in FIG. Figure 5BAs shown, in the width direction W, between the ceramic green sheets 14 adjacent in the stacking direction T, one end of the conductive paste 15 in the width direction W ( Figure 5B The left ends of the conductive pastes 15 are located at approximately the same position in the width direction W.

[0112] If so, the other end ( Figure 5B The conductive paste 15 (in the middle) gradually deviates to the left in the figure in the width direction W as it goes from top to bottom, and the line connecting the right ends becomes an inclined straight line.

[0113] (Master Block Formation Step S3)

[0114] On both sides of the stacked ceramic green sheets 14 in the stacking direction T, a ceramic green sheet 17A for the outer layer portion to be the first outer layer portion 7A and a ceramic green sheet 17B for the second outer layer portion 7B are stacked and thermocompression bonded to form a Figure 5B The mother block 20 is shown.

[0115] At this time, the multilayer ceramic capacitor 1 is pressed in the stacking direction T, causing the center portion of the inner layer portion 6 in the center portion in the stacking direction T to slightly extend in the width direction. As a result, the dimension of the first side spacer 8A in the center portion in the stacking direction T in the width direction W becomes W5, which is slightly smaller than W4 and W6. However, the rate of change in the stacking direction T of the dimension of the first side spacer 8A in the width direction W of the multilayer ceramic capacitor 1 is within 5%, and therefore can be considered to be substantially uniform compared to the change in the dimension of the second side spacer 8B in the width direction W.

[0116] (Master block cutting step S4)

[0117] Next, the mother block 20 is cut at regular intervals in the width direction W and the length direction L by a cutting blade 21 so as to have a predetermined size.

[0118] Figure 5B This figure explains a state where the mother block 20 is cut in the width direction W. In the width direction W, the cutting blade 21 is moved between adjacent conductive pastes 15 from the first main surface A1 side toward the second main surface A2 side, thereby cutting the mother block 20 .

[0119] At this time, on the ceramic green sheet 14t closest to the first main surface A1, the cutting blade 21 is positioned approximately in the center between adjacent conductive pastes 15, with a gap of approximately W1 + W4 (W1 ≈ W4). However, as the cutting blade 21 moves downward from the top, its position may gradually deviate from the center. In most cases, this deviation occurs in a fixed direction.

[0120] Here, unlike the embodiment, if the spacing between adjacent conductive pastes 15 in all ceramic green sheets 14 (i.e., the width of the side spacing portion) is equal, then as the cutting knife 21 gradually moves from top to bottom, it is possible that it deviates from the center between the conductive pastes 15 and gradually approaches the conductive paste 15 on one side.

[0121] The adhesive force between the conductive paste 15 and the ceramic green sheets 14 is weaker than that between directly stacked ceramic green sheets 14. Therefore, if the downward movement of the cutting blade 21 exerts a downward force on the conductive paste 15, the ceramic green sheet 14 printed with the conductive paste 15 may separate from the stacked ceramic green sheet 14, causing delamination. Furthermore, since delamination occurs at this point, the ultimately manufactured multilayer ceramic capacitor 1 also suffers from delamination.

[0122] However, in an embodiment, the ceramic green sheets 14 printed with the conductive paste 15 are stacked so that, in the width direction W, between the ceramic green sheets 14 adjacent in the stacking direction T, the left ends of the conductive paste 15 in the width direction W are in the same position in the width direction W, and the right ends of the conductive paste 15 in the width direction W deviate little by little toward the left in the figure in the width direction W as one moves from top to bottom, and the spacing between adjacent conductive pastes 15 gradually increases from top to bottom, and the line connecting the ends of the conductive paste 15 in the width direction W becomes inclined.

[0123] Therefore, in the mother block cutting step S4 , the mother block 20 is oriented so that the line connecting the ends of the conductive paste 15 in the width direction W is inclined, which is a direction in which the cutting blade 21 may deviate.

[0124] Thus, even if the cutting blade 21 deviates from the center of the conductive paste 15 as it moves downward, the cutting blade 21 is less likely to approach the conductive paste 15, making delamination less likely to occur.

[0125] In addition, in order to avoid interlayer peeling, it is also possible to consider widening the gap between adjacent conductive pastes 15 in the width direction W to the left and right directions in the figure, and making the lower side in the cutting direction wider than the upper side, so that the cutting knife 21 can move obliquely in any direction from the center of the conductive paste 15.

[0126] However, in recent years, multilayer ceramic capacitors have been required to be smaller and have higher capacitance. Consequently, if the width of the side spacers increases downward on both the left and right sides in the width direction W, the width of the lower conductive paste 15 (internal electrode layer) becomes significantly narrower, which is counterproductive to achieving higher capacitance.

[0127] In the multilayer ceramic capacitor 1 of the embodiment, since the width of one of the side spacing portions in the width direction W is fixed, the width of the lower conductive paste 15 (internal electrode layer) can be made wider than in the case where the width of the side spacing portion becomes wider toward the lower side on both sides in the width direction W.

[0128] That is, the multilayer ceramic capacitor 1 of the embodiment can minimize the decrease in capacitance and can avoid delamination between layers.

[0129] (External electrode forming step S5)

[0130] External electrodes 3 are formed at both ends of each laminate 2 manufactured by cutting the mother block 20 in this way.

[0131] (Firing step S6)

[0132] Then, at a set firing temperature, it is heated in a nitrogen atmosphere for a given time, whereby the external electrodes 3 are baked onto the laminate 2 to manufacture Figure 1 the multilayer ceramic capacitor shown in 1.

[0133] As described above, according to the present invention, it is possible to provide a multilayer ceramic capacitor that maintains capacitance and reduces the possibility of delamination between layers.

[0134] As described above, the embodiments of the present invention have been described, but the present invention is not limited to the foregoing embodiments, and various changes and modifications can be made as follows. Figure 6A And Figure 6B is a diagram showing the multilayer ceramic capacitor 1 of a modification example of the present invention.

[0135] In the above embodiment, in the second side spacing portion 8B, the dimension in the width direction W of the end portion on the first main surface A1 side in the stacking direction T is W1 (W1 < W2 < W3), and from the end portion on the first main surface A1 side in the stacking direction T toward the second main surface A2 side in the stacking direction T, the dimension gradually increases from W1 to W3.

[0136] However, it is not limited thereto, as long as the dimension in the width direction W of the second side spacing portion 8B gradually increases from the central portion in the stacking direction T toward the second main surface A2 side, it may be, for example, as Figure 6A shown, the dimension from the end portion on the first main surface A1 side in the stacking direction T to the central portion is the same W2.

[0137] In addition, in the above embodiment, the position in the width direction W of the other end portion in the width direction W of the conductive paste 15 is gradually deviated little by little from top to bottom, and the line connecting this end portion is an inclined straight line.

[0138] However, this is not limited to the above. As long as the dimension of the second side spacer 8B in the width direction W gradually increases from the center in the stacking direction T toward the second main surface A2, the straight line connecting the ends of the internal electrode layers may also be as shown in FIG. Figure 6B Bend as shown.

[0139] In addition, the following various changes and modifications are possible.

[0140] <1>

[0141] A laminated ceramic electronic component comprises a laminate and external electrodes.

[0142] The laminated body has:

[0143] An inner layer portion having an inner electrode layer and an inner dielectric layer stacked thereon;

[0144] The first main surface and the second main surface are opposite to each other in the stacking direction;

[0145] The first end face and the second end face are opposite to each other in a longitudinal direction intersecting the stacking direction;

[0146] The first side surface and the second side surface are opposite to each other in a width direction intersecting the stacking direction and the longitudinal direction;

[0147] two outer layer portions, arranged on both sides of the inner layer portion in the stacking direction;

[0148] a first lateral partition located on the first side surface of the inner portion; and

[0149] The second side partition is located on the second side surface of the inner layer portion.

[0150] The external electrodes are respectively arranged on the first end surface and the second end surface,

[0151] in,

[0152] The dimensions of the inner layer portion in the width direction are substantially equal on the first main surface side and the second main surface side in the stacking direction.

[0153] In a cross section passing through the stacking direction and the width direction at the center in the longitudinal direction,

[0154] The dimensions of the first side spacer in the width direction are substantially equal on the first main surface side and the second main surface side in the stacking direction.

[0155] A dimension of the second side spacer in the width direction gradually increases from a central portion in the stacking direction toward the second main surface.

[0156] <2>

[0157] according to <1> The multilayer ceramic electronic component, wherein:

[0158] A variation rate of a dimension of the first side spacer in the width direction along the stacking direction is 5% or less.

[0159] <3>

[0160] according to <1> or <2> The multilayer ceramic electronic component, wherein:

[0161] A dimension of the second side spacer in the width direction gradually increases from the first main surface toward the second main surface.

[0162] <4>

[0163] according to <1> to <3> The multilayer ceramic electronic component according to any one of claims , wherein

[0164] A maximum dimension of the second side spacer in the width direction is 1.5 times or more of a minimum dimension of the second side spacer in the width direction.

Claims

1. A multilayer ceramic electronic component comprising a multilayer body and external electrodes. The laminated body has: An inner layer portion having an inner electrode layer and an inner dielectric layer stacked thereon; The first main surface and the second main surface are opposite to each other in the stacking direction; The first end face and the second end face are opposite to each other in a longitudinal direction intersecting the stacking direction; The first side surface and the second side surface are opposite to each other in a width direction intersecting the stacking direction and the longitudinal direction; two outer layer portions, arranged on both sides of the inner layer portion in the stacking direction; a first lateral partition located on the first side surface of the inner portion; and The second side partition is located on the second side surface of the inner layer portion. The external electrodes are respectively arranged on the first end surface and the second end surface, in, The dimensions of the inner layer portion in the width direction are substantially equal on the first main surface side and the second main surface side in the stacking direction. In a cross section passing through the stacking direction and the width direction at the center in the longitudinal direction, The dimensions of the first side spacer in the width direction are substantially equal on the first main surface side and the second main surface side in the stacking direction. A dimension of the second side spacer in the width direction gradually increases from a central portion in the stacking direction toward the second main surface.

2. The multilayer ceramic electronic component according to claim 1, wherein A variation rate of a dimension of the first side spacer in the width direction along the stacking direction is 5% or less.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein A dimension of the second side spacer in the width direction gradually increases from the first main surface toward the second main surface.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein A maximum dimension of the second side spacer in the width direction is 1.5 times or more of a minimum dimension of the second side spacer in the width direction.

Images