Semiconductor element, semiconductor device, and method for manufacturing semiconductor element

Abstract

The embodiment of the invention provides a semiconductor element, a semiconductor device and a method for manufacturing the semiconductor element, wherein the risk of quality reduction caused by burrs is reduced. A semiconductor element according to an embodiment includes a semiconductor layer having a circuit pattern formed on a front surface thereof, an electrode layer disposed on a back surface of the semiconductor layer, and a cover layer covering a back surface of the electrode layer, a side surface of the semiconductor layer, and a side surface of the electrode layer.

Description

[0001] Related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2024-032278 (filing date: March 4, 2024), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor element, a semiconductor device, and a method for manufacturing a semiconductor element. Background Art

[0004] Semiconductor devices manufactured using lead frames include MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), FRD (Fast Recovery Diode), etc. In these semiconductor devices, semiconductor elements are mounted on the lead frame.

[0005] In the manufacturing process of these semiconductor devices, burrs may be generated on the side or back surface of the semiconductor device during the singulation process from the wafer. If such burrs generated in the semiconductor device are left untreated, there is a risk of reducing the quality of the semiconductor device. Summary of the Invention

[0006] Embodiments of the present invention provide a semiconductor element, a semiconductor device, and a method for manufacturing a semiconductor element in which the risk of quality degradation due to burrs is reduced.

[0007] The semiconductor element of this embodiment includes a semiconductor layer having a circuit pattern formed on the front surface, an electrode layer arranged on the back surface of the semiconductor layer, and a covering layer covering the back surface of the electrode layer and the side surfaces of the semiconductor layer and the side surfaces of the electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment.

[0009] Figure 2 It is a cross-sectional view of a semiconductor element according to an embodiment.

[0010] Figure 3A It is a diagram for explaining a manner of heating a semiconductor element according to an embodiment.

[0011] Figure 3B It is a diagram illustrating a method of cooling a semiconductor element according to an embodiment.

[0012] Figure 4 This is a flowchart showing the flow of a method for manufacturing a semiconductor device according to an embodiment.

[0013] Figure 5A It is a diagram for explaining the arrangement process in the method for manufacturing a semiconductor element.

[0014] Figure 5B yes Figure 5A A cross-sectional view along line VV in region R.

[0015] Figure 6A It is a diagram for explaining a covering step in a method for manufacturing a semiconductor element.

[0016] Figure 6B yes Figure 6A A cross-sectional view along line VI-VI in region R.

[0017] Figure 7A It is a diagram for explaining the second dicing step in the method for manufacturing a semiconductor element.

[0018] Figure 7B yes Figure 7A A cross-sectional view taken along line VII-VII in region R.

[0019] Figure 8 This is a cross-sectional view of a semiconductor element according to Modification 1.

[0020] Figure 9 This is a cross-sectional view of a semiconductor element according to Modification 2. DETAILED DESCRIPTION

[0021] The following describes embodiments of the present invention with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the ratios of the various components may not necessarily correspond to actual components. In the specification and drawings, elements identical to those previously described in connection with the accompanying drawings are denoted by the same reference numerals, and detailed descriptions are omitted as appropriate.

[0022] Furthermore, terms such as “parallel” and “identical” used in this specification to specify shapes, geometric conditions, and their degrees are not to be strictly defined but are to be interpreted to encompass a range in which the same function can be expected.

[0023] <Implementation Method>

[0024] (1. Semiconductor Device 1)

[0025] Reference Figures 1 and 2 , a semiconductor device 1 according to an embodiment will be described. Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment. Figure 2 It is a cross-sectional view of a semiconductor element according to an embodiment.

[0026] like Figures 1 and 2 As shown, the semiconductor device 1 of this embodiment includes a lead frame 10 , a semiconductor element 20 , and a bonding material 30 .

[0027] The lead frame 10 has a frame main surface 11. The frame main surface 11 serves as a region (mounting region) where the semiconductor element 20 is mounted via a bonding material 30. The lead frame 10 may also have leads and the like (not shown).

[0028] like Figure 2 As shown, the semiconductor element 20 includes a semiconductor layer 21 having a circuit pattern formed on the front surface 21a, an electrode layer 22 arranged on the back surface 21c of the semiconductor layer 21, and a covering layer 23 covering the back surface 22b of the electrode layer 22, the semiconductor layer 21 and the side surfaces 22a of the electrode layer 22.

[0029] In the semiconductor device 1, the electrode layer 22 of the semiconductor element 20 is bonded to the lead frame 10 via the bonding material 30. As an example, the semiconductor element 20 may be square in plan view or rectangular in plan view.

[0030] In this embodiment, the semiconductor element 20 is an IGBT. The type of the semiconductor element 20 is not particularly limited, and for example, the semiconductor element 20 may be a MOSFET, an FRD, or the like.

[0031] The semiconductor layer 21 includes a p-type semiconductor region and an n-type semiconductor region formed according to the type of semiconductor element 20. The semiconductor layer 21 is, for example, a semiconductor layer composed of a semiconductor including any one of silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). When silicon is used as the material for the semiconductor layer 21, arsenic, phosphorus, or antimony, for example, is used as an n-type impurity, and boron, for example, is used as a p-type impurity. In addition, the semiconductor layer 21 can be an epitaxial layer, a semiconductor substrate formed by singulating a wafer, or a combination of an epitaxial layer and a semiconductor substrate.

[0032] In this embodiment, the electrode layer 22 is a collector of the IGBT. In this case, the surface of the semiconductor layer 21 that is in contact with the electrode layer 22 is a p-type semiconductor region.

[0033] The bonding material 30 bonds the semiconductor element 20 to the lead frame 10. Various materials such as solder and conductive paste can be used as the bonding material 30. Figure 1 In the embodiment, the bonding material 30 is wider than the semiconductor element 20 in the lateral direction, but the present invention is not limited thereto. The bonding material 30 may also have the same width as the semiconductor element 20 .

[0034] Next, the electrode layer 22 will be described in detail. Figure 1 as well as Figure 2 As shown, burrs (protrusions) 24 are formed on at least one of the side surface 22a and the back surface 22b of the electrode layer 22. As an example, the burrs 24 are formed so as to surround the back surface 22b.

[0035] In addition, if Figure 2 As shown, in this embodiment, the outer side surface 24a of the burr 24 is flush with the side surface 21b of the semiconductor layer 21. In other words, the outer side surface 24a and the side surface 21b are located on the same plane. In more detail, the side surface 22a of the electrode layer 22 includes the outer side surface 24a of the burr 24, and the side surface 22a is flush with the side surface 21b of the semiconductor layer 21. On the other hand, the inner side surface 24b of the burr 24 intersects with the outer side surface 24a at an acute angle, and is shaped so as to move away from the front end toward the inner side (the central side of the back surface 22b). In more detail, the lateral length of the burr 24 increases as it moves from the front end of the burr 24 toward the back surface 22b. As described later, the burr 24 is formed during cutting and therefore has such a shape.

[0036] The covering layer 23 covers the back surface 22b of the electrode layer 22, the side surface 21b of the semiconductor layer 21, and the side surface 22a of the electrode layer 22. In other words, the covering layer 23 covers the burrs 24. The covering layer 23 is made of a different metal material from that of the electrode layer 22. If the material of the electrode layer 22 is a first metal material and the material of the covering layer 23 is a second metal material, the Young's modulus of the second metal material is higher than that of the first metal material. Furthermore, metals tend to have a lower linear expansion coefficient as their Young's modulus increases, and the linear expansion coefficient of the second metal material is lower than that of the first metal material.

[0037] The first metal material includes, for example, aluminum, silver, or both. As an example, in this embodiment, the first metal material is primarily aluminum. The second metal material includes, for example, nickel, copper, or both. As an example, in this embodiment, the second metal material is primarily nickel.

[0038] Reference Figure 3A and Figure 3B , thermal expansion of the semiconductor element 20 will be described. Figure 3A This is a diagram for explaining how to heat the semiconductor element 20. Figure 3AAs shown, when semiconductor element 20 is heated, forces that cause expansion act on electrode layer 22 and cover layer 23. Since cover layer 23 is made of a metal with a higher Young's modulus (or a lower linear expansion coefficient) than electrode layer 22, the thermal expansion coefficient of cover layer 23 is lower than that of electrode layer 22. Therefore, the strain P1 caused by the expansion of cover layer 23 due to heating is smaller than the strain P2 caused by the expansion of electrode layer 22. As a result, the expansion of electrode layer 22 that would otherwise occur is hindered or reduced by cover layer 23.

[0039] Figure 3B 1 is a diagram illustrating a method of cooling a semiconductor element according to an embodiment of the present invention. Figure 3B As shown, when semiconductor element 20 is cooled, forces acting to contract act on electrode layer 22 and cover layer 23. Since cover layer 23 is made of a metal with a higher Young's modulus (or a lower linear expansion coefficient) than electrode layer 22, the thermal expansion coefficient of cover layer 23 is lower than that of electrode layer 22. Therefore, the strain P3 caused by contraction in cover layer 23 due to cooling is smaller than the strain P4 caused by contraction in electrode layer 22. As a result, the contraction that would otherwise occur in electrode layer 22 is prevented or reduced by cover layer 23.

[0040] (2. Manufacturing Method)

[0041] Reference Figures 4 to 7B , a method for manufacturing the semiconductor element 20 according to the embodiment will be described. Figure 4 1 is a flow chart showing the process of the method for manufacturing the semiconductor element 20. Figure 4 As shown, the method for manufacturing the semiconductor element 20 includes a wafer preparation step ( S100 ), a first dicing step ( S200 ), an arrangement step ( S300 ), a covering step ( S400 ), and a second dicing step ( S500 ).

[0042] In the wafer preparation step (S100), a wafer having a circuit pattern formed on the front surface and an electrode layer on the back surface is prepared. As an example, the wafer can be prepared by performing the mask manufacturing step, wafer manufacturing step, and pre-processing (circuit pattern formation and electrode formation) in the semiconductor manufacturing process.

[0043] In the first dicing step (S200), the wafer prepared in the wafer preparation step (S100) is diced into a plurality of semiconductor elements 40. The first dicing step (S200) forms burrs 24 on at least one of the side surface and the back surface of the electrode layer 22 of the semiconductor element 40.

[0044] In the arrangement step (S300), a plurality of semiconductor elements 40 are arranged in a planar manner with the back surface facing upward and spaced apart from each other. Figure 5AAs shown, a plurality of semiconductor elements 40 are arranged in a planar manner on a dicing tape 100 .

[0045] Figure 5B yes Figure 5A The VV line cross-sectional view in the region R. Figure 5B As shown, by performing the arrangement step ( S300 ), the plurality of semiconductor elements 40 are arranged in a planar manner with the electrode layer 22 facing upward.

[0046] In the covering step (S400), the gaps formed between the back surfaces of the plurality of semiconductor elements 40 and the respective semiconductor elements 40 are covered with the covering material 50. Specifically, Figure 6A As shown, the plurality of semiconductor elements 40 arranged in a planar shape on the dicing tape 100 are entirely covered with a covering material 50. The covering material 50 is a second metal material and, as an example, includes nickel, copper, or both.

[0047] Figure 6B yes Figure 6A The VI-VI line cross-sectional view in the figure. Figure 6B As shown, by performing the covering step ( S400 ), the burrs 24 formed on at least one of the side surface and the back surface of the electrode layer 22 of the semiconductor element 40 are also covered with the covering material 50 .

[0048] In the second cutting step (S500), the gaps between the plurality of semiconductor elements 40 are cut and cut. Figure 7A As shown, the gaps between the plurality of semiconductor elements 40 (in Figure 7A The cover material 50 is cut off from above (shown by a dotted line).

[0049] Figure 7B yes Figure 7A The VII-VII line cross-sectional view in FIG. Figure 7B As shown, by performing the second dicing step ( S500 ), the plurality of semiconductor elements 40 covered with the cover material 50 are singulated, and the semiconductor element 20 having the cover layer 23 on the back surface can be obtained.

[0050] (3. Summary)

[0051] As described above, the semiconductor element 20 of this embodiment includes a semiconductor layer 21 having a circuit pattern formed on the front surface, an electrode layer 22 arranged on the back surface of the semiconductor layer 21, and a covering layer 23 covering the back surface of the electrode layer 22 and the sides of the semiconductor layer 21 and the electrode layer 22. By having such a structure, during the manufacturing process of the semiconductor element 20, burrs that may be generated on the side or back surface of the semiconductor element 20 can be covered by the covering layer 23, and the risk of quality degradation caused by the burrs can be reduced. In addition, as described above, the influence of thermal expansion can be reduced, so when the semiconductor element 20 is chip-bonded or when it is installed as a semiconductor chip, a reduction in warping can be expected. In addition, in the above embodiment, a semiconductor device that performs frame bonding is exemplified, but it is not limited to this method. The technical ideas in the above embodiment can also be applied to semiconductor devices with packages such as LGA (Land Grid Array).

[0052] (4. Modification 1)

[0053] Reference Figure 8 , a modification example 1 of the above embodiment is described. In modification example 1, the electrode layer 22 has a first layer 22A including a first metal material and a second layer 22B including a second metal material different from the first metal material. As an example, the first metal material may also use a metal with a low Young's modulus and a high linear expansion coefficient, such as aluminum, silver, etc. In addition, the second metal material may also use a metal with a high Young's modulus and a low linear expansion coefficient, such as nickel, copper, etc. In this way, the technical idea of ​​the present disclosure can also be applied to existing semiconductor elements in which the electrode layer 22 is multilayer, and the same effect as the above embodiment can be obtained.

[0054] (5. Modification 2)

[0055] Reference Figure 9 , a modification example 2 of the above embodiment is described. In modification example 2, an insulating covering layer 26 containing an insulating material is formed instead of the covering layer 23 in the above embodiment. As an example, the insulating material contains a resin material. Specifically, as the resin material of the insulating covering layer 26, a granular epoxy resin composition for semiconductor sealing can be used. By adopting such a structure, the same effect as the above embodiment can be obtained, and the electrode layer 22 is covered with an insulating material, so that the conduction between the electrode layer 22 and the pad electrode (not shown) arranged on the front surface 21a of the semiconductor layer 21 can be suppressed. Furthermore, it is possible to suppress the ionized substances that may be generated in the semiconductor device 1 from interfering with the semiconductor layer 21 or the electrode layer 22.

[0056] Several embodiments of the present invention have been described above, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the scope of the invention and its equivalents as described in the claims. In addition, the above-mentioned embodiments can also be implemented in combination with each other.

[0057] The present invention includes the following aspects.

[0058] (Note 1)

[0059] A semiconductor device comprising:

[0060] a semiconductor layer having a circuit pattern formed on the front surface;

[0061] an electrode layer, disposed on the back side of the semiconductor layer; and

[0062] The covering layer covers the back surface of the electrode layer and the side surfaces of the semiconductor layer and the electrode layer.

[0063] (Note 2)

[0064] The semiconductor device according to Supplementary Note 1, wherein the electrode layer comprises a first metal material,

[0065] The cover layer includes a second metal material different from the first metal material.

[0066] (Note 3)

[0067] The semiconductor device according to Supplementary Note 2, wherein the Young's modulus of the second metal material is higher than the Young's modulus of the first metal material.

[0068] (Note 4)

[0069] The semiconductor element according to Supplementary Note 1, wherein the electrode layer includes a first layer containing a first metal material and a second layer containing a second metal material different from the first metal material.

[0070] (Note 5)

[0071] The semiconductor element according to Supplementary Note 1, wherein the cover layer includes a resin material.

[0072] (Note 6)

[0073] The semiconductor element according to any one of Supplementary Notes 1 to 5, wherein a protrusion is formed on at least one of a side surface and a back surface of the electrode layer,

[0074] The covering layer covers the protrusion.

[0075] (Note 7)

[0076] A semiconductor device comprising:

[0077] lead frame; and

[0078] Semiconductor components are arranged on a lead frame.

[0079] The semiconductor element has:

[0080] a semiconductor layer having a circuit pattern formed on the front surface;

[0081] an electrode layer, disposed on the back side of the semiconductor layer; and

[0082] The covering layer covers the back surface of the electrode layer and the side surfaces of the semiconductor layer and the electrode layer.

[0083] (Note 8)

[0084] A method for manufacturing a semiconductor element comprises the following steps:

[0085] A wafer having a circuit pattern formed on the front surface and an electrode layer on the back surface is cut to form a plurality of semiconductor elements;

[0086] Arrange the plurality of semiconductor elements in a planar manner with the back surfaces facing upward and at intervals therebetween;

[0087] covering the back surface and the gap with a covering material; and

[0088] Cutting is performed by cutting the gap.

[0089] (Note 9)

[0090] The method for manufacturing a semiconductor element according to Supplementary Note 8, wherein a protrusion is formed on at least one of a side surface and a back surface of the electrode layer,

[0091] The step of covering the back surface and the gap with a covering material includes covering the protrusion with the covering material.

Claims

1. A semiconductor device comprising: a semiconductor layer having a circuit pattern formed on the front surface; an electrode layer, disposed on the back side of the semiconductor layer; and The covering layer covers the back surface of the electrode layer and the side surfaces of the semiconductor layer and the electrode layer.

2. The semiconductor element according to claim 1, wherein The electrode layer comprises a first metal material, The cover layer includes a second metal material different from the first metal material.

3. The semiconductor element according to claim 2, wherein The Young's modulus of the second metal material is higher than that of the first metal material.

4. The semiconductor element according to claim 1, wherein The electrode layer includes a first layer including a first metal material and a second layer including a second metal material different from the first metal material.

5. The semiconductor element according to claim 1, wherein The cover layer includes a resin material. The semiconductor element according to claim 1 , wherein A protrusion is formed on at least one of the side surface and the back surface of the electrode layer. The covering layer covers the protrusion.

7. A semiconductor device comprising: lead frame; and Semiconductor components are arranged on a lead frame. The semiconductor element has: a semiconductor layer having a circuit pattern formed on the front surface; an electrode layer, disposed on the back side of the semiconductor layer; as well as The covering layer covers the back surface of the electrode layer and the side surfaces of the semiconductor layer and the electrode layer.

8. A method for manufacturing a semiconductor device, comprising the following steps: A wafer having a circuit pattern formed on the front surface and an electrode layer on the back surface is cut to form a plurality of semiconductor elements; Arrange the plurality of semiconductor elements in a planar manner with the back surfaces facing upward and at intervals therebetween; covering the back surface and the gap with a covering material; as well as Cutting is performed by cutting the gap.

9. The method for manufacturing a semiconductor element according to claim 8, wherein: A protrusion is formed on at least one of the side surface and the back surface of the electrode layer. The step of covering the back surface and the gap with a covering material includes covering the protrusion with the covering material.

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