Semiconductor device

Abstract

According to one embodiment, a semiconductor device has a first terminal and a second terminal in which a first groove portion is formed through a top surface thereof. Further, the semiconductor device has a first transistor having a first drain electrode electrically connected to the first terminal, a first source electrode, and a nitride semiconductor layer, and disposed in the first groove portion. In addition, the semiconductor device includes a second transistor having a second drain electrode electrically connected to the second terminal and a second source electrode electrically connected to the first source electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Japanese patent application No. 2024-032212, filed on March 4, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments described herein generally relate to a semiconductor device. Background Art

[0004] Power semiconductors, including GaN transistors using gallium nitride (GaN), are already known. GaN transistors enable high-speed switching and are used in power conversion devices. Because these power semiconductors handle large amounts of electrical energy, heat dissipation measures are crucial. Summary of the Invention

[0005] The embodiment provides a semiconductor device, thereby improving heat dissipation performance.

[0006] One embodiment provides a semiconductor device, including:

[0007] First terminal;

[0008] a second terminal having a first groove portion formed through a top surface thereof;

[0009] a first transistor provided in the first recessed portion, the first transistor having a first drain electrode electrically connected to the first terminal, a first source electrode, and a nitride semiconductor layer;

[0010] The second transistor has a second drain electrode electrically connected to the second terminal and a second source electrode electrically connected to the first source electrode.

[0011] One embodiment provides a semiconductor device, including:

[0012] First terminal;

[0013] Second terminal;

[0014] a first transistor as a gallium nitride transistor mounted in a first recess formed through a top surface of the second terminal, the first transistor having a first drain electrode and a first source electrode electrically connected to the first terminal through a first bonding wire; and

[0015] A second transistor is mounted on the second terminal through a conductive bonding material, the second transistor having a second drain electrode electrically connected to the second terminal through the conductive bonding material and a second source electrode electrically connected to the first source electrode through a second bonding wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 1 is an example of a block diagram of a semiconductor device according to the first embodiment.

[0017] Figure 2 is an example of a circuit diagram of the semiconductor device according to the first embodiment.

[0018] Figure 3 is a plan view of the semiconductor device according to the first embodiment.

[0019] Figure 4 For the Figure 3 A schematic cross-sectional view of the semiconductor device taken along line AA is shown.

[0020] Figure 5 This is an example of the heat dissipation structure of the semiconductor device according to the first embodiment.

[0021] Figure 6 FIG. 4 is a plan view of a semiconductor device according to a second embodiment.

[0022] Figure 7 For the Figure 6 The schematic cross-sectional view of the semiconductor device taken along line BB is shown. DETAILED DESCRIPTION

[0023] The embodiment provides a semiconductor device, thereby improving heat dissipation performance.

[0024] In summary, according to one embodiment, a semiconductor device includes a first terminal and a second terminal, wherein a first recess is formed through the top surface of the first terminal. The semiconductor device also includes a first transistor, which has a first drain electrode electrically connected to the first terminal, a first source electrode, and a nitride semiconductor layer, and is disposed in the first recess. Furthermore, the semiconductor device includes a second transistor, which has a second drain electrode electrically connected to the second terminal and a second source electrode electrically connected to the first source electrode.

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In this description, identical parts are given identical reference symbols throughout the drawings.

[0026] The present disclosure is not limited to the embodiments, and the dimensional ratios of the drawings are not limited to the ratios shown in the drawings.

[0027] First embodiment

[0028] Figure 11 is a block diagram showing a configuration of a semiconductor device 1 according to a first embodiment. The semiconductor device according to the first embodiment is a power semiconductor, which can be used in a power conversion device such as an inverter or a converter.

[0029] The semiconductor device 1 includes a configuration such that a plurality of semiconductor chips are collected in one package. Figure 1 As shown, the semiconductor device 1 includes a switch unit 10 and a control unit 50. By switching, the switch unit 10 converts input direct current (DC) power into an alternating current (AC) signal and outputs the signal. The control unit 50 controls the switching operation of the switch unit 10.

[0030] Next, we will refer to Figure 2 A circuit configuration of the semiconductor device according to the embodiment is described.

[0031] Figure 2 1 is a circuit diagram showing an exemplary circuit configuration of a semiconductor device according to the embodiment. Figure 2 As shown, the semiconductor device 1 includes a first terminal 11, a second terminal 12, a gallium nitride (GaN) transistor 30, and a MOS transistor 20. The GaN transistor 30 and the MOS transistor 20 are connected in cascade between the first terminal 11 and the second terminal 12. The GaN transistor 30 is an example of a first transistor. The MOS transistor 20 is an example of a second transistor.

[0032] The GaN transistor 30 comprises a normally-on high electron mobility transistor (HEMT), which is in an on state when no signal is input to its gate. That is, when the potential difference between its gate and its source is 0V, its drain terminal and its source terminal are electrically connected.

[0033] The MOS transistor 20 is a metal oxide semiconductor field effect transistor (MOSFET) made of, for example, silicon. The MOS transistor 20 according to the first embodiment has a normally-off characteristic and is a p-type MOSFET. That is, when the potential difference between its gate and its source is 0 V, its drain terminal and its source terminal are electrically isolated.

[0034] Next, we will pass Figure 3 and Figure 4 The internal structure of the semiconductor device 1 according to the first embodiment is described.

[0035] Figure 3 is a top view showing an exemplary internal structure of the semiconductor device 1 according to the first embodiment, Figure 4 is shown along Figure 3 The schematic cross-sectional view of the semiconductor device is shown along line AA, with the control unit 50 omitted.

[0036] according to Figure 3 The GaN transistor 30 and the MOS transistor 20 are provided on the second terminal 12, and the first terminal 11, the GaN gate terminal 14, the source control terminal 15, and the MOS gate terminal 16 are provided on the same plane as the second terminal 12. Here, the source control terminal 15, for example, determines a reference potential for the voltage applied by the GaN gate terminal 14 and the MOS gate terminal 16. The GaN gate terminal 14 is an example of a first gate terminal, and the MOS gate terminal 16 is an example of a second gate terminal.

[0037] The first terminal 11 , the second terminal 12 , the GaN gate terminal 14 , the source control terminal 15 , and the MOS gate terminal 16 are formed using a lead frame made of metal.

[0038] Here, the plane where the lead frame is located is the XY plane, and the direction intersecting the XY plane and extending from the bottom surface to the top surface of the GaN transistor 30 and the MOS transistor 20 is the +Z direction or the upward direction.

[0039] In the lead frame lying in the XY plane, the direction extending from the second terminal 12 toward the first terminal 11 is the +Y direction. For example, the first terminal 11 is spaced apart from the second terminal 12 so that their ends face each other in the Y direction. In this case, the GaN gate terminal 14, the source control terminal 15, and the MOS gate terminal 16 are arranged parallel to each other in the Y direction.

[0040] There is also an X direction perpendicular to the Y direction. The direction extending from the GaN gate terminal 14, the source control terminal 15, and the MOS gate terminal 16 toward the second terminal 12 is the +X direction. The GaN gate terminal 14, the source control terminal 15, and the MOS gate terminal 16 are, for example, provided separately from the second terminal 12 so that their ends face each other in the X direction.

[0041] Here, the connection relationship of each terminal will be described.

[0042] First, the GaN gate terminal 14 , the source control terminal 15 , and the MOS gate terminal 16 are connected to, for example, the control unit 50 , which is a gate drive circuit or the like.

[0043] The GaN gate terminal 14 is connected to the GaN transistor 30 , and the source control terminal 15 is connected to both the GaN transistor 30 and the MOS transistor 20 . The MOS gate terminal 16 is connected to the MOS transistor 20 .

[0044] Furthermore, the GaN transistor 30 is electrically connected to the MOS transistor 20 . Based on control of the GaN gate terminal 14 , the source control terminal 15 , and the MOS gate terminal 16 , current flows from the first terminal 11 to the second terminal 12 via the GaN transistor 30 and the MOS transistor 20 .

[0045] Next, the configuration of the GaN transistor will be described.

[0046] like Figure 4 As shown, the GaN transistor 30 includes a first drain electrode 32 , a first source electrode 33 , a substrate 31 , and a first semiconductor layer 40 disposed on the substrate 31 .

[0047] The substrate 31 is, for example, a silicon substrate, and has an electrical resistance of, for example, 1 mΩ / cm or more and 1 Ω / cm or less.

[0048] The first semiconductor layer 40, for example, having a double-layer structure, has a heterojunction structure including a first nitride semiconductor layer 41 and a second nitride semiconductor layer 42. The first nitride semiconductor layer 41 is disposed on the substrate 31, and the second nitride semiconductor layer 42 is disposed on the first nitride semiconductor layer 41. The band gap of the second nitride semiconductor layer 42 is larger than the band gap of the first nitride semiconductor layer 41. For example, the first nitride semiconductor layer 41 is an undoped GaN layer, while the second nitride semiconductor layer 42 is an AlGaN layer. A two-dimensional electron gas is formed near the boundary between the first nitride semiconductor layer 41 and the second nitride semiconductor layer 42.

[0049] The first semiconductor layer 40 has a thickness of, for example, 5 μm or less, and the substrate 31 has a thickness of approximately 200 μm.

[0050] A first drain electrode 32 and a first source electrode 33 are provided on the first semiconductor layer 40 . The first drain electrode 32 and the first source electrode 33 are in contact with the second nitride semiconductor layer 42 . Figure 3 The illustrated first gate electrode 34 is provided on an insulating film (not shown) in a region on the second nitride semiconductor layer 42 . Figure 3 The first gate electrode 34 in the embodiment may extend into the region between the first drain electrode 32 and the first source electrode 33 .

[0051] like Figure 3 As shown, the GaN gate terminal 14 is connected to a first gate electrode 34 of the GaN transistor 30 , and controls driving of the GaN transistor 30 according to a gate voltage applied to the GaN transistor 30 .

[0052] The first drain electrode 32 of the GaN transistor 30 is electrically connected to the first terminal 11 through a plurality of first conductive lines 300 .

[0053] The first source electrode 33 of the GaN transistor 30 is electrically connected to the second source electrode 23 through a plurality of second wires 301 .

[0054] The GaN gate terminal 14 and the first gate electrode 34 of the GaN transistor 30 are also electrically connected to each other via a third wire 302 .

[0055] The first source electrode 33 of the GaN transistor 30 and the source control terminal 15 are also electrically connected to each other through the fourth wire 303 .

[0056] The conductive lines include, for example, bonding wires formed of conductive wires.

[0057] like Figure 3 and 4 As shown, the GaN transistor 30 is provided on a bonding material 45 such as a resin in a recess U formed via the top surface 12a of the second terminal 12. The recess U is an example of a first recess. The bonding material 45 is an example of a first bonding material.

[0058] A conductive material such as solder may also be used as the bonding material 45 .

[0059] The size of the recess portion U is equal to or larger than the size of the GaN transistor 30 so that the entire GaN transistor 30 can be accommodated therein.

[0060] Here, a height h1 from the bottom surface 12 e of the recess portion U to the top surface 12 a of the second terminal 12 represents the depth of the recess portion U. In the present embodiment, the height h1 is formed to be smaller than the thickness of the substrate 31 of the GaN transistor 30 .

[0061] That is, the bottom surface of the first semiconductor layer 40 is located above the top surface 12a of the second terminal 12. For example, when the thickness of the second terminal 12 is 500 μm and the thickness of the substrate 31 of the GaN transistor 30 is 200 μm, the height h1 of the recess U is less than 200 μm.

[0062] The bonding material 45 may be applied so as to cover the bottom surface and side surfaces of the substrate 31 of the GaN transistor 30 .

[0063] In addition, in the thickness direction of the second terminal 12, the distance from the bottom surface 12e of the groove portion U to the top surface 12a of the second terminal 12 is smaller than the thickness of the portion of the substrate 31. This allows the first semiconductor layer 40 and the bonding material 45 to be separated from each other. When the bonding material 45 is a conductive material such as solder, the risk of an electrical short circuit between the first semiconductor layer 40 and the second terminal 12 is reduced.

[0064] The groove portion U may be formed by a press process using a molding die or the like, or by an etching process using metal corrosion or the like.

[0065] Next, the configuration of the MOS transistor 20 will be described.

[0066] like Figure 4 As shown, the MOS transistor 20 is mounted on the second terminal 12 and has a second semiconductor layer 21 and a second drain electrode 22 arranged on the bottom surface of the second semiconductor layer 21. The second drain electrode 22 is bonded to the second terminal 12 by a conductive bonding material 46 such as solder. The bonding material 46 is an example of a second bonding material. The second drain electrode 22 is electrically connected to the second terminal 12. The MOS transistor 20 has a second source electrode 23 and a second gate electrode 24 on the other side of the second semiconductor layer 21 opposite to the second drain electrode 22 in the thickness direction. The second semiconductor layer 21 is, for example, a silicon layer and includes a p-type channel. The MOS transistor 20 is a vertical device in which current flows along the thickness direction of the second semiconductor layer 21 (the vertical direction connecting the second drain electrode 22 and the second source electrode 23). The channel of the MOS transistor 20 formed in the second semiconductor layer 21 can be formed in the horizontal direction or in the depth direction.

[0067] like Figure 3 As shown, the second source electrode 23 of the MOS transistor 20 and the source control terminal 15 are electrically connected via a fifth wire 304. The second gate electrode 24 of the MOS transistor 20 and the MOS gate terminal 16 are electrically connected via a sixth wire 305. The MOS gate terminal 16 controls the driving of the MOS transistor 20 according to the magnitude of the gate voltage applied to the MOS transistor 20.

[0068] The first source electrode 33 of the GaN transistor 30 is electrically connected to the second source electrode 23 . In addition, the first source electrode 33 of the GaN transistor 30 is electrically connected to the second terminal 12 through the MOS transistor 20 .

[0069] In this embodiment, the GaN transistor 30 is housed in the recess U of the second terminal 12. Therefore, the heights of the first drain electrode 32, the first source electrode 33, and the first gate electrode 34 in the Z direction are reduced. In this embodiment, the thickness of the first drain electrode 32 and the thickness of the first source electrode 33 are substantially the same.

[0070] In this embodiment, Figure 4As shown, the arch height h2 of the first wire 300 connecting the first drain electrode 32 and the first terminal 11 can be smaller than the arch height h3 of the second wire 301 connecting the first source electrode 33 and the second source electrode 23. A smaller arch height is conducive to reducing the size of the component, and the arch height is determined by the distance between the starting point of the wire and the end point of the wire and the height difference between them. The arch height h2 is the vertical distance between the highest position of the bend of the first wire 300 and the first source electrode 32. The arch height h3 is the vertical distance between the highest position of the bend of the second wire 301 and the first source electrode 33. In this embodiment, the highest position of the first wire 300 is below the highest position of the second wire 301.

[0071] The semiconductor device 1 constituting the above-described internal structure has a structure sealed by a sealing resin (not shown).

[0072] Next, we will pass Figure 5 The heat dissipation structure of the semiconductor device 1 according to the present embodiment will be described.

[0073] Figure 5 This is a schematic cross-sectional view showing the heat dissipation structure of semiconductor device 1. GaN transistor 30 is mounted in semiconductor device 1. Because GaN transistor 30 is subject to a large amount of electrical energy, cooling measures to mitigate heat generation are essential. A main substrate 70, on which semiconductor device 1 is mounted, is bonded to a heat sink 73 via an intermediate material 72, such as a thermal interface material (TIM).

[0074] The main substrate 70 is provided with heat dissipation through holes 71 extending from the front surface to the back surface of the main substrate 70 , so as to transfer heat from the semiconductor device 1 to the heat sink 73 .

[0075] A cooling method for a semiconductor device may be an air cooling method or a water cooling method using a heat sink or a heat pipe, but is not limited to this example.

[0076] In such Figure 5 In the case of the cooling method shown, the heat generated by semiconductor device 1 is dissipated along the following path: the heat is transferred from the bottom surface of semiconductor device 1 through heat dissipation vias 71, intermediate material 72, and heat sink 73 in this order, and is ultimately dissipated from heat sink 73. In other words, the heat generated in GaN transistor 30 is dissipated along the above-described heat dissipation path via main surface 12 b of second terminal 12 exposed on the bottom surface of semiconductor device 1.

[0077] According to the semiconductor device 1 of the present embodiment, the recess portion U for accommodating the GaN transistor 30 is formed in the region of the second terminal 12 .

[0078] Due to the recess U, heat is transferred to the main surface 12b not only from the bottom surface 12e in the recess U but also from the side surface 12c. Thus, a semiconductor device with high reliability in terms of heat dissipation performance and electrical characteristics can be obtained. The side surface 12c is perpendicular to the bottom surface 12e of the recess U at the peripheral edge of the bottom surface 12e.

[0079] Furthermore, since the distance h4 from the bottom surface of the GaN transistor 30 to the main surface 12 b is smaller than the thickness of the second terminal 12 , thermal resistance can be reduced compared to a structure in which the recess portion U is not provided.

[0080] In addition, as in the semiconductor device 1 according to the present embodiment, the semiconductor device using the GaN transistor 30 has high-speed switching characteristics, and therefore is greatly affected by parasitic inductance.

[0081] Because the GaN transistor 30 is housed in the recess U, as in the semiconductor device 1 according to this embodiment, the height of the first drain electrode 32 of the GaN transistor 30 in the Z direction is reduced. Consequently, the arch height h2 of the first wire 300 connecting the first drain electrode 32 and the first terminal 11 is reduced. As a result, the wire length between the first drain electrode 32 and the first terminal 11 is shortened, which means that the parasitic inductance of the wire is reduced.

[0082] Since the GaN transistor 30 is accommodated in the recess portion U provided in the second terminal 12 , heat dissipation performance and electrical characteristics can be improved.

[0083] Furthermore, the recess U prevents positional deviation of the GaN transistor 30 during mounting and restricts diffusion of the bonding material 45. This reduces the distance between components, which means that component size can be reduced and high-density mounting can be achieved.

[0084] Second embodiment

[0085] Next, a second embodiment will be described. Figure 6As shown, the second embodiment differs from the first embodiment in that a recessed portion P for accommodating the MOS transistor 20 is further provided. The recessed portion P is an example of a second recessed portion. The configuration of the semiconductor device 1 of the second embodiment is the same as that of the semiconductor device 1 of the first embodiment, except for the recessed portion P and the MOS transistor 20 disposed therein. Like the recessed portion U for accommodating the GaN transistor 30, the size of the recessed portion P is equal to or larger than the size of the MOS transistor 20. When the MOS transistor 20 is in the on state, current flows in the thickness direction of the transistor. In this embodiment, for example, the recessed portion P is formed to have a depth greater than the height of the MOS transistor 20, and is formed so that the side surface 12d of the recessed portion P is separated from the side surface of the MOS transistor 20. The side surface 12d is perpendicular to the bottom surface 12f of the recessed portion P in the peripheral portion of the bottom surface 12f.

[0086] In addition, a structure is adopted in which the MOS transistor 20 is provided on the bottom surface 12f of the recessed portion P via the bonding material 46. In this case, the bonding material 46 is separated from (not in contact with) at least the side surface 12d. Therefore, the risk of an electrical short circuit between the MOS transistor 20 and the second terminal 12 via the bonding material 46 can be reduced.

[0087] The semiconductor device according to this embodiment is configured such that the recess U for accommodating the GaN transistor 30 and the recess P for accommodating the MOS transistor 20 are respectively provided on the second terminal 12. Thus, the heat dissipation performance and electrical characteristics of the GaN transistor 30 and the MOS transistor 20 can be improved, thereby achieving a semiconductor device with higher reliability than that of the first embodiment.

[0088] Since the MOS transistor 20 is accommodated in the recessed portion P, the heat dissipation path in the thickness direction of the second terminal 12 can be shortened, thereby reducing thermal resistance.

[0089] In addition, if Figure 7 As shown, the height h3 of the second wire 301 between the second source electrode 23 of the MOS transistor 20 and the first source electrode 33 of the GaN transistor 30 is reduced. Therefore, the wire length between the second source electrode 23 and the first source electrode 33 is reduced, thereby reducing the parasitic inductance of the wire.

[0090] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes may be made to the embodiments described herein without departing from the spirit of the present disclosure. The appended claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the present disclosure.

Claims

1. A semiconductor device comprising: First terminal; a second terminal having a first groove portion formed through a top surface thereof; a first transistor provided in the first recessed portion, the first transistor having a first drain electrode electrically connected to the first terminal, a first source electrode, and a nitride semiconductor layer; The second transistor has a second drain electrode electrically connected to the second terminal and a second source electrode electrically connected to the first source electrode.

2. The semiconductor device according to claim 1, wherein The first transistor is a normally-on gallium nitride high electron mobility transistor (HEMT), and the second transistor is a normally-off metal oxide semiconductor field effect transistor (MOSFET).

3. The semiconductor device according to claim 1, wherein A first gate terminal of the first transistor, a second gate terminal of the second transistor, and a source control terminal are also provided. The source control terminal is electrically connected to the first source electrode and the second source electrode.

4. The semiconductor device according to claim 3, wherein The first gate terminal is electrically connected to a first gate electrode of the first transistor, and the second gate terminal is electrically connected to a second gate electrode of the second transistor.

5. The semiconductor device according to claim 1, wherein A highest position of a first wire connecting the first terminal and the first drain electrode is located below a highest position of a second wire connecting the first source electrode and the second source electrode. The semiconductor device according to claim 1 , wherein The first groove portion is lined with a first bonding material, and the first transistor is provided on the first bonding material in the first groove portion.

7. The semiconductor device according to claim 1, wherein A distance from a bottom surface of the first groove portion to a top surface of the second terminal in a thickness direction of the second terminal is smaller than a thickness of a portion of a substrate directly below the nitride semiconductor layer of the first transistor. 8 . The semiconductor device according to claim 1 , further comprising a second groove portion in the second terminal, wherein the second transistor is provided in the second groove portion through a second bonding material. 9 . The semiconductor device according to claim 1 , wherein the first recess portion has a sidewall in thermal contact with a side surface of the first transistor.

10. Semiconductor device comprising: First terminal; Second terminal; a first transistor as a gallium nitride transistor mounted in a first recess formed through a top surface of the second terminal, the first transistor having a first drain electrode and a first source electrode electrically connected to the first terminal via a first bonding wire; and A second transistor is mounted on the second terminal via a conductive bonding material, the second transistor having a second drain electrode electrically connected to the second terminal via the conductive bonding material and a second source electrode electrically connected to the first source electrode via a second bonding wire.

11. The semiconductor device according to claim 10, wherein The first transistor is a normally-on high electron mobility transistor (HEMT), and the second transistor is a normally-off metal oxide semiconductor field effect transistor (MOSFET).

12. The semiconductor device according to claim 10, further comprising a first gate terminal, a second gate terminal, and a source control terminal, wherein The source control terminal is electrically connected to the first source electrode through a third bonding wire, and is electrically connected to the second source electrode through a fourth bonding wire.

13. The semiconductor device according to claim 12, wherein The first gate terminal is electrically connected to the first gate electrode of the first transistor through a fifth bonding wire, and the second gate terminal is electrically connected to the second gate electrode of the second transistor through a sixth bonding wire.

14. The semiconductor device according to claim 10, wherein The highest position of the first bonding wire is located below the highest position of the second bonding wire.

15. The semiconductor device according to claim 10, wherein The first groove portion is lined with a bonding material, and the first transistor is provided on the bonding material in the first groove portion.

16. The semiconductor device according to claim 10, wherein A distance from a bottom surface of the first groove portion to a top surface of the second terminal along a thickness direction of the second terminal is smaller than a thickness of a portion of a substrate located directly below the first transistor.

17. The semiconductor device according to claim 10, further comprising a second recessed portion in the second terminal, wherein The second transistor is provided in the second groove portion via the conductive bonding material.

18. The semiconductor device according to claim 10, wherein The first recess portion has a sidewall in thermal contact with a side surface of the first transistor.

19. The semiconductor device according to claim 10, wherein The first source electrode and the first drain electrode are provided on the nitride semiconductor layer of the first transistor.

20. The semiconductor device according to claim 19, wherein The semiconductor layer of the second transistor is located between the second source electrode and the second drain electrode in a thickness direction of the second terminal.

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