Power management circuit
By utilizing power conversion and controllable discharge circuits in the power management circuit, combined with a timing circuit to monitor the capacitance of the energy storage capacitor, the energy reduction problem caused by aging of the energy storage capacitor is solved, ensuring the effectiveness of the backup power supply and the stability of normal functions.
Patent Information
- Application Number
- CN202410224226.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-27
- Publication Date
- 2025-09-05
AI Technical Summary
As energy storage capacitors age, their capacitance decreases and they cannot effectively serve as backup power sources. Existing technologies make it difficult to effectively monitor and reduce the impact on normal functions.
The terminal voltage is converted to a preset energy storage value or an overcharge preset value through a power conversion circuit, and the terminal voltage is reduced at different slopes through a controllable discharge circuit. The capacitance value is monitored in combination with a timing circuit, and the capacitance value is calculated using a formula.
Accurate monitoring of the capacitance of the energy storage capacitor is achieved to ensure that the energy storage capacitor is sufficient to meet the demand in the event of a power failure, reducing the impact on normal functions.
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Figure CN120601552A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a power management circuit. Background Art
[0002] A power management circuit, including a power conversion circuit and an energy storage capacitor, can store energy. The power management circuit controls the power conversion circuit to charge the energy storage capacitor. If a power failure occurs in the system where the power management circuit is located, the energy stored in the energy storage capacitor can be used as a backup power source.
[0003] According to the principle of capacitor energy storage, the energy stored in a storage capacitor is proportional to its capacitance. However, as capacitors age, their capacitance decreases, and their ability to store energy also decreases. In some applications, when the energy stored in a storage capacitor decreases to a certain level, it can no longer serve as a backup power source. Therefore, it is necessary to effectively monitor the capacitance of the storage capacitor and minimize the impact of monitoring on normal function. Summary of the Invention
[0004] The present application provides a power management circuit. The power management circuit includes a power conversion circuit coupled to an energy storage capacitor and a discharge circuit coupled to the energy storage capacitor. The power conversion circuit is configured to convert a bus voltage into a terminal voltage, while the discharge circuit is configured to provide a discharge path for the energy storage capacitor. The power conversion circuit is configured to convert the terminal voltage to a preset energy storage value or to an overcharge preset value, wherein the overcharge preset value is greater than the preset energy storage value.
[0005] The present application provides a power management circuit. The power management circuit includes a power conversion circuit coupled to an energy storage capacitor and a controllable discharge circuit coupled to the energy storage capacitor. The power conversion circuit is configured to convert a bus voltage into a terminal voltage, while the controllable discharge circuit is configured to be coupled to the energy storage capacitor to provide a discharge path for the energy storage capacitor. The controllable discharge circuit causes the terminal voltage to decrease at a first slope or a second slope, where the first slope is different from the second slope. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 FIG. 1 is a schematic diagram of a power management circuit 100 according to an embodiment of the present disclosure.
[0007] Figure 2 FIG. 4 is a terminal voltage waveform diagram of a power management circuit according to an embodiment of the present disclosure.
[0008] Figure 3 FIG. 1 is a schematic diagram of a power management circuit 100 according to an embodiment of the present disclosure.
[0009] Figure 4FIG. 4 is a terminal voltage waveform diagram of a power management circuit according to an embodiment of the present disclosure.
[0010] Figure 5 FIG. 4 is a terminal voltage waveform diagram of a power management circuit according to an embodiment of the present disclosure.
[0011] Figure 6 FIG. 4 is a terminal voltage waveform diagram of a power management circuit according to an embodiment of the present disclosure.
[0012] Figure 7 FIG. 4 is a terminal voltage waveform diagram of a power management circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0013] Specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are intended to illustrate and are not intended to limit the present invention. In the following description, a large number of specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these specific details are not necessarily required to practice the present invention. In other examples, known materials or methods are not specifically described to avoid obscuring the present invention.
[0014] Throughout this specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the present invention. Therefore, appearances of the phrases "in one embodiment," "in an embodiment," "an example," or "an example" in various places throughout this specification do not necessarily refer to the same embodiment or example. Throughout this specification, "coupled" includes both direct and indirect connections. Furthermore, particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples. Furthermore, those skilled in the art will appreciate that the figures provided herein are for illustrative purposes only and are not necessarily drawn to scale. In particular, while the waveform diagrams herein depict voltage values rising or falling relative to a certain amplitude, the magnitude of the rise and fall does not necessarily reflect any proportional relationship to the amplitude. Throughout this specification, identical reference numerals indicate identical elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0015] Reference Attachment Figure 1 The power management circuit 100 includes a power conversion circuit 101 and an energy storage capacitor C coupled thereto. STRG The power conversion circuit 101 can be a boost circuit, a buck circuit, a buck-boost circuit, etc. The energy storage capacitor C STRGIt can be an electrolytic capacitor, a stacked capacitor, a tantalum capacitor, a double-layer capacitor, a polymer capacitor or a battery. As the capacitor ages, the energy storage capacitor C STRG The energy that can be stored also gradually decreases. When the energy that the energy storage capacitor can store decreases to a certain extent, it will no longer be able to serve as a backup power source. For example, when the power management circuit 100 is used to provide power for a non-volatile semiconductor memory, the energy storage capacitor C STRG It is used to provide power-off protection for the memory in the event of a power failure in the system, and is stored in the energy storage capacitor C STRG The energy of the energy storage capacitor C1 should be sufficient to meet the data backup needs. In some cases, if the storage capacitor C1 decreases so that the memory no longer has the backup capability, the memory will be considered to have reached the end of life. For such applications, the energy storage capacitor C1 is usually STRG Set a threshold for the capacitance C1 and monitor the capacitance regularly.
[0016] Please refer to the attached Figure 1 In one embodiment of the present application, the power management circuit 100 includes a power conversion circuit 101, a discharge circuit 102, a timing circuit 103 (not shown) and an energy storage capacitor C STRG The power conversion circuit 101 is coupled to the energy storage capacitor C STRG The input terminal of the power conversion circuit 101 receives the bus voltage VBUS and combines it with the energy storage capacitor C STRG The power conversion circuit 100 is configured to convert the terminal voltage V_strg to the energy storage preset value VS or to convert the terminal voltage to the overcharge preset value V0, wherein the overcharge preset value V0 is greater than the energy storage preset value VS.
[0017] In some embodiments, in normal working mode, the power conversion circuit 101 is connected to the energy storage capacitor C STRG The terminal voltage V_strg is charged to reach the energy storage preset value VS. In the capacitance monitoring mode, the power conversion circuit is configured to convert the terminal voltage V_strg to an overcharge preset value V0, which is greater than the energy storage preset value VS.
[0018] In the normal working mode, the discharge circuit 102 does not work. In the partial time period of the capacitance monitoring mode, the discharge circuit 102 is configured as an energy storage capacitor C STRG Provides a discharge path. Figure 2 The capacitance monitoring period starts at time t0. The power conversion circuit 101 charges the terminal voltage V_strg of the energy storage capacitor to an overcharge preset value V0 exceeding the first threshold voltage V1. Then the power management circuit controls the discharge circuit 102 to discharge the energy storage capacitor C STRGAt this time, the discharge circuit 102 is configured to provide a first constant current I_dis1.
[0019] The power management circuit also senses and compares the terminal voltage V_strg of the energy storage capacitor. During the discharge phase during capacitance monitoring, the terminal voltage V_strg gradually decreases from the overcharge preset value V0, drops to the first threshold voltage V1 at time t1, and drops to the second threshold voltage V2 at time t2. The timing circuit 103 is configured to provide the time T1 it takes for the terminal voltage V_strg to drop from the first threshold voltage V1 to the second threshold voltage V2. In one embodiment, the first threshold voltage VI is greater than the second threshold voltage V2, and the second threshold voltage V2 is greater than the energy storage preset value VS. In another embodiment, the first threshold voltage V1 is greater than the second threshold voltage V2, the first threshold voltage V1 is greater than the energy storage preset value VS, and the second threshold voltage V2 is less than the energy storage preset value VS.
[0020] According to the above embodiment, the energy storage capacitor C STRG After overcharging, discharge and measure the change in terminal voltage during the T1 period. The capacitance C1 can be obtained based on the following formula:
[0021] C1=I_dis1*T1 / (V1-V2) (1)
[0022] In formula (1), I_dis1 is the first constant current value provided by the discharge circuit 102, V1 and V2 are preset voltage values, and T1 is the time it takes for the terminal voltage to drop from the first threshold voltage V1 to the second threshold voltage V2. Through the solution of the present application, these physical quantities can be preset or obtained in the controllable discharge process, and the circuit or module with calculation function can obtain the energy storage capacitor C according to formula (1). STRG Capacitance value.
[0023] As attached Figure 2 As shown, at time t3 when the capacitance monitoring period ends, the terminal voltage V_strg drops to the energy storage preset value VS, the discharge circuit stops working, the power management circuit 100 returns to the normal working mode, and the power conversion circuit 101 converts the terminal voltage V_strg to the energy storage preset value VS. According to this embodiment, during the entire period of the capacitance monitoring mode (t0 to t3), the energy storage capacitor C STRG The terminal voltage V_strg is greater than the preset energy storage value VS. In case of power failure, the energy stored in the energy storage capacitor C STRG of energy is sufficient to meet needs.
[0024] Attachment Figure 3FIG1 shows another embodiment of the present application, wherein the power management circuit 100 includes a power conversion circuit 101, a controllable discharge circuit 102, a timing circuit 103 (not shown) and an energy storage capacitor C. The input terminal of the power conversion circuit 101 receives the bus voltage VBUS and compares it with the energy storage capacitor C. STRG For example, in normal working mode, the power conversion circuit 101 converts the terminal voltage V_strg of the energy storage capacitor C STRG Charging is performed to make its terminal voltage V_strg reach the energy storage preset value VS. Figure 3 Also shown is the energy storage capacitor C STRG It should be noted that the technical solution of this application does not actually set the current source 104 in the circuit. Figure 3 The current source 104 is shown in the figure to be equivalent to the capacitor leakage phenomenon. In this application, the energy storage capacitor C STRG The leakage current is equivalent to a constant current source 104 with a current of I_1kg. In some embodiments, the controllable discharge circuit 102 is coupled to the energy storage capacitor C STRG The controllable discharge circuit causes the terminal voltage to decrease at a first slope or a second slope according to a control signal, wherein the first slope is different from the second slope.
[0025] In some embodiments, the controllable discharge circuit is configured to provide at least a second constant current I_dis2 and a third constant current I_dis3, wherein the second constant current I_dis2 and the third constant current I_dis3 have different magnitudes and are proportional to each other. The power management circuit 100 has a normal operating mode and a capacitance monitoring mode. In the normal operating mode, the controllable discharge circuit 102 does not operate. In the capacitance monitoring mode, the controllable discharge circuit 102 is configured to provide a discharge path for the energy storage capacitor using the second constant current I_dis2 or the third constant current I_dis3 during two capacitance monitoring periods, respectively.
[0026] Reference Attachment Figure 4 In one embodiment, the capacitance monitoring mode includes two capacitance monitoring periods. During the first capacitance monitoring period (t0-t3), the power conversion circuit 101 first converts the terminal voltage V_strg of the energy storage capacitor to a first overcharge value V0 greater than the first threshold voltage V1, and then the power management circuit 100 controls the controllable discharge circuit 102 to discharge the energy storage capacitor C STRG During the discharge phase of the first capacitance period, the controllable discharge circuit 102 is configured to provide a second constant current I_dis2 .
[0027] The power management circuit also senses and compares the terminal voltage V_strg of the energy storage capacitor. During the discharge phase of the first capacitance monitoring period, the terminal voltage V_strg gradually decreases from the first overcharge value V0, drops to the first threshold voltage V1 at time t1, and drops to the second threshold voltage V2 at time t2. The timing circuit 103 is configured to provide the time T1 it takes for the terminal voltage V_strg to drop from the first threshold voltage V1 to the second threshold voltage V2. In one embodiment, the first threshold voltage V1 is greater than the second threshold voltage V2, and the second threshold voltage V2 is greater than the energy storage preset value VS. In another embodiment, the first threshold voltage V1 is greater than the second threshold voltage V2, the first threshold voltage V1 is greater than the energy storage preset value VS, and the second threshold voltage V2 is less than the energy storage preset value VS.
[0028] During the T1 period, considering the leakage current of the energy storage capacitor, the energy storage capacitor C STRG The charge change ΔQ1 on the MOSFET can be expressed as follows:
[0029] ΔQ1=C1*(V1-V2)=(I_dis2+I_1kg)*T1 (2)
[0030] Reference Attachment Figure 4 During the second capacitance monitoring period (t4-t7), the power conversion circuit 101 first converts the terminal voltage V_strg of the energy storage capacitor to a second overcharge value V0' which is greater than the first threshold voltage V1, and then the power management circuit controls the controllable discharge circuit 102 to discharge the energy storage capacitor C STRG During the discharge phase of the second capacitance monitoring period, the controllable discharge circuit 102 provides a third constant current I_dis3, wherein there is a proportional relationship between the second constant current I_dis2 and the third constant current I_dis3, and the ratio is not 1, that is:
[0031] I_dis3=A*I_dis2, where A≠1 (3)
[0032] During the discharge phase of the second capacitance monitoring period, the terminal voltage V_strg gradually decreases from the second overcharge value V0' to the first threshold voltage V1 at time t5 and to the second threshold voltage V2 at time t6. The timing circuit 103 is configured to provide the time T2 it takes for the terminal voltage V_strg to decrease from the first threshold voltage V1 to the second threshold voltage V2 during the second charge and discharge period.
[0033] During the T2 period, considering the leakage current of the energy storage capacitor, the energy storage capacitor C STRG The charge change ΔQ2 on the CMOS can be expressed by the following formula:
[0034] ΔQ2=C1*(V1-V2)=(I_dis3+I_1kg)*T2=(A*I_dis2+I_1kg)*T2(4)
[0035] During the two capacitance monitoring periods, the energy storage capacitor C STRG The change in charge on the capacitor is C1*(V1-V2), so the expression of capacitance C1 can be obtained from equations (2) to (4):
[0036] C1=(A-1)*T1*T2*I_dis2 / (T1-T2)*(V1-V2) (5)
[0037] In formula (5), A is the ratio between the third constant current I_dis3 and the second constant current I_dis2, I_dis2 is the second constant current value provided by the discharge circuit 102, V1 and V2 are preset voltage values, T1 and T2 are the time it takes for the terminal voltage to drop from the first threshold voltage V1 to the second threshold voltage V2. Through the solution of the present application, these physical quantities can be preset or obtained in the controllable discharge process, and the circuit or module with calculation function can obtain the energy storage capacitor C according to formula (5). STRG Capacitance value.
[0038] In the attached Figure 4 In the embodiment, the first overcharge value V0 and the second overcharge value V0' are the same. In other embodiments, the two values may be different.
[0039] The present application also includes another embodiment, in which the first capacitance monitoring period is the same as the attached Figure 4 The difference is that during the discharge phase during the second capacitance monitoring period, the terminal voltage V_strg gradually decreases from the second overcharge value V0', drops to the third threshold voltage V3 (not shown) at time t5, and drops to the fourth threshold voltage V4 (not shown) at time t6. The difference between the first threshold voltage V1 and the second threshold voltage V2 (V1-V2) and the difference between the third threshold voltage V3 and the fourth threshold voltage V4 (V3-V4) are proportional to each other, that is, (V3-V4) = B*(V1-V2). Those skilled in the art can obtain the expression of the capacitance C1 under this embodiment based on the same principle as the above derivation, which will not be repeated here. In one embodiment, the third threshold voltage V3 is greater than the fourth threshold voltage V4, and the fourth threshold voltage is greater than the energy storage preset value VS. In another embodiment, the third threshold voltage V3 is greater than the fourth threshold voltage V4, the third threshold voltage V3 is greater than the energy storage preset value VS, and the fourth threshold voltage V4 is less than the energy storage preset value VS.
[0040] Attachment Figure 5 and attached Figure 6The other embodiments of the present application are shown respectively. The capacitance monitoring mode also includes two capacitance monitoring periods. During one capacitance monitoring period, the power conversion circuit 101 overcharges the terminal voltage V_strg of the energy storage capacitor to the first overcharge value V0. During the other capacitance monitoring period, the energy storage capacitor C STRG It is discharged directly without being overcharged.
[0041] The following is only attached Figure 5 As an example, the capacitance monitoring mode is briefly described. The first capacitance monitoring period (t0~t3) is Figure 4 Therefore, in the T1 period, considering the leakage current of the energy storage capacitor, the energy storage capacitor C STRG The charge change value ΔQ1 on the energy storage capacitor C can still be expressed by formula (1). During the second capacitance monitoring period (t4-t7), the power management circuit controls the controllable discharge circuit 102 to discharge the energy storage capacitor C STRG At this time, the controllable discharge circuit 102 is configured to provide a third constant current I_dis3, wherein there is a proportional relationship between the second constant current I_dis2 and the third constant current I_dis3, and the ratio is not 1. Figure 5 In the embodiment of the present invention, in the case of leakage current in the energy storage capacitor during the T2 period, the energy storage capacitor C STRG The charge change ΔQ2 on the CMOS can be expressed by the following formula:
[0042] ΔQ2=C1*(V3-V4)=(I_dis3+I_1kg)*T2=(A*I_dis2+I_1kg)*T2(6)
[0043] The difference between the first threshold voltage V1 and the second threshold voltage V2 (V1 - V2), and the difference between the third threshold voltage V3 and the fourth threshold voltage V4 (V3 - V4), are proportional: (V3 - V4) = B*(V1 - V2). Those skilled in the art can derive the expression for capacitance C1 in this embodiment using the same principles as described above, and this will not be repeated here.
[0044] In the attached Figure 5 and attached Figure 6 In the embodiment of the present invention, the first threshold voltage V1 and the second threshold voltage V2 can be Figure 6 Setting, that is, the first threshold voltage V1 is greater than the second threshold voltage V2, and the second threshold voltage V2 is greater than the energy storage preset value VS, or according to the attached Figure 5 The setting shown is that the first threshold voltage V1 is greater than the second threshold voltage V2, the first threshold voltage V1 is greater than the energy storage preset value VS and the second threshold voltage V2 is less than the energy storage preset value VS.
[0045] Attachment Figure 7Another embodiment of the present application is shown. In this embodiment, the energy storage capacitor C STRG During part of the first capacitance monitoring period (t0-t3), the controllable discharge circuit 102 is configured to discharge the energy storage capacitor C with the second constant current I_dis2. STRG Provides a discharge path. Considering the leakage current of the energy storage capacitor during the T1 period, the energy storage capacitor C STRG The charge change ΔQ1 on the MOSFET can be expressed as follows:
[0046] ΔQ1=C1*(V3-V4)=(I_dis2+I_lkg)*T1 (7)
[0047] During a portion of the second capacitance monitoring period (t4-t7), the controllable discharge circuit 102 is configured to use the third constant current I_dis3 to discharge the energy storage capacitor C STRG Provides a discharge path. Considering the leakage current of the energy storage capacitor during the T2 period, the energy storage capacitor C STRG The charge change ΔQ2 on the CMOS can be expressed by the following formula:
[0048] ΔQ2=C1*(V3-V4)=(I_dis3+I_lkg)*T2 (8)
[0049] There is a proportional relationship between the second constant current I_dis2 and the third constant current I_dis3, and the ratio is not 1. Those skilled in the art can derive the expression of the capacitance C1 in this embodiment based on the same principle as the above derivation, which will not be repeated here. Figure 7 In the discharge phase between the two capacitance monitoring periods, the timing circuit 103 is configured to provide the time taken for the terminal voltage V_strg to drop from the third threshold voltage V3 to the fourth threshold voltage V4. However, in other embodiments, the timing circuit may be configured to record the time difference T1 between the terminal voltage V_strg reaching the first threshold voltage V1 and the second threshold voltage V2 on the way down from the preset energy storage value VS, and further configured to record the time difference T2 between the terminal voltage V_strg reaching the third threshold voltage V3 and the fourth threshold voltage V4 on the way down from the preset energy storage value VS. The design purpose can be achieved by simply setting the difference (V1-V2) between the first threshold voltage V1 and the second threshold voltage V2 to have a proportional relationship with the difference (V3-V4) between the third threshold voltage V3 and the fourth threshold voltage V4.
[0050] Although the amplitude of the change in the terminal voltage V_strg during the capacitance monitoring period is significant relative to the preset energy storage value VS in the drawings of the present application, it should be understood by those skilled in the art that it can actually be small and moderate. Although the present invention has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present invention can be implemented in various forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be broadly interpreted within the spirit and scope defined by the appended claims, and therefore all changes and modifications that fall within the scope of the claims or their equivalents should be covered by the appended claims.
Claims
1. A power management circuit, comprising: a power conversion circuit configured to be coupled to the energy storage capacitor and configured to convert the bus voltage into a terminal voltage; a discharge circuit configured to be coupled to the energy storage capacitor; The power conversion circuit is configured to convert the terminal voltage to a preset energy storage value or to convert the terminal voltage to an overcharge preset value, and the overcharge preset value is greater than the preset energy storage value.
2. The power management circuit of claim 1, wherein the power management circuit has a normal operating mode and a capacitance monitoring mode. In the normal operating mode, the power conversion circuit is configured to convert the terminal voltage to the energy storage preset value. In the capacitance monitoring mode, the power conversion circuit is configured to convert the terminal voltage to the overcharge preset value.
3. The power management circuit of claim 1 , wherein the power management circuit has a normal operating mode and a capacitance monitoring mode, wherein in the normal operating mode, the discharge circuit does not operate, and in the capacitance monitoring mode, the discharge circuit is configured to provide a discharge path for the energy storage capacitor.
4. The power management circuit of claim 2 , further comprising a timing circuit for recording a time difference between when the terminal voltage reaches a first threshold voltage and when it reaches a second threshold voltage while decreasing from the overcharge preset value, wherein: The first threshold voltage is greater than the second threshold voltage.
5. A power management circuit, comprising: a power conversion circuit configured to be coupled to the energy storage capacitor and configured to convert the bus voltage into a terminal voltage; A controllable discharge circuit is configured to be coupled to an energy storage capacitor to provide a discharge path for the energy storage capacitor, and the controllable discharge circuit causes the terminal voltage to decrease at a first slope or a second slope, wherein the first slope is different from the second slope. 6 . The power management circuit of claim 5 , wherein the controllable discharge comprises a second constant current source and a third constant current source, and the second constant current source and the third constant current source have different sizes and are in a proportional relationship.
7. The power management circuit of claim 5, wherein the power management circuit comprises at least a normal operating mode, wherein the controllable discharge circuit does not operate, and the power conversion circuit converts the terminal voltage into a preset energy storage value.
8. The power management circuit of claim 5, wherein the power management circuit includes at least a capacitance monitoring mode, and the capacitance monitoring mode includes at least a first capacitance monitoring period and a second capacitance monitoring period; the controllable discharge circuit is configured to provide a discharge path for the energy storage capacitor with a second constant current during a portion of the first capacitance monitoring period, and to provide a discharge path for the energy storage capacitor with a third constant current during a portion of the second capacitance monitoring period.
9. The power management circuit of claim 5, wherein the power management circuit includes a capacitance monitoring mode, the capacitance monitoring mode including at least a first monitoring period and a second monitoring period, and during the first capacitance monitoring period, the power conversion circuit is configured to convert the terminal voltage to a first overcharge value.
10. The power management circuit of claim 5, comprising a capacitance monitoring mode, the capacitance monitoring mode comprising at least a first monitoring period and a second monitoring period, wherein during the second capacitance monitoring period, the power conversion circuit is configured to convert the terminal voltage to a second overcharge value.
11. The power management circuit of claim 8 , wherein during the first capacitance monitoring period, the power conversion circuit is configured to convert the terminal voltage to a first overcharge value, and during the second capacitance monitoring period, the power conversion circuit is configured to convert the terminal voltage to a second overcharge value, the power management circuit further comprising a timing circuit for recording a time difference between when the terminal voltage reaches a first threshold voltage and a second threshold voltage while decreasing from the first overcharge value, and for recording a time difference between when the terminal voltage reaches a third threshold voltage and a fourth threshold voltage while decreasing from the second overcharge value, wherein: A difference between the first threshold voltage and the second threshold voltage is a multiple of a difference between the third threshold voltage and the fourth threshold voltage.
12. The power management circuit of claim 9, further comprising a timing circuit for recording a time difference between when the terminal voltage reaches a first threshold voltage and when it reaches a second threshold voltage while decreasing from the first overcharge value during the first capacitance monitoring period, and for recording a time difference between when the terminal voltage reaches a third threshold voltage and when it reaches a fourth threshold voltage while it decreases from the preset energy storage value during the second capacitance monitoring period, wherein: A difference between the first threshold voltage and the second threshold voltage is a multiple of a difference between the third threshold voltage and the fourth threshold voltage.
13. The power management circuit of claim 10 , further comprising a timing circuit for recording a time difference between when the terminal voltage reaches a first threshold voltage and when it reaches a second threshold voltage while decreasing from the preset energy storage value during the first capacitance monitoring period, and for recording a time difference between when the terminal voltage reaches a third threshold voltage and when it reaches a fourth threshold voltage while it decreases from the second overcharge value during the second capacitance monitoring period, wherein: A difference between the first threshold voltage and the second threshold voltage is a multiple of a difference between the third threshold voltage and the fourth threshold voltage.
14. The power management circuit of claim 8, further comprising a timing circuit for recording a time difference between when the terminal voltage reaches a first threshold voltage and when it reaches a second threshold voltage while decreasing from a preset energy storage value during the first capacitance monitoring period, and for recording a time difference between when the terminal voltage reaches a third threshold voltage and when it reaches a fourth threshold voltage while it decreases from the preset energy storage value during the second capacitance monitoring period, wherein: A difference between the first threshold voltage and the second threshold voltage is a multiple of a difference between the third threshold voltage and the fourth threshold voltage. 15 . The power management circuit according to claim 10 , wherein the third threshold voltage is equal to the first threshold voltage, and the fourth threshold voltage is equal to the second threshold voltage.