Driving protection circuit of power semiconductor device

Abstract

According to the driving protection circuit of the power semiconductor device provided by the embodiment of the invention, when a capacitor is under-voltage, a first control signal transmitted by a first control circuit is high level, a first power semiconductor device is conducted, a second power supply charges the capacitor, and a second control signal transmitted by a second control circuit is low level; the second power semiconductor device is cut off so as to carry out under-voltage protection on the second power semiconductor device; and when the capacitor is overvoltage, the first control signal transmitted by the first control circuit is low level, the first power semiconductor device is cut off, and the second power semiconductor device is cut off, so that overvoltage protection is carried out on the second power semiconductor device. According to the embodiment of the invention, the second power semiconductor device is in a cut-off state under the condition that the capacitor voltage is too low or too high, so that the second power semiconductor device is prevented from being affected by abnormal conditions such as overvoltage, overcurrent and short circuit when the driving voltage is too low or too high, and the device is prevented from being damaged or the performance of the second power semiconductor device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a driving protection circuit for a power semiconductor device. Background Art

[0002] Power semiconductors are specialized devices designed to control and convert electrical power. They are widely used in various power electronics systems, such as power management, motor drives, electric vehicles, and renewable energy generation. They efficiently convert electrical energy from one form to another and operate under high voltage and high current conditions. Power semiconductors, such as insulated-gate bipolar transistors (IGBTs), are susceptible to abnormal conditions such as overvoltage, overcurrent, and short circuits, which can lead to device damage or performance degradation. Summary of the Invention In view of the above problems, embodiments of the present invention are proposed to provide a driving protection circuit for a power semiconductor device that overcomes the above problems or at least partially solves the above problems.

[0003] In order to solve the above problem, an embodiment of the present invention discloses a driving protection circuit for a power semiconductor device, comprising a first power semiconductor device, wherein the output terminal of the first power semiconductor device is grounded, and the control terminal is used to receive a first control signal; a first control circuit connected to the control terminal of the first power semiconductor device, and configured to output the first control signal to the control terminal of the first power semiconductor device; a second power semiconductor device, wherein the output terminal of the second power semiconductor device is connected to the input terminal of the first power semiconductor device, the control terminal is used to receive a second control signal, and the input terminal is connected to the first power supply; a second control circuit connected to the control terminal of the second power semiconductor device, and configured to output the second control signal to the control terminal of the second power semiconductor device; a capacitor, one end of which is respectively connected to the first control circuit, the second control circuit, and the second power supply, and the other end of which is respectively connected to the input end of the first power semiconductor device and the output end of the second power semiconductor device; When the capacitor is undervoltage, the first control signal transmitted by the first control circuit is at a high level, the first power semiconductor device is turned on, and the second power supply charges the capacitor; the second control signal transmitted by the second control circuit is at a low level, and the second power semiconductor device is turned off, so as to perform undervoltage protection on the second power semiconductor device; When the capacitor is over-voltage, the first control signal transmitted by the first control circuit is at a low level, the first power semiconductor device is turned off, and the second power semiconductor device is turned off to protect the second power semiconductor device from over-voltage.

[0004] Optionally, the first control circuit includes: a first comparator, wherein a positive input terminal of the first comparator is connected to one end of the capacitor, and a negative input terminal of the first comparator is connected to the second power supply; a first triode, wherein an emitter of the first triode is connected to the output end of the first comparator, and a collector of the first triode is connected to the second power supply; a second transistor, wherein the base of the second transistor is connected to the base of the first transistor, the collector of the second transistor receives the first pulse modulation signal, the emitter of the second transistor is grounded and connected to the control terminal of the first power semiconductor device; the second transistor is used to output the first control signal; When the capacitor is undervoltage, the first comparator outputs a low level, and the first transistor is turned on. When the first pulse modulation signal is high, the second transistor is turned on, and the first control signal output by the second transistor is high. When the capacitor is over-voltage, the first comparator outputs a high level, the first transistor is turned off, and the first control signal output by the second transistor is a low level.

[0005] Optionally, the second control circuit includes: a second comparator, wherein a positive input terminal of the second comparator is connected to the second power supply, and a negative input terminal of the second comparator is connected to the second power supply and the capacitor respectively; a third triode, wherein the emitter of the third triode is connected to the output end of the second comparator, and the collector of the third triode is connected to the second power supply and the capacitor respectively; a fourth transistor, wherein the base of the fourth transistor is connected to the base of the third transistor, the collector of the fourth transistor is connected to the second pulse modulation signal, the emitter of the fourth transistor is grounded and connected to the control terminal of the second power semiconductor device; the fourth transistor is configured to output the second control signal; When the capacitor is undervoltage, the second comparator outputs a high level, and the third transistor is turned off; the second control signal output by the fourth transistor is a low level.

[0006] Optionally, the first power semiconductor device and the second power semiconductor device are IGBTs.

[0007] Optionally, the circuit further includes a diode, the anode of the diode is connected to the second power supply, and the cathode of the diode is respectively connected to the inverting input terminal of the second comparator, the collector of the third transistor and the capacitor.

[0008] Optionally, the circuit further includes: a first resistor, one end of the first resistor being connected to the second power supply, and the other end of the first resistor being connected to the inverting input terminal of the first comparator; a second resistor, one end of the second resistor being connected to the first resistor and the inverting input end of the first comparator respectively, and the other end being grounded.

[0009] Optionally, the circuit further includes: a third resistor, one end of the third resistor being connected to the second power supply, and the other end of the third resistor being connected to the positive input terminal of the second comparator; a fourth resistor, one end of the fourth resistor being connected to the third resistor and the positive input end of the second comparator respectively, and the other end being grounded.

[0010] Optionally, the circuit further includes: a fifth resistor, one end of the fifth resistor being connected to the output end of the first comparator, and the other end of the fifth resistor being connected to the second power supply.

[0011] Optionally, the circuit further includes: a sixth resistor, one end of the sixth resistor being connected to the output end of the second comparator, and the other end of the sixth resistor being connected to the second power supply.

[0012] Optionally, the circuit further includes: a seventh resistor, one end of the seventh resistor being connected to the emitter of the second transistor, and the other end of the seventh resistor being connected to the control end of the first power semiconductor device.

[0013] Optionally, the circuit further includes: an eighth resistor, one end of the eighth resistor being connected to the emitter of the fourth transistor, and the other end of the eighth resistor being connected to the control end of the second power semiconductor device.

[0014] The embodiments of the present invention include the following advantages: A driving protection circuit for a power semiconductor device according to an embodiment of the present invention includes a first power semiconductor device, wherein the output terminal of the first power semiconductor device is grounded, and the control terminal is used to receive a first control signal; a first control circuit is connected to the control terminal of the first power semiconductor device and is used to output the first control signal to the control terminal of the first power semiconductor device; a second power semiconductor device, wherein the output terminal of the second power semiconductor device is connected to the input terminal of the first power semiconductor device, the control terminal is used to receive a second control signal, and the input terminal is connected to a first power source; a second control circuit is connected to the control terminal of the second power semiconductor device and is used to output the second control signal to the control terminal of the second power semiconductor device; a capacitor , one end is respectively connected to the first control circuit, the second control circuit and the second power supply, and the other end is respectively connected to the input end of the first power semiconductor device and the output end of the second power semiconductor device; when the capacitor is undervoltage, the first control signal transmitted by the first control circuit is high, the first power semiconductor device is turned on, the second power supply charges the capacitor, and the second control signal transmitted by the second control circuit is low, the second power semiconductor device is turned off, so as to provide undervoltage protection for the second power semiconductor device; when the capacitor is overvoltage, the first control signal transmitted by the first control circuit is low, the first power semiconductor device is turned off, and the second power semiconductor device is turned off, so as to provide overvoltage protection for the second power semiconductor device. In the embodiment of the present invention, when the capacitor voltage is too low or too high, the second power semiconductor device is in the cut-off state, thereby preventing the second power semiconductor device from being affected by abnormal conditions such as overvoltage, overcurrent, short circuit, etc. when the driving voltage is too low or too high, resulting in device damage or performance degradation. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic structural diagram of a driving protection circuit for a power semiconductor device according to an embodiment of the present invention; Figure 2 It is a structural diagram of another driving protection circuit of a power semiconductor device according to an embodiment of the present invention.

[0016] Figure numerals: first power semiconductor device 10, first control circuit 20, first comparator 21, first transistor 22, second transistor 23, first pulse modulation signal 24, second power semiconductor device 30, first power supply 40, second control circuit 50, second comparator 51, third transistor 52, fourth transistor 53, second pulse modulation signal 54, capacitor 60, second power supply 70, diode 80, first resistor 90, second resistor 91, third resistor 92, fourth resistor 93, fifth resistor 94, sixth resistor 95, seventh resistor 96, eighth resistor 97. DETAILED DESCRIPTION

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] Power semiconductors are specialized devices designed to control and convert electrical power. They are widely used in various power electronics systems, such as power management, motor drives, electric vehicles, and renewable energy generation. They efficiently convert electrical energy from one form to another and operate under high voltage and high current conditions. Power semiconductors, such as insulated-gate bipolar transistors (IGBTs), are susceptible to abnormal conditions such as overvoltage, overcurrent, and short circuits, which can lead to device damage or performance degradation.

[0019] According to the operating characteristics of IGBTs, their drive voltage should be within ±20V. When the drive voltage is below 9V, the IGBT operates in the amplification region, resulting in a large on-state voltage drop. As the drive voltage increases, the saturation on-state voltage drop decreases. Excessively low drive voltages result in a large saturation on-state voltage drop, leading to low efficiency. Drive voltages below 12V can cause severe IGBT overheating. However, excessively high drive voltages shorten the time the IGBT can withstand short circuits and overcurrents, making protection difficult and potentially damaging. The ideal IGBT drive voltage is 15±1V. Therefore, the IGBT's drive protection circuit is crucial to the reliability of the entire operating system.

[0020] One of the core concepts of the embodiments of the present invention is that when the capacitor is undervoltage, the first control signal transmitted by the first control circuit is high, the first power semiconductor device is turned on, the second power supply charges the capacitor, and the second control signal transmitted by the second control circuit is low, the second power semiconductor device is turned off, thereby providing undervoltage protection for the second power semiconductor device; when the capacitor is overvoltage, the first control signal transmitted by the first control circuit is low, the first power semiconductor device is turned off, and the second power semiconductor device is turned off, thereby providing overvoltage protection for the second power semiconductor device. In the embodiments of the present invention, when the capacitor voltage is too low or too high, the second power semiconductor device is in the off state, thereby preventing the second power semiconductor device from being affected by abnormal conditions such as overvoltage, overcurrent, short circuit, etc. when the driving voltage is too low or too high, resulting in device damage or performance degradation.

[0021] Reference Figure 1 , shows a schematic structural diagram of a driving protection circuit for a power semiconductor device according to an embodiment of the present invention, which may specifically include the following structures: The first power semiconductor device 10 has an output terminal connected to the ground, and a control terminal connected to the ground, and is used to receive a first control signal.

[0022] When the first control signal is at a high level, the control end of the first power semiconductor device 10 receives a high level, and the first power semiconductor device 10 is in an on state; when the first control signal is at a low level, the control end of the first power semiconductor device 10 receives a low level, and the first power semiconductor device 10 is in an off state.

[0023] The first control circuit 20 is connected to the control terminal of the first power semiconductor device 10 , and is configured to output a first control signal to the control terminal of the first power semiconductor device 10 .

[0024] The first control circuit 20 is configured to output a first control signal to the control terminal of the first power semiconductor device 10 . The first control signal may be a high level or a low level.

[0025] The second power semiconductor device 30 has an output terminal connected to the input terminal of the first power semiconductor device 10 , a control terminal for receiving a second control signal, and an input terminal connected to the first power source 40 .

[0026] When the second control signal is at a high level, the control end of the second power semiconductor device 30 receives a high level, and when the first power semiconductor device 10 is in the on state, the second power semiconductor device 30 is in the on state; when the second control signal is at a low level, the control end of the second power semiconductor device 30 receives a low level, and the second power semiconductor device 30 is in the off state.

[0027] The first power source 40 connected to the input terminal of the second power semiconductor device 30 is a positive power supply voltage, which can be a high voltage, such as several hundred volts.

[0028] The second control circuit 50 is connected to the control terminal of the second power semiconductor device 30 , and is configured to output a second control signal to the control terminal of the second power semiconductor device 30 .

[0029] The second control circuit 50 is configured to output a second control signal to the control terminal of the second power semiconductor device 30 . The second control signal may be a high level or a low level.

[0030] The capacitor 60 has one end connected to the first control circuit 20 , the second control circuit 50 and the second power supply 70 , and the other end connected to the input end of the first power semiconductor device 10 and the output end of the second power semiconductor device 30 .

[0031] The voltage of the second power supply 70 can be within 10-20 V, which is lower than the voltage of the first power supply 40. When the first power semiconductor device 10 is turned on, the capacitor 60 can be charged through the second power supply 70-capacitor 60-first power semiconductor device 10.

[0032] When the capacitor 60 is undervoltage, the first control signal transmitted by the first control circuit 20 is at a high level, the first power semiconductor device 10 is turned on, the second power supply 70 charges the capacitor 60, and the second control signal transmitted by the second control circuit 50 is at a low level, and the second power semiconductor device 30 is turned off to perform undervoltage protection on the second power semiconductor device 30.

[0033] When the capacitor 60 is over-voltage, the first control signal transmitted by the first control circuit 20 is at a low level, the first power semiconductor device 10 is turned off, and the second power semiconductor device 30 is turned off to protect the second power semiconductor device 30 from over-voltage.

[0034] Before capacitor 60 begins charging, the voltage is very low. The first control signal transmitted by the first control circuit 20 is at a high level, turning on the first power semiconductor device 10 and allowing the second power source 70 to charge capacitor 60. Furthermore, the second control signal transmitted by the second control circuit 50 is at a low level, turning off the second power semiconductor device 30 to provide undervoltage protection for the second power semiconductor device 30. When the second power source 70 charges capacitor 60 to a voltage that is too high, the first control signal transmitted by the first control circuit 20 is at a low level, turning off the first power semiconductor device 10, stopping charging of capacitor 60, and turning off the second power semiconductor device 30. Both the first power semiconductor device 10 and the second power semiconductor device 30 are deactivated, thus providing overvoltage protection for the devices.

[0035] A driving protection circuit for a power semiconductor device according to an embodiment of the present invention includes a first power semiconductor device, wherein the output terminal of the first power semiconductor device is grounded, and the control terminal is used to receive a first control signal; a first control circuit is connected to the control terminal of the first power semiconductor device and is used to output the first control signal to the control terminal of the first power semiconductor device; a second power semiconductor device, wherein the output terminal of the second power semiconductor device is connected to the input terminal of the first power semiconductor device, the control terminal is used to receive a second control signal, and the input terminal is connected to a first power source; a second control circuit is connected to the control terminal of the second power semiconductor device and is used to output the second control signal to the control terminal of the second power semiconductor device; a capacitor , one end is respectively connected to the first control circuit, the second control circuit and the second power supply, and the other end is respectively connected to the input end of the first power semiconductor device and the output end of the second power semiconductor device; when the capacitor is undervoltage, the first control signal transmitted by the first control circuit is high, the first power semiconductor device is turned on, the second power supply charges the capacitor, and the second control signal transmitted by the second control circuit is low, the second power semiconductor device is turned off, so as to provide undervoltage protection for the second power semiconductor device; when the capacitor is overvoltage, the first control signal transmitted by the first control circuit is low, the first power semiconductor device is turned off, and the second power semiconductor device is turned off, so as to provide overvoltage protection for the second power semiconductor device. In the embodiment of the present invention, when the capacitor voltage is too low or too high, the second power semiconductor device is in the cut-off state, thereby preventing the second power semiconductor device from being affected by abnormal conditions such as overvoltage, overcurrent, short circuit, etc. when the driving voltage is too low or too high, resulting in device damage or performance degradation.

[0036] In the embodiment of the present invention, the first power semiconductor device 10 and the second power semiconductor device 30 are IGBTs.

[0037] The output terminal of the first power semiconductor device 10 is the emitter, the input terminal is the collector, and the control terminal is the gate. The same is true for the second power semiconductor device 30. The first power semiconductor device 10 is a bottom-side IGBT, and the second power semiconductor device 30 is a top-side IGBT. The second power semiconductor device 30 requires a capacitor 60 to conduct normally.

[0038] IGBTs are widely used in power electronic devices due to their high efficiency and fast switching characteristics. However, in practical applications, IGBTs are susceptible to abnormal conditions such as overvoltage, overcurrent, and short circuits, which can cause device damage or performance degradation.

[0039] According to the operating characteristics of IGBTs, their drive voltage should be within ±20V. When the drive voltage is below 9V, the IGBT operates in the amplification region, resulting in a large on-state voltage drop. As the drive voltage increases, the saturation on-state voltage drop decreases. Excessively low drive voltages result in a large saturation on-state voltage drop, leading to low efficiency. Drive voltages below 12V can cause severe IGBT overheating. However, excessively high drive voltages shorten the time the IGBT can withstand short circuits and overcurrents, making protection difficult and potentially damaging. The ideal IGBT drive voltage is 15±1V. Therefore, the IGBT's drive protection circuit is crucial to the reliability of the entire operating system.

[0040] Reference Figure 2 , shows a schematic structural diagram of another driving protection circuit of a power semiconductor device according to an embodiment of the present invention, wherein the first control circuit 20 includes: The first comparator 21 has a positive input terminal connected to one end of the capacitor 60 , and a negative input terminal connected to the second power supply 70 .

[0041] When the capacitor 60 has not been charged, or the capacitor 60 has been charged for a period of time and the voltage of the capacitor 60 is still very low, the voltage at the positive input terminal of the first comparator 21 is less than the voltage at the reverse input terminal, and the first comparator 21 outputs a low level; when the capacitor 60 is charged to an overly high voltage, the voltage at the positive input terminal of the first comparator 21 is greater than the voltage at the reverse input terminal, and the first comparator 21 outputs a high level.

[0042] The first triode 22 has an emitter connected to the output end of the first comparator 21 , and a collector connected to the second power supply 70 .

[0043] The first transistor 22 is a PNP transistor. When the voltages at pins 1 and 2 of the first transistor 22 are higher than the turn-on voltage of the first transistor 22, the first transistor 22 is turned on. Therefore, when the first comparator 21 outputs a low level, the first transistor 22 is turned on; when the first comparator 21 outputs a high level, the first transistor 22 is turned off.

[0044] The second transistor 23 has a base connected to the base of the first transistor 22, a collector of the second transistor 23 receives the first pulse modulation signal 24, and an emitter of the second transistor 23 is grounded and connected to the control end of the first power semiconductor device 10; the second transistor 23 is used to output the first control signal.

[0045] The second transistor 23 is an NPN transistor. When the first transistor 22 is in the on state and the first pulse modulation signal 24 received by the second transistor 23 is at a high level, the second transistor 23 is turned on, that is, the first control signal output by the second transistor 23 is at a high level. At this time, the first power semiconductor device 10 is turned on; when the first transistor 22 is in the off state, the first pulse modulation signal 24 cannot be input to the control end of the first power semiconductor device 10, that is, the first control signal output by the second transistor 23 is at a low level, and at this time, the first power semiconductor device 10 is turned off.

[0046] When the capacitor 60 is undervoltage, the first comparator 21 outputs a low level, the first transistor 22 is turned on, and when the first pulse modulation signal 24 is high, the second transistor 23 is turned on, and the first control signal output by the second transistor 23 is high.

[0047] When the capacitor 60 is over-voltage, the first comparator 21 outputs a high level, the first transistor 22 is turned off, and the first control signal output by the second transistor 23 is a low level.

[0048] Capacitor 60 is a bootstrap capacitor. Initially, when capacitor 60 is uncharged, the voltage on capacitor 60 is very low. The first comparator 21 outputs a low level, turning on the first transistor 22. When the first pulse modulation signal 24 is high, the second transistor 23 turns on. Therefore, the VCC second power supply 70 connected to pin 1 of the first transistor 22 is output through the first transistor 22 to the control terminal of the first power semiconductor device 10. At this time, the first power semiconductor device 10 is turned on, and capacitor 60 can be charged through the VCC second power supply 70 connected to one end of capacitor 60, capacitor 60, and first power semiconductor device 10. When the voltage of capacitor 60 is too high, the first comparator 21 outputs a high level, turning off the first transistor 22. The first pulse modulation signal 24 cannot be input to the control terminal of the first power semiconductor device 10. At this time, capacitor 60 cannot be charged through the first power semiconductor device 10. Both the first power semiconductor device 10 and the second power semiconductor device 30 are in the off state, thereby achieving bootstrap voltage overvoltage protection for the second power semiconductor device 30.

[0049] By connecting the positive input terminal of the first comparator 21 to the capacitor 60, the output signal of the first comparator 21 can change with the voltage state of the capacitor 60. When the capacitor 60 is undervoltage, the first comparator 21 outputs a low level. When the capacitor 60 is overvoltage, the first comparator 21 outputs a high level. The output terminal of the first comparator 21 is connected to the first transistor 22, which is connected to the second transistor 23. The second transistor 23 is connected to the control terminal of the first power semiconductor device 10. This allows the voltage state of the capacitor 60 to control the operating state of the first power semiconductor device 10. When the capacitor 60 is undervoltage, the first power semiconductor device 10 is turned on and the capacitor 60 is charged. When the capacitor 60 is overvoltage, the first power semiconductor device 10 is turned off and the second power semiconductor device 30 is turned off, thereby achieving overvoltage protection for the second power semiconductor device 30.

[0050] Since the driving voltage of the first power semiconductor device 10 is the second power supply 70 connected to pin 1 of the first triode 22, and the second power supply 70 is a stable voltage source, the first power semiconductor device 10 will not suffer from driving voltage overvoltage or undervoltage issues. However, the driving voltage of the second power semiconductor device 30 is the voltage of the bootstrap capacitor 60, which is not a stable voltage source. Therefore, the second power semiconductor device 30 may suffer from driving voltage overvoltage or undervoltage issues, and overvoltage and undervoltage protection of the driving voltage is required.

[0051] In an embodiment of the present invention, the second control circuit 50 includes: The second comparator 51 has a positive input terminal connected to the second power supply 70 , and a negative input terminal connected to the second power supply 70 and the capacitor 60 , respectively.

[0052] After the capacitor 60 is charged for a period of time, when the voltage of the capacitor 60 is still too low, the voltage at the positive input terminal of the second comparator 51 is greater than the voltage at the negative input terminal, and the second comparator 51 outputs a high level.

[0053] The third transistor 52 has an emitter connected to the output end of the second comparator 51 , and a collector connected to the second power supply 70 and the capacitor 60 , respectively.

[0054] The third transistor 52 is a PNP transistor. The emitter of the third transistor 52, i.e., pin 2 of the third transistor 52, is connected to the output of the second comparator 51. The collector of the third transistor 52, i.e., pin 1 of the third transistor 52, is connected to the second power supply 70 and the capacitor 60, respectively. When the second comparator 51 outputs a high level, the third transistor 52 is turned off. When the second comparator 51 outputs a low level, the third transistor 52 is turned on.

[0055] The fourth transistor 53 has a base connected to the base of the third transistor 52, a collector of the fourth transistor 53 receives the second pulse modulation signal 54, and an emitter of the fourth transistor 53 is grounded and connected to the control end of the second power semiconductor device 30; the fourth transistor 53 is used to output the second control signal 54.

[0056] The base of the fourth transistor 53, i.e., pin 3 of the fourth transistor 53, is connected to the base of the third transistor 52, i.e., pin 3. The collector of the fourth transistor 53, i.e., pin 1, receives the second pulse modulation signal 54. The emitter of the fourth transistor 53, i.e., pin 2, is grounded and connected to the control terminal of the second power semiconductor device 30. When the third transistor 52 is turned off, the second pulse modulation signal 54 cannot be input to the control terminal of the second power semiconductor device 30. Regardless of whether the second pulse modulation signal 54 is at a high level or a low level, the fourth transistor 53 will not conduct, and neither will the second power semiconductor device 30.

[0057] When the capacitor 60 is undervoltage, the second comparator 51 outputs a high level, and the third transistor 52 is turned off; the second control signal output by the fourth transistor 53 is a low level.

[0058] When the capacitor 60 is undervoltage, the voltage at the positive input terminal of the second comparator 51 is greater than the voltage at the reverse input terminal, the second comparator 51 outputs a high level, and the third transistor 52 is cut off. At this time, whether the second pulse modulation signal 54 is high or low, the fourth transistor 53 will not be turned on, and the second power semiconductor device 30 will not be turned on, thereby achieving the function of protecting the second power semiconductor device 30 by the low bootstrap voltage of the bootstrap capacitor 60.

[0059] The second power semiconductor device 30 requires a bootstrap capacitor 60 to conduct properly. The charging circuit for the bootstrap capacitor 60 consists of a diode 80 and the bootstrap capacitor 60. The driver comprises a fourth transistor 53 and a third transistor 52. The voltage of the capacitor 60 is compared by a second comparator 51 to control the second pulse modulation signal 54, the input signal to the second power semiconductor device 30. The driver of the first power semiconductor device 10 comprises a first transistor 22 and a second transistor 23. The voltage of the capacitor 60 is compared by a first comparator 21 to control the first pulse modulation signal 24, the input signal to the first power semiconductor device 10.

[0060] For example, the voltage of capacitor 60 is set to three levels: 12V, 15V, and 17V. When the voltage of capacitor 60 is lower than 12V, that is, when the voltage of capacitor 60 is too low, the first comparator 21 outputs a low level, the first transistor 22 is turned on, and when the first pulse modulation signal 24 is at a high level, the second transistor 23 is turned on, the first power semiconductor device 10 is turned on, and the capacitor 60 is charged. At the same time, the second comparator 51 outputs a high level, the third transistor 52 is turned off, and at this time, whether the second pulse modulation signal 54 is at a high level or a low level, the fourth transistor 53 will not be turned on, and the second power semiconductor device 30 will not be turned on either, thereby achieving undervoltage protection for the driving voltage of the second power semiconductor device 30.

[0061] When the voltage of the capacitor 60 is 15V, that is, when the voltage of the capacitor 60 is at the ideal driving voltage level of the second power semiconductor device 30, the voltage of the positive input terminal of the second comparator 51 is less than the voltage of the reverse input terminal, the second comparator 51 outputs a low level, the third transistor 52 is turned on, and the second pulse modulation signal 54 can be input to the control terminal of the second power semiconductor device 30 to control the working state of the second power semiconductor device 30. When the second pulse modulation signal 54 is a high level, the fourth transistor 53 is turned on, and the second power semiconductor device 30 can be turned on.

[0062] When the voltage of the capacitor 60 is 17V, that is, the voltage of the capacitor 60 is too high, the first comparator 21 outputs a high level, the first transistor 22 is cut off, and the second transistor 23 and the first power semiconductor device 10 cannot be turned on regardless of whether the first pulse modulation signal 24 is a high level or a low level. Therefore, the capacitor 60 cannot be charged and the second power semiconductor device 30 will not be turned on, thereby achieving overvoltage protection for the driving voltage of the second power semiconductor device 30.

[0063] The present invention utilizes a bootstrap capacitor voltage detection capacitor to ensure that the IGBT drive signal enters the IGBT only when the bootstrap voltage reaches a limit. Furthermore, the capacitor cuts off the input signal when the bootstrap voltage is too high, effectively protecting the IGBT and the bootstrap capacitor from damage. This improves the IGBT's protection performance under abnormal conditions.

[0064] In the embodiment of the present invention, the circuit further includes a diode 80, the anode of the diode 80 is connected to the second power supply 70, and the cathode of the diode 80 is respectively connected to the inverting input terminal of the second comparator 51, the collector of the third transistor 52 and the capacitor 60.

[0065] When the first power semiconductor device 10 is turned on, the charging circuit of the capacitor 60 is the second power source 70 - diode 80 - capacitor 60 - first power semiconductor device 10 , and the diode 80 is used for reverse clamping.

[0066] In an embodiment of the present invention, the circuit further includes: a first resistor 90 , one end of the first resistor 90 being connected to the second power supply 70 , and the other end being connected to the inverting input terminal of the first comparator 21 ; The second resistor 91 has one end connected to the first resistor 90 and the inverting input terminal of the first comparator 21 , and the other end grounded.

[0067] The first resistor 90 and the second resistor 91 are voltage-dividing resistors connected to the inverting input terminal of the first comparator 21. After voltage division, they serve as the input voltage of the inverting input terminal of the first comparator 21. By adjusting the parameters of the first resistor 90 and the second resistor 91, it can be achieved that when the voltage across the capacitor 60 is lower than a certain threshold (the capacitor 60 is not charged or has not been fully charged), the voltage at the inverting input terminal of the first comparator 21 is greater than the voltage at the positive input terminal, so that the first comparator 21 outputs a low level when the capacitor 60 is not charged or has not been fully charged.

[0068] In an embodiment of the present invention, the circuit further includes: a third resistor 92 , one end of the third resistor 92 being connected to the second power supply 70 , and the other end of the third resistor 92 being connected to the positive input terminal of the second comparator 51 ; The fourth resistor 93 has one end connected to the third resistor 92 and the positive input terminal of the second comparator 51 respectively, and the other end grounded.

[0069] The third resistor 92 and the fourth resistor 93 are voltage-dividing resistors connected to the positive input terminal of the second comparator 51. After voltage division, they serve as the input voltage of the positive input terminal of the second comparator 51. By adjusting the parameters of the third resistor 92 and the fourth resistor 93, it can be achieved that when the voltage across the capacitor 60 reaches the ideal driving voltage of the second power semiconductor device 30, the voltage at the reverse input terminal of the second comparator 51 is greater than the voltage at the positive input terminal, so that when the voltage of the capacitor 60 meets the ideal driving voltage of the second power semiconductor device 30, the second comparator 51 outputs a low level.

[0070] In an embodiment of the present invention, the circuit further includes: The fifth resistor 94 has one end connected to the output end of the first comparator 21 and the other end connected to the second power supply 70 .

[0071] Resistor 94 is a pull-up resistor. The comparator itself typically has an open-drain output structure. This means it can only pull the output low (connected to ground) and cannot actively pull the output high. Therefore, when the comparator is off, the output is in a high-impedance state, requiring external components to determine its logic level. The pull-up resistor provides a path that pulls the comparator output toward the power supply voltage (Vcc) when the comparator output is off, resulting in a clear high-level signal.

[0072] In an embodiment of the present invention, the circuit further includes: The sixth resistor 95 has one end connected to the output end of the second comparator 51 and the other end connected to the second power supply 70 .

[0073] Resistor 95 is a pull-up resistor. The comparator itself typically has an open-drain output structure. This means it can only pull the output low (connected to ground) and cannot actively pull the output high. Therefore, when the comparator is off, the output is in a high-impedance state, requiring external components to determine its logic level. The pull-up resistor provides a path that pulls the comparator output toward the power supply voltage (Vcc) when the comparator output is off, resulting in a clear high-level signal.

[0074] In an embodiment of the present invention, the circuit further includes: The seventh resistor 96 has one end connected to the emitter of the second transistor 23 , and the other end connected to the control terminal of the first power semiconductor device 10 .

[0075] The seventh resistor 96 is a current-limiting resistor that can limit the charging current of the control terminal, i.e., the gate, of the first power semiconductor device 10 to prevent overload or damage to the drive circuit; it can also adjust the switching speed of the first power semiconductor device 10 to achieve a balance between switching loss and electromagnetic interference; it can suppress parasitic oscillations and improve the stability of the device operation; and it can also protect the gate oxide layer of the first power semiconductor device 10 from damage by voltage spikes.

[0076] In an embodiment of the present invention, the circuit further includes: The eighth resistor 97 has one end connected to the emitter of the fourth transistor 53 , and the other end connected to the control end of the second power semiconductor device 30 .

[0077] The eighth resistor 97 is a current-limiting resistor, which can limit the charging current of the control terminal, i.e., the gate, of the second power semiconductor device 30 to prevent overload or damage to the drive circuit; it can also adjust the switching speed of the second power semiconductor device 30, thereby achieving a balance between switching loss and electromagnetic interference; suppress parasitic oscillations and improve the stability of device operation; and at the same time protect the gate oxide layer of the second power semiconductor device 30 from damage by voltage spikes.

[0078] A driving protection circuit for a power semiconductor device according to an embodiment of the present invention includes a first power semiconductor device, wherein the output terminal of the first power semiconductor device is grounded, and the control terminal is used to receive a first control signal; a first control circuit is connected to the control terminal of the first power semiconductor device and is used to output the first control signal to the control terminal of the first power semiconductor device; a second power semiconductor device, wherein the output terminal of the second power semiconductor device is connected to the input terminal of the first power semiconductor device, the control terminal is used to receive a second control signal, and the input terminal is connected to a first power source; a second control circuit is connected to the control terminal of the second power semiconductor device and is used to output the second control signal to the control terminal of the second power semiconductor device; a capacitor , one end is respectively connected to the first control circuit, the second control circuit and the second power supply, and the other end is respectively connected to the input end of the first power semiconductor device and the output end of the second power semiconductor device; when the capacitor is undervoltage, the first control signal transmitted by the first control circuit is high, the first power semiconductor device is turned on, the second power supply charges the capacitor, and the second control signal transmitted by the second control circuit is low, the second power semiconductor device is turned off, so as to provide undervoltage protection for the second power semiconductor device; when the capacitor is overvoltage, the first control signal transmitted by the first control circuit is low, the first power semiconductor device is turned off, and the second power semiconductor device is turned off, so as to provide overvoltage protection for the second power semiconductor device. In the embodiment of the present invention, when the capacitor voltage is too low or too high, the second power semiconductor device is in the cut-off state, thereby preventing the second power semiconductor device from being affected by abnormal conditions such as overvoltage, overcurrent, short circuit, etc. when the driving voltage is too low or too high, resulting in device damage or performance degradation.

[0079] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0080] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatuses, or computer program products. Thus, embodiments of the present invention may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0081] The embodiments of the present invention are described with reference to flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0082] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0083] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0084] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0085] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0086] The above is a detailed introduction to a driving protection circuit for a power semiconductor device provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A driving protection circuit for a power semiconductor device, characterized in that: The circuit comprises: a first power semiconductor device, wherein an output terminal of the first power semiconductor device is grounded, and a control terminal is used to receive a first control signal; a first control circuit connected to the control terminal of the first power semiconductor device, and configured to output the first control signal to the control terminal of the first power semiconductor device; a second power semiconductor device, wherein the output terminal of the second power semiconductor device is connected to the input terminal of the first power semiconductor device, the control terminal is used to receive a second control signal, and the input terminal is connected to the first power supply; a second control circuit connected to the control terminal of the second power semiconductor device, and configured to output the second control signal to the control terminal of the second power semiconductor device; a capacitor, one end of which is respectively connected to the first control circuit, the second control circuit, and the second power supply, and the other end of which is respectively connected to the input end of the first power semiconductor device and the output end of the second power semiconductor device; When the capacitor is undervoltage, the first control signal transmitted by the first control circuit is at a high level, the first power semiconductor device is turned on, and the second power supply charges the capacitor; the second control signal transmitted by the second control circuit is at a low level, and the second power semiconductor device is turned off, so as to perform undervoltage protection on the second power semiconductor device; When the capacitor is over-voltage, the first control signal transmitted by the first control circuit is at a low level, the first power semiconductor device is turned off, and the second power semiconductor device is turned off to protect the second power semiconductor device from over-voltage.

2. The driving protection circuit of the power semiconductor device according to claim 1, characterized in that: The first control circuit includes: a first comparator, wherein a positive input terminal of the first comparator is connected to one end of the capacitor, and a negative input terminal of the first comparator is connected to the second power supply; a first triode, wherein an emitter of the first triode is connected to the output end of the first comparator, and a collector of the first triode is connected to the second power supply; a second transistor, wherein the base of the second transistor is connected to the base of the first transistor, the collector of the second transistor receives the first pulse modulation signal, the emitter of the second transistor is grounded and connected to the control terminal of the first power semiconductor device; the second transistor is used to output the first control signal; When the capacitor is undervoltage, the first comparator outputs a low level, and the first transistor is turned on. When the first pulse modulation signal is high, the second transistor is turned on, and the first control signal output by the second transistor is high. When the capacitor is over-voltage, the first comparator outputs a high level, the first transistor is turned off, and the first control signal output by the second transistor is a low level.

3. The driving protection circuit of the power semiconductor device according to claim 1, characterized in that: The second control circuit includes: a second comparator, wherein a positive input terminal of the second comparator is connected to the second power supply, and a negative input terminal of the second comparator is connected to the second power supply and the capacitor respectively; a third triode, wherein the emitter of the third triode is connected to the output end of the second comparator, and the collector of the third triode is connected to the second power supply and the capacitor respectively; a fourth transistor, wherein the base of the fourth transistor is connected to the base of the third transistor, the collector of the fourth transistor receives the second pulse modulation signal, the emitter of the fourth transistor is grounded and connected to the control terminal of the second power semiconductor device; the fourth transistor is configured to output the second control signal; When the capacitor is undervoltage, the second comparator outputs a high level, and the third transistor is turned off; the second control signal output by the fourth transistor is a low level.

4. The driving protection circuit of a power semiconductor device according to claim 1, characterized in that: The first power semiconductor device and the second power semiconductor device are IGBTs.

5. The driving protection circuit of the power semiconductor device according to claim 3, characterized in that: The circuit further includes a diode, an anode of the diode is connected to the second power supply, and a cathode of the diode is respectively connected to the inverting input terminal of the second comparator, the collector of the third transistor, and the capacitor.

6. The driving protection circuit of a power semiconductor device according to claim 2, characterized in that: The circuit further comprises: a first resistor, one end of the first resistor being connected to the second power supply, and the other end of the first resistor being connected to the inverting input terminal of the first comparator; a second resistor, one end of the second resistor being connected to the first resistor and the inverting input end of the first comparator respectively, and the other end being grounded.

7. The driving protection circuit of a power semiconductor device according to claim 3, characterized in that: The circuit further comprises: a third resistor, one end of the third resistor being connected to the second power supply, and the other end of the third resistor being connected to the positive input terminal of the second comparator; a fourth resistor, one end of the fourth resistor being connected to the third resistor and the positive input end of the second comparator respectively, and the other end being grounded.

8. The driving protection circuit of a power semiconductor device according to claim 2, characterized in that: The circuit further comprises: a fifth resistor, one end of the fifth resistor being connected to the output end of the first comparator, and the other end of the fifth resistor being connected to the second power supply.

9. The driving protection circuit of a power semiconductor device according to claim 3, characterized in that: The circuit further comprises: a sixth resistor, one end of the sixth resistor being connected to the output end of the second comparator, and the other end of the sixth resistor being connected to the second power supply.

10. The driving protection circuit of a power semiconductor device according to claim 2, characterized in that: The circuit further comprises: a seventh resistor, one end of the seventh resistor being connected to the emitter of the second transistor, and the other end of the seventh resistor being connected to the control end of the first power semiconductor device.

11. The driving protection circuit of a power semiconductor device according to claim 3, characterized in that: The circuit further comprises: an eighth resistor, one end of the eighth resistor being connected to the emitter of the fourth transistor, and the other end of the eighth resistor being connected to the control end of the second power semiconductor device.

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